1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Selectable predicate operand for CMOV instructions. We can't use a normal
159 // predicate because the default values interfere with instruction selection. In
160 // all other respects it is identical though: pseudo-instruction expansion
161 // relies on the MachineOperands being compatible.
162 def cmovpred : Operand<i32>, PredicateOp,
163 ComplexPattern<i32, 2, "SelectCMOVPred"> {
164 let MIOperandInfo = (ops i32imm, i32imm);
165 let PrintMethod = "printPredicateOperand";
168 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
169 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
170 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
171 let EncoderMethod = "getCCOutOpValue";
172 let PrintMethod = "printSBitModifierOperand";
173 let ParserMatchClass = CCOutOperand;
174 let DecoderMethod = "DecodeCCOutOperand";
177 // Same as cc_out except it defaults to setting CPSR.
178 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
179 let EncoderMethod = "getCCOutOpValue";
180 let PrintMethod = "printSBitModifierOperand";
181 let ParserMatchClass = CCOutOperand;
182 let DecoderMethod = "DecodeCCOutOperand";
185 // ARM special operands for disassembly only.
187 def SetEndAsmOperand : ImmAsmOperand {
188 let Name = "SetEndImm";
189 let ParserMethod = "parseSetEndImm";
191 def setend_op : Operand<i32> {
192 let PrintMethod = "printSetendOperand";
193 let ParserMatchClass = SetEndAsmOperand;
196 def MSRMaskOperand : AsmOperandClass {
197 let Name = "MSRMask";
198 let ParserMethod = "parseMSRMaskOperand";
200 def msr_mask : Operand<i32> {
201 let PrintMethod = "printMSRMaskOperand";
202 let DecoderMethod = "DecodeMSRMask";
203 let ParserMatchClass = MSRMaskOperand;
206 def BankedRegOperand : AsmOperandClass {
207 let Name = "BankedReg";
208 let ParserMethod = "parseBankedRegOperand";
210 def banked_reg : Operand<i32> {
211 let PrintMethod = "printBankedRegOperand";
212 let DecoderMethod = "DecodeBankedReg";
213 let ParserMatchClass = BankedRegOperand;
216 // Shift Right Immediate - A shift right immediate is encoded differently from
217 // other shift immediates. The imm6 field is encoded like so:
220 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
221 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
222 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
223 // 64 64 - <imm> is encoded in imm6<5:0>
224 def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
225 def shr_imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 8; }]> {
226 let EncoderMethod = "getShiftRight8Imm";
227 let DecoderMethod = "DecodeShiftRight8Imm";
228 let ParserMatchClass = shr_imm8_asm_operand;
230 def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
231 def shr_imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 16; }]> {
232 let EncoderMethod = "getShiftRight16Imm";
233 let DecoderMethod = "DecodeShiftRight16Imm";
234 let ParserMatchClass = shr_imm16_asm_operand;
236 def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
237 def shr_imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]> {
238 let EncoderMethod = "getShiftRight32Imm";
239 let DecoderMethod = "DecodeShiftRight32Imm";
240 let ParserMatchClass = shr_imm32_asm_operand;
242 def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
243 def shr_imm64 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 64; }]> {
244 let EncoderMethod = "getShiftRight64Imm";
245 let DecoderMethod = "DecodeShiftRight64Imm";
246 let ParserMatchClass = shr_imm64_asm_operand;
249 //===----------------------------------------------------------------------===//
250 // ARM Assembler alias templates.
252 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
253 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
254 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
255 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
256 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
257 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
258 class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
259 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
260 class VFP2DPInstAlias<string Asm, dag Result, bit Emit = 0b1>
261 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2,HasDPVFP]>;
262 class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
263 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
264 class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
265 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
268 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
270 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
273 //===----------------------------------------------------------------------===//
274 // ARM Instruction templates.
278 class InstTemplate<AddrMode am, int sz, IndexMode im,
279 Format f, Domain d, string cstr, InstrItinClass itin>
281 let Namespace = "ARM";
286 bits<2> IndexModeBits = IM.Value;
288 bits<6> Form = F.Value;
290 bit isUnaryDataProc = 0;
291 bit canXformTo16Bit = 0;
292 // The instruction is a 16-bit flag setting Thumb instruction. Used
293 // by the parser to determine whether to require the 'S' suffix on the
294 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
295 bit thumbArithFlagSetting = 0;
297 // If this is a pseudo instruction, mark it isCodeGenOnly.
298 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
300 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
301 let TSFlags{4-0} = AM.Value;
302 let TSFlags{6-5} = IndexModeBits;
303 let TSFlags{12-7} = Form;
304 let TSFlags{13} = isUnaryDataProc;
305 let TSFlags{14} = canXformTo16Bit;
306 let TSFlags{17-15} = D.Value;
307 let TSFlags{18} = thumbArithFlagSetting;
309 let Constraints = cstr;
310 let Itinerary = itin;
315 // Mask of bits that cause an encoding to be UNPREDICTABLE.
316 // If a bit is set, then if the corresponding bit in the
317 // target encoding differs from its value in the "Inst" field,
318 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
319 field bits<32> Unpredictable = 0;
320 // SoftFail is the generic name for this field, but we alias it so
321 // as to make it more obvious what it means in ARM-land.
322 field bits<32> SoftFail = Unpredictable;
325 class InstARM<AddrMode am, int sz, IndexMode im,
326 Format f, Domain d, string cstr, InstrItinClass itin>
327 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
328 let DecoderNamespace = "ARM";
331 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
332 // on by adding flavors to specific instructions.
333 class InstThumb<AddrMode am, int sz, IndexMode im,
334 Format f, Domain d, string cstr, InstrItinClass itin>
335 : InstTemplate<am, sz, im, f, d, cstr, itin> {
336 let DecoderNamespace = "Thumb";
339 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
340 // These are aliases that require C++ handling to convert to the target
341 // instruction, while InstAliases can be handled directly by tblgen.
342 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
343 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
345 let OutOperandList = oops;
346 let InOperandList = iops;
348 let isCodeGenOnly = 0; // So we get asm matcher for it.
353 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
354 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
355 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
356 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
357 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
358 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
359 class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
360 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
361 class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)>
362 : AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>;
364 // Pseudo instructions for the code generator.
365 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
366 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
367 GenericDomain, "", itin> {
368 let OutOperandList = oops;
369 let InOperandList = iops;
370 let Pattern = pattern;
371 let isCodeGenOnly = 1;
375 // PseudoInst that's ARM-mode only.
376 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
378 : PseudoInst<oops, iops, itin, pattern> {
380 list<Predicate> Predicates = [IsARM];
383 // PseudoInst that's Thumb-mode only.
384 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
386 : PseudoInst<oops, iops, itin, pattern> {
388 list<Predicate> Predicates = [IsThumb];
391 // PseudoInst that's Thumb2-mode only.
392 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
394 : PseudoInst<oops, iops, itin, pattern> {
396 list<Predicate> Predicates = [IsThumb2];
399 class ARMPseudoExpand<dag oops, dag iops, int sz,
400 InstrItinClass itin, list<dag> pattern,
402 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
403 PseudoInstExpansion<Result>;
405 class tPseudoExpand<dag oops, dag iops, int sz,
406 InstrItinClass itin, list<dag> pattern,
408 : tPseudoInst<oops, iops, sz, itin, pattern>,
409 PseudoInstExpansion<Result>;
411 class t2PseudoExpand<dag oops, dag iops, int sz,
412 InstrItinClass itin, list<dag> pattern,
414 : t2PseudoInst<oops, iops, sz, itin, pattern>,
415 PseudoInstExpansion<Result>;
417 // Almost all ARM instructions are predicable.
418 class I<dag oops, dag iops, AddrMode am, int sz,
419 IndexMode im, Format f, InstrItinClass itin,
420 string opc, string asm, string cstr,
422 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
425 let OutOperandList = oops;
426 let InOperandList = !con(iops, (ins pred:$p));
427 let AsmString = !strconcat(opc, "${p}", asm);
428 let Pattern = pattern;
429 list<Predicate> Predicates = [IsARM];
432 // A few are not predicable
433 class InoP<dag oops, dag iops, AddrMode am, int sz,
434 IndexMode im, Format f, InstrItinClass itin,
435 string opc, string asm, string cstr,
437 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
438 let OutOperandList = oops;
439 let InOperandList = iops;
440 let AsmString = !strconcat(opc, asm);
441 let Pattern = pattern;
442 let isPredicable = 0;
443 list<Predicate> Predicates = [IsARM];
446 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
447 // operand since by default it's a zero register. It will become an implicit def
448 // once it's "flipped".
449 class sI<dag oops, dag iops, AddrMode am, int sz,
450 IndexMode im, Format f, InstrItinClass itin,
451 string opc, string asm, string cstr,
453 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
454 bits<4> p; // Predicate operand
455 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
459 let OutOperandList = oops;
460 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
461 let AsmString = !strconcat(opc, "${s}${p}", asm);
462 let Pattern = pattern;
463 list<Predicate> Predicates = [IsARM];
467 class XI<dag oops, dag iops, AddrMode am, int sz,
468 IndexMode im, Format f, InstrItinClass itin,
469 string asm, string cstr, list<dag> pattern>
470 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
471 let OutOperandList = oops;
472 let InOperandList = iops;
474 let Pattern = pattern;
475 list<Predicate> Predicates = [IsARM];
478 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
479 string opc, string asm, list<dag> pattern>
480 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
481 opc, asm, "", pattern>;
482 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
483 string opc, string asm, list<dag> pattern>
484 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
485 opc, asm, "", pattern>;
486 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
487 string asm, list<dag> pattern>
488 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
490 class AXIM<dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin,
491 string asm, list<dag> pattern>
492 : XI<oops, iops, am, 4, IndexModeNone, f, itin,
494 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
495 string opc, string asm, list<dag> pattern>
496 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
497 opc, asm, "", pattern>;
499 // Ctrl flow instructions
500 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
501 string opc, string asm, list<dag> pattern>
502 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
503 opc, asm, "", pattern> {
504 let Inst{27-24} = opcod;
506 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
507 string asm, list<dag> pattern>
508 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
510 let Inst{27-24} = opcod;
513 // BR_JT instructions
514 class JTI<dag oops, dag iops, InstrItinClass itin,
515 string asm, list<dag> pattern>
516 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
519 class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
520 string opc, string asm, list<dag> pattern>
521 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
522 opc, asm, "", pattern> {
525 let Inst{27-23} = 0b00011;
526 let Inst{22-21} = opcod;
528 let Inst{19-16} = addr;
529 let Inst{15-12} = Rt;
530 let Inst{11-10} = 0b11;
531 let Inst{9-8} = opcod2;
532 let Inst{7-0} = 0b10011111;
534 class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
535 string opc, string asm, list<dag> pattern>
536 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
537 opc, asm, "", pattern> {
540 let Inst{27-23} = 0b00011;
541 let Inst{22-21} = opcod;
543 let Inst{19-16} = addr;
544 let Inst{11-10} = 0b11;
545 let Inst{9-8} = opcod2;
546 let Inst{7-4} = 0b1001;
549 // Atomic load/store instructions
550 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
551 string opc, string asm, list<dag> pattern>
552 : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>;
554 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
555 string opc, string asm, list<dag> pattern>
556 : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> {
558 let Inst{15-12} = Rd;
561 // Exclusive load/store instructions
563 class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
564 string opc, string asm, list<dag> pattern>
565 : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
566 Requires<[IsARM, HasV8]>;
568 class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
569 string opc, string asm, list<dag> pattern>
570 : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
571 Requires<[IsARM, HasV8]> {
573 let Inst{15-12} = Rd;
576 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
577 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
581 let Inst{27-23} = 0b00010;
583 let Inst{21-20} = 0b00;
584 let Inst{19-16} = addr;
585 let Inst{15-12} = Rt;
586 let Inst{11-4} = 0b00001001;
589 let Unpredictable{11-8} = 0b1111;
590 let DecoderMethod = "DecodeSwap";
592 // Acquire/Release load/store instructions
593 class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
594 string opc, string asm, list<dag> pattern>
595 : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
596 Requires<[IsARM, HasV8]>;
598 class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
599 string opc, string asm, list<dag> pattern>
600 : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
601 Requires<[IsARM, HasV8]> {
602 let Inst{15-12} = 0b1111;
605 // addrmode1 instructions
606 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
607 string opc, string asm, list<dag> pattern>
608 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
609 opc, asm, "", pattern> {
610 let Inst{24-21} = opcod;
611 let Inst{27-26} = 0b00;
613 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
614 string opc, string asm, list<dag> pattern>
615 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
616 opc, asm, "", pattern> {
617 let Inst{24-21} = opcod;
618 let Inst{27-26} = 0b00;
620 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
621 string asm, list<dag> pattern>
622 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
624 let Inst{24-21} = opcod;
625 let Inst{27-26} = 0b00;
630 // LDR/LDRB/STR/STRB/...
631 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
632 Format f, InstrItinClass itin, string opc, string asm,
634 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
636 let Inst{27-25} = op;
637 let Inst{24} = 1; // 24 == P
639 let Inst{22} = isByte;
640 let Inst{21} = 0; // 21 == W
643 // Indexed load/stores
644 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
645 IndexMode im, Format f, InstrItinClass itin, string opc,
646 string asm, string cstr, list<dag> pattern>
647 : I<oops, iops, AddrMode2, 4, im, f, itin,
648 opc, asm, cstr, pattern> {
650 let Inst{27-26} = 0b01;
651 let Inst{24} = isPre; // P bit
652 let Inst{22} = isByte; // B bit
653 let Inst{21} = isPre; // W bit
654 let Inst{20} = isLd; // L bit
655 let Inst{15-12} = Rt;
657 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
658 IndexMode im, Format f, InstrItinClass itin, string opc,
659 string asm, string cstr, list<dag> pattern>
660 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
662 // AM2 store w/ two operands: (GPR, am2offset)
668 let Inst{23} = offset{12};
669 let Inst{19-16} = Rn;
670 let Inst{11-5} = offset{11-5};
672 let Inst{3-0} = offset{3-0};
675 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
676 IndexMode im, Format f, InstrItinClass itin, string opc,
677 string asm, string cstr, list<dag> pattern>
678 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
680 // AM2 store w/ two operands: (GPR, am2offset)
686 let Inst{23} = offset{12};
687 let Inst{19-16} = Rn;
688 let Inst{11-0} = offset{11-0};
692 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
693 // but for now use this class for STRT and STRBT.
694 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
695 IndexMode im, Format f, InstrItinClass itin, string opc,
696 string asm, string cstr, list<dag> pattern>
697 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
699 // AM2 store w/ two operands: (GPR, am2offset)
701 // {13} 1 == Rm, 0 == imm12
705 let Inst{25} = addr{13};
706 let Inst{23} = addr{12};
707 let Inst{19-16} = addr{17-14};
708 let Inst{11-0} = addr{11-0};
711 // addrmode3 instructions
712 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
713 InstrItinClass itin, string opc, string asm, list<dag> pattern>
714 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
715 opc, asm, "", pattern> {
718 let Inst{27-25} = 0b000;
719 let Inst{24} = 1; // P bit
720 let Inst{23} = addr{8}; // U bit
721 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
722 let Inst{21} = 0; // W bit
723 let Inst{20} = op20; // L bit
724 let Inst{19-16} = addr{12-9}; // Rn
725 let Inst{15-12} = Rt; // Rt
726 let Inst{11-8} = addr{7-4}; // imm7_4/zero
728 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
730 let DecoderMethod = "DecodeAddrMode3Instruction";
733 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
734 IndexMode im, Format f, InstrItinClass itin, string opc,
735 string asm, string cstr, list<dag> pattern>
736 : I<oops, iops, AddrMode3, 4, im, f, itin,
737 opc, asm, cstr, pattern> {
739 let Inst{27-25} = 0b000;
740 let Inst{24} = isPre; // P bit
741 let Inst{21} = isPre; // W bit
742 let Inst{20} = op20; // L bit
743 let Inst{15-12} = Rt; // Rt
747 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
748 // but for now use this class for LDRSBT, LDRHT, LDSHT.
749 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
750 IndexMode im, Format f, InstrItinClass itin, string opc,
751 string asm, string cstr, list<dag> pattern>
752 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
753 // {13} 1 == imm8, 0 == Rm
760 let Inst{27-25} = 0b000;
761 let Inst{24} = 0; // P bit
763 let Inst{20} = isLoad; // L bit
764 let Inst{19-16} = addr; // Rn
765 let Inst{15-12} = Rt; // Rt
770 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
771 string opc, string asm, list<dag> pattern>
772 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
773 opc, asm, "", pattern> {
776 let Inst{27-25} = 0b000;
777 let Inst{24} = 1; // P bit
778 let Inst{23} = addr{8}; // U bit
779 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
780 let Inst{21} = 0; // W bit
781 let Inst{20} = 0; // L bit
782 let Inst{19-16} = addr{12-9}; // Rn
783 let Inst{15-12} = Rt; // Rt
784 let Inst{11-8} = addr{7-4}; // imm7_4/zero
786 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
787 let DecoderMethod = "DecodeAddrMode3Instruction";
790 // addrmode4 instructions
791 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
792 string asm, string cstr, list<dag> pattern>
793 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
798 let Inst{27-25} = 0b100;
799 let Inst{22} = 0; // S bit
800 let Inst{19-16} = Rn;
801 let Inst{15-0} = regs;
804 // Unsigned multiply, multiply-accumulate instructions.
805 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
806 string opc, string asm, list<dag> pattern>
807 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
808 opc, asm, "", pattern> {
809 let Inst{7-4} = 0b1001;
810 let Inst{20} = 0; // S bit
811 let Inst{27-21} = opcod;
813 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
814 string opc, string asm, list<dag> pattern>
815 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
816 opc, asm, "", pattern> {
817 let Inst{7-4} = 0b1001;
818 let Inst{27-21} = opcod;
821 // Most significant word multiply
822 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
823 InstrItinClass itin, string opc, string asm, list<dag> pattern>
824 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
825 opc, asm, "", pattern> {
829 let Inst{7-4} = opc7_4;
831 let Inst{27-21} = opcod;
832 let Inst{19-16} = Rd;
836 // MSW multiple w/ Ra operand
837 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
838 InstrItinClass itin, string opc, string asm, list<dag> pattern>
839 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
841 let Inst{15-12} = Ra;
844 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
845 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
846 InstrItinClass itin, string opc, string asm, list<dag> pattern>
847 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
848 opc, asm, "", pattern> {
854 let Inst{27-21} = opcod;
855 let Inst{6-5} = bit6_5;
859 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
860 InstrItinClass itin, string opc, string asm, list<dag> pattern>
861 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
863 let Inst{19-16} = Rd;
866 // AMulxyI with Ra operand
867 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
868 InstrItinClass itin, string opc, string asm, list<dag> pattern>
869 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
871 let Inst{15-12} = Ra;
874 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
875 InstrItinClass itin, string opc, string asm, list<dag> pattern>
876 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
879 let Inst{19-16} = RdHi;
880 let Inst{15-12} = RdLo;
883 // Extend instructions.
884 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
885 string opc, string asm, list<dag> pattern>
886 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
887 opc, asm, "", pattern> {
888 // All AExtI instructions have Rd and Rm register operands.
891 let Inst{15-12} = Rd;
893 let Inst{7-4} = 0b0111;
894 let Inst{9-8} = 0b00;
895 let Inst{27-20} = opcod;
897 let Unpredictable{9-8} = 0b11;
900 // Misc Arithmetic instructions.
901 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
902 InstrItinClass itin, string opc, string asm, list<dag> pattern>
903 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
904 opc, asm, "", pattern> {
907 let Inst{27-20} = opcod;
908 let Inst{19-16} = 0b1111;
909 let Inst{15-12} = Rd;
910 let Inst{11-8} = 0b1111;
911 let Inst{7-4} = opc7_4;
915 // Division instructions.
916 class ADivA1I<bits<3> opcod, dag oops, dag iops,
917 InstrItinClass itin, string opc, string asm, list<dag> pattern>
918 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
919 opc, asm, "", pattern> {
923 let Inst{27-23} = 0b01110;
924 let Inst{22-20} = opcod;
925 let Inst{19-16} = Rd;
926 let Inst{15-12} = 0b1111;
928 let Inst{7-4} = 0b0001;
933 def PKHLSLAsmOperand : ImmAsmOperand {
934 let Name = "PKHLSLImm";
935 let ParserMethod = "parsePKHLSLImm";
937 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
938 let PrintMethod = "printPKHLSLShiftImm";
939 let ParserMatchClass = PKHLSLAsmOperand;
941 def PKHASRAsmOperand : AsmOperandClass {
942 let Name = "PKHASRImm";
943 let ParserMethod = "parsePKHASRImm";
945 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
946 let PrintMethod = "printPKHASRShiftImm";
947 let ParserMatchClass = PKHASRAsmOperand;
950 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
951 string opc, string asm, list<dag> pattern>
952 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
953 opc, asm, "", pattern> {
958 let Inst{27-20} = opcod;
959 let Inst{19-16} = Rn;
960 let Inst{15-12} = Rd;
963 let Inst{5-4} = 0b01;
967 //===----------------------------------------------------------------------===//
969 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
970 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
971 list<Predicate> Predicates = [IsARM];
973 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
974 list<Predicate> Predicates = [IsARM, HasV5T];
976 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
977 list<Predicate> Predicates = [IsARM, HasV5TE];
979 // ARMV5MOPat - Same as ARMV5TEPat with UseMulOps.
980 class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> {
981 list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
983 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
984 list<Predicate> Predicates = [IsARM, HasV6];
986 class VFPPat<dag pattern, dag result> : Pat<pattern, result> {
987 list<Predicate> Predicates = [HasVFP2];
989 class VFPNoNEONPat<dag pattern, dag result> : Pat<pattern, result> {
990 list<Predicate> Predicates = [HasVFP2, DontUseNEONForFP];
992 //===----------------------------------------------------------------------===//
993 // Thumb Instruction Format Definitions.
996 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
997 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
998 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
999 let OutOperandList = oops;
1000 let InOperandList = iops;
1001 let AsmString = asm;
1002 let Pattern = pattern;
1003 list<Predicate> Predicates = [IsThumb];
1006 // TI - Thumb instruction.
1007 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
1008 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
1010 // Two-address instructions
1011 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1013 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
1016 // tBL, tBX 32-bit instructions
1017 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1018 dag oops, dag iops, InstrItinClass itin, string asm,
1020 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
1022 let Inst{31-27} = opcod1;
1023 let Inst{15-14} = opcod2;
1024 let Inst{12} = opcod3;
1027 // BR_JT instructions
1028 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1030 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1033 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
1034 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1035 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1036 let OutOperandList = oops;
1037 let InOperandList = iops;
1038 let AsmString = asm;
1039 let Pattern = pattern;
1040 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1043 class T1I<dag oops, dag iops, InstrItinClass itin,
1044 string asm, list<dag> pattern>
1045 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
1046 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1047 string asm, list<dag> pattern>
1048 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1050 // Two-address instructions
1051 class T1It<dag oops, dag iops, InstrItinClass itin,
1052 string asm, string cstr, list<dag> pattern>
1053 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
1054 asm, cstr, pattern>;
1056 // Thumb1 instruction that can either be predicated or set CPSR.
1057 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
1058 InstrItinClass itin,
1059 string opc, string asm, string cstr, list<dag> pattern>
1060 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1061 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1062 let InOperandList = !con(iops, (ins pred:$p));
1063 let AsmString = !strconcat(opc, "${s}${p}", asm);
1064 let Pattern = pattern;
1065 let thumbArithFlagSetting = 1;
1066 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1067 let DecoderNamespace = "ThumbSBit";
1070 class T1sI<dag oops, dag iops, InstrItinClass itin,
1071 string opc, string asm, list<dag> pattern>
1072 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1074 // Two-address instructions
1075 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1076 string opc, string asm, list<dag> pattern>
1077 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1078 "$Rn = $Rdn", pattern>;
1080 // Thumb1 instruction that can be predicated.
1081 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
1082 InstrItinClass itin,
1083 string opc, string asm, string cstr, list<dag> pattern>
1084 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1085 let OutOperandList = oops;
1086 let InOperandList = !con(iops, (ins pred:$p));
1087 let AsmString = !strconcat(opc, "${p}", asm);
1088 let Pattern = pattern;
1089 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1092 class T1pI<dag oops, dag iops, InstrItinClass itin,
1093 string opc, string asm, list<dag> pattern>
1094 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1096 // Two-address instructions
1097 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1098 string opc, string asm, list<dag> pattern>
1099 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1100 "$Rn = $Rdn", pattern>;
1102 class T1pIs<dag oops, dag iops,
1103 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1104 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1106 class Encoding16 : Encoding {
1107 let Inst{31-16} = 0x0000;
1110 // A6.2 16-bit Thumb instruction encoding
1111 class T1Encoding<bits<6> opcode> : Encoding16 {
1112 let Inst{15-10} = opcode;
1115 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1116 class T1General<bits<5> opcode> : Encoding16 {
1117 let Inst{15-14} = 0b00;
1118 let Inst{13-9} = opcode;
1121 // A6.2.2 Data-processing encoding.
1122 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1123 let Inst{15-10} = 0b010000;
1124 let Inst{9-6} = opcode;
1127 // A6.2.3 Special data instructions and branch and exchange encoding.
1128 class T1Special<bits<4> opcode> : Encoding16 {
1129 let Inst{15-10} = 0b010001;
1130 let Inst{9-6} = opcode;
1133 // A6.2.4 Load/store single data item encoding.
1134 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1135 let Inst{15-12} = opA;
1136 let Inst{11-9} = opB;
1138 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1140 class T1BranchCond<bits<4> opcode> : Encoding16 {
1141 let Inst{15-12} = opcode;
1144 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1145 // following bits are used for "opA" (see A6.2.4):
1147 // 0b0110 => Immediate, 4 bytes
1148 // 0b1000 => Immediate, 2 bytes
1149 // 0b0111 => Immediate, 1 byte
1150 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1151 InstrItinClass itin, string opc, string asm,
1153 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1154 T1LoadStore<0b0101, opcode> {
1157 let Inst{8-6} = addr{5-3}; // Rm
1158 let Inst{5-3} = addr{2-0}; // Rn
1161 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1162 InstrItinClass itin, string opc, string asm,
1164 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1165 T1LoadStore<opA, {opB,?,?}> {
1168 let Inst{10-6} = addr{7-3}; // imm5
1169 let Inst{5-3} = addr{2-0}; // Rn
1173 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1174 class T1Misc<bits<7> opcode> : Encoding16 {
1175 let Inst{15-12} = 0b1011;
1176 let Inst{11-5} = opcode;
1179 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1180 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1181 InstrItinClass itin,
1182 string opc, string asm, string cstr, list<dag> pattern>
1183 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1184 let OutOperandList = oops;
1185 let InOperandList = !con(iops, (ins pred:$p));
1186 let AsmString = !strconcat(opc, "${p}", asm);
1187 let Pattern = pattern;
1188 list<Predicate> Predicates = [IsThumb2];
1189 let DecoderNamespace = "Thumb2";
1192 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1193 // input operand since by default it's a zero register. It will become an
1194 // implicit def once it's "flipped".
1196 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1198 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1199 InstrItinClass itin,
1200 string opc, string asm, string cstr, list<dag> pattern>
1201 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1202 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1205 let OutOperandList = oops;
1206 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1207 let AsmString = !strconcat(opc, "${s}${p}", asm);
1208 let Pattern = pattern;
1209 list<Predicate> Predicates = [IsThumb2];
1210 let DecoderNamespace = "Thumb2";
1214 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1215 InstrItinClass itin,
1216 string asm, string cstr, list<dag> pattern>
1217 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1218 let OutOperandList = oops;
1219 let InOperandList = iops;
1220 let AsmString = asm;
1221 let Pattern = pattern;
1222 list<Predicate> Predicates = [IsThumb2];
1223 let DecoderNamespace = "Thumb2";
1226 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1227 InstrItinClass itin,
1228 string asm, string cstr, list<dag> pattern>
1229 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1230 let OutOperandList = oops;
1231 let InOperandList = iops;
1232 let AsmString = asm;
1233 let Pattern = pattern;
1234 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1235 let DecoderNamespace = "Thumb";
1238 class T2I<dag oops, dag iops, InstrItinClass itin,
1239 string opc, string asm, list<dag> pattern>
1240 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1241 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1242 string opc, string asm, list<dag> pattern>
1243 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1244 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1245 string opc, string asm, list<dag> pattern>
1246 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1247 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1248 string opc, string asm, list<dag> pattern>
1249 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1250 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1251 string opc, string asm, list<dag> pattern>
1252 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1253 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1254 string opc, string asm, string cstr, list<dag> pattern>
1255 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1260 let Inst{31-25} = 0b1110100;
1262 let Inst{23} = addr{8};
1265 let Inst{20} = isLoad;
1266 let Inst{19-16} = addr{12-9};
1267 let Inst{15-12} = Rt{3-0};
1268 let Inst{11-8} = Rt2{3-0};
1269 let Inst{7-0} = addr{7-0};
1271 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1272 InstrItinClass itin, string opc, string asm, string cstr,
1274 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1280 let Inst{31-25} = 0b1110100;
1282 let Inst{23} = imm{8};
1285 let Inst{20} = isLoad;
1286 let Inst{19-16} = addr;
1287 let Inst{15-12} = Rt{3-0};
1288 let Inst{11-8} = Rt2{3-0};
1289 let Inst{7-0} = imm{7-0};
1292 class T2sI<dag oops, dag iops, InstrItinClass itin,
1293 string opc, string asm, list<dag> pattern>
1294 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1296 class T2XI<dag oops, dag iops, InstrItinClass itin,
1297 string asm, list<dag> pattern>
1298 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1299 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1300 string asm, list<dag> pattern>
1301 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1303 // Move to/from coprocessor instructions
1304 class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
1306 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
1307 let Inst{31-28} = opc;
1310 // Two-address instructions
1311 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1312 string asm, string cstr, list<dag> pattern>
1313 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1315 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1316 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1318 AddrMode am, IndexMode im, InstrItinClass itin,
1319 string opc, string asm, string cstr, list<dag> pattern>
1320 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1321 let OutOperandList = oops;
1322 let InOperandList = !con(iops, (ins pred:$p));
1323 let AsmString = !strconcat(opc, "${p}", asm);
1324 let Pattern = pattern;
1325 list<Predicate> Predicates = [IsThumb2];
1326 let DecoderNamespace = "Thumb2";
1330 let Inst{31-27} = 0b11111;
1331 let Inst{26-25} = 0b00;
1332 let Inst{24} = signed;
1334 let Inst{22-21} = opcod;
1335 let Inst{20} = load;
1336 let Inst{19-16} = addr{12-9};
1337 let Inst{15-12} = Rt{3-0};
1339 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1340 let Inst{10} = pre; // The P bit.
1341 let Inst{9} = addr{8}; // Sign bit
1342 let Inst{8} = 1; // The W bit.
1343 let Inst{7-0} = addr{7-0};
1345 let DecoderMethod = "DecodeT2LdStPre";
1348 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1349 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1351 AddrMode am, IndexMode im, InstrItinClass itin,
1352 string opc, string asm, string cstr, list<dag> pattern>
1353 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1354 let OutOperandList = oops;
1355 let InOperandList = !con(iops, (ins pred:$p));
1356 let AsmString = !strconcat(opc, "${p}", asm);
1357 let Pattern = pattern;
1358 list<Predicate> Predicates = [IsThumb2];
1359 let DecoderNamespace = "Thumb2";
1364 let Inst{31-27} = 0b11111;
1365 let Inst{26-25} = 0b00;
1366 let Inst{24} = signed;
1368 let Inst{22-21} = opcod;
1369 let Inst{20} = load;
1370 let Inst{19-16} = Rn;
1371 let Inst{15-12} = Rt{3-0};
1373 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1374 let Inst{10} = pre; // The P bit.
1375 let Inst{9} = offset{8}; // Sign bit
1376 let Inst{8} = 1; // The W bit.
1377 let Inst{7-0} = offset{7-0};
1379 let DecoderMethod = "DecodeT2LdStPre";
1382 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1383 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1384 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1387 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1388 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1389 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1392 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1393 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1394 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1397 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1398 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1399 list<Predicate> Predicates = [IsThumb2];
1402 //===----------------------------------------------------------------------===//
1404 //===----------------------------------------------------------------------===//
1405 // ARM VFP Instruction templates.
1408 // Almost all VFP instructions are predicable.
1409 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1410 IndexMode im, Format f, InstrItinClass itin,
1411 string opc, string asm, string cstr, list<dag> pattern>
1412 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1414 let Inst{31-28} = p;
1415 let OutOperandList = oops;
1416 let InOperandList = !con(iops, (ins pred:$p));
1417 let AsmString = !strconcat(opc, "${p}", asm);
1418 let Pattern = pattern;
1419 let PostEncoderMethod = "VFPThumb2PostEncoder";
1420 let DecoderNamespace = "VFP";
1421 list<Predicate> Predicates = [HasVFP2];
1425 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1426 IndexMode im, Format f, InstrItinClass itin,
1427 string asm, string cstr, list<dag> pattern>
1428 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1430 let Inst{31-28} = p;
1431 let OutOperandList = oops;
1432 let InOperandList = iops;
1433 let AsmString = asm;
1434 let Pattern = pattern;
1435 let PostEncoderMethod = "VFPThumb2PostEncoder";
1436 let DecoderNamespace = "VFP";
1437 list<Predicate> Predicates = [HasVFP2];
1440 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1441 string opc, string asm, list<dag> pattern>
1442 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1443 opc, asm, "", pattern> {
1444 let PostEncoderMethod = "VFPThumb2PostEncoder";
1447 // ARM VFP addrmode5 loads and stores
1448 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1449 InstrItinClass itin,
1450 string opc, string asm, list<dag> pattern>
1451 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1452 VFPLdStFrm, itin, opc, asm, "", pattern> {
1453 // Instruction operands.
1457 // Encode instruction operands.
1458 let Inst{23} = addr{8}; // U (add = (U == '1'))
1459 let Inst{22} = Dd{4};
1460 let Inst{19-16} = addr{12-9}; // Rn
1461 let Inst{15-12} = Dd{3-0};
1462 let Inst{7-0} = addr{7-0}; // imm8
1464 let Inst{27-24} = opcod1;
1465 let Inst{21-20} = opcod2;
1466 let Inst{11-9} = 0b101;
1467 let Inst{8} = 1; // Double precision
1469 // Loads & stores operate on both NEON and VFP pipelines.
1470 let D = VFPNeonDomain;
1473 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1474 InstrItinClass itin,
1475 string opc, string asm, list<dag> pattern>
1476 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1477 VFPLdStFrm, itin, opc, asm, "", pattern> {
1478 // Instruction operands.
1482 // Encode instruction operands.
1483 let Inst{23} = addr{8}; // U (add = (U == '1'))
1484 let Inst{22} = Sd{0};
1485 let Inst{19-16} = addr{12-9}; // Rn
1486 let Inst{15-12} = Sd{4-1};
1487 let Inst{7-0} = addr{7-0}; // imm8
1489 let Inst{27-24} = opcod1;
1490 let Inst{21-20} = opcod2;
1491 let Inst{11-9} = 0b101;
1492 let Inst{8} = 0; // Single precision
1494 // Loads & stores operate on both NEON and VFP pipelines.
1495 let D = VFPNeonDomain;
1498 // VFP Load / store multiple pseudo instructions.
1499 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1501 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1503 let OutOperandList = oops;
1504 let InOperandList = !con(iops, (ins pred:$p));
1505 let Pattern = pattern;
1506 list<Predicate> Predicates = [HasVFP2];
1509 // Load / store multiple
1511 // Unknown precision
1512 class AXXI4<dag oops, dag iops, IndexMode im,
1513 string asm, string cstr, list<dag> pattern>
1514 : VFPXI<oops, iops, AddrMode4, 4, im,
1515 VFPLdStFrm, NoItinerary, asm, cstr, pattern> {
1516 // Instruction operands.
1520 // Encode instruction operands.
1521 let Inst{19-16} = Rn;
1523 let Inst{15-12} = regs{11-8};
1524 let Inst{7-1} = regs{7-1};
1526 let Inst{27-25} = 0b110;
1527 let Inst{11-8} = 0b1011;
1532 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1533 string asm, string cstr, list<dag> pattern>
1534 : VFPXI<oops, iops, AddrMode4, 4, im,
1535 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1536 // Instruction operands.
1540 // Encode instruction operands.
1541 let Inst{19-16} = Rn;
1542 let Inst{22} = regs{12};
1543 let Inst{15-12} = regs{11-8};
1544 let Inst{7-1} = regs{7-1};
1546 let Inst{27-25} = 0b110;
1547 let Inst{11-9} = 0b101;
1548 let Inst{8} = 1; // Double precision
1553 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1554 string asm, string cstr, list<dag> pattern>
1555 : VFPXI<oops, iops, AddrMode4, 4, im,
1556 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1557 // Instruction operands.
1561 // Encode instruction operands.
1562 let Inst{19-16} = Rn;
1563 let Inst{22} = regs{8};
1564 let Inst{15-12} = regs{12-9};
1565 let Inst{7-0} = regs{7-0};
1567 let Inst{27-25} = 0b110;
1568 let Inst{11-9} = 0b101;
1569 let Inst{8} = 0; // Single precision
1572 // Double precision, unary
1573 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1574 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1575 string asm, list<dag> pattern>
1576 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1577 // Instruction operands.
1581 // Encode instruction operands.
1582 let Inst{3-0} = Dm{3-0};
1583 let Inst{5} = Dm{4};
1584 let Inst{15-12} = Dd{3-0};
1585 let Inst{22} = Dd{4};
1587 let Inst{27-23} = opcod1;
1588 let Inst{21-20} = opcod2;
1589 let Inst{19-16} = opcod3;
1590 let Inst{11-9} = 0b101;
1591 let Inst{8} = 1; // Double precision
1592 let Inst{7-6} = opcod4;
1593 let Inst{4} = opcod5;
1595 let Predicates = [HasVFP2, HasDPVFP];
1598 // Double precision, unary, not-predicated
1599 class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1600 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1601 string asm, list<dag> pattern>
1602 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> {
1603 // Instruction operands.
1607 let Inst{31-28} = 0b1111;
1609 // Encode instruction operands.
1610 let Inst{3-0} = Dm{3-0};
1611 let Inst{5} = Dm{4};
1612 let Inst{15-12} = Dd{3-0};
1613 let Inst{22} = Dd{4};
1615 let Inst{27-23} = opcod1;
1616 let Inst{21-20} = opcod2;
1617 let Inst{19-16} = opcod3;
1618 let Inst{11-9} = 0b101;
1619 let Inst{8} = 1; // Double precision
1620 let Inst{7-6} = opcod4;
1621 let Inst{4} = opcod5;
1624 // Double precision, binary
1625 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1626 dag iops, InstrItinClass itin, string opc, string asm,
1628 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1629 // Instruction operands.
1634 // Encode instruction operands.
1635 let Inst{3-0} = Dm{3-0};
1636 let Inst{5} = Dm{4};
1637 let Inst{19-16} = Dn{3-0};
1638 let Inst{7} = Dn{4};
1639 let Inst{15-12} = Dd{3-0};
1640 let Inst{22} = Dd{4};
1642 let Inst{27-23} = opcod1;
1643 let Inst{21-20} = opcod2;
1644 let Inst{11-9} = 0b101;
1645 let Inst{8} = 1; // Double precision
1649 let Predicates = [HasVFP2, HasDPVFP];
1652 // FP, binary, not predicated
1653 class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1654 InstrItinClass itin, string asm, list<dag> pattern>
1655 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin,
1658 // Instruction operands.
1663 let Inst{31-28} = 0b1111;
1665 // Encode instruction operands.
1666 let Inst{3-0} = Dm{3-0};
1667 let Inst{5} = Dm{4};
1668 let Inst{19-16} = Dn{3-0};
1669 let Inst{7} = Dn{4};
1670 let Inst{15-12} = Dd{3-0};
1671 let Inst{22} = Dd{4};
1673 let Inst{27-23} = opcod1;
1674 let Inst{21-20} = opcod2;
1675 let Inst{11-9} = 0b101;
1676 let Inst{8} = 1; // double precision
1677 let Inst{6} = opcod3;
1680 let Predicates = [HasVFP2, HasDPVFP];
1683 // Single precision, unary, predicated
1684 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1685 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1686 string asm, list<dag> pattern>
1687 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1688 // Instruction operands.
1692 // Encode instruction operands.
1693 let Inst{3-0} = Sm{4-1};
1694 let Inst{5} = Sm{0};
1695 let Inst{15-12} = Sd{4-1};
1696 let Inst{22} = Sd{0};
1698 let Inst{27-23} = opcod1;
1699 let Inst{21-20} = opcod2;
1700 let Inst{19-16} = opcod3;
1701 let Inst{11-9} = 0b101;
1702 let Inst{8} = 0; // Single precision
1703 let Inst{7-6} = opcod4;
1704 let Inst{4} = opcod5;
1707 // Single precision, unary, non-predicated
1708 class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1709 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1710 string asm, list<dag> pattern>
1711 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1712 VFPUnaryFrm, itin, asm, "", pattern> {
1713 // Instruction operands.
1717 let Inst{31-28} = 0b1111;
1719 // Encode instruction operands.
1720 let Inst{3-0} = Sm{4-1};
1721 let Inst{5} = Sm{0};
1722 let Inst{15-12} = Sd{4-1};
1723 let Inst{22} = Sd{0};
1725 let Inst{27-23} = opcod1;
1726 let Inst{21-20} = opcod2;
1727 let Inst{19-16} = opcod3;
1728 let Inst{11-9} = 0b101;
1729 let Inst{8} = 0; // Single precision
1730 let Inst{7-6} = opcod4;
1731 let Inst{4} = opcod5;
1734 // Single precision unary, if no NEON. Same as ASuI except not available if
1736 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1737 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1738 string asm, list<dag> pattern>
1739 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1741 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1744 // Single precision, binary
1745 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1746 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1747 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1748 // Instruction operands.
1753 // Encode instruction operands.
1754 let Inst{3-0} = Sm{4-1};
1755 let Inst{5} = Sm{0};
1756 let Inst{19-16} = Sn{4-1};
1757 let Inst{7} = Sn{0};
1758 let Inst{15-12} = Sd{4-1};
1759 let Inst{22} = Sd{0};
1761 let Inst{27-23} = opcod1;
1762 let Inst{21-20} = opcod2;
1763 let Inst{11-9} = 0b101;
1764 let Inst{8} = 0; // Single precision
1769 // Single precision, binary, not predicated
1770 class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1771 InstrItinClass itin, string asm, list<dag> pattern>
1772 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1773 VFPBinaryFrm, itin, asm, "", pattern>
1775 // Instruction operands.
1780 let Inst{31-28} = 0b1111;
1782 // Encode instruction operands.
1783 let Inst{3-0} = Sm{4-1};
1784 let Inst{5} = Sm{0};
1785 let Inst{19-16} = Sn{4-1};
1786 let Inst{7} = Sn{0};
1787 let Inst{15-12} = Sd{4-1};
1788 let Inst{22} = Sd{0};
1790 let Inst{27-23} = opcod1;
1791 let Inst{21-20} = opcod2;
1792 let Inst{11-9} = 0b101;
1793 let Inst{8} = 0; // Single precision
1794 let Inst{6} = opcod3;
1798 // Single precision binary, if no NEON. Same as ASbI except not available if
1800 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1801 dag iops, InstrItinClass itin, string opc, string asm,
1803 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1804 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1806 // Instruction operands.
1811 // Encode instruction operands.
1812 let Inst{3-0} = Sm{4-1};
1813 let Inst{5} = Sm{0};
1814 let Inst{19-16} = Sn{4-1};
1815 let Inst{7} = Sn{0};
1816 let Inst{15-12} = Sd{4-1};
1817 let Inst{22} = Sd{0};
1820 // VFP conversion instructions
1821 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1822 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1824 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1825 let Inst{27-23} = opcod1;
1826 let Inst{21-20} = opcod2;
1827 let Inst{19-16} = opcod3;
1828 let Inst{11-8} = opcod4;
1833 // VFP conversion between floating-point and fixed-point
1834 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1835 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1837 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1839 // size (fixed-point number): sx == 0 ? 16 : 32
1840 let Inst{7} = op5; // sx
1841 let Inst{5} = fbits{0};
1842 let Inst{3-0} = fbits{4-1};
1845 // VFP conversion instructions, if no NEON
1846 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1847 dag oops, dag iops, InstrItinClass itin,
1848 string opc, string asm, list<dag> pattern>
1849 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1851 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1854 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1855 InstrItinClass itin,
1856 string opc, string asm, list<dag> pattern>
1857 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1858 let Inst{27-20} = opcod1;
1859 let Inst{11-8} = opcod2;
1863 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1864 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1865 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1867 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1868 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1869 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1871 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1872 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1873 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1875 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1876 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1877 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1879 //===----------------------------------------------------------------------===//
1881 //===----------------------------------------------------------------------===//
1882 // ARM NEON Instruction templates.
1885 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1886 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1888 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1889 let OutOperandList = oops;
1890 let InOperandList = !con(iops, (ins pred:$p));
1891 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1892 let Pattern = pattern;
1893 list<Predicate> Predicates = [HasNEON];
1894 let DecoderNamespace = "NEON";
1897 // Same as NeonI except it does not have a "data type" specifier.
1898 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1899 InstrItinClass itin, string opc, string asm, string cstr,
1901 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1902 let OutOperandList = oops;
1903 let InOperandList = !con(iops, (ins pred:$p));
1904 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1905 let Pattern = pattern;
1906 list<Predicate> Predicates = [HasNEON];
1907 let DecoderNamespace = "NEON";
1910 // Same as NeonI except it is not predicated
1911 class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1912 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1914 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1915 let OutOperandList = oops;
1916 let InOperandList = iops;
1917 let AsmString = !strconcat(opc, ".", dt, "\t", asm);
1918 let Pattern = pattern;
1919 list<Predicate> Predicates = [HasNEON];
1920 let DecoderNamespace = "NEON";
1922 let Inst{31-28} = 0b1111;
1925 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1926 dag oops, dag iops, InstrItinClass itin,
1927 string opc, string dt, string asm, string cstr, list<dag> pattern>
1928 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1930 let Inst{31-24} = 0b11110100;
1931 let Inst{23} = op23;
1932 let Inst{21-20} = op21_20;
1933 let Inst{11-8} = op11_8;
1934 let Inst{7-4} = op7_4;
1936 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1937 let DecoderNamespace = "NEONLoadStore";
1943 let Inst{22} = Vd{4};
1944 let Inst{15-12} = Vd{3-0};
1945 let Inst{19-16} = Rn{3-0};
1946 let Inst{3-0} = Rm{3-0};
1949 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1950 dag oops, dag iops, InstrItinClass itin,
1951 string opc, string dt, string asm, string cstr, list<dag> pattern>
1952 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1953 dt, asm, cstr, pattern> {
1957 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1958 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1960 let OutOperandList = oops;
1961 let InOperandList = !con(iops, (ins pred:$p));
1962 list<Predicate> Predicates = [HasNEON];
1965 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1967 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1969 let OutOperandList = oops;
1970 let InOperandList = !con(iops, (ins pred:$p));
1971 let Pattern = pattern;
1972 list<Predicate> Predicates = [HasNEON];
1975 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1976 string opc, string dt, string asm, string cstr, list<dag> pattern>
1977 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1979 let Inst{31-25} = 0b1111001;
1980 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1981 let DecoderNamespace = "NEONData";
1984 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1985 string opc, string asm, string cstr, list<dag> pattern>
1986 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1988 let Inst{31-25} = 0b1111001;
1989 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1990 let DecoderNamespace = "NEONData";
1993 // NEON "one register and a modified immediate" format.
1994 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1996 dag oops, dag iops, InstrItinClass itin,
1997 string opc, string dt, string asm, string cstr,
1999 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
2000 let Inst{23} = op23;
2001 let Inst{21-19} = op21_19;
2002 let Inst{11-8} = op11_8;
2008 // Instruction operands.
2012 let Inst{15-12} = Vd{3-0};
2013 let Inst{22} = Vd{4};
2014 let Inst{24} = SIMM{7};
2015 let Inst{18-16} = SIMM{6-4};
2016 let Inst{3-0} = SIMM{3-0};
2017 let DecoderMethod = "DecodeNEONModImmInstruction";
2020 // NEON 2 vector register format.
2021 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2022 bits<5> op11_7, bit op6, bit op4,
2023 dag oops, dag iops, InstrItinClass itin,
2024 string opc, string dt, string asm, string cstr, list<dag> pattern>
2025 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
2026 let Inst{24-23} = op24_23;
2027 let Inst{21-20} = op21_20;
2028 let Inst{19-18} = op19_18;
2029 let Inst{17-16} = op17_16;
2030 let Inst{11-7} = op11_7;
2034 // Instruction operands.
2038 let Inst{15-12} = Vd{3-0};
2039 let Inst{22} = Vd{4};
2040 let Inst{3-0} = Vm{3-0};
2041 let Inst{5} = Vm{4};
2044 // Same as N2V but not predicated.
2045 class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
2046 dag oops, dag iops, InstrItinClass itin, string OpcodeStr,
2047 string Dt, list<dag> pattern>
2048 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin,
2049 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
2053 // Encode instruction operands
2054 let Inst{22} = Vd{4};
2055 let Inst{15-12} = Vd{3-0};
2056 let Inst{5} = Vm{4};
2057 let Inst{3-0} = Vm{3-0};
2059 // Encode constant bits
2060 let Inst{27-23} = 0b00111;
2061 let Inst{21-20} = 0b11;
2062 let Inst{19-18} = op19_18;
2063 let Inst{17-16} = op17_16;
2065 let Inst{10-8} = op10_8;
2070 let DecoderNamespace = "NEON";
2073 // Same as N2V except it doesn't have a datatype suffix.
2074 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2075 bits<5> op11_7, bit op6, bit op4,
2076 dag oops, dag iops, InstrItinClass itin,
2077 string opc, string asm, string cstr, list<dag> pattern>
2078 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
2079 let Inst{24-23} = op24_23;
2080 let Inst{21-20} = op21_20;
2081 let Inst{19-18} = op19_18;
2082 let Inst{17-16} = op17_16;
2083 let Inst{11-7} = op11_7;
2087 // Instruction operands.
2091 let Inst{15-12} = Vd{3-0};
2092 let Inst{22} = Vd{4};
2093 let Inst{3-0} = Vm{3-0};
2094 let Inst{5} = Vm{4};
2097 // NEON 2 vector register with immediate.
2098 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2099 dag oops, dag iops, Format f, InstrItinClass itin,
2100 string opc, string dt, string asm, string cstr, list<dag> pattern>
2101 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2102 let Inst{24} = op24;
2103 let Inst{23} = op23;
2104 let Inst{11-8} = op11_8;
2109 // Instruction operands.
2114 let Inst{15-12} = Vd{3-0};
2115 let Inst{22} = Vd{4};
2116 let Inst{3-0} = Vm{3-0};
2117 let Inst{5} = Vm{4};
2118 let Inst{21-16} = SIMM{5-0};
2121 // NEON 3 vector register format.
2123 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2124 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2125 string opc, string dt, string asm, string cstr,
2127 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2128 let Inst{24} = op24;
2129 let Inst{23} = op23;
2130 let Inst{21-20} = op21_20;
2131 let Inst{11-8} = op11_8;
2136 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
2137 dag oops, dag iops, Format f, InstrItinClass itin,
2138 string opc, string dt, string asm, string cstr, list<dag> pattern>
2139 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2140 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2141 // Instruction operands.
2146 let Inst{15-12} = Vd{3-0};
2147 let Inst{22} = Vd{4};
2148 let Inst{19-16} = Vn{3-0};
2149 let Inst{7} = Vn{4};
2150 let Inst{3-0} = Vm{3-0};
2151 let Inst{5} = Vm{4};
2154 class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2155 bit op4, dag oops, dag iops,Format f, InstrItinClass itin,
2156 string OpcodeStr, string Dt, list<dag> pattern>
2157 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr,
2158 Dt, "$Vd, $Vn, $Vm", "", pattern> {
2163 // Encode instruction operands
2164 let Inst{22} = Vd{4};
2165 let Inst{15-12} = Vd{3-0};
2166 let Inst{19-16} = Vn{3-0};
2167 let Inst{7} = Vn{4};
2168 let Inst{5} = Vm{4};
2169 let Inst{3-0} = Vm{3-0};
2171 // Encode constant bits
2172 let Inst{27-23} = op27_23;
2173 let Inst{21-20} = op21_20;
2174 let Inst{11-8} = op11_8;
2179 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2180 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2181 string opc, string dt, string asm, string cstr,
2183 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2184 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2186 // Instruction operands.
2192 let Inst{15-12} = Vd{3-0};
2193 let Inst{22} = Vd{4};
2194 let Inst{19-16} = Vn{3-0};
2195 let Inst{7} = Vn{4};
2196 let Inst{3-0} = Vm{3-0};
2200 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2201 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2202 string opc, string dt, string asm, string cstr,
2204 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2205 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2207 // Instruction operands.
2213 let Inst{15-12} = Vd{3-0};
2214 let Inst{22} = Vd{4};
2215 let Inst{19-16} = Vn{3-0};
2216 let Inst{7} = Vn{4};
2217 let Inst{2-0} = Vm{2-0};
2218 let Inst{5} = lane{1};
2219 let Inst{3} = lane{0};
2222 // Same as N3V except it doesn't have a data type suffix.
2223 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2225 dag oops, dag iops, Format f, InstrItinClass itin,
2226 string opc, string asm, string cstr, list<dag> pattern>
2227 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
2228 let Inst{24} = op24;
2229 let Inst{23} = op23;
2230 let Inst{21-20} = op21_20;
2231 let Inst{11-8} = op11_8;
2235 // Instruction operands.
2240 let Inst{15-12} = Vd{3-0};
2241 let Inst{22} = Vd{4};
2242 let Inst{19-16} = Vn{3-0};
2243 let Inst{7} = Vn{4};
2244 let Inst{3-0} = Vm{3-0};
2245 let Inst{5} = Vm{4};
2248 // NEON VMOVs between scalar and core registers.
2249 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2250 dag oops, dag iops, Format f, InstrItinClass itin,
2251 string opc, string dt, string asm, list<dag> pattern>
2252 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
2254 let Inst{27-20} = opcod1;
2255 let Inst{11-8} = opcod2;
2256 let Inst{6-5} = opcod3;
2258 // A8.6.303, A8.6.328, A8.6.329
2259 let Inst{3-0} = 0b0000;
2261 let OutOperandList = oops;
2262 let InOperandList = !con(iops, (ins pred:$p));
2263 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
2264 let Pattern = pattern;
2265 list<Predicate> Predicates = [HasNEON];
2267 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
2268 let DecoderNamespace = "NEONDup";
2275 let Inst{31-28} = p{3-0};
2277 let Inst{19-16} = V{3-0};
2278 let Inst{15-12} = R{3-0};
2280 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2281 dag oops, dag iops, InstrItinClass itin,
2282 string opc, string dt, string asm, list<dag> pattern>
2283 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
2284 opc, dt, asm, pattern>;
2285 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2286 dag oops, dag iops, InstrItinClass itin,
2287 string opc, string dt, string asm, list<dag> pattern>
2288 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
2289 opc, dt, asm, pattern>;
2290 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2291 dag oops, dag iops, InstrItinClass itin,
2292 string opc, string dt, string asm, list<dag> pattern>
2293 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
2294 opc, dt, asm, pattern>;
2296 // Vector Duplicate Lane (from scalar to all elements)
2297 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2298 InstrItinClass itin, string opc, string dt, string asm,
2300 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2301 let Inst{24-23} = 0b11;
2302 let Inst{21-20} = 0b11;
2303 let Inst{19-16} = op19_16;
2304 let Inst{11-7} = 0b11000;
2311 let Inst{22} = Vd{4};
2312 let Inst{15-12} = Vd{3-0};
2313 let Inst{5} = Vm{4};
2314 let Inst{3-0} = Vm{3-0};
2317 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2318 // for single-precision FP.
2319 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2320 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2323 // VFP/NEON Instruction aliases for type suffices.
2324 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
2325 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
2327 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
2328 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2329 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2330 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2331 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2334 multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> {
2335 let Predicates = [HasNEON] in {
2336 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2337 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2338 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2339 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2343 // The same alias classes using AsmPseudo instead, for the more complex
2344 // stuff in NEON that InstAlias can't quite handle.
2345 // Note that we can't use anonymous defm references here like we can
2346 // above, as we care about the ultimate instruction enum names generated, unlike
2347 // for instalias defs.
2348 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2349 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2351 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2352 def : TokenAlias<".s8", ".i8">;
2353 def : TokenAlias<".u8", ".i8">;
2354 def : TokenAlias<".s16", ".i16">;
2355 def : TokenAlias<".u16", ".i16">;
2356 def : TokenAlias<".s32", ".i32">;
2357 def : TokenAlias<".u32", ".i32">;
2358 def : TokenAlias<".s64", ".i64">;
2359 def : TokenAlias<".u64", ".i64">;
2361 def : TokenAlias<".i8", ".8">;
2362 def : TokenAlias<".i16", ".16">;
2363 def : TokenAlias<".i32", ".32">;
2364 def : TokenAlias<".i64", ".64">;
2366 def : TokenAlias<".p8", ".8">;
2367 def : TokenAlias<".p16", ".16">;
2369 def : TokenAlias<".f32", ".32">;
2370 def : TokenAlias<".f64", ".64">;
2371 def : TokenAlias<".f", ".f32">;
2372 def : TokenAlias<".d", ".f64">;