1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def ExtFrm : Format<13>;
41 def VFPUnaryFrm : Format<14>;
42 def VFPBinaryFrm : Format<15>;
43 def VFPConv1Frm : Format<16>;
44 def VFPConv2Frm : Format<17>;
45 def VFPConv3Frm : Format<18>;
46 def VFPConv4Frm : Format<19>;
47 def VFPConv5Frm : Format<20>;
48 def VFPLdStFrm : Format<21>;
49 def VFPLdStMulFrm : Format<22>;
50 def VFPMiscFrm : Format<23>;
52 def ThumbFrm : Format<24>;
54 def NEONFrm : Format<25>;
55 def NEONGetLnFrm : Format<26>;
56 def NEONSetLnFrm : Format<27>;
57 def NEONDupFrm : Format<28>;
59 def MiscFrm : Format<29>;
60 def ThumbMiscFrm : Format<30>;
64 // the instruction has a Rn register operand.
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
67 class UnaryDP { bit isUnaryDataProc = 1; }
69 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
70 // a 16-bit Thumb instruction if certain conditions are met.
71 class Xform16Bit { bit canXformTo16Bit = 1; }
73 //===----------------------------------------------------------------------===//
74 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
78 class AddrMode<bits<4> val> {
81 def AddrModeNone : AddrMode<0>;
82 def AddrMode1 : AddrMode<1>;
83 def AddrMode2 : AddrMode<2>;
84 def AddrMode3 : AddrMode<3>;
85 def AddrMode4 : AddrMode<4>;
86 def AddrMode5 : AddrMode<5>;
87 def AddrMode6 : AddrMode<6>;
88 def AddrModeT1_1 : AddrMode<7>;
89 def AddrModeT1_2 : AddrMode<8>;
90 def AddrModeT1_4 : AddrMode<9>;
91 def AddrModeT1_s : AddrMode<10>;
92 def AddrModeT2_i12: AddrMode<11>;
93 def AddrModeT2_i8 : AddrMode<12>;
94 def AddrModeT2_so : AddrMode<13>;
95 def AddrModeT2_pc : AddrMode<14>;
96 def AddrModeT2_i8s4 : AddrMode<15>;
99 class SizeFlagVal<bits<3> val> {
102 def SizeInvalid : SizeFlagVal<0>; // Unset.
103 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
104 def Size8Bytes : SizeFlagVal<2>;
105 def Size4Bytes : SizeFlagVal<3>;
106 def Size2Bytes : SizeFlagVal<4>;
108 // Load / store index mode.
109 class IndexMode<bits<2> val> {
112 def IndexModeNone : IndexMode<0>;
113 def IndexModePre : IndexMode<1>;
114 def IndexModePost : IndexMode<2>;
115 def IndexModeUpd : IndexMode<3>;
117 // Instruction execution domain.
118 class Domain<bits<2> val> {
121 def GenericDomain : Domain<0>;
122 def VFPDomain : Domain<1>; // Instructions in VFP domain only
123 def NeonDomain : Domain<2>; // Instructions in Neon domain only
124 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
126 //===----------------------------------------------------------------------===//
128 // ARM special operands.
131 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
132 // register whose default is 0 (no register).
133 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
134 (ops (i32 14), (i32 zero_reg))> {
135 let PrintMethod = "printPredicateOperand";
138 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
139 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
140 let PrintMethod = "printSBitModifierOperand";
143 // Same as cc_out except it defaults to setting CPSR.
144 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
145 let PrintMethod = "printSBitModifierOperand";
148 // ARM special operands for disassembly only.
151 def cps_opt : Operand<i32> {
152 let PrintMethod = "printCPSOptionOperand";
155 def msr_mask : Operand<i32> {
156 let PrintMethod = "printMSRMaskOperand";
159 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
160 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
161 def neg_zero : Operand<i32> {
162 let PrintMethod = "printNegZeroOperand";
165 //===----------------------------------------------------------------------===//
167 // ARM Instruction templates.
170 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
171 Format f, Domain d, string cstr, InstrItinClass itin>
173 let Namespace = "ARM";
177 bits<4> AddrModeBits = AM.Value;
180 bits<3> SizeFlag = SZ.Value;
183 bits<2> IndexModeBits = IM.Value;
186 bits<6> Form = F.Value;
189 bits<2> Dom = D.Value;
192 // Attributes specific to ARM instructions...
194 bit isUnaryDataProc = 0;
195 bit canXformTo16Bit = 0;
197 let Constraints = cstr;
198 let Itinerary = itin;
205 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
206 Format f, Domain d, string cstr, InstrItinClass itin>
207 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
209 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
210 // on by adding flavors to specific instructions.
211 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
212 Format f, Domain d, string cstr, InstrItinClass itin>
213 : InstTemplate<am, sz, im, f, d, cstr, itin>;
215 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
216 string asm, list<dag> pattern>
217 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
219 let OutOperandList = oops;
220 let InOperandList = iops;
222 let Pattern = pattern;
225 // Almost all ARM instructions are predicable.
226 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
227 IndexMode im, Format f, InstrItinClass itin,
228 string opc, string asm, string cstr,
230 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
231 let OutOperandList = oops;
232 let InOperandList = !con(iops, (ins pred:$p));
233 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
234 let Pattern = pattern;
235 list<Predicate> Predicates = [IsARM];
237 // A few are not predicable
238 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
239 IndexMode im, Format f, InstrItinClass itin,
240 string opc, string asm, string cstr,
242 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
243 let OutOperandList = oops;
244 let InOperandList = iops;
245 let AsmString = !strconcat(opc, asm);
246 let Pattern = pattern;
247 let isPredicable = 0;
248 list<Predicate> Predicates = [IsARM];
251 // Same as I except it can optionally modify CPSR. Note it's modeled as
252 // an input operand since by default it's a zero register. It will
253 // become an implicit def once it's "flipped".
254 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
255 IndexMode im, Format f, InstrItinClass itin,
256 string opc, string asm, string cstr,
258 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
259 let OutOperandList = oops;
260 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
261 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
262 let Pattern = pattern;
263 list<Predicate> Predicates = [IsARM];
267 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
268 IndexMode im, Format f, InstrItinClass itin,
269 string asm, string cstr, list<dag> pattern>
270 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
271 let OutOperandList = oops;
272 let InOperandList = iops;
274 let Pattern = pattern;
275 list<Predicate> Predicates = [IsARM];
278 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
279 string opc, string asm, list<dag> pattern>
280 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
281 opc, asm, "", pattern>;
282 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
283 string opc, string asm, list<dag> pattern>
284 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
285 opc, asm, "", pattern>;
286 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
287 string asm, list<dag> pattern>
288 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
290 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
291 string opc, string asm, list<dag> pattern>
292 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
293 opc, asm, "", pattern>;
295 // Ctrl flow instructions
296 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
297 string opc, string asm, list<dag> pattern>
298 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
299 opc, asm, "", pattern> {
300 let Inst{27-24} = opcod;
302 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
303 string asm, list<dag> pattern>
304 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
306 let Inst{27-24} = opcod;
308 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
309 string asm, list<dag> pattern>
310 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
313 // BR_JT instructions
314 class JTI<dag oops, dag iops, InstrItinClass itin,
315 string asm, list<dag> pattern>
316 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
320 // Atomic load/store instructions
322 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
323 string opc, string asm, list<dag> pattern>
324 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
325 opc, asm, "", pattern> {
326 let Inst{27-23} = 0b00011;
327 let Inst{22-21} = opcod;
329 let Inst{11-0} = 0b111110011111;
331 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
332 string opc, string asm, list<dag> pattern>
333 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
334 opc, asm, "", pattern> {
335 let Inst{27-23} = 0b00011;
336 let Inst{22-21} = opcod;
338 let Inst{11-4} = 0b11111001;
341 // addrmode1 instructions
342 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
343 string opc, string asm, list<dag> pattern>
344 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
345 opc, asm, "", pattern> {
346 let Inst{24-21} = opcod;
347 let Inst{27-26} = {0,0};
349 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
352 opc, asm, "", pattern> {
353 let Inst{24-21} = opcod;
354 let Inst{27-26} = {0,0};
356 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
357 string asm, list<dag> pattern>
358 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
360 let Inst{24-21} = opcod;
361 let Inst{27-26} = {0,0};
363 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
364 string opc, string asm, list<dag> pattern>
365 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
366 opc, asm, "", pattern>;
369 // addrmode2 loads and stores
370 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
371 string opc, string asm, list<dag> pattern>
372 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
373 opc, asm, "", pattern> {
374 let Inst{27-26} = {0,1};
378 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
379 string opc, string asm, list<dag> pattern>
380 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
381 opc, asm, "", pattern> {
382 let Inst{20} = 1; // L bit
383 let Inst{21} = 0; // W bit
384 let Inst{22} = 0; // B bit
385 let Inst{24} = 1; // P bit
386 let Inst{27-26} = {0,1};
388 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
389 string asm, list<dag> pattern>
390 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
392 let Inst{20} = 1; // L bit
393 let Inst{21} = 0; // W bit
394 let Inst{22} = 0; // B bit
395 let Inst{24} = 1; // P bit
396 let Inst{27-26} = {0,1};
398 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
401 opc, asm, "", pattern> {
402 let Inst{20} = 1; // L bit
403 let Inst{21} = 0; // W bit
404 let Inst{22} = 1; // B bit
405 let Inst{24} = 1; // P bit
406 let Inst{27-26} = {0,1};
408 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
409 string asm, list<dag> pattern>
410 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
412 let Inst{20} = 1; // L bit
413 let Inst{21} = 0; // W bit
414 let Inst{22} = 1; // B bit
415 let Inst{24} = 1; // P bit
416 let Inst{27-26} = {0,1};
420 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
421 string opc, string asm, list<dag> pattern>
422 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
423 opc, asm, "", pattern> {
424 let Inst{20} = 0; // L bit
425 let Inst{21} = 0; // W bit
426 let Inst{22} = 0; // B bit
427 let Inst{24} = 1; // P bit
428 let Inst{27-26} = {0,1};
430 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
431 string asm, list<dag> pattern>
432 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
434 let Inst{20} = 0; // L bit
435 let Inst{21} = 0; // W bit
436 let Inst{22} = 0; // B bit
437 let Inst{24} = 1; // P bit
438 let Inst{27-26} = {0,1};
440 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
441 string opc, string asm, list<dag> pattern>
442 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
443 opc, asm, "", pattern> {
444 let Inst{20} = 0; // L bit
445 let Inst{21} = 0; // W bit
446 let Inst{22} = 1; // B bit
447 let Inst{24} = 1; // P bit
448 let Inst{27-26} = {0,1};
450 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
451 string asm, list<dag> pattern>
452 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
454 let Inst{20} = 0; // L bit
455 let Inst{21} = 0; // W bit
456 let Inst{22} = 1; // B bit
457 let Inst{24} = 1; // P bit
458 let Inst{27-26} = {0,1};
462 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
463 string opc, string asm, string cstr, list<dag> pattern>
464 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
465 opc, asm, cstr, pattern> {
466 let Inst{20} = 1; // L bit
467 let Inst{21} = 1; // W bit
468 let Inst{22} = 0; // B bit
469 let Inst{24} = 1; // P bit
470 let Inst{27-26} = {0,1};
472 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
473 string opc, string asm, string cstr, list<dag> pattern>
474 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
475 opc, asm, cstr, pattern> {
476 let Inst{20} = 1; // L bit
477 let Inst{21} = 1; // W bit
478 let Inst{22} = 1; // B bit
479 let Inst{24} = 1; // P bit
480 let Inst{27-26} = {0,1};
483 // Pre-indexed stores
484 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
485 string opc, string asm, string cstr, list<dag> pattern>
486 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
487 opc, asm, cstr, pattern> {
488 let Inst{20} = 0; // L bit
489 let Inst{21} = 1; // W bit
490 let Inst{22} = 0; // B bit
491 let Inst{24} = 1; // P bit
492 let Inst{27-26} = {0,1};
494 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
495 string opc, string asm, string cstr, list<dag> pattern>
496 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
497 opc, asm, cstr, pattern> {
498 let Inst{20} = 0; // L bit
499 let Inst{21} = 1; // W bit
500 let Inst{22} = 1; // B bit
501 let Inst{24} = 1; // P bit
502 let Inst{27-26} = {0,1};
505 // Post-indexed loads
506 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
507 string opc, string asm, string cstr, list<dag> pattern>
508 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
509 opc, asm, cstr,pattern> {
510 let Inst{20} = 1; // L bit
511 let Inst{21} = 0; // W bit
512 let Inst{22} = 0; // B bit
513 let Inst{24} = 0; // P bit
514 let Inst{27-26} = {0,1};
516 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
517 string opc, string asm, string cstr, list<dag> pattern>
518 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
519 opc, asm, cstr,pattern> {
520 let Inst{20} = 1; // L bit
521 let Inst{21} = 0; // W bit
522 let Inst{22} = 1; // B bit
523 let Inst{24} = 0; // P bit
524 let Inst{27-26} = {0,1};
527 // Post-indexed stores
528 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
529 string opc, string asm, string cstr, list<dag> pattern>
530 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
531 opc, asm, cstr,pattern> {
532 let Inst{20} = 0; // L bit
533 let Inst{21} = 0; // W bit
534 let Inst{22} = 0; // B bit
535 let Inst{24} = 0; // P bit
536 let Inst{27-26} = {0,1};
538 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
539 string opc, string asm, string cstr, list<dag> pattern>
540 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
541 opc, asm, cstr,pattern> {
542 let Inst{20} = 0; // L bit
543 let Inst{21} = 0; // W bit
544 let Inst{22} = 1; // B bit
545 let Inst{24} = 0; // P bit
546 let Inst{27-26} = {0,1};
549 // addrmode3 instructions
550 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
551 string opc, string asm, list<dag> pattern>
552 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
553 opc, asm, "", pattern>;
554 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
555 string asm, list<dag> pattern>
556 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
560 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
561 string opc, string asm, list<dag> pattern>
562 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
563 opc, asm, "", pattern> {
565 let Inst{5} = 1; // H bit
566 let Inst{6} = 0; // S bit
568 let Inst{20} = 1; // L bit
569 let Inst{21} = 0; // W bit
570 let Inst{24} = 1; // P bit
571 let Inst{27-25} = 0b000;
573 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
574 string asm, list<dag> pattern>
575 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
578 let Inst{5} = 1; // H bit
579 let Inst{6} = 0; // S bit
581 let Inst{20} = 1; // L bit
582 let Inst{21} = 0; // W bit
583 let Inst{24} = 1; // P bit
585 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
586 string opc, string asm, list<dag> pattern>
587 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
588 opc, asm, "", pattern> {
590 let Inst{5} = 1; // H bit
591 let Inst{6} = 1; // S bit
593 let Inst{20} = 1; // L bit
594 let Inst{21} = 0; // W bit
595 let Inst{24} = 1; // P bit
596 let Inst{27-25} = 0b000;
598 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
599 string asm, list<dag> pattern>
600 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
603 let Inst{5} = 1; // H bit
604 let Inst{6} = 1; // S bit
606 let Inst{20} = 1; // L bit
607 let Inst{21} = 0; // W bit
608 let Inst{24} = 1; // P bit
610 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
611 string opc, string asm, list<dag> pattern>
612 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
613 opc, asm, "", pattern> {
615 let Inst{5} = 0; // H bit
616 let Inst{6} = 1; // S bit
618 let Inst{20} = 1; // L bit
619 let Inst{21} = 0; // W bit
620 let Inst{24} = 1; // P bit
621 let Inst{27-25} = 0b000;
623 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
624 string asm, list<dag> pattern>
625 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
628 let Inst{5} = 0; // H bit
629 let Inst{6} = 1; // S bit
631 let Inst{20} = 1; // L bit
632 let Inst{21} = 0; // W bit
633 let Inst{24} = 1; // P bit
635 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
636 string opc, string asm, list<dag> pattern>
637 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
638 opc, asm, "", pattern> {
640 let Inst{5} = 0; // H bit
641 let Inst{6} = 1; // S bit
643 let Inst{20} = 0; // L bit
644 let Inst{21} = 0; // W bit
645 let Inst{24} = 1; // P bit
646 let Inst{27-25} = 0b000;
650 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
651 string opc, string asm, list<dag> pattern>
652 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
653 opc, asm, "", pattern> {
655 let Inst{5} = 1; // H bit
656 let Inst{6} = 0; // S bit
658 let Inst{20} = 0; // L bit
659 let Inst{21} = 0; // W bit
660 let Inst{24} = 1; // P bit
661 let Inst{27-25} = 0b000;
663 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
664 string asm, list<dag> pattern>
665 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
668 let Inst{5} = 1; // H bit
669 let Inst{6} = 0; // S bit
671 let Inst{20} = 0; // L bit
672 let Inst{21} = 0; // W bit
673 let Inst{24} = 1; // P bit
675 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
676 string opc, string asm, list<dag> pattern>
677 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
678 opc, asm, "", pattern> {
680 let Inst{5} = 1; // H bit
681 let Inst{6} = 1; // S bit
683 let Inst{20} = 0; // L bit
684 let Inst{21} = 0; // W bit
685 let Inst{24} = 1; // P bit
686 let Inst{27-25} = 0b000;
690 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
691 string opc, string asm, string cstr, list<dag> pattern>
692 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
693 opc, asm, cstr, pattern> {
695 let Inst{5} = 1; // H bit
696 let Inst{6} = 0; // S bit
698 let Inst{20} = 1; // L bit
699 let Inst{21} = 1; // W bit
700 let Inst{24} = 1; // P bit
701 let Inst{27-25} = 0b000;
703 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
704 string opc, string asm, string cstr, list<dag> pattern>
705 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
706 opc, asm, cstr, pattern> {
708 let Inst{5} = 1; // H bit
709 let Inst{6} = 1; // S bit
711 let Inst{20} = 1; // L bit
712 let Inst{21} = 1; // W bit
713 let Inst{24} = 1; // P bit
714 let Inst{27-25} = 0b000;
716 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
717 string opc, string asm, string cstr, list<dag> pattern>
718 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
719 opc, asm, cstr, pattern> {
721 let Inst{5} = 0; // H bit
722 let Inst{6} = 1; // S bit
724 let Inst{20} = 1; // L bit
725 let Inst{21} = 1; // W bit
726 let Inst{24} = 1; // P bit
727 let Inst{27-25} = 0b000;
729 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
730 string opc, string asm, string cstr, list<dag> pattern>
731 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
732 opc, asm, cstr, pattern> {
734 let Inst{5} = 0; // H bit
735 let Inst{6} = 1; // S bit
737 let Inst{20} = 0; // L bit
738 let Inst{21} = 1; // W bit
739 let Inst{24} = 1; // P bit
740 let Inst{27-25} = 0b000;
744 // Pre-indexed stores
745 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
746 string opc, string asm, string cstr, list<dag> pattern>
747 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
748 opc, asm, cstr, pattern> {
750 let Inst{5} = 1; // H bit
751 let Inst{6} = 0; // S bit
753 let Inst{20} = 0; // L bit
754 let Inst{21} = 1; // W bit
755 let Inst{24} = 1; // P bit
756 let Inst{27-25} = 0b000;
758 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
759 string opc, string asm, string cstr, list<dag> pattern>
760 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
761 opc, asm, cstr, pattern> {
763 let Inst{5} = 1; // H bit
764 let Inst{6} = 1; // S bit
766 let Inst{20} = 0; // L bit
767 let Inst{21} = 1; // W bit
768 let Inst{24} = 1; // P bit
769 let Inst{27-25} = 0b000;
772 // Post-indexed loads
773 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
774 string opc, string asm, string cstr, list<dag> pattern>
775 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
776 opc, asm, cstr,pattern> {
778 let Inst{5} = 1; // H bit
779 let Inst{6} = 0; // S bit
781 let Inst{20} = 1; // L bit
782 let Inst{21} = 0; // W bit
783 let Inst{24} = 0; // P bit
784 let Inst{27-25} = 0b000;
786 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
787 string opc, string asm, string cstr, list<dag> pattern>
788 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
789 opc, asm, cstr,pattern> {
791 let Inst{5} = 1; // H bit
792 let Inst{6} = 1; // S bit
794 let Inst{20} = 1; // L bit
795 let Inst{21} = 0; // W bit
796 let Inst{24} = 0; // P bit
797 let Inst{27-25} = 0b000;
799 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
800 string opc, string asm, string cstr, list<dag> pattern>
801 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
802 opc, asm, cstr,pattern> {
804 let Inst{5} = 0; // H bit
805 let Inst{6} = 1; // S bit
807 let Inst{20} = 1; // L bit
808 let Inst{21} = 0; // W bit
809 let Inst{24} = 0; // P bit
810 let Inst{27-25} = 0b000;
812 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
813 string opc, string asm, string cstr, list<dag> pattern>
814 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
815 opc, asm, cstr, pattern> {
817 let Inst{5} = 0; // H bit
818 let Inst{6} = 1; // S bit
820 let Inst{20} = 0; // L bit
821 let Inst{21} = 0; // W bit
822 let Inst{24} = 0; // P bit
823 let Inst{27-25} = 0b000;
826 // Post-indexed stores
827 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
828 string opc, string asm, string cstr, list<dag> pattern>
829 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
830 opc, asm, cstr,pattern> {
832 let Inst{5} = 1; // H bit
833 let Inst{6} = 0; // S bit
835 let Inst{20} = 0; // L bit
836 let Inst{21} = 0; // W bit
837 let Inst{24} = 0; // P bit
838 let Inst{27-25} = 0b000;
840 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
841 string opc, string asm, string cstr, list<dag> pattern>
842 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
843 opc, asm, cstr, pattern> {
845 let Inst{5} = 1; // H bit
846 let Inst{6} = 1; // S bit
848 let Inst{20} = 0; // L bit
849 let Inst{21} = 0; // W bit
850 let Inst{24} = 0; // P bit
851 let Inst{27-25} = 0b000;
855 // addrmode4 instructions
856 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
857 string asm, string cstr, list<dag> pattern>
858 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
859 asm, cstr, pattern> {
860 let Inst{20} = 1; // L bit
861 let Inst{22} = 0; // S bit
862 let Inst{27-25} = 0b100;
864 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
865 string asm, string cstr, list<dag> pattern>
866 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
867 asm, cstr, pattern> {
868 let Inst{20} = 0; // L bit
869 let Inst{22} = 0; // S bit
870 let Inst{27-25} = 0b100;
873 // Unsigned multiply, multiply-accumulate instructions.
874 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
875 string opc, string asm, list<dag> pattern>
876 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
877 opc, asm, "", pattern> {
878 let Inst{7-4} = 0b1001;
879 let Inst{20} = 0; // S bit
880 let Inst{27-21} = opcod;
882 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
883 string opc, string asm, list<dag> pattern>
884 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
885 opc, asm, "", pattern> {
886 let Inst{7-4} = 0b1001;
887 let Inst{27-21} = opcod;
890 // Most significant word multiply
891 class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
892 string opc, string asm, list<dag> pattern>
893 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
894 opc, asm, "", pattern> {
895 let Inst{7-4} = 0b1001;
897 let Inst{27-21} = opcod;
900 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
901 class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
902 string opc, string asm, list<dag> pattern>
903 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
904 opc, asm, "", pattern> {
908 let Inst{27-21} = opcod;
911 // Extend instructions.
912 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
913 string opc, string asm, list<dag> pattern>
914 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
915 opc, asm, "", pattern> {
916 let Inst{7-4} = 0b0111;
917 let Inst{27-20} = opcod;
920 // Misc Arithmetic instructions.
921 class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
922 string opc, string asm, list<dag> pattern>
923 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
924 opc, asm, "", pattern> {
925 let Inst{27-20} = opcod;
928 //===----------------------------------------------------------------------===//
930 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
931 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
932 list<Predicate> Predicates = [IsARM];
934 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
935 list<Predicate> Predicates = [IsARM, HasV5TE];
937 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
938 list<Predicate> Predicates = [IsARM, HasV6];
940 class VFPPat<dag pattern, dag result> : Pat<pattern, result> {
941 list<Predicate> Predicates = [HasVFP2];
944 //===----------------------------------------------------------------------===//
946 // Thumb Instruction Format Definitions.
949 // TI - Thumb instruction.
951 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
952 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
953 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
954 let OutOperandList = oops;
955 let InOperandList = iops;
957 let Pattern = pattern;
958 list<Predicate> Predicates = [IsThumb];
961 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
962 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
964 // Two-address instructions
965 class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
966 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
968 // tBL, tBX 32-bit instructions
969 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
970 dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
971 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
972 let Inst{31-27} = opcod1;
973 let Inst{15-14} = opcod2;
974 let Inst{12} = opcod3;
977 // BR_JT instructions
978 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
979 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
982 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
983 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
984 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
985 let OutOperandList = oops;
986 let InOperandList = iops;
988 let Pattern = pattern;
989 list<Predicate> Predicates = [IsThumb1Only];
992 class T1I<dag oops, dag iops, InstrItinClass itin,
993 string asm, list<dag> pattern>
994 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
995 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
996 string asm, list<dag> pattern>
997 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
998 class T1JTI<dag oops, dag iops, InstrItinClass itin,
999 string asm, list<dag> pattern>
1000 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1002 // Two-address instructions
1003 class T1It<dag oops, dag iops, InstrItinClass itin,
1004 string asm, string cstr, list<dag> pattern>
1005 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1006 asm, cstr, pattern>;
1008 // Thumb1 instruction that can either be predicated or set CPSR.
1009 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1010 InstrItinClass itin,
1011 string opc, string asm, string cstr, list<dag> pattern>
1012 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1013 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1014 let InOperandList = !con(iops, (ins pred:$p));
1015 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1016 let Pattern = pattern;
1017 list<Predicate> Predicates = [IsThumb1Only];
1020 class T1sI<dag oops, dag iops, InstrItinClass itin,
1021 string opc, string asm, list<dag> pattern>
1022 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1024 // Two-address instructions
1025 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1026 string opc, string asm, list<dag> pattern>
1027 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1028 "$lhs = $dst", pattern>;
1030 // Thumb1 instruction that can be predicated.
1031 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1032 InstrItinClass itin,
1033 string opc, string asm, string cstr, list<dag> pattern>
1034 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1035 let OutOperandList = oops;
1036 let InOperandList = !con(iops, (ins pred:$p));
1037 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1038 let Pattern = pattern;
1039 list<Predicate> Predicates = [IsThumb1Only];
1042 class T1pI<dag oops, dag iops, InstrItinClass itin,
1043 string opc, string asm, list<dag> pattern>
1044 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1046 // Two-address instructions
1047 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1048 string opc, string asm, list<dag> pattern>
1049 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1050 "$lhs = $dst", pattern>;
1052 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1053 string opc, string asm, list<dag> pattern>
1054 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1055 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1056 string opc, string asm, list<dag> pattern>
1057 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1058 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1059 string opc, string asm, list<dag> pattern>
1060 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1061 class T1pIs<dag oops, dag iops,
1062 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1063 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1065 class Encoding16 : Encoding {
1066 let Inst{31-16} = 0x0000;
1069 // A6.2 16-bit Thumb instruction encoding
1070 class T1Encoding<bits<6> opcode> : Encoding16 {
1071 let Inst{15-10} = opcode;
1074 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1075 class T1General<bits<5> opcode> : Encoding16 {
1076 let Inst{15-14} = 0b00;
1077 let Inst{13-9} = opcode;
1080 // A6.2.2 Data-processing encoding.
1081 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1082 let Inst{15-10} = 0b010000;
1083 let Inst{9-6} = opcode;
1086 // A6.2.3 Special data instructions and branch and exchange encoding.
1087 class T1Special<bits<4> opcode> : Encoding16 {
1088 let Inst{15-10} = 0b010001;
1089 let Inst{9-6} = opcode;
1092 // A6.2.4 Load/store single data item encoding.
1093 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1094 let Inst{15-12} = opA;
1095 let Inst{11-9} = opB;
1097 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1098 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1099 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1100 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1101 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1103 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1104 class T1Misc<bits<7> opcode> : Encoding16 {
1105 let Inst{15-12} = 0b1011;
1106 let Inst{11-5} = opcode;
1109 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1110 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1111 InstrItinClass itin,
1112 string opc, string asm, string cstr, list<dag> pattern>
1113 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1114 let OutOperandList = oops;
1115 let InOperandList = !con(iops, (ins pred:$p));
1116 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1117 let Pattern = pattern;
1118 list<Predicate> Predicates = [IsThumb2];
1121 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
1122 // an input operand since by default it's a zero register. It will
1123 // become an implicit def once it's "flipped".
1124 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1126 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1127 InstrItinClass itin,
1128 string opc, string asm, string cstr, list<dag> pattern>
1129 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1130 let OutOperandList = oops;
1131 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1132 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1133 let Pattern = pattern;
1134 list<Predicate> Predicates = [IsThumb2];
1138 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1139 InstrItinClass itin,
1140 string asm, string cstr, list<dag> pattern>
1141 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1142 let OutOperandList = oops;
1143 let InOperandList = iops;
1144 let AsmString = asm;
1145 let Pattern = pattern;
1146 list<Predicate> Predicates = [IsThumb2];
1149 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1150 InstrItinClass itin,
1151 string asm, string cstr, list<dag> pattern>
1152 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1153 let OutOperandList = oops;
1154 let InOperandList = iops;
1155 let AsmString = asm;
1156 let Pattern = pattern;
1157 list<Predicate> Predicates = [IsThumb1Only];
1160 class T2I<dag oops, dag iops, InstrItinClass itin,
1161 string opc, string asm, list<dag> pattern>
1162 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1163 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1164 string opc, string asm, list<dag> pattern>
1165 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>;
1166 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1167 string opc, string asm, list<dag> pattern>
1168 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1169 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1170 string opc, string asm, list<dag> pattern>
1171 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1172 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1173 string opc, string asm, list<dag> pattern>
1174 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1175 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1176 string opc, string asm, list<dag> pattern>
1177 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1179 let Inst{31-27} = 0b11101;
1180 let Inst{26-25} = 0b00;
1182 let Inst{23} = ?; // The U bit.
1185 let Inst{20} = load;
1188 class T2sI<dag oops, dag iops, InstrItinClass itin,
1189 string opc, string asm, list<dag> pattern>
1190 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1192 class T2XI<dag oops, dag iops, InstrItinClass itin,
1193 string asm, list<dag> pattern>
1194 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1195 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1196 string asm, list<dag> pattern>
1197 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1199 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1200 string opc, string asm, list<dag> pattern>
1201 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1203 // Two-address instructions
1204 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1205 string asm, string cstr, list<dag> pattern>
1206 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1208 // T2Iidxldst - Thumb2 indexed load / store instructions.
1209 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1211 AddrMode am, IndexMode im, InstrItinClass itin,
1212 string opc, string asm, string cstr, list<dag> pattern>
1213 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1214 let OutOperandList = oops;
1215 let InOperandList = !con(iops, (ins pred:$p));
1216 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1217 let Pattern = pattern;
1218 list<Predicate> Predicates = [IsThumb2];
1219 let Inst{31-27} = 0b11111;
1220 let Inst{26-25} = 0b00;
1221 let Inst{24} = signed;
1223 let Inst{22-21} = opcod;
1224 let Inst{20} = load;
1226 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1227 let Inst{10} = pre; // The P bit.
1228 let Inst{8} = 1; // The W bit.
1231 // Helper class for disassembly only
1232 // A6.3.16 & A6.3.17
1233 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1234 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1235 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1236 : T2I<oops, iops, itin, opc, asm, pattern> {
1237 let Inst{31-27} = 0b11111;
1238 let Inst{26-24} = 0b011;
1239 let Inst{23} = long;
1240 let Inst{22-20} = op22_20;
1241 let Inst{7-4} = op7_4;
1244 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1245 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1246 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1249 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1250 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1251 list<Predicate> Predicates = [IsThumb1Only];
1254 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1255 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1256 list<Predicate> Predicates = [IsThumb2];
1259 //===----------------------------------------------------------------------===//
1261 //===----------------------------------------------------------------------===//
1262 // ARM VFP Instruction templates.
1265 // Almost all VFP instructions are predicable.
1266 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1267 IndexMode im, Format f, InstrItinClass itin,
1268 string opc, string asm, string cstr, list<dag> pattern>
1269 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1270 let OutOperandList = oops;
1271 let InOperandList = !con(iops, (ins pred:$p));
1272 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1273 let Pattern = pattern;
1274 list<Predicate> Predicates = [HasVFP2];
1278 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1279 IndexMode im, Format f, InstrItinClass itin,
1280 string asm, string cstr, list<dag> pattern>
1281 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1282 let OutOperandList = oops;
1283 let InOperandList = iops;
1284 let AsmString = asm;
1285 let Pattern = pattern;
1286 list<Predicate> Predicates = [HasVFP2];
1289 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1290 string opc, string asm, list<dag> pattern>
1291 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1292 opc, asm, "", pattern>;
1294 // ARM VFP addrmode5 loads and stores
1295 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1296 InstrItinClass itin,
1297 string opc, string asm, list<dag> pattern>
1298 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1299 VFPLdStFrm, itin, opc, asm, "", pattern> {
1300 // TODO: Mark the instructions with the appropriate subtarget info.
1301 let Inst{27-24} = opcod1;
1302 let Inst{21-20} = opcod2;
1303 let Inst{11-8} = 0b1011;
1305 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1306 let Dom = VFPNeonDomain.Value;
1309 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1310 InstrItinClass itin,
1311 string opc, string asm, list<dag> pattern>
1312 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1313 VFPLdStFrm, itin, opc, asm, "", pattern> {
1314 // TODO: Mark the instructions with the appropriate subtarget info.
1315 let Inst{27-24} = opcod1;
1316 let Inst{21-20} = opcod2;
1317 let Inst{11-8} = 0b1010;
1320 // Load / store multiple
1321 class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1322 string asm, string cstr, list<dag> pattern>
1323 : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
1324 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1325 // TODO: Mark the instructions with the appropriate subtarget info.
1326 let Inst{27-25} = 0b110;
1327 let Inst{11-8} = 0b1011;
1329 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1330 let Dom = VFPNeonDomain.Value;
1333 class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1334 string asm, string cstr, list<dag> pattern>
1335 : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
1336 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1337 // TODO: Mark the instructions with the appropriate subtarget info.
1338 let Inst{27-25} = 0b110;
1339 let Inst{11-8} = 0b1010;
1342 // Double precision, unary
1343 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1344 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1345 string asm, list<dag> pattern>
1346 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1347 let Inst{27-23} = opcod1;
1348 let Inst{21-20} = opcod2;
1349 let Inst{19-16} = opcod3;
1350 let Inst{11-8} = 0b1011;
1351 let Inst{7-6} = opcod4;
1352 let Inst{4} = opcod5;
1355 // Double precision, binary
1356 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1357 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1358 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1359 let Inst{27-23} = opcod1;
1360 let Inst{21-20} = opcod2;
1361 let Inst{11-8} = 0b1011;
1366 // Single precision, unary
1367 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1368 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1369 string asm, list<dag> pattern>
1370 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1371 let Inst{27-23} = opcod1;
1372 let Inst{21-20} = opcod2;
1373 let Inst{19-16} = opcod3;
1374 let Inst{11-8} = 0b1010;
1375 let Inst{7-6} = opcod4;
1376 let Inst{4} = opcod5;
1379 // Single precision unary, if no NEON
1380 // Same as ASuI except not available if NEON is enabled
1381 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1382 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1383 string asm, list<dag> pattern>
1384 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1386 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1389 // Single precision, binary
1390 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1391 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1392 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1393 let Inst{27-23} = opcod1;
1394 let Inst{21-20} = opcod2;
1395 let Inst{11-8} = 0b1010;
1400 // Single precision binary, if no NEON
1401 // Same as ASbI except not available if NEON is enabled
1402 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1403 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1404 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1405 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1408 // VFP conversion instructions
1409 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1410 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1412 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1413 let Inst{27-23} = opcod1;
1414 let Inst{21-20} = opcod2;
1415 let Inst{19-16} = opcod3;
1416 let Inst{11-8} = opcod4;
1421 // VFP conversion between floating-point and fixed-point
1422 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1423 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1425 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1426 // size (fixed-point number): sx == 0 ? 16 : 32
1427 let Inst{7} = op5; // sx
1430 // VFP conversion instructions, if no NEON
1431 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1432 dag oops, dag iops, InstrItinClass itin,
1433 string opc, string asm, list<dag> pattern>
1434 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1436 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1439 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1440 InstrItinClass itin,
1441 string opc, string asm, list<dag> pattern>
1442 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1443 let Inst{27-20} = opcod1;
1444 let Inst{11-8} = opcod2;
1448 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1449 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1450 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1452 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1453 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1454 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1456 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1457 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1458 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1460 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1461 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1462 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1464 //===----------------------------------------------------------------------===//
1466 //===----------------------------------------------------------------------===//
1467 // ARM NEON Instruction templates.
1470 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1471 string opc, string dt, string asm, string cstr, list<dag> pattern>
1472 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1473 let OutOperandList = oops;
1474 let InOperandList = !con(iops, (ins pred:$p));
1475 let AsmString = !strconcat(
1476 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1477 !strconcat("\t", asm));
1478 let Pattern = pattern;
1479 list<Predicate> Predicates = [HasNEON];
1482 // Same as NeonI except it does not have a "data type" specifier.
1483 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
1484 string opc, string asm, string cstr, list<dag> pattern>
1485 : InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
1486 let OutOperandList = oops;
1487 let InOperandList = !con(iops, (ins pred:$p));
1488 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
1489 let Pattern = pattern;
1490 list<Predicate> Predicates = [HasNEON];
1493 class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1495 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
1499 class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
1500 string asm, list<dag> pattern>
1501 : NeonXI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "",
1505 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1506 dag oops, dag iops, InstrItinClass itin,
1507 string opc, string dt, string asm, string cstr, list<dag> pattern>
1508 : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, dt, asm, cstr,
1510 let Inst{31-24} = 0b11110100;
1511 let Inst{23} = op23;
1512 let Inst{21-20} = op21_20;
1513 let Inst{11-8} = op11_8;
1514 let Inst{7-4} = op7_4;
1517 class NDataI<dag oops, dag iops, InstrItinClass itin,
1518 string opc, string dt, string asm, string cstr, list<dag> pattern>
1519 : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, dt, asm,
1521 let Inst{31-25} = 0b1111001;
1524 class NDataXI<dag oops, dag iops, InstrItinClass itin,
1525 string opc, string asm, string cstr, list<dag> pattern>
1526 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
1528 let Inst{31-25} = 0b1111001;
1531 // NEON "one register and a modified immediate" format.
1532 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1534 dag oops, dag iops, InstrItinClass itin,
1535 string opc, string dt, string asm, string cstr, list<dag> pattern>
1536 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1537 let Inst{23} = op23;
1538 let Inst{21-19} = op21_19;
1539 let Inst{11-8} = op11_8;
1546 // NEON 2 vector register format.
1547 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1548 bits<5> op11_7, bit op6, bit op4,
1549 dag oops, dag iops, InstrItinClass itin,
1550 string opc, string dt, string asm, string cstr, list<dag> pattern>
1551 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1552 let Inst{24-23} = op24_23;
1553 let Inst{21-20} = op21_20;
1554 let Inst{19-18} = op19_18;
1555 let Inst{17-16} = op17_16;
1556 let Inst{11-7} = op11_7;
1561 // Same as N2V except it doesn't have a datatype suffix.
1562 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1563 bits<5> op11_7, bit op6, bit op4,
1564 dag oops, dag iops, InstrItinClass itin,
1565 string opc, string asm, string cstr, list<dag> pattern>
1566 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1567 let Inst{24-23} = op24_23;
1568 let Inst{21-20} = op21_20;
1569 let Inst{19-18} = op19_18;
1570 let Inst{17-16} = op17_16;
1571 let Inst{11-7} = op11_7;
1576 // NEON 2 vector register with immediate.
1577 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1578 dag oops, dag iops, InstrItinClass itin,
1579 string opc, string dt, string asm, string cstr, list<dag> pattern>
1580 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1581 let Inst{24} = op24;
1582 let Inst{23} = op23;
1583 let Inst{11-8} = op11_8;
1589 // NEON 3 vector register format.
1590 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1591 dag oops, dag iops, InstrItinClass itin,
1592 string opc, string dt, string asm, string cstr, list<dag> pattern>
1593 : NDataI<oops, iops, itin, opc, dt, asm, cstr, pattern> {
1594 let Inst{24} = op24;
1595 let Inst{23} = op23;
1596 let Inst{21-20} = op21_20;
1597 let Inst{11-8} = op11_8;
1602 // Same as N3VX except it doesn't have a data type suffix.
1603 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1604 dag oops, dag iops, InstrItinClass itin,
1605 string opc, string asm, string cstr, list<dag> pattern>
1606 : NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
1607 let Inst{24} = op24;
1608 let Inst{23} = op23;
1609 let Inst{21-20} = op21_20;
1610 let Inst{11-8} = op11_8;
1615 // NEON VMOVs between scalar and core registers.
1616 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1617 dag oops, dag iops, Format f, InstrItinClass itin,
1618 string opc, string dt, string asm, list<dag> pattern>
1619 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
1621 let Inst{27-20} = opcod1;
1622 let Inst{11-8} = opcod2;
1623 let Inst{6-5} = opcod3;
1626 let OutOperandList = oops;
1627 let InOperandList = !con(iops, (ins pred:$p));
1628 let AsmString = !strconcat(
1629 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1630 !strconcat("\t", asm));
1631 let Pattern = pattern;
1632 list<Predicate> Predicates = [HasNEON];
1634 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1635 dag oops, dag iops, InstrItinClass itin,
1636 string opc, string dt, string asm, list<dag> pattern>
1637 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin,
1638 opc, dt, asm, pattern>;
1639 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1640 dag oops, dag iops, InstrItinClass itin,
1641 string opc, string dt, string asm, list<dag> pattern>
1642 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin,
1643 opc, dt, asm, pattern>;
1644 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1645 dag oops, dag iops, InstrItinClass itin,
1646 string opc, string dt, string asm, list<dag> pattern>
1647 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
1648 opc, dt, asm, pattern>;
1650 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1651 // for single-precision FP.
1652 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1653 list<Predicate> Predicates = [HasNEON,UseNEONForFP];