1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // The instruction has an Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
87 // FIXME: Once the JIT is MC-ized, these can go away.
89 class AddrMode<bits<5> val> {
92 def AddrModeNone : AddrMode<0>;
93 def AddrMode1 : AddrMode<1>;
94 def AddrMode2 : AddrMode<2>;
95 def AddrMode3 : AddrMode<3>;
96 def AddrMode4 : AddrMode<4>;
97 def AddrMode5 : AddrMode<5>;
98 def AddrMode6 : AddrMode<6>;
99 def AddrModeT1_1 : AddrMode<7>;
100 def AddrModeT1_2 : AddrMode<8>;
101 def AddrModeT1_4 : AddrMode<9>;
102 def AddrModeT1_s : AddrMode<10>;
103 def AddrModeT2_i12 : AddrMode<11>;
104 def AddrModeT2_i8 : AddrMode<12>;
105 def AddrModeT2_so : AddrMode<13>;
106 def AddrModeT2_pc : AddrMode<14>;
107 def AddrModeT2_i8s4 : AddrMode<15>;
108 def AddrMode_i12 : AddrMode<16>;
111 class SizeFlagVal<bits<3> val> {
114 def SizeInvalid : SizeFlagVal<0>; // Unset.
115 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
116 def Size8Bytes : SizeFlagVal<2>;
117 def Size4Bytes : SizeFlagVal<3>;
118 def Size2Bytes : SizeFlagVal<4>;
120 // Load / store index mode.
121 class IndexMode<bits<2> val> {
124 def IndexModeNone : IndexMode<0>;
125 def IndexModePre : IndexMode<1>;
126 def IndexModePost : IndexMode<2>;
127 def IndexModeUpd : IndexMode<3>;
129 // Instruction execution domain.
130 class Domain<bits<3> val> {
133 def GenericDomain : Domain<0>;
134 def VFPDomain : Domain<1>; // Instructions in VFP domain only
135 def NeonDomain : Domain<2>; // Instructions in Neon domain only
136 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
139 //===----------------------------------------------------------------------===//
140 // ARM special operands.
143 def CondCodeOperand : AsmOperandClass {
144 let Name = "CondCode";
145 let SuperClasses = [];
148 def CCOutOperand : AsmOperandClass {
150 let SuperClasses = [];
153 def MemBarrierOptOperand : AsmOperandClass {
154 let Name = "MemBarrierOpt";
155 let SuperClasses = [];
156 let ParserMethod = "tryParseMemBarrierOptOperand";
159 def ProcIFlagsOperand : AsmOperandClass {
160 let Name = "ProcIFlags";
161 let SuperClasses = [];
162 let ParserMethod = "tryParseProcIFlagsOperand";
165 def MSRMaskOperand : AsmOperandClass {
166 let Name = "MSRMask";
167 let SuperClasses = [];
168 let ParserMethod = "tryParseMSRMaskOperand";
171 // ARM imod and iflag operands, used only by the CPS instruction.
172 def imod_op : Operand<i32> {
173 let PrintMethod = "printCPSIMod";
176 def iflags_op : Operand<i32> {
177 let PrintMethod = "printCPSIFlag";
178 let ParserMatchClass = ProcIFlagsOperand;
181 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
182 // register whose default is 0 (no register).
183 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
184 (ops (i32 14), (i32 zero_reg))> {
185 let PrintMethod = "printPredicateOperand";
186 let ParserMatchClass = CondCodeOperand;
189 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
190 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
191 let EncoderMethod = "getCCOutOpValue";
192 let PrintMethod = "printSBitModifierOperand";
193 let ParserMatchClass = CCOutOperand;
196 // Same as cc_out except it defaults to setting CPSR.
197 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
198 let EncoderMethod = "getCCOutOpValue";
199 let PrintMethod = "printSBitModifierOperand";
200 let ParserMatchClass = CCOutOperand;
203 // ARM special operands for disassembly only.
205 def setend_op : Operand<i32> {
206 let PrintMethod = "printSetendOperand";
209 def msr_mask : Operand<i32> {
210 let PrintMethod = "printMSRMaskOperand";
211 let ParserMatchClass = MSRMaskOperand;
214 // Shift Right Immediate - A shift right immediate is encoded differently from
215 // other shift immediates. The imm6 field is encoded like so:
218 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
219 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
220 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
221 // 64 64 - <imm> is encoded in imm6<5:0>
222 def shr_imm8 : Operand<i32> {
223 let EncoderMethod = "getShiftRight8Imm";
225 def shr_imm16 : Operand<i32> {
226 let EncoderMethod = "getShiftRight16Imm";
228 def shr_imm32 : Operand<i32> {
229 let EncoderMethod = "getShiftRight32Imm";
231 def shr_imm64 : Operand<i32> {
232 let EncoderMethod = "getShiftRight64Imm";
235 //===----------------------------------------------------------------------===//
236 // ARM Instruction templates.
239 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
240 Format f, Domain d, string cstr, InstrItinClass itin>
242 let Namespace = "ARM";
247 bits<2> IndexModeBits = IM.Value;
249 bits<6> Form = F.Value;
251 bit isUnaryDataProc = 0;
252 bit canXformTo16Bit = 0;
254 // If this is a pseudo instruction, mark it isCodeGenOnly.
255 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
257 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
258 let TSFlags{4-0} = AM.Value;
259 let TSFlags{7-5} = SZ.Value;
260 let TSFlags{9-8} = IndexModeBits;
261 let TSFlags{15-10} = Form;
262 let TSFlags{16} = isUnaryDataProc;
263 let TSFlags{17} = canXformTo16Bit;
264 let TSFlags{20-18} = D.Value;
266 let Constraints = cstr;
267 let Itinerary = itin;
274 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
275 Format f, Domain d, string cstr, InstrItinClass itin>
276 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
278 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
279 // on by adding flavors to specific instructions.
280 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
281 Format f, Domain d, string cstr, InstrItinClass itin>
282 : InstTemplate<am, sz, im, f, d, cstr, itin>;
284 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
285 // FIXME: This really should derive from InstTemplate instead, as pseudos
286 // don't need encoding information. TableGen doesn't like that
287 // currently. Need to figure out why and fix it.
288 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
290 let OutOperandList = oops;
291 let InOperandList = iops;
292 let Pattern = pattern;
293 let isCodeGenOnly = 1;
296 // PseudoInst that's ARM-mode only.
297 class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
299 : PseudoInst<oops, iops, itin, pattern> {
301 list<Predicate> Predicates = [IsARM];
304 // PseudoInst that's Thumb-mode only.
305 class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
307 : PseudoInst<oops, iops, itin, pattern> {
309 list<Predicate> Predicates = [IsThumb];
312 // PseudoInst that's Thumb2-mode only.
313 class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
315 : PseudoInst<oops, iops, itin, pattern> {
317 list<Predicate> Predicates = [IsThumb2];
319 // Almost all ARM instructions are predicable.
320 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
321 IndexMode im, Format f, InstrItinClass itin,
322 string opc, string asm, string cstr,
324 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
327 let OutOperandList = oops;
328 let InOperandList = !con(iops, (ins pred:$p));
329 let AsmString = !strconcat(opc, "${p}", asm);
330 let Pattern = pattern;
331 list<Predicate> Predicates = [IsARM];
334 // A few are not predicable
335 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
336 IndexMode im, Format f, InstrItinClass itin,
337 string opc, string asm, string cstr,
339 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
340 let OutOperandList = oops;
341 let InOperandList = iops;
342 let AsmString = !strconcat(opc, asm);
343 let Pattern = pattern;
344 let isPredicable = 0;
345 list<Predicate> Predicates = [IsARM];
348 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
349 // operand since by default it's a zero register. It will become an implicit def
350 // once it's "flipped".
351 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
352 IndexMode im, Format f, InstrItinClass itin,
353 string opc, string asm, string cstr,
355 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
356 bits<4> p; // Predicate operand
357 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
361 let OutOperandList = oops;
362 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
363 let AsmString = !strconcat(opc, "${s}${p}", asm);
364 let Pattern = pattern;
365 list<Predicate> Predicates = [IsARM];
369 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
370 IndexMode im, Format f, InstrItinClass itin,
371 string asm, string cstr, list<dag> pattern>
372 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
373 let OutOperandList = oops;
374 let InOperandList = iops;
376 let Pattern = pattern;
377 list<Predicate> Predicates = [IsARM];
380 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
383 opc, asm, "", pattern>;
384 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
385 string opc, string asm, list<dag> pattern>
386 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
387 opc, asm, "", pattern>;
388 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
389 string asm, list<dag> pattern>
390 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
392 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
393 string opc, string asm, list<dag> pattern>
394 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
395 opc, asm, "", pattern>;
397 // Ctrl flow instructions
398 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
401 opc, asm, "", pattern> {
402 let Inst{27-24} = opcod;
404 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
405 string asm, list<dag> pattern>
406 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
408 let Inst{27-24} = opcod;
411 // BR_JT instructions
412 class JTI<dag oops, dag iops, InstrItinClass itin,
413 string asm, list<dag> pattern>
414 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
417 // Atomic load/store instructions
418 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
419 string opc, string asm, list<dag> pattern>
420 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
421 opc, asm, "", pattern> {
424 let Inst{27-23} = 0b00011;
425 let Inst{22-21} = opcod;
427 let Inst{19-16} = Rn;
428 let Inst{15-12} = Rt;
429 let Inst{11-0} = 0b111110011111;
431 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
432 string opc, string asm, list<dag> pattern>
433 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
434 opc, asm, "", pattern> {
438 let Inst{27-23} = 0b00011;
439 let Inst{22-21} = opcod;
441 let Inst{19-16} = addr;
442 let Inst{15-12} = Rd;
443 let Inst{11-4} = 0b11111001;
446 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
447 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
451 let Inst{27-23} = 0b00010;
453 let Inst{21-20} = 0b00;
454 let Inst{19-16} = Rn;
455 let Inst{15-12} = Rt;
456 let Inst{11-4} = 0b00001001;
460 // addrmode1 instructions
461 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
462 string opc, string asm, list<dag> pattern>
463 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
464 opc, asm, "", pattern> {
465 let Inst{24-21} = opcod;
466 let Inst{27-26} = 0b00;
468 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
471 opc, asm, "", pattern> {
472 let Inst{24-21} = opcod;
473 let Inst{27-26} = 0b00;
475 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
476 string asm, list<dag> pattern>
477 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
479 let Inst{24-21} = opcod;
480 let Inst{27-26} = 0b00;
485 // LDR/LDRB/STR/STRB/...
486 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
487 Format f, InstrItinClass itin, string opc, string asm,
489 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
491 let Inst{27-25} = op;
492 let Inst{24} = 1; // 24 == P
494 let Inst{22} = isByte;
495 let Inst{21} = 0; // 21 == W
498 // Indexed load/stores
499 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
500 IndexMode im, Format f, InstrItinClass itin, string opc,
501 string asm, string cstr, list<dag> pattern>
502 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
503 opc, asm, cstr, pattern> {
505 let Inst{27-26} = 0b01;
506 let Inst{24} = isPre; // P bit
507 let Inst{22} = isByte; // B bit
508 let Inst{21} = isPre; // W bit
509 let Inst{20} = isLd; // L bit
510 let Inst{15-12} = Rt;
512 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
513 IndexMode im, Format f, InstrItinClass itin, string opc,
514 string asm, string cstr, list<dag> pattern>
515 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
517 // AM2 store w/ two operands: (GPR, am2offset)
518 // {13} 1 == Rm, 0 == imm12
523 let Inst{25} = offset{13};
524 let Inst{23} = offset{12};
525 let Inst{19-16} = Rn;
526 let Inst{11-0} = offset{11-0};
528 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
529 // but for now use this class for STRT and STRBT.
530 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
531 IndexMode im, Format f, InstrItinClass itin, string opc,
532 string asm, string cstr, list<dag> pattern>
533 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
535 // AM2 store w/ two operands: (GPR, am2offset)
537 // {13} 1 == Rm, 0 == imm12
541 let Inst{25} = addr{13};
542 let Inst{23} = addr{12};
543 let Inst{19-16} = addr{17-14};
544 let Inst{11-0} = addr{11-0};
547 // addrmode3 instructions
548 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
549 InstrItinClass itin, string opc, string asm, list<dag> pattern>
550 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
551 opc, asm, "", pattern> {
554 let Inst{27-25} = 0b000;
555 let Inst{24} = 1; // P bit
556 let Inst{23} = addr{8}; // U bit
557 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
558 let Inst{21} = 0; // W bit
559 let Inst{20} = op20; // L bit
560 let Inst{19-16} = addr{12-9}; // Rn
561 let Inst{15-12} = Rt; // Rt
562 let Inst{11-8} = addr{7-4}; // imm7_4/zero
564 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
567 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
568 IndexMode im, Format f, InstrItinClass itin, string opc,
569 string asm, string cstr, list<dag> pattern>
570 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
571 opc, asm, cstr, pattern> {
573 let Inst{27-25} = 0b000;
574 let Inst{24} = isPre; // P bit
575 let Inst{21} = isPre; // W bit
576 let Inst{20} = op20; // L bit
577 let Inst{15-12} = Rt; // Rt
581 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
582 // but for now use this class for LDRSBT, LDRHT, LDSHT.
583 class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
584 IndexMode im, Format f, InstrItinClass itin, string opc,
585 string asm, string cstr, list<dag> pattern>
586 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
587 opc, asm, cstr, pattern> {
588 // {13} 1 == imm8, 0 == Rm
595 let Inst{27-25} = 0b000;
596 let Inst{24} = isPre; // P bit
597 let Inst{23} = addr{8}; // U bit
598 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
599 let Inst{20} = op20; // L bit
600 let Inst{19-16} = addr{12-9}; // Rn
601 let Inst{15-12} = Rt; // Rt
602 let Inst{11-8} = addr{7-4}; // imm7_4/zero
604 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
605 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3";
608 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
609 IndexMode im, Format f, InstrItinClass itin, string opc,
610 string asm, string cstr, list<dag> pattern>
611 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
613 // AM3 store w/ two operands: (GPR, am3offset)
617 let Inst{27-25} = 0b000;
618 let Inst{23} = offset{8};
619 let Inst{22} = offset{9};
620 let Inst{19-16} = Rn;
621 let Inst{15-12} = Rt; // Rt
622 let Inst{11-8} = offset{7-4}; // imm7_4/zero
624 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
628 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
629 string opc, string asm, list<dag> pattern>
630 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
631 opc, asm, "", pattern> {
634 let Inst{27-25} = 0b000;
635 let Inst{24} = 1; // P bit
636 let Inst{23} = addr{8}; // U bit
637 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
638 let Inst{21} = 0; // W bit
639 let Inst{20} = 0; // L bit
640 let Inst{19-16} = addr{12-9}; // Rn
641 let Inst{15-12} = Rt; // Rt
642 let Inst{11-8} = addr{7-4}; // imm7_4/zero
644 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
647 // Pre-indexed stores
648 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
649 string opc, string asm, string cstr, list<dag> pattern>
650 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
651 opc, asm, cstr, pattern> {
653 let Inst{5} = 1; // H bit
654 let Inst{6} = 0; // S bit
656 let Inst{20} = 0; // L bit
657 let Inst{21} = 1; // W bit
658 let Inst{24} = 1; // P bit
659 let Inst{27-25} = 0b000;
661 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
662 string opc, string asm, string cstr, list<dag> pattern>
663 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
664 opc, asm, cstr, pattern> {
666 let Inst{5} = 1; // H bit
667 let Inst{6} = 1; // S bit
669 let Inst{20} = 0; // L bit
670 let Inst{21} = 1; // W bit
671 let Inst{24} = 1; // P bit
672 let Inst{27-25} = 0b000;
675 // Post-indexed stores
676 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
677 string opc, string asm, string cstr, list<dag> pattern>
678 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
679 opc, asm, cstr,pattern> {
680 // {13} 1 == imm8, 0 == Rm
687 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
689 let Inst{5} = 1; // H bit
690 let Inst{6} = 0; // S bit
692 let Inst{11-8} = addr{7-4}; // imm7_4/zero
693 let Inst{15-12} = Rt; // Rt
694 let Inst{19-16} = addr{12-9}; // Rn
695 let Inst{20} = 0; // L bit
696 let Inst{21} = 0; // W bit
697 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
698 let Inst{23} = addr{8}; // U bit
699 let Inst{24} = 0; // P bit
700 let Inst{27-25} = 0b000;
702 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
703 string opc, string asm, string cstr, list<dag> pattern>
704 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
705 opc, asm, cstr, pattern> {
707 let Inst{5} = 1; // H bit
708 let Inst{6} = 1; // S bit
710 let Inst{20} = 0; // L bit
711 let Inst{21} = 0; // W bit
712 let Inst{24} = 0; // P bit
713 let Inst{27-25} = 0b000;
716 // addrmode4 instructions
717 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
718 string asm, string cstr, list<dag> pattern>
719 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
724 let Inst{27-25} = 0b100;
725 let Inst{22} = 0; // S bit
726 let Inst{19-16} = Rn;
727 let Inst{15-0} = regs;
730 // Unsigned multiply, multiply-accumulate instructions.
731 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
732 string opc, string asm, list<dag> pattern>
733 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
734 opc, asm, "", pattern> {
735 let Inst{7-4} = 0b1001;
736 let Inst{20} = 0; // S bit
737 let Inst{27-21} = opcod;
739 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
740 string opc, string asm, list<dag> pattern>
741 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
742 opc, asm, "", pattern> {
743 let Inst{7-4} = 0b1001;
744 let Inst{27-21} = opcod;
747 // Most significant word multiply
748 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
749 InstrItinClass itin, string opc, string asm, list<dag> pattern>
750 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
751 opc, asm, "", pattern> {
755 let Inst{7-4} = opc7_4;
757 let Inst{27-21} = opcod;
758 let Inst{19-16} = Rd;
762 // MSW multiple w/ Ra operand
763 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
764 InstrItinClass itin, string opc, string asm, list<dag> pattern>
765 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
767 let Inst{15-12} = Ra;
770 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
771 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
772 InstrItinClass itin, string opc, string asm, list<dag> pattern>
773 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
774 opc, asm, "", pattern> {
780 let Inst{27-21} = opcod;
781 let Inst{6-5} = bit6_5;
785 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
786 InstrItinClass itin, string opc, string asm, list<dag> pattern>
787 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
789 let Inst{19-16} = Rd;
792 // AMulxyI with Ra operand
793 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
794 InstrItinClass itin, string opc, string asm, list<dag> pattern>
795 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
797 let Inst{15-12} = Ra;
800 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
801 InstrItinClass itin, string opc, string asm, list<dag> pattern>
802 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
805 let Inst{19-16} = RdHi;
806 let Inst{15-12} = RdLo;
809 // Extend instructions.
810 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
811 string opc, string asm, list<dag> pattern>
812 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
813 opc, asm, "", pattern> {
814 // All AExtI instructions have Rd and Rm register operands.
817 let Inst{15-12} = Rd;
819 let Inst{7-4} = 0b0111;
820 let Inst{9-8} = 0b00;
821 let Inst{27-20} = opcod;
824 // Misc Arithmetic instructions.
825 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
826 InstrItinClass itin, string opc, string asm, list<dag> pattern>
827 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
828 opc, asm, "", pattern> {
831 let Inst{27-20} = opcod;
832 let Inst{19-16} = 0b1111;
833 let Inst{15-12} = Rd;
834 let Inst{11-8} = 0b1111;
835 let Inst{7-4} = opc7_4;
840 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
841 string opc, string asm, list<dag> pattern>
842 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
843 opc, asm, "", pattern> {
848 let Inst{27-20} = opcod;
849 let Inst{19-16} = Rn;
850 let Inst{15-12} = Rd;
851 let Inst{11-7} = sh{7-3};
853 let Inst{5-4} = 0b01;
857 //===----------------------------------------------------------------------===//
859 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
860 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
861 list<Predicate> Predicates = [IsARM];
863 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
864 list<Predicate> Predicates = [IsARM, HasV5TE];
866 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
867 list<Predicate> Predicates = [IsARM, HasV6];
870 //===----------------------------------------------------------------------===//
871 // Thumb Instruction Format Definitions.
874 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
875 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
876 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
877 let OutOperandList = oops;
878 let InOperandList = iops;
880 let Pattern = pattern;
881 list<Predicate> Predicates = [IsThumb];
884 // TI - Thumb instruction.
885 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
886 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
888 // Two-address instructions
889 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
891 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
894 // tBL, tBX 32-bit instructions
895 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
896 dag oops, dag iops, InstrItinClass itin, string asm,
898 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
900 let Inst{31-27} = opcod1;
901 let Inst{15-14} = opcod2;
902 let Inst{12} = opcod3;
905 // Move to/from coprocessor instructions
906 class T1Cop<dag oops, dag iops, string asm, list<dag> pattern>
907 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>,
908 Encoding, Requires<[IsThumb, HasV6]> {
909 let Inst{31-28} = 0b1110;
912 // BR_JT instructions
913 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
915 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
918 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
919 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
920 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
921 let OutOperandList = oops;
922 let InOperandList = iops;
924 let Pattern = pattern;
925 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
928 class T1I<dag oops, dag iops, InstrItinClass itin,
929 string asm, list<dag> pattern>
930 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
931 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
932 string asm, list<dag> pattern>
933 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
935 // Two-address instructions
936 class T1It<dag oops, dag iops, InstrItinClass itin,
937 string asm, string cstr, list<dag> pattern>
938 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
941 // Thumb1 instruction that can either be predicated or set CPSR.
942 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
944 string opc, string asm, string cstr, list<dag> pattern>
945 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
946 let OutOperandList = !con(oops, (outs s_cc_out:$s));
947 let InOperandList = !con(iops, (ins pred:$p));
948 let AsmString = !strconcat(opc, "${s}${p}", asm);
949 let Pattern = pattern;
950 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
953 class T1sI<dag oops, dag iops, InstrItinClass itin,
954 string opc, string asm, list<dag> pattern>
955 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
957 // Two-address instructions
958 class T1sIt<dag oops, dag iops, InstrItinClass itin,
959 string opc, string asm, list<dag> pattern>
960 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
961 "$Rn = $Rdn", pattern>;
963 // Thumb1 instruction that can be predicated.
964 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
966 string opc, string asm, string cstr, list<dag> pattern>
967 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
968 let OutOperandList = oops;
969 let InOperandList = !con(iops, (ins pred:$p));
970 let AsmString = !strconcat(opc, "${p}", asm);
971 let Pattern = pattern;
972 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
975 class T1pI<dag oops, dag iops, InstrItinClass itin,
976 string opc, string asm, list<dag> pattern>
977 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
979 // Two-address instructions
980 class T1pIt<dag oops, dag iops, InstrItinClass itin,
981 string opc, string asm, list<dag> pattern>
982 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
983 "$Rn = $Rdn", pattern>;
985 class T1pIs<dag oops, dag iops,
986 InstrItinClass itin, string opc, string asm, list<dag> pattern>
987 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
989 class Encoding16 : Encoding {
990 let Inst{31-16} = 0x0000;
993 // A6.2 16-bit Thumb instruction encoding
994 class T1Encoding<bits<6> opcode> : Encoding16 {
995 let Inst{15-10} = opcode;
998 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
999 class T1General<bits<5> opcode> : Encoding16 {
1000 let Inst{15-14} = 0b00;
1001 let Inst{13-9} = opcode;
1004 // A6.2.2 Data-processing encoding.
1005 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1006 let Inst{15-10} = 0b010000;
1007 let Inst{9-6} = opcode;
1010 // A6.2.3 Special data instructions and branch and exchange encoding.
1011 class T1Special<bits<4> opcode> : Encoding16 {
1012 let Inst{15-10} = 0b010001;
1013 let Inst{9-6} = opcode;
1016 // A6.2.4 Load/store single data item encoding.
1017 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1018 let Inst{15-12} = opA;
1019 let Inst{11-9} = opB;
1021 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1023 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1024 // following bits are used for "opA" (see A6.2.4):
1026 // 0b0110 => Immediate, 4 bytes
1027 // 0b1000 => Immediate, 2 bytes
1028 // 0b0111 => Immediate, 1 byte
1029 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1030 InstrItinClass itin, string opc, string asm,
1032 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
1033 T1LoadStore<0b0101, opcode> {
1036 let Inst{8-6} = addr{5-3}; // Rm
1037 let Inst{5-3} = addr{2-0}; // Rn
1040 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1041 InstrItinClass itin, string opc, string asm,
1043 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
1044 T1LoadStore<opA, {opB,?,?}> {
1047 let Inst{10-6} = addr{7-3}; // imm5
1048 let Inst{5-3} = addr{2-0}; // Rn
1052 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1053 class T1Misc<bits<7> opcode> : Encoding16 {
1054 let Inst{15-12} = 0b1011;
1055 let Inst{11-5} = opcode;
1058 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1059 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1060 InstrItinClass itin,
1061 string opc, string asm, string cstr, list<dag> pattern>
1062 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1063 let OutOperandList = oops;
1064 let InOperandList = !con(iops, (ins pred:$p));
1065 let AsmString = !strconcat(opc, "${p}", asm);
1066 let Pattern = pattern;
1067 list<Predicate> Predicates = [IsThumb2];
1070 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1071 // input operand since by default it's a zero register. It will become an
1072 // implicit def once it's "flipped".
1074 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1076 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1077 InstrItinClass itin,
1078 string opc, string asm, string cstr, list<dag> pattern>
1079 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1080 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1083 let OutOperandList = oops;
1084 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1085 let AsmString = !strconcat(opc, "${s}${p}", asm);
1086 let Pattern = pattern;
1087 list<Predicate> Predicates = [IsThumb2];
1091 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1092 InstrItinClass itin,
1093 string asm, string cstr, list<dag> pattern>
1094 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1095 let OutOperandList = oops;
1096 let InOperandList = iops;
1097 let AsmString = asm;
1098 let Pattern = pattern;
1099 list<Predicate> Predicates = [IsThumb2];
1102 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1103 InstrItinClass itin,
1104 string asm, string cstr, list<dag> pattern>
1105 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1106 let OutOperandList = oops;
1107 let InOperandList = iops;
1108 let AsmString = asm;
1109 let Pattern = pattern;
1110 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1113 class T2I<dag oops, dag iops, InstrItinClass itin,
1114 string opc, string asm, list<dag> pattern>
1115 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1116 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1117 string opc, string asm, list<dag> pattern>
1118 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1119 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1120 string opc, string asm, list<dag> pattern>
1121 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1122 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1123 string opc, string asm, list<dag> pattern>
1124 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1125 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1126 string opc, string asm, list<dag> pattern>
1127 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1128 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1129 string opc, string asm, list<dag> pattern>
1130 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1135 let Inst{31-25} = 0b1110100;
1137 let Inst{23} = addr{8};
1140 let Inst{20} = isLoad;
1141 let Inst{19-16} = addr{12-9};
1142 let Inst{15-12} = Rt{3-0};
1143 let Inst{11-8} = Rt2{3-0};
1144 let Inst{7-0} = addr{7-0};
1147 class T2sI<dag oops, dag iops, InstrItinClass itin,
1148 string opc, string asm, list<dag> pattern>
1149 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1151 class T2XI<dag oops, dag iops, InstrItinClass itin,
1152 string asm, list<dag> pattern>
1153 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1154 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1155 string asm, list<dag> pattern>
1156 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1158 // Move to/from coprocessor instructions
1159 class T2Cop<dag oops, dag iops, string asm, list<dag> pattern>
1160 : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> {
1161 let Inst{31-28} = 0b1111;
1164 // Two-address instructions
1165 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1166 string asm, string cstr, list<dag> pattern>
1167 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1169 // T2Iidxldst - Thumb2 indexed load / store instructions.
1170 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1172 AddrMode am, IndexMode im, InstrItinClass itin,
1173 string opc, string asm, string cstr, list<dag> pattern>
1174 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1175 let OutOperandList = oops;
1176 let InOperandList = !con(iops, (ins pred:$p));
1177 let AsmString = !strconcat(opc, "${p}", asm);
1178 let Pattern = pattern;
1179 list<Predicate> Predicates = [IsThumb2];
1180 let Inst{31-27} = 0b11111;
1181 let Inst{26-25} = 0b00;
1182 let Inst{24} = signed;
1184 let Inst{22-21} = opcod;
1185 let Inst{20} = load;
1187 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1188 let Inst{10} = pre; // The P bit.
1189 let Inst{8} = 1; // The W bit.
1192 let Inst{7-0} = addr{7-0};
1193 let Inst{9} = addr{8}; // Sign bit
1197 let Inst{15-12} = Rt{3-0};
1198 let Inst{19-16} = Rn{3-0};
1201 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1202 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1203 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1206 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1207 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1208 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1211 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1212 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1213 list<Predicate> Predicates = [IsThumb2];
1216 //===----------------------------------------------------------------------===//
1218 //===----------------------------------------------------------------------===//
1219 // ARM VFP Instruction templates.
1222 // Almost all VFP instructions are predicable.
1223 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1224 IndexMode im, Format f, InstrItinClass itin,
1225 string opc, string asm, string cstr, list<dag> pattern>
1226 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1228 let Inst{31-28} = p;
1229 let OutOperandList = oops;
1230 let InOperandList = !con(iops, (ins pred:$p));
1231 let AsmString = !strconcat(opc, "${p}", asm);
1232 let Pattern = pattern;
1233 let PostEncoderMethod = "VFPThumb2PostEncoder";
1234 list<Predicate> Predicates = [HasVFP2];
1238 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1239 IndexMode im, Format f, InstrItinClass itin,
1240 string asm, string cstr, list<dag> pattern>
1241 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1243 let Inst{31-28} = p;
1244 let OutOperandList = oops;
1245 let InOperandList = iops;
1246 let AsmString = asm;
1247 let Pattern = pattern;
1248 let PostEncoderMethod = "VFPThumb2PostEncoder";
1249 list<Predicate> Predicates = [HasVFP2];
1252 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1253 string opc, string asm, list<dag> pattern>
1254 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1255 opc, asm, "", pattern> {
1256 let PostEncoderMethod = "VFPThumb2PostEncoder";
1259 // ARM VFP addrmode5 loads and stores
1260 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1261 InstrItinClass itin,
1262 string opc, string asm, list<dag> pattern>
1263 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1264 VFPLdStFrm, itin, opc, asm, "", pattern> {
1265 // Instruction operands.
1269 // Encode instruction operands.
1270 let Inst{23} = addr{8}; // U (add = (U == '1'))
1271 let Inst{22} = Dd{4};
1272 let Inst{19-16} = addr{12-9}; // Rn
1273 let Inst{15-12} = Dd{3-0};
1274 let Inst{7-0} = addr{7-0}; // imm8
1276 // TODO: Mark the instructions with the appropriate subtarget info.
1277 let Inst{27-24} = opcod1;
1278 let Inst{21-20} = opcod2;
1279 let Inst{11-9} = 0b101;
1280 let Inst{8} = 1; // Double precision
1282 // Loads & stores operate on both NEON and VFP pipelines.
1283 let D = VFPNeonDomain;
1286 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1287 InstrItinClass itin,
1288 string opc, string asm, list<dag> pattern>
1289 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1290 VFPLdStFrm, itin, opc, asm, "", pattern> {
1291 // Instruction operands.
1295 // Encode instruction operands.
1296 let Inst{23} = addr{8}; // U (add = (U == '1'))
1297 let Inst{22} = Sd{0};
1298 let Inst{19-16} = addr{12-9}; // Rn
1299 let Inst{15-12} = Sd{4-1};
1300 let Inst{7-0} = addr{7-0}; // imm8
1302 // TODO: Mark the instructions with the appropriate subtarget info.
1303 let Inst{27-24} = opcod1;
1304 let Inst{21-20} = opcod2;
1305 let Inst{11-9} = 0b101;
1306 let Inst{8} = 0; // Single precision
1308 // Loads & stores operate on both NEON and VFP pipelines.
1309 let D = VFPNeonDomain;
1312 // VFP Load / store multiple pseudo instructions.
1313 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1315 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1317 let OutOperandList = oops;
1318 let InOperandList = !con(iops, (ins pred:$p));
1319 let Pattern = pattern;
1320 list<Predicate> Predicates = [HasVFP2];
1323 // Load / store multiple
1324 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1325 string asm, string cstr, list<dag> pattern>
1326 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1327 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1328 // Instruction operands.
1332 // Encode instruction operands.
1333 let Inst{19-16} = Rn;
1334 let Inst{22} = regs{12};
1335 let Inst{15-12} = regs{11-8};
1336 let Inst{7-0} = regs{7-0};
1338 // TODO: Mark the instructions with the appropriate subtarget info.
1339 let Inst{27-25} = 0b110;
1340 let Inst{11-9} = 0b101;
1341 let Inst{8} = 1; // Double precision
1344 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1345 string asm, string cstr, list<dag> pattern>
1346 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1347 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1348 // Instruction operands.
1352 // Encode instruction operands.
1353 let Inst{19-16} = Rn;
1354 let Inst{22} = regs{8};
1355 let Inst{15-12} = regs{12-9};
1356 let Inst{7-0} = regs{7-0};
1358 // TODO: Mark the instructions with the appropriate subtarget info.
1359 let Inst{27-25} = 0b110;
1360 let Inst{11-9} = 0b101;
1361 let Inst{8} = 0; // Single precision
1364 // Double precision, unary
1365 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1366 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1367 string asm, list<dag> pattern>
1368 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1369 // Instruction operands.
1373 // Encode instruction operands.
1374 let Inst{3-0} = Dm{3-0};
1375 let Inst{5} = Dm{4};
1376 let Inst{15-12} = Dd{3-0};
1377 let Inst{22} = Dd{4};
1379 let Inst{27-23} = opcod1;
1380 let Inst{21-20} = opcod2;
1381 let Inst{19-16} = opcod3;
1382 let Inst{11-9} = 0b101;
1383 let Inst{8} = 1; // Double precision
1384 let Inst{7-6} = opcod4;
1385 let Inst{4} = opcod5;
1388 // Double precision, binary
1389 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1390 dag iops, InstrItinClass itin, string opc, string asm,
1392 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1393 // Instruction operands.
1398 // Encode instruction operands.
1399 let Inst{3-0} = Dm{3-0};
1400 let Inst{5} = Dm{4};
1401 let Inst{19-16} = Dn{3-0};
1402 let Inst{7} = Dn{4};
1403 let Inst{15-12} = Dd{3-0};
1404 let Inst{22} = Dd{4};
1406 let Inst{27-23} = opcod1;
1407 let Inst{21-20} = opcod2;
1408 let Inst{11-9} = 0b101;
1409 let Inst{8} = 1; // Double precision
1414 // Single precision, unary
1415 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1416 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1417 string asm, list<dag> pattern>
1418 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1419 // Instruction operands.
1423 // Encode instruction operands.
1424 let Inst{3-0} = Sm{4-1};
1425 let Inst{5} = Sm{0};
1426 let Inst{15-12} = Sd{4-1};
1427 let Inst{22} = Sd{0};
1429 let Inst{27-23} = opcod1;
1430 let Inst{21-20} = opcod2;
1431 let Inst{19-16} = opcod3;
1432 let Inst{11-9} = 0b101;
1433 let Inst{8} = 0; // Single precision
1434 let Inst{7-6} = opcod4;
1435 let Inst{4} = opcod5;
1438 // Single precision unary, if no NEON. Same as ASuI except not available if
1440 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1441 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1442 string asm, list<dag> pattern>
1443 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1445 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1448 // Single precision, binary
1449 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1450 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1451 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1452 // Instruction operands.
1457 // Encode instruction operands.
1458 let Inst{3-0} = Sm{4-1};
1459 let Inst{5} = Sm{0};
1460 let Inst{19-16} = Sn{4-1};
1461 let Inst{7} = Sn{0};
1462 let Inst{15-12} = Sd{4-1};
1463 let Inst{22} = Sd{0};
1465 let Inst{27-23} = opcod1;
1466 let Inst{21-20} = opcod2;
1467 let Inst{11-9} = 0b101;
1468 let Inst{8} = 0; // Single precision
1473 // Single precision binary, if no NEON. Same as ASbI except not available if
1475 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1476 dag iops, InstrItinClass itin, string opc, string asm,
1478 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1479 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1481 // Instruction operands.
1486 // Encode instruction operands.
1487 let Inst{3-0} = Sm{4-1};
1488 let Inst{5} = Sm{0};
1489 let Inst{19-16} = Sn{4-1};
1490 let Inst{7} = Sn{0};
1491 let Inst{15-12} = Sd{4-1};
1492 let Inst{22} = Sd{0};
1495 // VFP conversion instructions
1496 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1497 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1499 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1500 let Inst{27-23} = opcod1;
1501 let Inst{21-20} = opcod2;
1502 let Inst{19-16} = opcod3;
1503 let Inst{11-8} = opcod4;
1508 // VFP conversion between floating-point and fixed-point
1509 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1510 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1512 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1513 // size (fixed-point number): sx == 0 ? 16 : 32
1514 let Inst{7} = op5; // sx
1517 // VFP conversion instructions, if no NEON
1518 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1519 dag oops, dag iops, InstrItinClass itin,
1520 string opc, string asm, list<dag> pattern>
1521 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1523 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1526 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1527 InstrItinClass itin,
1528 string opc, string asm, list<dag> pattern>
1529 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1530 let Inst{27-20} = opcod1;
1531 let Inst{11-8} = opcod2;
1535 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1536 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1537 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1539 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1540 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1541 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1543 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1544 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1545 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1547 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1548 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1549 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1551 //===----------------------------------------------------------------------===//
1553 //===----------------------------------------------------------------------===//
1554 // ARM NEON Instruction templates.
1557 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1558 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1560 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1561 let OutOperandList = oops;
1562 let InOperandList = !con(iops, (ins pred:$p));
1563 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1564 let Pattern = pattern;
1565 list<Predicate> Predicates = [HasNEON];
1568 // Same as NeonI except it does not have a "data type" specifier.
1569 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1570 InstrItinClass itin, string opc, string asm, string cstr,
1572 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1573 let OutOperandList = oops;
1574 let InOperandList = !con(iops, (ins pred:$p));
1575 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1576 let Pattern = pattern;
1577 list<Predicate> Predicates = [HasNEON];
1580 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1581 dag oops, dag iops, InstrItinClass itin,
1582 string opc, string dt, string asm, string cstr, list<dag> pattern>
1583 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1585 let Inst{31-24} = 0b11110100;
1586 let Inst{23} = op23;
1587 let Inst{21-20} = op21_20;
1588 let Inst{11-8} = op11_8;
1589 let Inst{7-4} = op7_4;
1591 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1597 let Inst{22} = Vd{4};
1598 let Inst{15-12} = Vd{3-0};
1599 let Inst{19-16} = Rn{3-0};
1600 let Inst{3-0} = Rm{3-0};
1603 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1604 dag oops, dag iops, InstrItinClass itin,
1605 string opc, string dt, string asm, string cstr, list<dag> pattern>
1606 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1607 dt, asm, cstr, pattern> {
1611 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1612 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1614 let OutOperandList = oops;
1615 let InOperandList = !con(iops, (ins pred:$p));
1616 list<Predicate> Predicates = [HasNEON];
1619 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1621 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1623 let OutOperandList = oops;
1624 let InOperandList = !con(iops, (ins pred:$p));
1625 let Pattern = pattern;
1626 list<Predicate> Predicates = [HasNEON];
1629 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1630 string opc, string dt, string asm, string cstr, list<dag> pattern>
1631 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1633 let Inst{31-25} = 0b1111001;
1634 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1637 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1638 string opc, string asm, string cstr, list<dag> pattern>
1639 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1641 let Inst{31-25} = 0b1111001;
1642 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1645 // NEON "one register and a modified immediate" format.
1646 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1648 dag oops, dag iops, InstrItinClass itin,
1649 string opc, string dt, string asm, string cstr,
1651 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1652 let Inst{23} = op23;
1653 let Inst{21-19} = op21_19;
1654 let Inst{11-8} = op11_8;
1660 // Instruction operands.
1664 let Inst{15-12} = Vd{3-0};
1665 let Inst{22} = Vd{4};
1666 let Inst{24} = SIMM{7};
1667 let Inst{18-16} = SIMM{6-4};
1668 let Inst{3-0} = SIMM{3-0};
1671 // NEON 2 vector register format.
1672 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1673 bits<5> op11_7, bit op6, bit op4,
1674 dag oops, dag iops, InstrItinClass itin,
1675 string opc, string dt, string asm, string cstr, list<dag> pattern>
1676 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1677 let Inst{24-23} = op24_23;
1678 let Inst{21-20} = op21_20;
1679 let Inst{19-18} = op19_18;
1680 let Inst{17-16} = op17_16;
1681 let Inst{11-7} = op11_7;
1685 // Instruction operands.
1689 let Inst{15-12} = Vd{3-0};
1690 let Inst{22} = Vd{4};
1691 let Inst{3-0} = Vm{3-0};
1692 let Inst{5} = Vm{4};
1695 // Same as N2V except it doesn't have a datatype suffix.
1696 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1697 bits<5> op11_7, bit op6, bit op4,
1698 dag oops, dag iops, InstrItinClass itin,
1699 string opc, string asm, string cstr, list<dag> pattern>
1700 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1701 let Inst{24-23} = op24_23;
1702 let Inst{21-20} = op21_20;
1703 let Inst{19-18} = op19_18;
1704 let Inst{17-16} = op17_16;
1705 let Inst{11-7} = op11_7;
1709 // Instruction operands.
1713 let Inst{15-12} = Vd{3-0};
1714 let Inst{22} = Vd{4};
1715 let Inst{3-0} = Vm{3-0};
1716 let Inst{5} = Vm{4};
1719 // NEON 2 vector register with immediate.
1720 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1721 dag oops, dag iops, Format f, InstrItinClass itin,
1722 string opc, string dt, string asm, string cstr, list<dag> pattern>
1723 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1724 let Inst{24} = op24;
1725 let Inst{23} = op23;
1726 let Inst{11-8} = op11_8;
1731 // Instruction operands.
1736 let Inst{15-12} = Vd{3-0};
1737 let Inst{22} = Vd{4};
1738 let Inst{3-0} = Vm{3-0};
1739 let Inst{5} = Vm{4};
1740 let Inst{21-16} = SIMM{5-0};
1743 // NEON 3 vector register format.
1745 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1746 dag oops, dag iops, Format f, InstrItinClass itin,
1747 string opc, string dt, string asm, string cstr, list<dag> pattern>
1748 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1749 let Inst{24} = op24;
1750 let Inst{23} = op23;
1751 let Inst{21-20} = op21_20;
1752 let Inst{11-8} = op11_8;
1757 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1758 dag oops, dag iops, Format f, InstrItinClass itin,
1759 string opc, string dt, string asm, string cstr, list<dag> pattern>
1760 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1761 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1763 // Instruction operands.
1768 let Inst{15-12} = Vd{3-0};
1769 let Inst{22} = Vd{4};
1770 let Inst{19-16} = Vn{3-0};
1771 let Inst{7} = Vn{4};
1772 let Inst{3-0} = Vm{3-0};
1773 let Inst{5} = Vm{4};
1776 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1777 dag oops, dag iops, Format f, InstrItinClass itin,
1778 string opc, string dt, string asm, string cstr, list<dag> pattern>
1779 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1780 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1782 // Instruction operands.
1788 let Inst{15-12} = Vd{3-0};
1789 let Inst{22} = Vd{4};
1790 let Inst{19-16} = Vn{3-0};
1791 let Inst{7} = Vn{4};
1792 let Inst{3-0} = Vm{3-0};
1796 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1797 dag oops, dag iops, Format f, InstrItinClass itin,
1798 string opc, string dt, string asm, string cstr, list<dag> pattern>
1799 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1800 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1802 // Instruction operands.
1808 let Inst{15-12} = Vd{3-0};
1809 let Inst{22} = Vd{4};
1810 let Inst{19-16} = Vn{3-0};
1811 let Inst{7} = Vn{4};
1812 let Inst{2-0} = Vm{2-0};
1813 let Inst{5} = lane{1};
1814 let Inst{3} = lane{0};
1817 // Same as N3V except it doesn't have a data type suffix.
1818 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1820 dag oops, dag iops, Format f, InstrItinClass itin,
1821 string opc, string asm, string cstr, list<dag> pattern>
1822 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1823 let Inst{24} = op24;
1824 let Inst{23} = op23;
1825 let Inst{21-20} = op21_20;
1826 let Inst{11-8} = op11_8;
1830 // Instruction operands.
1835 let Inst{15-12} = Vd{3-0};
1836 let Inst{22} = Vd{4};
1837 let Inst{19-16} = Vn{3-0};
1838 let Inst{7} = Vn{4};
1839 let Inst{3-0} = Vm{3-0};
1840 let Inst{5} = Vm{4};
1843 // NEON VMOVs between scalar and core registers.
1844 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1845 dag oops, dag iops, Format f, InstrItinClass itin,
1846 string opc, string dt, string asm, list<dag> pattern>
1847 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1849 let Inst{27-20} = opcod1;
1850 let Inst{11-8} = opcod2;
1851 let Inst{6-5} = opcod3;
1853 // A8.6.303, A8.6.328, A8.6.329
1854 let Inst{3-0} = 0b0000;
1856 let OutOperandList = oops;
1857 let InOperandList = !con(iops, (ins pred:$p));
1858 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1859 let Pattern = pattern;
1860 list<Predicate> Predicates = [HasNEON];
1862 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1869 let Inst{31-28} = p{3-0};
1871 let Inst{19-16} = V{3-0};
1872 let Inst{15-12} = R{3-0};
1874 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1875 dag oops, dag iops, InstrItinClass itin,
1876 string opc, string dt, string asm, list<dag> pattern>
1877 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1878 opc, dt, asm, pattern>;
1879 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1880 dag oops, dag iops, InstrItinClass itin,
1881 string opc, string dt, string asm, list<dag> pattern>
1882 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1883 opc, dt, asm, pattern>;
1884 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1885 dag oops, dag iops, InstrItinClass itin,
1886 string opc, string dt, string asm, list<dag> pattern>
1887 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1888 opc, dt, asm, pattern>;
1890 // Vector Duplicate Lane (from scalar to all elements)
1891 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1892 InstrItinClass itin, string opc, string dt, string asm,
1894 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1895 let Inst{24-23} = 0b11;
1896 let Inst{21-20} = 0b11;
1897 let Inst{19-16} = op19_16;
1898 let Inst{11-7} = 0b11000;
1906 let Inst{22} = Vd{4};
1907 let Inst{15-12} = Vd{3-0};
1908 let Inst{5} = Vm{4};
1909 let Inst{3-0} = Vm{3-0};
1912 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1913 // for single-precision FP.
1914 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1915 list<Predicate> Predicates = [HasNEON,UseNEONForFP];