1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
157 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
158 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
159 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
160 let EncoderMethod = "getCCOutOpValue";
161 let PrintMethod = "printSBitModifierOperand";
162 let ParserMatchClass = CCOutOperand;
165 // Same as cc_out except it defaults to setting CPSR.
166 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
167 let EncoderMethod = "getCCOutOpValue";
168 let PrintMethod = "printSBitModifierOperand";
169 let ParserMatchClass = CCOutOperand;
172 // ARM special operands for disassembly only.
174 def SetEndAsmOperand : AsmOperandClass {
175 let Name = "SetEndImm";
176 let ParserMethod = "parseSetEndImm";
178 def setend_op : Operand<i32> {
179 let PrintMethod = "printSetendOperand";
180 let ParserMatchClass = SetEndAsmOperand;
183 def MSRMaskOperand : AsmOperandClass {
184 let Name = "MSRMask";
185 let ParserMethod = "parseMSRMaskOperand";
187 def msr_mask : Operand<i32> {
188 let PrintMethod = "printMSRMaskOperand";
189 let ParserMatchClass = MSRMaskOperand;
192 // Shift Right Immediate - A shift right immediate is encoded differently from
193 // other shift immediates. The imm6 field is encoded like so:
196 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
197 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
198 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
199 // 64 64 - <imm> is encoded in imm6<5:0>
200 def shr_imm8 : Operand<i32> {
201 let EncoderMethod = "getShiftRight8Imm";
203 def shr_imm16 : Operand<i32> {
204 let EncoderMethod = "getShiftRight16Imm";
206 def shr_imm32 : Operand<i32> {
207 let EncoderMethod = "getShiftRight32Imm";
209 def shr_imm64 : Operand<i32> {
210 let EncoderMethod = "getShiftRight64Imm";
213 //===----------------------------------------------------------------------===//
214 // ARM Instruction templates.
217 class InstTemplate<AddrMode am, int sz, IndexMode im,
218 Format f, Domain d, string cstr, InstrItinClass itin>
220 let Namespace = "ARM";
225 bits<2> IndexModeBits = IM.Value;
227 bits<6> Form = F.Value;
229 bit isUnaryDataProc = 0;
230 bit canXformTo16Bit = 0;
232 // If this is a pseudo instruction, mark it isCodeGenOnly.
233 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
235 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
236 let TSFlags{4-0} = AM.Value;
237 let TSFlags{6-5} = IndexModeBits;
238 let TSFlags{12-7} = Form;
239 let TSFlags{13} = isUnaryDataProc;
240 let TSFlags{14} = canXformTo16Bit;
241 let TSFlags{17-15} = D.Value;
243 let Constraints = cstr;
244 let Itinerary = itin;
251 class InstARM<AddrMode am, int sz, IndexMode im,
252 Format f, Domain d, string cstr, InstrItinClass itin>
253 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
254 let DecoderNamespace = "ARM";
257 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
258 // on by adding flavors to specific instructions.
259 class InstThumb<AddrMode am, int sz, IndexMode im,
260 Format f, Domain d, string cstr, InstrItinClass itin>
261 : InstTemplate<am, sz, im, f, d, cstr, itin> {
262 let DecoderNamespace = "Thumb";
265 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
266 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
267 GenericDomain, "", itin> {
268 let OutOperandList = oops;
269 let InOperandList = iops;
270 let Pattern = pattern;
271 let isCodeGenOnly = 1;
275 // PseudoInst that's ARM-mode only.
276 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
278 : PseudoInst<oops, iops, itin, pattern> {
280 list<Predicate> Predicates = [IsARM];
283 // PseudoInst that's Thumb-mode only.
284 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
286 : PseudoInst<oops, iops, itin, pattern> {
288 list<Predicate> Predicates = [IsThumb];
291 // PseudoInst that's Thumb2-mode only.
292 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
294 : PseudoInst<oops, iops, itin, pattern> {
296 list<Predicate> Predicates = [IsThumb2];
299 class ARMPseudoExpand<dag oops, dag iops, int sz,
300 InstrItinClass itin, list<dag> pattern,
302 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
303 PseudoInstExpansion<Result>;
305 class tPseudoExpand<dag oops, dag iops, int sz,
306 InstrItinClass itin, list<dag> pattern,
308 : tPseudoInst<oops, iops, sz, itin, pattern>,
309 PseudoInstExpansion<Result>;
311 class t2PseudoExpand<dag oops, dag iops, int sz,
312 InstrItinClass itin, list<dag> pattern,
314 : t2PseudoInst<oops, iops, sz, itin, pattern>,
315 PseudoInstExpansion<Result>;
317 // Almost all ARM instructions are predicable.
318 class I<dag oops, dag iops, AddrMode am, int sz,
319 IndexMode im, Format f, InstrItinClass itin,
320 string opc, string asm, string cstr,
322 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
325 let OutOperandList = oops;
326 let InOperandList = !con(iops, (ins pred:$p));
327 let AsmString = !strconcat(opc, "${p}", asm);
328 let Pattern = pattern;
329 list<Predicate> Predicates = [IsARM];
332 // A few are not predicable
333 class InoP<dag oops, dag iops, AddrMode am, int sz,
334 IndexMode im, Format f, InstrItinClass itin,
335 string opc, string asm, string cstr,
337 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
338 let OutOperandList = oops;
339 let InOperandList = iops;
340 let AsmString = !strconcat(opc, asm);
341 let Pattern = pattern;
342 let isPredicable = 0;
343 list<Predicate> Predicates = [IsARM];
346 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
347 // operand since by default it's a zero register. It will become an implicit def
348 // once it's "flipped".
349 class sI<dag oops, dag iops, AddrMode am, int sz,
350 IndexMode im, Format f, InstrItinClass itin,
351 string opc, string asm, string cstr,
353 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
354 bits<4> p; // Predicate operand
355 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
359 let OutOperandList = oops;
360 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
361 let AsmString = !strconcat(opc, "${s}${p}", asm);
362 let Pattern = pattern;
363 list<Predicate> Predicates = [IsARM];
367 class XI<dag oops, dag iops, AddrMode am, int sz,
368 IndexMode im, Format f, InstrItinClass itin,
369 string asm, string cstr, list<dag> pattern>
370 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
371 let OutOperandList = oops;
372 let InOperandList = iops;
374 let Pattern = pattern;
375 list<Predicate> Predicates = [IsARM];
378 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
379 string opc, string asm, list<dag> pattern>
380 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
381 opc, asm, "", pattern>;
382 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
383 string opc, string asm, list<dag> pattern>
384 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
385 opc, asm, "", pattern>;
386 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
387 string asm, list<dag> pattern>
388 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
390 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
393 opc, asm, "", pattern>;
395 // Ctrl flow instructions
396 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
397 string opc, string asm, list<dag> pattern>
398 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
399 opc, asm, "", pattern> {
400 let Inst{27-24} = opcod;
402 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
403 string asm, list<dag> pattern>
404 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
406 let Inst{27-24} = opcod;
409 // BR_JT instructions
410 class JTI<dag oops, dag iops, InstrItinClass itin,
411 string asm, list<dag> pattern>
412 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
415 // Atomic load/store instructions
416 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
417 string opc, string asm, list<dag> pattern>
418 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
419 opc, asm, "", pattern> {
422 let Inst{27-23} = 0b00011;
423 let Inst{22-21} = opcod;
425 let Inst{19-16} = Rn;
426 let Inst{15-12} = Rt;
427 let Inst{11-0} = 0b111110011111;
429 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
430 string opc, string asm, list<dag> pattern>
431 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
432 opc, asm, "", pattern> {
436 let Inst{27-23} = 0b00011;
437 let Inst{22-21} = opcod;
439 let Inst{19-16} = addr;
440 let Inst{15-12} = Rd;
441 let Inst{11-4} = 0b11111001;
444 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
445 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
449 let Inst{27-23} = 0b00010;
451 let Inst{21-20} = 0b00;
452 let Inst{19-16} = Rn;
453 let Inst{15-12} = Rt;
454 let Inst{11-4} = 0b00001001;
458 // addrmode1 instructions
459 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
460 string opc, string asm, list<dag> pattern>
461 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
462 opc, asm, "", pattern> {
463 let Inst{24-21} = opcod;
464 let Inst{27-26} = 0b00;
466 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
467 string opc, string asm, list<dag> pattern>
468 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
469 opc, asm, "", pattern> {
470 let Inst{24-21} = opcod;
471 let Inst{27-26} = 0b00;
473 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
474 string asm, list<dag> pattern>
475 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
477 let Inst{24-21} = opcod;
478 let Inst{27-26} = 0b00;
483 // LDR/LDRB/STR/STRB/...
484 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
485 Format f, InstrItinClass itin, string opc, string asm,
487 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
489 let Inst{27-25} = op;
490 let Inst{24} = 1; // 24 == P
492 let Inst{22} = isByte;
493 let Inst{21} = 0; // 21 == W
496 // Indexed load/stores
497 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
498 IndexMode im, Format f, InstrItinClass itin, string opc,
499 string asm, string cstr, list<dag> pattern>
500 : I<oops, iops, AddrMode2, 4, im, f, itin,
501 opc, asm, cstr, pattern> {
503 let Inst{27-26} = 0b01;
504 let Inst{24} = isPre; // P bit
505 let Inst{22} = isByte; // B bit
506 let Inst{21} = isPre; // W bit
507 let Inst{20} = isLd; // L bit
508 let Inst{15-12} = Rt;
510 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
511 IndexMode im, Format f, InstrItinClass itin, string opc,
512 string asm, string cstr, list<dag> pattern>
513 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
515 // AM2 store w/ two operands: (GPR, am2offset)
516 // {13} 1 == Rm, 0 == imm12
521 let Inst{25} = offset{13};
522 let Inst{23} = offset{12};
523 let Inst{19-16} = Rn;
524 let Inst{11-0} = offset{11-0};
526 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
527 // but for now use this class for STRT and STRBT.
528 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
529 IndexMode im, Format f, InstrItinClass itin, string opc,
530 string asm, string cstr, list<dag> pattern>
531 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
533 // AM2 store w/ two operands: (GPR, am2offset)
535 // {13} 1 == Rm, 0 == imm12
539 let Inst{25} = addr{13};
540 let Inst{23} = addr{12};
541 let Inst{19-16} = addr{17-14};
542 let Inst{11-0} = addr{11-0};
545 // addrmode3 instructions
546 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
547 InstrItinClass itin, string opc, string asm, list<dag> pattern>
548 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
549 opc, asm, "", pattern> {
552 let Inst{27-25} = 0b000;
553 let Inst{24} = 1; // P bit
554 let Inst{23} = addr{8}; // U bit
555 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
556 let Inst{21} = 0; // W bit
557 let Inst{20} = op20; // L bit
558 let Inst{19-16} = addr{12-9}; // Rn
559 let Inst{15-12} = Rt; // Rt
560 let Inst{11-8} = addr{7-4}; // imm7_4/zero
562 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
565 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
566 IndexMode im, Format f, InstrItinClass itin, string opc,
567 string asm, string cstr, list<dag> pattern>
568 : I<oops, iops, AddrMode3, 4, im, f, itin,
569 opc, asm, cstr, pattern> {
571 let Inst{27-25} = 0b000;
572 let Inst{24} = isPre; // P bit
573 let Inst{21} = isPre; // W bit
574 let Inst{20} = op20; // L bit
575 let Inst{15-12} = Rt; // Rt
579 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
580 // but for now use this class for LDRSBT, LDRHT, LDSHT.
581 class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
582 IndexMode im, Format f, InstrItinClass itin, string opc,
583 string asm, string cstr, list<dag> pattern>
584 : I<oops, iops, AddrMode3, 4, im, f, itin,
585 opc, asm, cstr, pattern> {
586 // {13} 1 == imm8, 0 == Rm
593 let Inst{27-25} = 0b000;
594 let Inst{24} = isPre; // P bit
595 let Inst{23} = addr{8}; // U bit
596 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
597 let Inst{20} = op20; // L bit
598 let Inst{19-16} = addr{12-9}; // Rn
599 let Inst{15-12} = Rt; // Rt
600 let Inst{11-8} = addr{7-4}; // imm7_4/zero
602 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
603 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
606 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
607 IndexMode im, Format f, InstrItinClass itin, string opc,
608 string asm, string cstr, list<dag> pattern>
609 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
611 // AM3 store w/ two operands: (GPR, am3offset)
615 let Inst{27-25} = 0b000;
616 let Inst{23} = offset{8};
617 let Inst{22} = offset{9};
618 let Inst{19-16} = Rn;
619 let Inst{15-12} = Rt; // Rt
620 let Inst{11-8} = offset{7-4}; // imm7_4/zero
622 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
626 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
627 string opc, string asm, list<dag> pattern>
628 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
629 opc, asm, "", pattern> {
632 let Inst{27-25} = 0b000;
633 let Inst{24} = 1; // P bit
634 let Inst{23} = addr{8}; // U bit
635 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
636 let Inst{21} = 0; // W bit
637 let Inst{20} = 0; // L bit
638 let Inst{19-16} = addr{12-9}; // Rn
639 let Inst{15-12} = Rt; // Rt
640 let Inst{11-8} = addr{7-4}; // imm7_4/zero
642 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
645 // Pre-indexed stores
646 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
647 string opc, string asm, string cstr, list<dag> pattern>
648 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
649 opc, asm, cstr, pattern> {
651 let Inst{5} = 1; // H bit
652 let Inst{6} = 0; // S bit
654 let Inst{20} = 0; // L bit
655 let Inst{21} = 1; // W bit
656 let Inst{24} = 1; // P bit
657 let Inst{27-25} = 0b000;
659 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
660 string opc, string asm, string cstr, list<dag> pattern>
661 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
662 opc, asm, cstr, pattern> {
664 let Inst{5} = 1; // H bit
665 let Inst{6} = 1; // S bit
667 let Inst{20} = 0; // L bit
668 let Inst{21} = 1; // W bit
669 let Inst{24} = 1; // P bit
670 let Inst{27-25} = 0b000;
673 // Post-indexed stores
674 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
675 string opc, string asm, string cstr, list<dag> pattern>
676 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin,
677 opc, asm, cstr,pattern> {
678 // {13} 1 == imm8, 0 == Rm
685 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
687 let Inst{5} = 1; // H bit
688 let Inst{6} = 0; // S bit
690 let Inst{11-8} = addr{7-4}; // imm7_4/zero
691 let Inst{15-12} = Rt; // Rt
692 let Inst{19-16} = addr{12-9}; // Rn
693 let Inst{20} = 0; // L bit
694 let Inst{21} = 0; // W bit
695 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
696 let Inst{23} = addr{8}; // U bit
697 let Inst{24} = 0; // P bit
698 let Inst{27-25} = 0b000;
700 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
701 string opc, string asm, string cstr, list<dag> pattern>
702 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin,
703 opc, asm, cstr, pattern> {
705 let Inst{5} = 1; // H bit
706 let Inst{6} = 1; // S bit
708 let Inst{20} = 0; // L bit
709 let Inst{21} = 0; // W bit
710 let Inst{24} = 0; // P bit
711 let Inst{27-25} = 0b000;
714 // addrmode4 instructions
715 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
716 string asm, string cstr, list<dag> pattern>
717 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
722 let Inst{27-25} = 0b100;
723 let Inst{22} = 0; // S bit
724 let Inst{19-16} = Rn;
725 let Inst{15-0} = regs;
728 // Unsigned multiply, multiply-accumulate instructions.
729 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
730 string opc, string asm, list<dag> pattern>
731 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
732 opc, asm, "", pattern> {
733 let Inst{7-4} = 0b1001;
734 let Inst{20} = 0; // S bit
735 let Inst{27-21} = opcod;
737 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
738 string opc, string asm, list<dag> pattern>
739 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
740 opc, asm, "", pattern> {
741 let Inst{7-4} = 0b1001;
742 let Inst{27-21} = opcod;
745 // Most significant word multiply
746 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
747 InstrItinClass itin, string opc, string asm, list<dag> pattern>
748 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
749 opc, asm, "", pattern> {
753 let Inst{7-4} = opc7_4;
755 let Inst{27-21} = opcod;
756 let Inst{19-16} = Rd;
760 // MSW multiple w/ Ra operand
761 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
762 InstrItinClass itin, string opc, string asm, list<dag> pattern>
763 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
765 let Inst{15-12} = Ra;
768 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
769 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
770 InstrItinClass itin, string opc, string asm, list<dag> pattern>
771 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
772 opc, asm, "", pattern> {
778 let Inst{27-21} = opcod;
779 let Inst{6-5} = bit6_5;
783 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
784 InstrItinClass itin, string opc, string asm, list<dag> pattern>
785 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
787 let Inst{19-16} = Rd;
790 // AMulxyI with Ra operand
791 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
792 InstrItinClass itin, string opc, string asm, list<dag> pattern>
793 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
795 let Inst{15-12} = Ra;
798 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
799 InstrItinClass itin, string opc, string asm, list<dag> pattern>
800 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
803 let Inst{19-16} = RdHi;
804 let Inst{15-12} = RdLo;
807 // Extend instructions.
808 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
811 opc, asm, "", pattern> {
812 // All AExtI instructions have Rd and Rm register operands.
815 let Inst{15-12} = Rd;
817 let Inst{7-4} = 0b0111;
818 let Inst{9-8} = 0b00;
819 let Inst{27-20} = opcod;
822 // Misc Arithmetic instructions.
823 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
824 InstrItinClass itin, string opc, string asm, list<dag> pattern>
825 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
826 opc, asm, "", pattern> {
829 let Inst{27-20} = opcod;
830 let Inst{19-16} = 0b1111;
831 let Inst{15-12} = Rd;
832 let Inst{11-8} = 0b1111;
833 let Inst{7-4} = opc7_4;
838 def PKHLSLAsmOperand : AsmOperandClass {
839 let Name = "PKHLSLImm";
840 let ParserMethod = "parsePKHLSLImm";
842 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
843 let PrintMethod = "printPKHLSLShiftImm";
844 let ParserMatchClass = PKHLSLAsmOperand;
846 def PKHASRAsmOperand : AsmOperandClass {
847 let Name = "PKHASRImm";
848 let ParserMethod = "parsePKHASRImm";
850 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
851 let PrintMethod = "printPKHASRShiftImm";
852 let ParserMatchClass = PKHASRAsmOperand;
855 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
856 string opc, string asm, list<dag> pattern>
857 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
858 opc, asm, "", pattern> {
863 let Inst{27-20} = opcod;
864 let Inst{19-16} = Rn;
865 let Inst{15-12} = Rd;
868 let Inst{5-4} = 0b01;
872 //===----------------------------------------------------------------------===//
874 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
875 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
876 list<Predicate> Predicates = [IsARM];
878 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
879 list<Predicate> Predicates = [IsARM, HasV5T];
881 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
882 list<Predicate> Predicates = [IsARM, HasV5TE];
884 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
885 list<Predicate> Predicates = [IsARM, HasV6];
888 //===----------------------------------------------------------------------===//
889 // Thumb Instruction Format Definitions.
892 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
893 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
894 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
895 let OutOperandList = oops;
896 let InOperandList = iops;
898 let Pattern = pattern;
899 list<Predicate> Predicates = [IsThumb];
902 // TI - Thumb instruction.
903 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
904 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
906 // Two-address instructions
907 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
909 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
912 // tBL, tBX 32-bit instructions
913 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
914 dag oops, dag iops, InstrItinClass itin, string asm,
916 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
918 let Inst{31-27} = opcod1;
919 let Inst{15-14} = opcod2;
920 let Inst{12} = opcod3;
923 // BR_JT instructions
924 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
926 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
929 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
930 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
931 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
932 let OutOperandList = oops;
933 let InOperandList = iops;
935 let Pattern = pattern;
936 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
939 class T1I<dag oops, dag iops, InstrItinClass itin,
940 string asm, list<dag> pattern>
941 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
942 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
943 string asm, list<dag> pattern>
944 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
946 // Two-address instructions
947 class T1It<dag oops, dag iops, InstrItinClass itin,
948 string asm, string cstr, list<dag> pattern>
949 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
952 // Thumb1 instruction that can either be predicated or set CPSR.
953 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
955 string opc, string asm, string cstr, list<dag> pattern>
956 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
957 let OutOperandList = !con(oops, (outs s_cc_out:$s));
958 let InOperandList = !con(iops, (ins pred:$p));
959 let AsmString = !strconcat(opc, "${s}${p}", asm);
960 let Pattern = pattern;
961 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
964 class T1sI<dag oops, dag iops, InstrItinClass itin,
965 string opc, string asm, list<dag> pattern>
966 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
968 // Two-address instructions
969 class T1sIt<dag oops, dag iops, InstrItinClass itin,
970 string opc, string asm, list<dag> pattern>
971 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
972 "$Rn = $Rdn", pattern>;
974 // Thumb1 instruction that can be predicated.
975 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
977 string opc, string asm, string cstr, list<dag> pattern>
978 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
979 let OutOperandList = oops;
980 let InOperandList = !con(iops, (ins pred:$p));
981 let AsmString = !strconcat(opc, "${p}", asm);
982 let Pattern = pattern;
983 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
986 class T1pI<dag oops, dag iops, InstrItinClass itin,
987 string opc, string asm, list<dag> pattern>
988 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
990 // Two-address instructions
991 class T1pIt<dag oops, dag iops, InstrItinClass itin,
992 string opc, string asm, list<dag> pattern>
993 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
994 "$Rn = $Rdn", pattern>;
996 class T1pIs<dag oops, dag iops,
997 InstrItinClass itin, string opc, string asm, list<dag> pattern>
998 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1000 class Encoding16 : Encoding {
1001 let Inst{31-16} = 0x0000;
1004 // A6.2 16-bit Thumb instruction encoding
1005 class T1Encoding<bits<6> opcode> : Encoding16 {
1006 let Inst{15-10} = opcode;
1009 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1010 class T1General<bits<5> opcode> : Encoding16 {
1011 let Inst{15-14} = 0b00;
1012 let Inst{13-9} = opcode;
1015 // A6.2.2 Data-processing encoding.
1016 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1017 let Inst{15-10} = 0b010000;
1018 let Inst{9-6} = opcode;
1021 // A6.2.3 Special data instructions and branch and exchange encoding.
1022 class T1Special<bits<4> opcode> : Encoding16 {
1023 let Inst{15-10} = 0b010001;
1024 let Inst{9-6} = opcode;
1027 // A6.2.4 Load/store single data item encoding.
1028 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1029 let Inst{15-12} = opA;
1030 let Inst{11-9} = opB;
1032 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1034 class T1BranchCond<bits<4> opcode> : Encoding16 {
1035 let Inst{15-12} = opcode;
1038 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1039 // following bits are used for "opA" (see A6.2.4):
1041 // 0b0110 => Immediate, 4 bytes
1042 // 0b1000 => Immediate, 2 bytes
1043 // 0b0111 => Immediate, 1 byte
1044 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1045 InstrItinClass itin, string opc, string asm,
1047 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1048 T1LoadStore<0b0101, opcode> {
1051 let Inst{8-6} = addr{5-3}; // Rm
1052 let Inst{5-3} = addr{2-0}; // Rn
1055 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1056 InstrItinClass itin, string opc, string asm,
1058 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1059 T1LoadStore<opA, {opB,?,?}> {
1062 let Inst{10-6} = addr{7-3}; // imm5
1063 let Inst{5-3} = addr{2-0}; // Rn
1067 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1068 class T1Misc<bits<7> opcode> : Encoding16 {
1069 let Inst{15-12} = 0b1011;
1070 let Inst{11-5} = opcode;
1073 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1074 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1075 InstrItinClass itin,
1076 string opc, string asm, string cstr, list<dag> pattern>
1077 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1078 let OutOperandList = oops;
1079 let InOperandList = !con(iops, (ins pred:$p));
1080 let AsmString = !strconcat(opc, "${p}", asm);
1081 let Pattern = pattern;
1082 list<Predicate> Predicates = [IsThumb2];
1083 let DecoderNamespace = "Thumb2";
1086 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1087 // input operand since by default it's a zero register. It will become an
1088 // implicit def once it's "flipped".
1090 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1092 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1093 InstrItinClass itin,
1094 string opc, string asm, string cstr, list<dag> pattern>
1095 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1096 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1099 let OutOperandList = oops;
1100 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1101 let AsmString = !strconcat(opc, "${s}${p}", asm);
1102 let Pattern = pattern;
1103 list<Predicate> Predicates = [IsThumb2];
1104 let DecoderNamespace = "Thumb2";
1108 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1109 InstrItinClass itin,
1110 string asm, string cstr, list<dag> pattern>
1111 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1112 let OutOperandList = oops;
1113 let InOperandList = iops;
1114 let AsmString = asm;
1115 let Pattern = pattern;
1116 list<Predicate> Predicates = [IsThumb2];
1117 let DecoderNamespace = "Thumb2";
1120 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1121 InstrItinClass itin,
1122 string asm, string cstr, list<dag> pattern>
1123 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1124 let OutOperandList = oops;
1125 let InOperandList = iops;
1126 let AsmString = asm;
1127 let Pattern = pattern;
1128 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1129 let DecoderNamespace = "Thumb";
1132 class T2I<dag oops, dag iops, InstrItinClass itin,
1133 string opc, string asm, list<dag> pattern>
1134 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1135 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1136 string opc, string asm, list<dag> pattern>
1137 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1138 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1139 string opc, string asm, list<dag> pattern>
1140 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1141 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1142 string opc, string asm, list<dag> pattern>
1143 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1144 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1145 string opc, string asm, list<dag> pattern>
1146 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1147 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1148 string opc, string asm, list<dag> pattern>
1149 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "",
1154 let Inst{31-25} = 0b1110100;
1156 let Inst{23} = addr{8};
1159 let Inst{20} = isLoad;
1160 let Inst{19-16} = addr{12-9};
1161 let Inst{15-12} = Rt{3-0};
1162 let Inst{11-8} = Rt2{3-0};
1163 let Inst{7-0} = addr{7-0};
1166 class T2sI<dag oops, dag iops, InstrItinClass itin,
1167 string opc, string asm, list<dag> pattern>
1168 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1170 class T2XI<dag oops, dag iops, InstrItinClass itin,
1171 string asm, list<dag> pattern>
1172 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1173 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1174 string asm, list<dag> pattern>
1175 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1177 // Move to/from coprocessor instructions
1178 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1179 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1180 let Inst{31-28} = opc;
1183 // Two-address instructions
1184 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1185 string asm, string cstr, list<dag> pattern>
1186 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1188 // T2Iidxldst - Thumb2 indexed load / store instructions.
1189 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1191 AddrMode am, IndexMode im, InstrItinClass itin,
1192 string opc, string asm, string cstr, list<dag> pattern>
1193 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1194 let OutOperandList = oops;
1195 let InOperandList = !con(iops, (ins pred:$p));
1196 let AsmString = !strconcat(opc, "${p}", asm);
1197 let Pattern = pattern;
1198 list<Predicate> Predicates = [IsThumb2];
1199 let DecoderNamespace = "Thumb2";
1200 let Inst{31-27} = 0b11111;
1201 let Inst{26-25} = 0b00;
1202 let Inst{24} = signed;
1204 let Inst{22-21} = opcod;
1205 let Inst{20} = load;
1207 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1208 let Inst{10} = pre; // The P bit.
1209 let Inst{8} = 1; // The W bit.
1212 let Inst{7-0} = addr{7-0};
1213 let Inst{9} = addr{8}; // Sign bit
1217 let Inst{15-12} = Rt{3-0};
1218 let Inst{19-16} = Rn{3-0};
1221 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1222 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1223 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1226 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1227 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1228 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1231 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1232 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1233 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1236 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1237 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1238 list<Predicate> Predicates = [IsThumb2];
1241 //===----------------------------------------------------------------------===//
1243 //===----------------------------------------------------------------------===//
1244 // ARM VFP Instruction templates.
1247 // Almost all VFP instructions are predicable.
1248 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1249 IndexMode im, Format f, InstrItinClass itin,
1250 string opc, string asm, string cstr, list<dag> pattern>
1251 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1253 let Inst{31-28} = p;
1254 let OutOperandList = oops;
1255 let InOperandList = !con(iops, (ins pred:$p));
1256 let AsmString = !strconcat(opc, "${p}", asm);
1257 let Pattern = pattern;
1258 let PostEncoderMethod = "VFPThumb2PostEncoder";
1259 list<Predicate> Predicates = [HasVFP2];
1263 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1264 IndexMode im, Format f, InstrItinClass itin,
1265 string asm, string cstr, list<dag> pattern>
1266 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1268 let Inst{31-28} = p;
1269 let OutOperandList = oops;
1270 let InOperandList = iops;
1271 let AsmString = asm;
1272 let Pattern = pattern;
1273 let PostEncoderMethod = "VFPThumb2PostEncoder";
1274 list<Predicate> Predicates = [HasVFP2];
1277 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1278 string opc, string asm, list<dag> pattern>
1279 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1280 opc, asm, "", pattern> {
1281 let PostEncoderMethod = "VFPThumb2PostEncoder";
1284 // ARM VFP addrmode5 loads and stores
1285 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1286 InstrItinClass itin,
1287 string opc, string asm, list<dag> pattern>
1288 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1289 VFPLdStFrm, itin, opc, asm, "", pattern> {
1290 // Instruction operands.
1294 // Encode instruction operands.
1295 let Inst{23} = addr{8}; // U (add = (U == '1'))
1296 let Inst{22} = Dd{4};
1297 let Inst{19-16} = addr{12-9}; // Rn
1298 let Inst{15-12} = Dd{3-0};
1299 let Inst{7-0} = addr{7-0}; // imm8
1301 // TODO: Mark the instructions with the appropriate subtarget info.
1302 let Inst{27-24} = opcod1;
1303 let Inst{21-20} = opcod2;
1304 let Inst{11-9} = 0b101;
1305 let Inst{8} = 1; // Double precision
1307 // Loads & stores operate on both NEON and VFP pipelines.
1308 let D = VFPNeonDomain;
1311 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1312 InstrItinClass itin,
1313 string opc, string asm, list<dag> pattern>
1314 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1315 VFPLdStFrm, itin, opc, asm, "", pattern> {
1316 // Instruction operands.
1320 // Encode instruction operands.
1321 let Inst{23} = addr{8}; // U (add = (U == '1'))
1322 let Inst{22} = Sd{0};
1323 let Inst{19-16} = addr{12-9}; // Rn
1324 let Inst{15-12} = Sd{4-1};
1325 let Inst{7-0} = addr{7-0}; // imm8
1327 // TODO: Mark the instructions with the appropriate subtarget info.
1328 let Inst{27-24} = opcod1;
1329 let Inst{21-20} = opcod2;
1330 let Inst{11-9} = 0b101;
1331 let Inst{8} = 0; // Single precision
1333 // Loads & stores operate on both NEON and VFP pipelines.
1334 let D = VFPNeonDomain;
1337 // VFP Load / store multiple pseudo instructions.
1338 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1340 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1342 let OutOperandList = oops;
1343 let InOperandList = !con(iops, (ins pred:$p));
1344 let Pattern = pattern;
1345 list<Predicate> Predicates = [HasVFP2];
1348 // Load / store multiple
1349 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1350 string asm, string cstr, list<dag> pattern>
1351 : VFPXI<oops, iops, AddrMode4, 4, im,
1352 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1353 // Instruction operands.
1357 // Encode instruction operands.
1358 let Inst{19-16} = Rn;
1359 let Inst{22} = regs{12};
1360 let Inst{15-12} = regs{11-8};
1361 let Inst{7-0} = regs{7-0};
1363 // TODO: Mark the instructions with the appropriate subtarget info.
1364 let Inst{27-25} = 0b110;
1365 let Inst{11-9} = 0b101;
1366 let Inst{8} = 1; // Double precision
1369 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1370 string asm, string cstr, list<dag> pattern>
1371 : VFPXI<oops, iops, AddrMode4, 4, im,
1372 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1373 // Instruction operands.
1377 // Encode instruction operands.
1378 let Inst{19-16} = Rn;
1379 let Inst{22} = regs{8};
1380 let Inst{15-12} = regs{12-9};
1381 let Inst{7-0} = regs{7-0};
1383 // TODO: Mark the instructions with the appropriate subtarget info.
1384 let Inst{27-25} = 0b110;
1385 let Inst{11-9} = 0b101;
1386 let Inst{8} = 0; // Single precision
1389 // Double precision, unary
1390 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1391 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1392 string asm, list<dag> pattern>
1393 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1394 // Instruction operands.
1398 // Encode instruction operands.
1399 let Inst{3-0} = Dm{3-0};
1400 let Inst{5} = Dm{4};
1401 let Inst{15-12} = Dd{3-0};
1402 let Inst{22} = Dd{4};
1404 let Inst{27-23} = opcod1;
1405 let Inst{21-20} = opcod2;
1406 let Inst{19-16} = opcod3;
1407 let Inst{11-9} = 0b101;
1408 let Inst{8} = 1; // Double precision
1409 let Inst{7-6} = opcod4;
1410 let Inst{4} = opcod5;
1413 // Double precision, binary
1414 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1415 dag iops, InstrItinClass itin, string opc, string asm,
1417 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1418 // Instruction operands.
1423 // Encode instruction operands.
1424 let Inst{3-0} = Dm{3-0};
1425 let Inst{5} = Dm{4};
1426 let Inst{19-16} = Dn{3-0};
1427 let Inst{7} = Dn{4};
1428 let Inst{15-12} = Dd{3-0};
1429 let Inst{22} = Dd{4};
1431 let Inst{27-23} = opcod1;
1432 let Inst{21-20} = opcod2;
1433 let Inst{11-9} = 0b101;
1434 let Inst{8} = 1; // Double precision
1439 // Single precision, unary
1440 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1441 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1442 string asm, list<dag> pattern>
1443 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1444 // Instruction operands.
1448 // Encode instruction operands.
1449 let Inst{3-0} = Sm{4-1};
1450 let Inst{5} = Sm{0};
1451 let Inst{15-12} = Sd{4-1};
1452 let Inst{22} = Sd{0};
1454 let Inst{27-23} = opcod1;
1455 let Inst{21-20} = opcod2;
1456 let Inst{19-16} = opcod3;
1457 let Inst{11-9} = 0b101;
1458 let Inst{8} = 0; // Single precision
1459 let Inst{7-6} = opcod4;
1460 let Inst{4} = opcod5;
1463 // Single precision unary, if no NEON. Same as ASuI except not available if
1465 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1466 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1467 string asm, list<dag> pattern>
1468 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1470 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1473 // Single precision, binary
1474 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1475 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1476 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1477 // Instruction operands.
1482 // Encode instruction operands.
1483 let Inst{3-0} = Sm{4-1};
1484 let Inst{5} = Sm{0};
1485 let Inst{19-16} = Sn{4-1};
1486 let Inst{7} = Sn{0};
1487 let Inst{15-12} = Sd{4-1};
1488 let Inst{22} = Sd{0};
1490 let Inst{27-23} = opcod1;
1491 let Inst{21-20} = opcod2;
1492 let Inst{11-9} = 0b101;
1493 let Inst{8} = 0; // Single precision
1498 // Single precision binary, if no NEON. Same as ASbI except not available if
1500 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1501 dag iops, InstrItinClass itin, string opc, string asm,
1503 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1504 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1506 // Instruction operands.
1511 // Encode instruction operands.
1512 let Inst{3-0} = Sm{4-1};
1513 let Inst{5} = Sm{0};
1514 let Inst{19-16} = Sn{4-1};
1515 let Inst{7} = Sn{0};
1516 let Inst{15-12} = Sd{4-1};
1517 let Inst{22} = Sd{0};
1520 // VFP conversion instructions
1521 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1522 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1524 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1525 let Inst{27-23} = opcod1;
1526 let Inst{21-20} = opcod2;
1527 let Inst{19-16} = opcod3;
1528 let Inst{11-8} = opcod4;
1533 // VFP conversion between floating-point and fixed-point
1534 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1535 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1537 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1538 // size (fixed-point number): sx == 0 ? 16 : 32
1539 let Inst{7} = op5; // sx
1542 // VFP conversion instructions, if no NEON
1543 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1544 dag oops, dag iops, InstrItinClass itin,
1545 string opc, string asm, list<dag> pattern>
1546 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1548 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1551 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1552 InstrItinClass itin,
1553 string opc, string asm, list<dag> pattern>
1554 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1555 let Inst{27-20} = opcod1;
1556 let Inst{11-8} = opcod2;
1560 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1561 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1562 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1564 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1565 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1566 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1568 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1569 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1570 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1572 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1573 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1574 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1576 //===----------------------------------------------------------------------===//
1578 //===----------------------------------------------------------------------===//
1579 // ARM NEON Instruction templates.
1582 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1583 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1585 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1586 let OutOperandList = oops;
1587 let InOperandList = !con(iops, (ins pred:$p));
1588 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1589 let Pattern = pattern;
1590 list<Predicate> Predicates = [HasNEON];
1593 // Same as NeonI except it does not have a "data type" specifier.
1594 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1595 InstrItinClass itin, string opc, string asm, string cstr,
1597 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1598 let OutOperandList = oops;
1599 let InOperandList = !con(iops, (ins pred:$p));
1600 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1601 let Pattern = pattern;
1602 list<Predicate> Predicates = [HasNEON];
1605 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1606 dag oops, dag iops, InstrItinClass itin,
1607 string opc, string dt, string asm, string cstr, list<dag> pattern>
1608 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1610 let Inst{31-24} = 0b11110100;
1611 let Inst{23} = op23;
1612 let Inst{21-20} = op21_20;
1613 let Inst{11-8} = op11_8;
1614 let Inst{7-4} = op7_4;
1616 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1622 let Inst{22} = Vd{4};
1623 let Inst{15-12} = Vd{3-0};
1624 let Inst{19-16} = Rn{3-0};
1625 let Inst{3-0} = Rm{3-0};
1628 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1629 dag oops, dag iops, InstrItinClass itin,
1630 string opc, string dt, string asm, string cstr, list<dag> pattern>
1631 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1632 dt, asm, cstr, pattern> {
1636 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1637 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1639 let OutOperandList = oops;
1640 let InOperandList = !con(iops, (ins pred:$p));
1641 list<Predicate> Predicates = [HasNEON];
1644 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1646 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1648 let OutOperandList = oops;
1649 let InOperandList = !con(iops, (ins pred:$p));
1650 let Pattern = pattern;
1651 list<Predicate> Predicates = [HasNEON];
1654 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1655 string opc, string dt, string asm, string cstr, list<dag> pattern>
1656 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1658 let Inst{31-25} = 0b1111001;
1659 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1662 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1663 string opc, string asm, string cstr, list<dag> pattern>
1664 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1666 let Inst{31-25} = 0b1111001;
1667 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1670 // NEON "one register and a modified immediate" format.
1671 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1673 dag oops, dag iops, InstrItinClass itin,
1674 string opc, string dt, string asm, string cstr,
1676 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1677 let Inst{23} = op23;
1678 let Inst{21-19} = op21_19;
1679 let Inst{11-8} = op11_8;
1685 // Instruction operands.
1689 let Inst{15-12} = Vd{3-0};
1690 let Inst{22} = Vd{4};
1691 let Inst{24} = SIMM{7};
1692 let Inst{18-16} = SIMM{6-4};
1693 let Inst{3-0} = SIMM{3-0};
1696 // NEON 2 vector register format.
1697 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1698 bits<5> op11_7, bit op6, bit op4,
1699 dag oops, dag iops, InstrItinClass itin,
1700 string opc, string dt, string asm, string cstr, list<dag> pattern>
1701 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1702 let Inst{24-23} = op24_23;
1703 let Inst{21-20} = op21_20;
1704 let Inst{19-18} = op19_18;
1705 let Inst{17-16} = op17_16;
1706 let Inst{11-7} = op11_7;
1710 // Instruction operands.
1714 let Inst{15-12} = Vd{3-0};
1715 let Inst{22} = Vd{4};
1716 let Inst{3-0} = Vm{3-0};
1717 let Inst{5} = Vm{4};
1720 // Same as N2V except it doesn't have a datatype suffix.
1721 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1722 bits<5> op11_7, bit op6, bit op4,
1723 dag oops, dag iops, InstrItinClass itin,
1724 string opc, string asm, string cstr, list<dag> pattern>
1725 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1726 let Inst{24-23} = op24_23;
1727 let Inst{21-20} = op21_20;
1728 let Inst{19-18} = op19_18;
1729 let Inst{17-16} = op17_16;
1730 let Inst{11-7} = op11_7;
1734 // Instruction operands.
1738 let Inst{15-12} = Vd{3-0};
1739 let Inst{22} = Vd{4};
1740 let Inst{3-0} = Vm{3-0};
1741 let Inst{5} = Vm{4};
1744 // NEON 2 vector register with immediate.
1745 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1746 dag oops, dag iops, Format f, InstrItinClass itin,
1747 string opc, string dt, string asm, string cstr, list<dag> pattern>
1748 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1749 let Inst{24} = op24;
1750 let Inst{23} = op23;
1751 let Inst{11-8} = op11_8;
1756 // Instruction operands.
1761 let Inst{15-12} = Vd{3-0};
1762 let Inst{22} = Vd{4};
1763 let Inst{3-0} = Vm{3-0};
1764 let Inst{5} = Vm{4};
1765 let Inst{21-16} = SIMM{5-0};
1768 // NEON 3 vector register format.
1770 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1771 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1772 string opc, string dt, string asm, string cstr,
1774 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1775 let Inst{24} = op24;
1776 let Inst{23} = op23;
1777 let Inst{21-20} = op21_20;
1778 let Inst{11-8} = op11_8;
1783 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1784 dag oops, dag iops, Format f, InstrItinClass itin,
1785 string opc, string dt, string asm, string cstr, list<dag> pattern>
1786 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1787 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1789 // Instruction operands.
1794 let Inst{15-12} = Vd{3-0};
1795 let Inst{22} = Vd{4};
1796 let Inst{19-16} = Vn{3-0};
1797 let Inst{7} = Vn{4};
1798 let Inst{3-0} = Vm{3-0};
1799 let Inst{5} = Vm{4};
1802 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1803 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1804 string opc, string dt, string asm, string cstr,
1806 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1807 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1809 // Instruction operands.
1815 let Inst{15-12} = Vd{3-0};
1816 let Inst{22} = Vd{4};
1817 let Inst{19-16} = Vn{3-0};
1818 let Inst{7} = Vn{4};
1819 let Inst{3-0} = Vm{3-0};
1823 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1824 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1825 string opc, string dt, string asm, string cstr,
1827 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1828 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1830 // Instruction operands.
1836 let Inst{15-12} = Vd{3-0};
1837 let Inst{22} = Vd{4};
1838 let Inst{19-16} = Vn{3-0};
1839 let Inst{7} = Vn{4};
1840 let Inst{2-0} = Vm{2-0};
1841 let Inst{5} = lane{1};
1842 let Inst{3} = lane{0};
1845 // Same as N3V except it doesn't have a data type suffix.
1846 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1848 dag oops, dag iops, Format f, InstrItinClass itin,
1849 string opc, string asm, string cstr, list<dag> pattern>
1850 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1851 let Inst{24} = op24;
1852 let Inst{23} = op23;
1853 let Inst{21-20} = op21_20;
1854 let Inst{11-8} = op11_8;
1858 // Instruction operands.
1863 let Inst{15-12} = Vd{3-0};
1864 let Inst{22} = Vd{4};
1865 let Inst{19-16} = Vn{3-0};
1866 let Inst{7} = Vn{4};
1867 let Inst{3-0} = Vm{3-0};
1868 let Inst{5} = Vm{4};
1871 // NEON VMOVs between scalar and core registers.
1872 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1873 dag oops, dag iops, Format f, InstrItinClass itin,
1874 string opc, string dt, string asm, list<dag> pattern>
1875 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1877 let Inst{27-20} = opcod1;
1878 let Inst{11-8} = opcod2;
1879 let Inst{6-5} = opcod3;
1881 // A8.6.303, A8.6.328, A8.6.329
1882 let Inst{3-0} = 0b0000;
1884 let OutOperandList = oops;
1885 let InOperandList = !con(iops, (ins pred:$p));
1886 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1887 let Pattern = pattern;
1888 list<Predicate> Predicates = [HasNEON];
1890 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1897 let Inst{31-28} = p{3-0};
1899 let Inst{19-16} = V{3-0};
1900 let Inst{15-12} = R{3-0};
1902 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1903 dag oops, dag iops, InstrItinClass itin,
1904 string opc, string dt, string asm, list<dag> pattern>
1905 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1906 opc, dt, asm, pattern>;
1907 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1908 dag oops, dag iops, InstrItinClass itin,
1909 string opc, string dt, string asm, list<dag> pattern>
1910 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1911 opc, dt, asm, pattern>;
1912 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1913 dag oops, dag iops, InstrItinClass itin,
1914 string opc, string dt, string asm, list<dag> pattern>
1915 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1916 opc, dt, asm, pattern>;
1918 // Vector Duplicate Lane (from scalar to all elements)
1919 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1920 InstrItinClass itin, string opc, string dt, string asm,
1922 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1923 let Inst{24-23} = 0b11;
1924 let Inst{21-20} = 0b11;
1925 let Inst{19-16} = op19_16;
1926 let Inst{11-7} = 0b11000;
1934 let Inst{22} = Vd{4};
1935 let Inst{15-12} = Vd{3-0};
1936 let Inst{5} = Vm{4};
1937 let Inst{3-0} = Vm{3-0};
1940 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1941 // for single-precision FP.
1942 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1943 list<Predicate> Predicates = [HasNEON,UseNEONForFP];