1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
159 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
160 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
161 let EncoderMethod = "getCCOutOpValue";
162 let PrintMethod = "printSBitModifierOperand";
163 let ParserMatchClass = CCOutOperand;
164 let DecoderMethod = "DecodeCCOutOperand";
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
172 let DecoderMethod = "DecodeCCOutOperand";
175 // ARM special operands for disassembly only.
177 def SetEndAsmOperand : ImmAsmOperand {
178 let Name = "SetEndImm";
179 let ParserMethod = "parseSetEndImm";
181 def setend_op : Operand<i32> {
182 let PrintMethod = "printSetendOperand";
183 let ParserMatchClass = SetEndAsmOperand;
186 def MSRMaskOperand : AsmOperandClass {
187 let Name = "MSRMask";
188 let ParserMethod = "parseMSRMaskOperand";
190 def msr_mask : Operand<i32> {
191 let PrintMethod = "printMSRMaskOperand";
192 let DecoderMethod = "DecodeMSRMask";
193 let ParserMatchClass = MSRMaskOperand;
196 // Shift Right Immediate - A shift right immediate is encoded differently from
197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
204 def shr_imm8 : Operand<i32> {
205 let EncoderMethod = "getShiftRight8Imm";
206 let DecoderMethod = "DecodeShiftRight8Imm";
208 def shr_imm16 : Operand<i32> {
209 let EncoderMethod = "getShiftRight16Imm";
210 let DecoderMethod = "DecodeShiftRight16Imm";
212 def shr_imm32 : Operand<i32> {
213 let EncoderMethod = "getShiftRight32Imm";
214 let DecoderMethod = "DecodeShiftRight32Imm";
216 def shr_imm64 : Operand<i32> {
217 let EncoderMethod = "getShiftRight64Imm";
218 let DecoderMethod = "DecodeShiftRight64Imm";
221 //===----------------------------------------------------------------------===//
222 // ARM Assembler alias templates.
224 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
225 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
226 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
227 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
228 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
229 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
230 class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
231 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
232 class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
233 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
234 class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
235 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
237 //===----------------------------------------------------------------------===//
238 // ARM Instruction templates.
242 class InstTemplate<AddrMode am, int sz, IndexMode im,
243 Format f, Domain d, string cstr, InstrItinClass itin>
245 let Namespace = "ARM";
250 bits<2> IndexModeBits = IM.Value;
252 bits<6> Form = F.Value;
254 bit isUnaryDataProc = 0;
255 bit canXformTo16Bit = 0;
256 // The instruction is a 16-bit flag setting Thumb instruction. Used
257 // by the parser to determine whether to require the 'S' suffix on the
258 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
259 bit thumbArithFlagSetting = 0;
261 // If this is a pseudo instruction, mark it isCodeGenOnly.
262 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
264 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
265 let TSFlags{4-0} = AM.Value;
266 let TSFlags{6-5} = IndexModeBits;
267 let TSFlags{12-7} = Form;
268 let TSFlags{13} = isUnaryDataProc;
269 let TSFlags{14} = canXformTo16Bit;
270 let TSFlags{17-15} = D.Value;
271 let TSFlags{18} = thumbArithFlagSetting;
273 let Constraints = cstr;
274 let Itinerary = itin;
281 class InstARM<AddrMode am, int sz, IndexMode im,
282 Format f, Domain d, string cstr, InstrItinClass itin>
283 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
284 let DecoderNamespace = "ARM";
287 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
288 // on by adding flavors to specific instructions.
289 class InstThumb<AddrMode am, int sz, IndexMode im,
290 Format f, Domain d, string cstr, InstrItinClass itin>
291 : InstTemplate<am, sz, im, f, d, cstr, itin> {
292 let DecoderNamespace = "Thumb";
295 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
296 // These are aliases that require C++ handling to convert to the target
297 // instruction, while InstAliases can be handled directly by tblgen.
298 class AsmPseudoInst<string asm, dag iops>
299 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
301 let OutOperandList = (outs);
302 let InOperandList = iops;
304 let isCodeGenOnly = 0; // So we get asm matcher for it.
309 class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
311 class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
313 class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
314 Requires<[IsThumb2]>;
315 class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
317 class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
320 // Pseudo instructions for the code generator.
321 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
322 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
323 GenericDomain, "", itin> {
324 let OutOperandList = oops;
325 let InOperandList = iops;
326 let Pattern = pattern;
327 let isCodeGenOnly = 1;
331 // PseudoInst that's ARM-mode only.
332 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
334 : PseudoInst<oops, iops, itin, pattern> {
336 list<Predicate> Predicates = [IsARM];
339 // PseudoInst that's Thumb-mode only.
340 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
342 : PseudoInst<oops, iops, itin, pattern> {
344 list<Predicate> Predicates = [IsThumb];
347 // PseudoInst that's Thumb2-mode only.
348 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
350 : PseudoInst<oops, iops, itin, pattern> {
352 list<Predicate> Predicates = [IsThumb2];
355 class ARMPseudoExpand<dag oops, dag iops, int sz,
356 InstrItinClass itin, list<dag> pattern,
358 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
359 PseudoInstExpansion<Result>;
361 class tPseudoExpand<dag oops, dag iops, int sz,
362 InstrItinClass itin, list<dag> pattern,
364 : tPseudoInst<oops, iops, sz, itin, pattern>,
365 PseudoInstExpansion<Result>;
367 class t2PseudoExpand<dag oops, dag iops, int sz,
368 InstrItinClass itin, list<dag> pattern,
370 : t2PseudoInst<oops, iops, sz, itin, pattern>,
371 PseudoInstExpansion<Result>;
373 // Almost all ARM instructions are predicable.
374 class I<dag oops, dag iops, AddrMode am, int sz,
375 IndexMode im, Format f, InstrItinClass itin,
376 string opc, string asm, string cstr,
378 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
381 let OutOperandList = oops;
382 let InOperandList = !con(iops, (ins pred:$p));
383 let AsmString = !strconcat(opc, "${p}", asm);
384 let Pattern = pattern;
385 list<Predicate> Predicates = [IsARM];
388 // A few are not predicable
389 class InoP<dag oops, dag iops, AddrMode am, int sz,
390 IndexMode im, Format f, InstrItinClass itin,
391 string opc, string asm, string cstr,
393 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
394 let OutOperandList = oops;
395 let InOperandList = iops;
396 let AsmString = !strconcat(opc, asm);
397 let Pattern = pattern;
398 let isPredicable = 0;
399 list<Predicate> Predicates = [IsARM];
402 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
403 // operand since by default it's a zero register. It will become an implicit def
404 // once it's "flipped".
405 class sI<dag oops, dag iops, AddrMode am, int sz,
406 IndexMode im, Format f, InstrItinClass itin,
407 string opc, string asm, string cstr,
409 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
410 bits<4> p; // Predicate operand
411 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
415 let OutOperandList = oops;
416 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
417 let AsmString = !strconcat(opc, "${s}${p}", asm);
418 let Pattern = pattern;
419 list<Predicate> Predicates = [IsARM];
423 class XI<dag oops, dag iops, AddrMode am, int sz,
424 IndexMode im, Format f, InstrItinClass itin,
425 string asm, string cstr, list<dag> pattern>
426 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
427 let OutOperandList = oops;
428 let InOperandList = iops;
430 let Pattern = pattern;
431 list<Predicate> Predicates = [IsARM];
434 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
435 string opc, string asm, list<dag> pattern>
436 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
437 opc, asm, "", pattern>;
438 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
439 string opc, string asm, list<dag> pattern>
440 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
441 opc, asm, "", pattern>;
442 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
443 string asm, list<dag> pattern>
444 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
446 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
447 string opc, string asm, list<dag> pattern>
448 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
449 opc, asm, "", pattern>;
451 // Ctrl flow instructions
452 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
453 string opc, string asm, list<dag> pattern>
454 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
455 opc, asm, "", pattern> {
456 let Inst{27-24} = opcod;
458 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
459 string asm, list<dag> pattern>
460 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
462 let Inst{27-24} = opcod;
465 // BR_JT instructions
466 class JTI<dag oops, dag iops, InstrItinClass itin,
467 string asm, list<dag> pattern>
468 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
471 // Atomic load/store instructions
472 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
473 string opc, string asm, list<dag> pattern>
474 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
475 opc, asm, "", pattern> {
478 let Inst{27-23} = 0b00011;
479 let Inst{22-21} = opcod;
481 let Inst{19-16} = addr;
482 let Inst{15-12} = Rt;
483 let Inst{11-0} = 0b111110011111;
485 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
486 string opc, string asm, list<dag> pattern>
487 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
488 opc, asm, "", pattern> {
492 let Inst{27-23} = 0b00011;
493 let Inst{22-21} = opcod;
495 let Inst{19-16} = addr;
496 let Inst{15-12} = Rd;
497 let Inst{11-4} = 0b11111001;
500 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
501 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
505 let Inst{27-23} = 0b00010;
507 let Inst{21-20} = 0b00;
508 let Inst{19-16} = addr;
509 let Inst{15-12} = Rt;
510 let Inst{11-4} = 0b00001001;
513 let DecoderMethod = "DecodeSwap";
516 // addrmode1 instructions
517 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
518 string opc, string asm, list<dag> pattern>
519 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
520 opc, asm, "", pattern> {
521 let Inst{24-21} = opcod;
522 let Inst{27-26} = 0b00;
524 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
525 string opc, string asm, list<dag> pattern>
526 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
527 opc, asm, "", pattern> {
528 let Inst{24-21} = opcod;
529 let Inst{27-26} = 0b00;
531 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
532 string asm, list<dag> pattern>
533 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
535 let Inst{24-21} = opcod;
536 let Inst{27-26} = 0b00;
541 // LDR/LDRB/STR/STRB/...
542 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
543 Format f, InstrItinClass itin, string opc, string asm,
545 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
547 let Inst{27-25} = op;
548 let Inst{24} = 1; // 24 == P
550 let Inst{22} = isByte;
551 let Inst{21} = 0; // 21 == W
554 // Indexed load/stores
555 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
556 IndexMode im, Format f, InstrItinClass itin, string opc,
557 string asm, string cstr, list<dag> pattern>
558 : I<oops, iops, AddrMode2, 4, im, f, itin,
559 opc, asm, cstr, pattern> {
561 let Inst{27-26} = 0b01;
562 let Inst{24} = isPre; // P bit
563 let Inst{22} = isByte; // B bit
564 let Inst{21} = isPre; // W bit
565 let Inst{20} = isLd; // L bit
566 let Inst{15-12} = Rt;
568 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
569 IndexMode im, Format f, InstrItinClass itin, string opc,
570 string asm, string cstr, list<dag> pattern>
571 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
573 // AM2 store w/ two operands: (GPR, am2offset)
579 let Inst{23} = offset{12};
580 let Inst{19-16} = Rn;
581 let Inst{11-5} = offset{11-5};
583 let Inst{3-0} = offset{3-0};
586 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
587 IndexMode im, Format f, InstrItinClass itin, string opc,
588 string asm, string cstr, list<dag> pattern>
589 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
591 // AM2 store w/ two operands: (GPR, am2offset)
597 let Inst{23} = offset{12};
598 let Inst{19-16} = Rn;
599 let Inst{11-0} = offset{11-0};
603 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
604 // but for now use this class for STRT and STRBT.
605 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
606 IndexMode im, Format f, InstrItinClass itin, string opc,
607 string asm, string cstr, list<dag> pattern>
608 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
610 // AM2 store w/ two operands: (GPR, am2offset)
612 // {13} 1 == Rm, 0 == imm12
616 let Inst{25} = addr{13};
617 let Inst{23} = addr{12};
618 let Inst{19-16} = addr{17-14};
619 let Inst{11-0} = addr{11-0};
622 // addrmode3 instructions
623 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
624 InstrItinClass itin, string opc, string asm, list<dag> pattern>
625 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
626 opc, asm, "", pattern> {
629 let Inst{27-25} = 0b000;
630 let Inst{24} = 1; // P bit
631 let Inst{23} = addr{8}; // U bit
632 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
633 let Inst{21} = 0; // W bit
634 let Inst{20} = op20; // L bit
635 let Inst{19-16} = addr{12-9}; // Rn
636 let Inst{15-12} = Rt; // Rt
637 let Inst{11-8} = addr{7-4}; // imm7_4/zero
639 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
641 let DecoderMethod = "DecodeAddrMode3Instruction";
644 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
645 IndexMode im, Format f, InstrItinClass itin, string opc,
646 string asm, string cstr, list<dag> pattern>
647 : I<oops, iops, AddrMode3, 4, im, f, itin,
648 opc, asm, cstr, pattern> {
650 let Inst{27-25} = 0b000;
651 let Inst{24} = isPre; // P bit
652 let Inst{21} = isPre; // W bit
653 let Inst{20} = op20; // L bit
654 let Inst{15-12} = Rt; // Rt
658 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
659 // but for now use this class for LDRSBT, LDRHT, LDSHT.
660 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
661 IndexMode im, Format f, InstrItinClass itin, string opc,
662 string asm, string cstr, list<dag> pattern>
663 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
664 // {13} 1 == imm8, 0 == Rm
671 let Inst{27-25} = 0b000;
672 let Inst{24} = 0; // P bit
674 let Inst{20} = isLoad; // L bit
675 let Inst{19-16} = addr; // Rn
676 let Inst{15-12} = Rt; // Rt
681 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
682 string opc, string asm, list<dag> pattern>
683 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
684 opc, asm, "", pattern> {
687 let Inst{27-25} = 0b000;
688 let Inst{24} = 1; // P bit
689 let Inst{23} = addr{8}; // U bit
690 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
691 let Inst{21} = 0; // W bit
692 let Inst{20} = 0; // L bit
693 let Inst{19-16} = addr{12-9}; // Rn
694 let Inst{15-12} = Rt; // Rt
695 let Inst{11-8} = addr{7-4}; // imm7_4/zero
697 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
698 let DecoderMethod = "DecodeAddrMode3Instruction";
701 // addrmode4 instructions
702 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
703 string asm, string cstr, list<dag> pattern>
704 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
709 let Inst{27-25} = 0b100;
710 let Inst{22} = 0; // S bit
711 let Inst{19-16} = Rn;
712 let Inst{15-0} = regs;
715 // Unsigned multiply, multiply-accumulate instructions.
716 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
717 string opc, string asm, list<dag> pattern>
718 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
719 opc, asm, "", pattern> {
720 let Inst{7-4} = 0b1001;
721 let Inst{20} = 0; // S bit
722 let Inst{27-21} = opcod;
724 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
725 string opc, string asm, list<dag> pattern>
726 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
727 opc, asm, "", pattern> {
728 let Inst{7-4} = 0b1001;
729 let Inst{27-21} = opcod;
732 // Most significant word multiply
733 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
734 InstrItinClass itin, string opc, string asm, list<dag> pattern>
735 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
736 opc, asm, "", pattern> {
740 let Inst{7-4} = opc7_4;
742 let Inst{27-21} = opcod;
743 let Inst{19-16} = Rd;
747 // MSW multiple w/ Ra operand
748 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
749 InstrItinClass itin, string opc, string asm, list<dag> pattern>
750 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
752 let Inst{15-12} = Ra;
755 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
756 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
757 InstrItinClass itin, string opc, string asm, list<dag> pattern>
758 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
759 opc, asm, "", pattern> {
765 let Inst{27-21} = opcod;
766 let Inst{6-5} = bit6_5;
770 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
771 InstrItinClass itin, string opc, string asm, list<dag> pattern>
772 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
774 let Inst{19-16} = Rd;
777 // AMulxyI with Ra operand
778 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
779 InstrItinClass itin, string opc, string asm, list<dag> pattern>
780 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
782 let Inst{15-12} = Ra;
785 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
786 InstrItinClass itin, string opc, string asm, list<dag> pattern>
787 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
790 let Inst{19-16} = RdHi;
791 let Inst{15-12} = RdLo;
794 // Extend instructions.
795 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
796 string opc, string asm, list<dag> pattern>
797 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
798 opc, asm, "", pattern> {
799 // All AExtI instructions have Rd and Rm register operands.
802 let Inst{15-12} = Rd;
804 let Inst{7-4} = 0b0111;
805 let Inst{9-8} = 0b00;
806 let Inst{27-20} = opcod;
809 // Misc Arithmetic instructions.
810 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
811 InstrItinClass itin, string opc, string asm, list<dag> pattern>
812 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
813 opc, asm, "", pattern> {
816 let Inst{27-20} = opcod;
817 let Inst{19-16} = 0b1111;
818 let Inst{15-12} = Rd;
819 let Inst{11-8} = 0b1111;
820 let Inst{7-4} = opc7_4;
825 def PKHLSLAsmOperand : ImmAsmOperand {
826 let Name = "PKHLSLImm";
827 let ParserMethod = "parsePKHLSLImm";
829 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
830 let PrintMethod = "printPKHLSLShiftImm";
831 let ParserMatchClass = PKHLSLAsmOperand;
833 def PKHASRAsmOperand : AsmOperandClass {
834 let Name = "PKHASRImm";
835 let ParserMethod = "parsePKHASRImm";
837 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
838 let PrintMethod = "printPKHASRShiftImm";
839 let ParserMatchClass = PKHASRAsmOperand;
842 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
843 string opc, string asm, list<dag> pattern>
844 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
845 opc, asm, "", pattern> {
850 let Inst{27-20} = opcod;
851 let Inst{19-16} = Rn;
852 let Inst{15-12} = Rd;
855 let Inst{5-4} = 0b01;
859 //===----------------------------------------------------------------------===//
861 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
862 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
863 list<Predicate> Predicates = [IsARM];
865 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
866 list<Predicate> Predicates = [IsARM, HasV5T];
868 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
869 list<Predicate> Predicates = [IsARM, HasV5TE];
871 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
872 list<Predicate> Predicates = [IsARM, HasV6];
875 //===----------------------------------------------------------------------===//
876 // Thumb Instruction Format Definitions.
879 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
880 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
881 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
882 let OutOperandList = oops;
883 let InOperandList = iops;
885 let Pattern = pattern;
886 list<Predicate> Predicates = [IsThumb];
889 // TI - Thumb instruction.
890 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
891 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
893 // Two-address instructions
894 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
896 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
899 // tBL, tBX 32-bit instructions
900 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
901 dag oops, dag iops, InstrItinClass itin, string asm,
903 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
905 let Inst{31-27} = opcod1;
906 let Inst{15-14} = opcod2;
907 let Inst{12} = opcod3;
910 // BR_JT instructions
911 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
913 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
916 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
917 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
918 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
919 let OutOperandList = oops;
920 let InOperandList = iops;
922 let Pattern = pattern;
923 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
926 class T1I<dag oops, dag iops, InstrItinClass itin,
927 string asm, list<dag> pattern>
928 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
929 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
930 string asm, list<dag> pattern>
931 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
933 // Two-address instructions
934 class T1It<dag oops, dag iops, InstrItinClass itin,
935 string asm, string cstr, list<dag> pattern>
936 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
939 // Thumb1 instruction that can either be predicated or set CPSR.
940 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
942 string opc, string asm, string cstr, list<dag> pattern>
943 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
944 let OutOperandList = !con(oops, (outs s_cc_out:$s));
945 let InOperandList = !con(iops, (ins pred:$p));
946 let AsmString = !strconcat(opc, "${s}${p}", asm);
947 let Pattern = pattern;
948 let thumbArithFlagSetting = 1;
949 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
950 let DecoderNamespace = "ThumbSBit";
953 class T1sI<dag oops, dag iops, InstrItinClass itin,
954 string opc, string asm, list<dag> pattern>
955 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
957 // Two-address instructions
958 class T1sIt<dag oops, dag iops, InstrItinClass itin,
959 string opc, string asm, list<dag> pattern>
960 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
961 "$Rn = $Rdn", pattern>;
963 // Thumb1 instruction that can be predicated.
964 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
966 string opc, string asm, string cstr, list<dag> pattern>
967 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
968 let OutOperandList = oops;
969 let InOperandList = !con(iops, (ins pred:$p));
970 let AsmString = !strconcat(opc, "${p}", asm);
971 let Pattern = pattern;
972 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
975 class T1pI<dag oops, dag iops, InstrItinClass itin,
976 string opc, string asm, list<dag> pattern>
977 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
979 // Two-address instructions
980 class T1pIt<dag oops, dag iops, InstrItinClass itin,
981 string opc, string asm, list<dag> pattern>
982 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
983 "$Rn = $Rdn", pattern>;
985 class T1pIs<dag oops, dag iops,
986 InstrItinClass itin, string opc, string asm, list<dag> pattern>
987 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
989 class Encoding16 : Encoding {
990 let Inst{31-16} = 0x0000;
993 // A6.2 16-bit Thumb instruction encoding
994 class T1Encoding<bits<6> opcode> : Encoding16 {
995 let Inst{15-10} = opcode;
998 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
999 class T1General<bits<5> opcode> : Encoding16 {
1000 let Inst{15-14} = 0b00;
1001 let Inst{13-9} = opcode;
1004 // A6.2.2 Data-processing encoding.
1005 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1006 let Inst{15-10} = 0b010000;
1007 let Inst{9-6} = opcode;
1010 // A6.2.3 Special data instructions and branch and exchange encoding.
1011 class T1Special<bits<4> opcode> : Encoding16 {
1012 let Inst{15-10} = 0b010001;
1013 let Inst{9-6} = opcode;
1016 // A6.2.4 Load/store single data item encoding.
1017 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1018 let Inst{15-12} = opA;
1019 let Inst{11-9} = opB;
1021 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1023 class T1BranchCond<bits<4> opcode> : Encoding16 {
1024 let Inst{15-12} = opcode;
1027 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1028 // following bits are used for "opA" (see A6.2.4):
1030 // 0b0110 => Immediate, 4 bytes
1031 // 0b1000 => Immediate, 2 bytes
1032 // 0b0111 => Immediate, 1 byte
1033 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1034 InstrItinClass itin, string opc, string asm,
1036 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1037 T1LoadStore<0b0101, opcode> {
1040 let Inst{8-6} = addr{5-3}; // Rm
1041 let Inst{5-3} = addr{2-0}; // Rn
1044 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1045 InstrItinClass itin, string opc, string asm,
1047 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1048 T1LoadStore<opA, {opB,?,?}> {
1051 let Inst{10-6} = addr{7-3}; // imm5
1052 let Inst{5-3} = addr{2-0}; // Rn
1056 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1057 class T1Misc<bits<7> opcode> : Encoding16 {
1058 let Inst{15-12} = 0b1011;
1059 let Inst{11-5} = opcode;
1062 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1063 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1064 InstrItinClass itin,
1065 string opc, string asm, string cstr, list<dag> pattern>
1066 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1067 let OutOperandList = oops;
1068 let InOperandList = !con(iops, (ins pred:$p));
1069 let AsmString = !strconcat(opc, "${p}", asm);
1070 let Pattern = pattern;
1071 list<Predicate> Predicates = [IsThumb2];
1072 let DecoderNamespace = "Thumb2";
1075 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1076 // input operand since by default it's a zero register. It will become an
1077 // implicit def once it's "flipped".
1079 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1081 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1082 InstrItinClass itin,
1083 string opc, string asm, string cstr, list<dag> pattern>
1084 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1085 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1088 let OutOperandList = oops;
1089 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1090 let AsmString = !strconcat(opc, "${s}${p}", asm);
1091 let Pattern = pattern;
1092 list<Predicate> Predicates = [IsThumb2];
1093 let DecoderNamespace = "Thumb2";
1097 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1098 InstrItinClass itin,
1099 string asm, string cstr, list<dag> pattern>
1100 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1101 let OutOperandList = oops;
1102 let InOperandList = iops;
1103 let AsmString = asm;
1104 let Pattern = pattern;
1105 list<Predicate> Predicates = [IsThumb2];
1106 let DecoderNamespace = "Thumb2";
1109 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1110 InstrItinClass itin,
1111 string asm, string cstr, list<dag> pattern>
1112 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1113 let OutOperandList = oops;
1114 let InOperandList = iops;
1115 let AsmString = asm;
1116 let Pattern = pattern;
1117 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1118 let DecoderNamespace = "Thumb";
1121 class T2I<dag oops, dag iops, InstrItinClass itin,
1122 string opc, string asm, list<dag> pattern>
1123 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1124 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1125 string opc, string asm, list<dag> pattern>
1126 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1127 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1128 string opc, string asm, list<dag> pattern>
1129 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1130 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1131 string opc, string asm, list<dag> pattern>
1132 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1133 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1134 string opc, string asm, list<dag> pattern>
1135 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1136 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1137 string opc, string asm, string cstr, list<dag> pattern>
1138 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1143 let Inst{31-25} = 0b1110100;
1145 let Inst{23} = addr{8};
1148 let Inst{20} = isLoad;
1149 let Inst{19-16} = addr{12-9};
1150 let Inst{15-12} = Rt{3-0};
1151 let Inst{11-8} = Rt2{3-0};
1152 let Inst{7-0} = addr{7-0};
1154 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1155 InstrItinClass itin, string opc, string asm, string cstr,
1157 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1163 let Inst{31-25} = 0b1110100;
1165 let Inst{23} = imm{8};
1168 let Inst{20} = isLoad;
1169 let Inst{19-16} = addr;
1170 let Inst{15-12} = Rt{3-0};
1171 let Inst{11-8} = Rt2{3-0};
1172 let Inst{7-0} = imm{7-0};
1175 class T2sI<dag oops, dag iops, InstrItinClass itin,
1176 string opc, string asm, list<dag> pattern>
1177 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1179 class T2XI<dag oops, dag iops, InstrItinClass itin,
1180 string asm, list<dag> pattern>
1181 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1182 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1183 string asm, list<dag> pattern>
1184 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1186 // Move to/from coprocessor instructions
1187 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1188 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1189 let Inst{31-28} = opc;
1192 // Two-address instructions
1193 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1194 string asm, string cstr, list<dag> pattern>
1195 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1197 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1198 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1200 AddrMode am, IndexMode im, InstrItinClass itin,
1201 string opc, string asm, string cstr, list<dag> pattern>
1202 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1203 let OutOperandList = oops;
1204 let InOperandList = !con(iops, (ins pred:$p));
1205 let AsmString = !strconcat(opc, "${p}", asm);
1206 let Pattern = pattern;
1207 list<Predicate> Predicates = [IsThumb2];
1208 let DecoderNamespace = "Thumb2";
1212 let Inst{31-27} = 0b11111;
1213 let Inst{26-25} = 0b00;
1214 let Inst{24} = signed;
1216 let Inst{22-21} = opcod;
1217 let Inst{20} = load;
1218 let Inst{19-16} = addr{12-9};
1219 let Inst{15-12} = Rt{3-0};
1221 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1222 let Inst{10} = pre; // The P bit.
1223 let Inst{9} = addr{8}; // Sign bit
1224 let Inst{8} = 1; // The W bit.
1225 let Inst{7-0} = addr{7-0};
1227 let DecoderMethod = "DecodeT2LdStPre";
1230 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1231 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1233 AddrMode am, IndexMode im, InstrItinClass itin,
1234 string opc, string asm, string cstr, list<dag> pattern>
1235 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1236 let OutOperandList = oops;
1237 let InOperandList = !con(iops, (ins pred:$p));
1238 let AsmString = !strconcat(opc, "${p}", asm);
1239 let Pattern = pattern;
1240 list<Predicate> Predicates = [IsThumb2];
1241 let DecoderNamespace = "Thumb2";
1246 let Inst{31-27} = 0b11111;
1247 let Inst{26-25} = 0b00;
1248 let Inst{24} = signed;
1250 let Inst{22-21} = opcod;
1251 let Inst{20} = load;
1252 let Inst{19-16} = Rn;
1253 let Inst{15-12} = Rt{3-0};
1255 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1256 let Inst{10} = pre; // The P bit.
1257 let Inst{9} = offset{8}; // Sign bit
1258 let Inst{8} = 1; // The W bit.
1259 let Inst{7-0} = offset{7-0};
1261 let DecoderMethod = "DecodeT2LdStPre";
1264 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1265 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1266 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1269 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1270 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1271 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1274 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1275 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1276 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1279 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1280 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1281 list<Predicate> Predicates = [IsThumb2];
1284 //===----------------------------------------------------------------------===//
1286 //===----------------------------------------------------------------------===//
1287 // ARM VFP Instruction templates.
1290 // Almost all VFP instructions are predicable.
1291 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1292 IndexMode im, Format f, InstrItinClass itin,
1293 string opc, string asm, string cstr, list<dag> pattern>
1294 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1296 let Inst{31-28} = p;
1297 let OutOperandList = oops;
1298 let InOperandList = !con(iops, (ins pred:$p));
1299 let AsmString = !strconcat(opc, "${p}", asm);
1300 let Pattern = pattern;
1301 let PostEncoderMethod = "VFPThumb2PostEncoder";
1302 let DecoderNamespace = "VFP";
1303 list<Predicate> Predicates = [HasVFP2];
1307 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1308 IndexMode im, Format f, InstrItinClass itin,
1309 string asm, string cstr, list<dag> pattern>
1310 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1312 let Inst{31-28} = p;
1313 let OutOperandList = oops;
1314 let InOperandList = iops;
1315 let AsmString = asm;
1316 let Pattern = pattern;
1317 let PostEncoderMethod = "VFPThumb2PostEncoder";
1318 let DecoderNamespace = "VFP";
1319 list<Predicate> Predicates = [HasVFP2];
1322 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1323 string opc, string asm, list<dag> pattern>
1324 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1325 opc, asm, "", pattern> {
1326 let PostEncoderMethod = "VFPThumb2PostEncoder";
1329 // ARM VFP addrmode5 loads and stores
1330 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1331 InstrItinClass itin,
1332 string opc, string asm, list<dag> pattern>
1333 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1334 VFPLdStFrm, itin, opc, asm, "", pattern> {
1335 // Instruction operands.
1339 // Encode instruction operands.
1340 let Inst{23} = addr{8}; // U (add = (U == '1'))
1341 let Inst{22} = Dd{4};
1342 let Inst{19-16} = addr{12-9}; // Rn
1343 let Inst{15-12} = Dd{3-0};
1344 let Inst{7-0} = addr{7-0}; // imm8
1346 // TODO: Mark the instructions with the appropriate subtarget info.
1347 let Inst{27-24} = opcod1;
1348 let Inst{21-20} = opcod2;
1349 let Inst{11-9} = 0b101;
1350 let Inst{8} = 1; // Double precision
1352 // Loads & stores operate on both NEON and VFP pipelines.
1353 let D = VFPNeonDomain;
1356 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1357 InstrItinClass itin,
1358 string opc, string asm, list<dag> pattern>
1359 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1360 VFPLdStFrm, itin, opc, asm, "", pattern> {
1361 // Instruction operands.
1365 // Encode instruction operands.
1366 let Inst{23} = addr{8}; // U (add = (U == '1'))
1367 let Inst{22} = Sd{0};
1368 let Inst{19-16} = addr{12-9}; // Rn
1369 let Inst{15-12} = Sd{4-1};
1370 let Inst{7-0} = addr{7-0}; // imm8
1372 // TODO: Mark the instructions with the appropriate subtarget info.
1373 let Inst{27-24} = opcod1;
1374 let Inst{21-20} = opcod2;
1375 let Inst{11-9} = 0b101;
1376 let Inst{8} = 0; // Single precision
1378 // Loads & stores operate on both NEON and VFP pipelines.
1379 let D = VFPNeonDomain;
1382 // VFP Load / store multiple pseudo instructions.
1383 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1385 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1387 let OutOperandList = oops;
1388 let InOperandList = !con(iops, (ins pred:$p));
1389 let Pattern = pattern;
1390 list<Predicate> Predicates = [HasVFP2];
1393 // Load / store multiple
1394 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1395 string asm, string cstr, list<dag> pattern>
1396 : VFPXI<oops, iops, AddrMode4, 4, im,
1397 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1398 // Instruction operands.
1402 // Encode instruction operands.
1403 let Inst{19-16} = Rn;
1404 let Inst{22} = regs{12};
1405 let Inst{15-12} = regs{11-8};
1406 let Inst{7-0} = regs{7-0};
1408 // TODO: Mark the instructions with the appropriate subtarget info.
1409 let Inst{27-25} = 0b110;
1410 let Inst{11-9} = 0b101;
1411 let Inst{8} = 1; // Double precision
1414 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1415 string asm, string cstr, list<dag> pattern>
1416 : VFPXI<oops, iops, AddrMode4, 4, im,
1417 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1418 // Instruction operands.
1422 // Encode instruction operands.
1423 let Inst{19-16} = Rn;
1424 let Inst{22} = regs{8};
1425 let Inst{15-12} = regs{12-9};
1426 let Inst{7-0} = regs{7-0};
1428 // TODO: Mark the instructions with the appropriate subtarget info.
1429 let Inst{27-25} = 0b110;
1430 let Inst{11-9} = 0b101;
1431 let Inst{8} = 0; // Single precision
1434 // Double precision, unary
1435 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1436 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1437 string asm, list<dag> pattern>
1438 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1439 // Instruction operands.
1443 // Encode instruction operands.
1444 let Inst{3-0} = Dm{3-0};
1445 let Inst{5} = Dm{4};
1446 let Inst{15-12} = Dd{3-0};
1447 let Inst{22} = Dd{4};
1449 let Inst{27-23} = opcod1;
1450 let Inst{21-20} = opcod2;
1451 let Inst{19-16} = opcod3;
1452 let Inst{11-9} = 0b101;
1453 let Inst{8} = 1; // Double precision
1454 let Inst{7-6} = opcod4;
1455 let Inst{4} = opcod5;
1458 // Double precision, binary
1459 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1460 dag iops, InstrItinClass itin, string opc, string asm,
1462 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1463 // Instruction operands.
1468 // Encode instruction operands.
1469 let Inst{3-0} = Dm{3-0};
1470 let Inst{5} = Dm{4};
1471 let Inst{19-16} = Dn{3-0};
1472 let Inst{7} = Dn{4};
1473 let Inst{15-12} = Dd{3-0};
1474 let Inst{22} = Dd{4};
1476 let Inst{27-23} = opcod1;
1477 let Inst{21-20} = opcod2;
1478 let Inst{11-9} = 0b101;
1479 let Inst{8} = 1; // Double precision
1484 // Single precision, unary
1485 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1486 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1487 string asm, list<dag> pattern>
1488 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1489 // Instruction operands.
1493 // Encode instruction operands.
1494 let Inst{3-0} = Sm{4-1};
1495 let Inst{5} = Sm{0};
1496 let Inst{15-12} = Sd{4-1};
1497 let Inst{22} = Sd{0};
1499 let Inst{27-23} = opcod1;
1500 let Inst{21-20} = opcod2;
1501 let Inst{19-16} = opcod3;
1502 let Inst{11-9} = 0b101;
1503 let Inst{8} = 0; // Single precision
1504 let Inst{7-6} = opcod4;
1505 let Inst{4} = opcod5;
1508 // Single precision unary, if no NEON. Same as ASuI except not available if
1510 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1511 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1512 string asm, list<dag> pattern>
1513 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1515 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1518 // Single precision, binary
1519 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1520 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1521 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1522 // Instruction operands.
1527 // Encode instruction operands.
1528 let Inst{3-0} = Sm{4-1};
1529 let Inst{5} = Sm{0};
1530 let Inst{19-16} = Sn{4-1};
1531 let Inst{7} = Sn{0};
1532 let Inst{15-12} = Sd{4-1};
1533 let Inst{22} = Sd{0};
1535 let Inst{27-23} = opcod1;
1536 let Inst{21-20} = opcod2;
1537 let Inst{11-9} = 0b101;
1538 let Inst{8} = 0; // Single precision
1543 // Single precision binary, if no NEON. Same as ASbI except not available if
1545 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1546 dag iops, InstrItinClass itin, string opc, string asm,
1548 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1549 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1551 // Instruction operands.
1556 // Encode instruction operands.
1557 let Inst{3-0} = Sm{4-1};
1558 let Inst{5} = Sm{0};
1559 let Inst{19-16} = Sn{4-1};
1560 let Inst{7} = Sn{0};
1561 let Inst{15-12} = Sd{4-1};
1562 let Inst{22} = Sd{0};
1565 // VFP conversion instructions
1566 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1567 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1569 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1570 let Inst{27-23} = opcod1;
1571 let Inst{21-20} = opcod2;
1572 let Inst{19-16} = opcod3;
1573 let Inst{11-8} = opcod4;
1578 // VFP conversion between floating-point and fixed-point
1579 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1580 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1582 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1583 // size (fixed-point number): sx == 0 ? 16 : 32
1584 let Inst{7} = op5; // sx
1587 // VFP conversion instructions, if no NEON
1588 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1589 dag oops, dag iops, InstrItinClass itin,
1590 string opc, string asm, list<dag> pattern>
1591 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1593 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1596 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1597 InstrItinClass itin,
1598 string opc, string asm, list<dag> pattern>
1599 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1600 let Inst{27-20} = opcod1;
1601 let Inst{11-8} = opcod2;
1605 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1606 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1607 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1609 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1610 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1611 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1613 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1614 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1615 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1617 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1618 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1619 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1621 //===----------------------------------------------------------------------===//
1623 //===----------------------------------------------------------------------===//
1624 // ARM NEON Instruction templates.
1627 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1628 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1630 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1631 let OutOperandList = oops;
1632 let InOperandList = !con(iops, (ins pred:$p));
1633 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1634 let Pattern = pattern;
1635 list<Predicate> Predicates = [HasNEON];
1636 let DecoderNamespace = "NEON";
1639 // Same as NeonI except it does not have a "data type" specifier.
1640 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1641 InstrItinClass itin, string opc, string asm, string cstr,
1643 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1644 let OutOperandList = oops;
1645 let InOperandList = !con(iops, (ins pred:$p));
1646 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1647 let Pattern = pattern;
1648 list<Predicate> Predicates = [HasNEON];
1649 let DecoderNamespace = "NEON";
1652 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1653 dag oops, dag iops, InstrItinClass itin,
1654 string opc, string dt, string asm, string cstr, list<dag> pattern>
1655 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1657 let Inst{31-24} = 0b11110100;
1658 let Inst{23} = op23;
1659 let Inst{21-20} = op21_20;
1660 let Inst{11-8} = op11_8;
1661 let Inst{7-4} = op7_4;
1663 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1664 let DecoderNamespace = "NEONLoadStore";
1670 let Inst{22} = Vd{4};
1671 let Inst{15-12} = Vd{3-0};
1672 let Inst{19-16} = Rn{3-0};
1673 let Inst{3-0} = Rm{3-0};
1676 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1677 dag oops, dag iops, InstrItinClass itin,
1678 string opc, string dt, string asm, string cstr, list<dag> pattern>
1679 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1680 dt, asm, cstr, pattern> {
1684 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1685 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1687 let OutOperandList = oops;
1688 let InOperandList = !con(iops, (ins pred:$p));
1689 list<Predicate> Predicates = [HasNEON];
1692 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1694 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1696 let OutOperandList = oops;
1697 let InOperandList = !con(iops, (ins pred:$p));
1698 let Pattern = pattern;
1699 list<Predicate> Predicates = [HasNEON];
1702 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1703 string opc, string dt, string asm, string cstr, list<dag> pattern>
1704 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1706 let Inst{31-25} = 0b1111001;
1707 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1708 let DecoderNamespace = "NEONData";
1711 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1712 string opc, string asm, string cstr, list<dag> pattern>
1713 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1715 let Inst{31-25} = 0b1111001;
1716 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1717 let DecoderNamespace = "NEONData";
1720 // NEON "one register and a modified immediate" format.
1721 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1723 dag oops, dag iops, InstrItinClass itin,
1724 string opc, string dt, string asm, string cstr,
1726 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1727 let Inst{23} = op23;
1728 let Inst{21-19} = op21_19;
1729 let Inst{11-8} = op11_8;
1735 // Instruction operands.
1739 let Inst{15-12} = Vd{3-0};
1740 let Inst{22} = Vd{4};
1741 let Inst{24} = SIMM{7};
1742 let Inst{18-16} = SIMM{6-4};
1743 let Inst{3-0} = SIMM{3-0};
1744 let DecoderMethod = "DecodeNEONModImmInstruction";
1747 // NEON 2 vector register format.
1748 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1749 bits<5> op11_7, bit op6, bit op4,
1750 dag oops, dag iops, InstrItinClass itin,
1751 string opc, string dt, string asm, string cstr, list<dag> pattern>
1752 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1753 let Inst{24-23} = op24_23;
1754 let Inst{21-20} = op21_20;
1755 let Inst{19-18} = op19_18;
1756 let Inst{17-16} = op17_16;
1757 let Inst{11-7} = op11_7;
1761 // Instruction operands.
1765 let Inst{15-12} = Vd{3-0};
1766 let Inst{22} = Vd{4};
1767 let Inst{3-0} = Vm{3-0};
1768 let Inst{5} = Vm{4};
1771 // Same as N2V except it doesn't have a datatype suffix.
1772 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1773 bits<5> op11_7, bit op6, bit op4,
1774 dag oops, dag iops, InstrItinClass itin,
1775 string opc, string asm, string cstr, list<dag> pattern>
1776 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1777 let Inst{24-23} = op24_23;
1778 let Inst{21-20} = op21_20;
1779 let Inst{19-18} = op19_18;
1780 let Inst{17-16} = op17_16;
1781 let Inst{11-7} = op11_7;
1785 // Instruction operands.
1789 let Inst{15-12} = Vd{3-0};
1790 let Inst{22} = Vd{4};
1791 let Inst{3-0} = Vm{3-0};
1792 let Inst{5} = Vm{4};
1795 // NEON 2 vector register with immediate.
1796 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1797 dag oops, dag iops, Format f, InstrItinClass itin,
1798 string opc, string dt, string asm, string cstr, list<dag> pattern>
1799 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1800 let Inst{24} = op24;
1801 let Inst{23} = op23;
1802 let Inst{11-8} = op11_8;
1807 // Instruction operands.
1812 let Inst{15-12} = Vd{3-0};
1813 let Inst{22} = Vd{4};
1814 let Inst{3-0} = Vm{3-0};
1815 let Inst{5} = Vm{4};
1816 let Inst{21-16} = SIMM{5-0};
1819 // NEON 3 vector register format.
1821 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1822 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1823 string opc, string dt, string asm, string cstr,
1825 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1826 let Inst{24} = op24;
1827 let Inst{23} = op23;
1828 let Inst{21-20} = op21_20;
1829 let Inst{11-8} = op11_8;
1834 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1835 dag oops, dag iops, Format f, InstrItinClass itin,
1836 string opc, string dt, string asm, string cstr, list<dag> pattern>
1837 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1838 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1840 // Instruction operands.
1845 let Inst{15-12} = Vd{3-0};
1846 let Inst{22} = Vd{4};
1847 let Inst{19-16} = Vn{3-0};
1848 let Inst{7} = Vn{4};
1849 let Inst{3-0} = Vm{3-0};
1850 let Inst{5} = Vm{4};
1853 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1854 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1855 string opc, string dt, string asm, string cstr,
1857 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1858 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1860 // Instruction operands.
1866 let Inst{15-12} = Vd{3-0};
1867 let Inst{22} = Vd{4};
1868 let Inst{19-16} = Vn{3-0};
1869 let Inst{7} = Vn{4};
1870 let Inst{3-0} = Vm{3-0};
1874 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1875 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1876 string opc, string dt, string asm, string cstr,
1878 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1879 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1881 // Instruction operands.
1887 let Inst{15-12} = Vd{3-0};
1888 let Inst{22} = Vd{4};
1889 let Inst{19-16} = Vn{3-0};
1890 let Inst{7} = Vn{4};
1891 let Inst{2-0} = Vm{2-0};
1892 let Inst{5} = lane{1};
1893 let Inst{3} = lane{0};
1896 // Same as N3V except it doesn't have a data type suffix.
1897 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1899 dag oops, dag iops, Format f, InstrItinClass itin,
1900 string opc, string asm, string cstr, list<dag> pattern>
1901 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1902 let Inst{24} = op24;
1903 let Inst{23} = op23;
1904 let Inst{21-20} = op21_20;
1905 let Inst{11-8} = op11_8;
1909 // Instruction operands.
1914 let Inst{15-12} = Vd{3-0};
1915 let Inst{22} = Vd{4};
1916 let Inst{19-16} = Vn{3-0};
1917 let Inst{7} = Vn{4};
1918 let Inst{3-0} = Vm{3-0};
1919 let Inst{5} = Vm{4};
1922 // NEON VMOVs between scalar and core registers.
1923 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1924 dag oops, dag iops, Format f, InstrItinClass itin,
1925 string opc, string dt, string asm, list<dag> pattern>
1926 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1928 let Inst{27-20} = opcod1;
1929 let Inst{11-8} = opcod2;
1930 let Inst{6-5} = opcod3;
1932 // A8.6.303, A8.6.328, A8.6.329
1933 let Inst{3-0} = 0b0000;
1935 let OutOperandList = oops;
1936 let InOperandList = !con(iops, (ins pred:$p));
1937 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1938 let Pattern = pattern;
1939 list<Predicate> Predicates = [HasNEON];
1941 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1942 let DecoderNamespace = "NEONDup";
1949 let Inst{31-28} = p{3-0};
1951 let Inst{19-16} = V{3-0};
1952 let Inst{15-12} = R{3-0};
1954 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1955 dag oops, dag iops, InstrItinClass itin,
1956 string opc, string dt, string asm, list<dag> pattern>
1957 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1958 opc, dt, asm, pattern>;
1959 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1960 dag oops, dag iops, InstrItinClass itin,
1961 string opc, string dt, string asm, list<dag> pattern>
1962 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1963 opc, dt, asm, pattern>;
1964 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1965 dag oops, dag iops, InstrItinClass itin,
1966 string opc, string dt, string asm, list<dag> pattern>
1967 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1968 opc, dt, asm, pattern>;
1970 // Vector Duplicate Lane (from scalar to all elements)
1971 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1972 InstrItinClass itin, string opc, string dt, string asm,
1974 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1975 let Inst{24-23} = 0b11;
1976 let Inst{21-20} = 0b11;
1977 let Inst{19-16} = op19_16;
1978 let Inst{11-7} = 0b11000;
1985 let Inst{22} = Vd{4};
1986 let Inst{15-12} = Vd{3-0};
1987 let Inst{5} = Vm{4};
1988 let Inst{3-0} = Vm{3-0};
1991 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1992 // for single-precision FP.
1993 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1994 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
1997 // VFP/NEON Instruction aliases for type suffices.
1998 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
1999 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
2001 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
2002 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2003 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2004 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2005 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2008 // The same alias classes using AsmPseudo instead, for the more complex
2009 // stuff in NEON that InstAlias can't quite handle.
2010 // Note that we can't use anonymous defm references here like we can
2011 // above, as we care about the ultimate instruction enum names generated, unlike
2012 // for instalias defs.
2013 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2014 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2015 multiclass NEONDT8ReqAsmPseudoInst<string opc, string asm, dag iops> {
2016 def I8 : NEONDataTypeAsmPseudoInst<opc, ".i8", asm, iops>;
2017 def S8 : NEONDataTypeAsmPseudoInst<opc, ".s8", asm, iops>;
2018 def U8 : NEONDataTypeAsmPseudoInst<opc, ".u8", asm, iops>;
2019 def P8 : NEONDataTypeAsmPseudoInst<opc, ".p8", asm, iops>;
2021 // NEONDT8ReqAsmPseudoInst plus plain ".8"
2022 multiclass NEONDT8AsmPseudoInst<string opc, string asm, dag iops> {
2023 def _8 : NEONDataTypeAsmPseudoInst<opc, ".8", asm, iops>;
2024 defm _ : NEONDT8ReqAsmPseudoInst<opc, asm, iops>;
2026 multiclass NEONDT16ReqAsmPseudoInst<string opc, string asm, dag iops> {
2027 def I16 : NEONDataTypeAsmPseudoInst<opc, ".i16", asm, iops>;
2028 def S16 : NEONDataTypeAsmPseudoInst<opc, ".s16", asm, iops>;
2029 def U16 : NEONDataTypeAsmPseudoInst<opc, ".u16", asm, iops>;
2030 def P16 : NEONDataTypeAsmPseudoInst<opc, ".p16", asm, iops>;
2032 // NEONDT16ReqAsmPseudoInst plus plain ".16"
2033 multiclass NEONDT16AsmPseudoInst<string opc, string asm, dag iops> {
2034 def _16 : NEONDataTypeAsmPseudoInst<opc, ".16", asm, iops>;
2035 defm _ : NEONDT16ReqAsmPseudoInst<opc, asm, iops>;
2037 multiclass NEONDT32ReqAsmPseudoInst<string opc, string asm, dag iops> {
2038 def I32 : NEONDataTypeAsmPseudoInst<opc, ".i32", asm, iops>;
2039 def S32 : NEONDataTypeAsmPseudoInst<opc, ".s32", asm, iops>;
2040 def U32 : NEONDataTypeAsmPseudoInst<opc, ".u32", asm, iops>;
2041 def F32 : NEONDataTypeAsmPseudoInst<opc, ".f32", asm, iops>;
2042 def F : NEONDataTypeAsmPseudoInst<opc, ".f", asm, iops>;
2044 // NEONDT32ReqAsmPseudoInst plus plain ".32"
2045 multiclass NEONDT32AsmPseudoInst<string opc, string asm, dag iops> {
2046 def _32 : NEONDataTypeAsmPseudoInst<opc, ".32", asm, iops>;
2047 defm _ : NEONDT32ReqAsmPseudoInst<opc, asm, iops>;
2049 multiclass NEONDT64ReqAsmPseudoInst<string opc, string asm, dag iops> {
2050 def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
2051 def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
2052 def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
2053 def F64 : NEONDataTypeAsmPseudoInst<opc, ".f64", asm, iops>;
2054 def D : NEONDataTypeAsmPseudoInst<opc, ".d", asm, iops>;
2056 // NEONDT64ReqAsmPseudoInst plus plain ".64"
2057 multiclass NEONDT64AsmPseudoInst<string opc, string asm, dag iops> {
2058 def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
2059 defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
2061 multiclass NEONDT64NoF64ReqAsmPseudoInst<string opc, string asm, dag iops> {
2062 def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
2063 def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
2064 def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
2065 def D : NEONDataTypeAsmPseudoInst<opc, ".d", asm, iops>;
2067 // NEONDT64ReqAsmPseudoInst plus plain ".64"
2068 multiclass NEONDT64NoF64AsmPseudoInst<string opc, string asm, dag iops> {
2069 def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
2070 defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
2072 multiclass NEONDTAnyAsmPseudoInst<string opc, string asm, dag iops> {
2073 defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
2074 defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
2075 defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
2076 defm _ : NEONDT64AsmPseudoInst<opc, asm, iops>;
2078 multiclass NEONDTAnyNoF64AsmPseudoInst<string opc, string asm, dag iops> {
2079 defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
2080 defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
2081 defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
2082 defm _ : NEONDT64NoF64AsmPseudoInst<opc, asm, iops>;
2085 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2086 def : TokenAlias<".s8", ".i8">;
2087 def : TokenAlias<".u8", ".i8">;
2088 def : TokenAlias<".s16", ".i16">;
2089 def : TokenAlias<".u16", ".i16">;
2090 def : TokenAlias<".s32", ".i32">;
2091 def : TokenAlias<".u32", ".i32">;
2092 def : TokenAlias<".s64", ".i64">;
2093 def : TokenAlias<".u64", ".i64">;
2095 def : TokenAlias<".i8", ".8">;
2096 def : TokenAlias<".i16", ".16">;
2097 def : TokenAlias<".i32", ".32">;
2098 def : TokenAlias<".i64", ".64">;
2100 def : TokenAlias<".p8", ".8">;
2101 def : TokenAlias<".p16", ".16">;
2103 def : TokenAlias<".f32", ".32">;
2104 def : TokenAlias<".f64", ".64">;
2105 def : TokenAlias<".f", ".f32">;
2106 def : TokenAlias<".d", ".f64">;