1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def ArithMiscFrm : Format<11>;
37 def ExtFrm : Format<12>;
39 def VFPUnaryFrm : Format<13>;
40 def VFPBinaryFrm : Format<14>;
41 def VFPConv1Frm : Format<15>;
42 def VFPConv2Frm : Format<16>;
43 def VFPConv3Frm : Format<17>;
44 def VFPConv4Frm : Format<18>;
45 def VFPConv5Frm : Format<19>;
46 def VFPLdStFrm : Format<20>;
47 def VFPLdStMulFrm : Format<21>;
48 def VFPMiscFrm : Format<22>;
50 def ThumbFrm : Format<23>;
52 def NEONFrm : Format<24>;
53 def NEONGetLnFrm : Format<25>;
54 def NEONSetLnFrm : Format<26>;
55 def NEONDupFrm : Format<27>;
59 // the instruction has a Rn register operand.
60 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
61 // it doesn't have a Rn operand.
62 class UnaryDP { bit isUnaryDataProc = 1; }
64 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
65 // a 16-bit Thumb instruction if certain conditions are met.
66 class Xform16Bit { bit canXformTo16Bit = 1; }
68 //===----------------------------------------------------------------------===//
69 // ARM Instruction flags. These need to match ARMInstrInfo.h.
73 class AddrMode<bits<4> val> {
76 def AddrModeNone : AddrMode<0>;
77 def AddrMode1 : AddrMode<1>;
78 def AddrMode2 : AddrMode<2>;
79 def AddrMode3 : AddrMode<3>;
80 def AddrMode4 : AddrMode<4>;
81 def AddrMode5 : AddrMode<5>;
82 def AddrMode6 : AddrMode<6>;
83 def AddrModeT1_1 : AddrMode<7>;
84 def AddrModeT1_2 : AddrMode<8>;
85 def AddrModeT1_4 : AddrMode<9>;
86 def AddrModeT1_s : AddrMode<10>;
87 def AddrModeT2_i12: AddrMode<12>;
88 def AddrModeT2_i8 : AddrMode<12>;
89 def AddrModeT2_so : AddrMode<13>;
90 def AddrModeT2_pc : AddrMode<14>;
91 def AddrModeT2_i8s4 : AddrMode<15>;
94 class SizeFlagVal<bits<3> val> {
97 def SizeInvalid : SizeFlagVal<0>; // Unset.
98 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
99 def Size8Bytes : SizeFlagVal<2>;
100 def Size4Bytes : SizeFlagVal<3>;
101 def Size2Bytes : SizeFlagVal<4>;
103 // Load / store index mode.
104 class IndexMode<bits<2> val> {
107 def IndexModeNone : IndexMode<0>;
108 def IndexModePre : IndexMode<1>;
109 def IndexModePost : IndexMode<2>;
111 //===----------------------------------------------------------------------===//
113 // ARM Instruction templates.
116 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
117 Format f, string cstr>
121 let Namespace = "ARM";
125 bits<4> AddrModeBits = AM.Value;
128 bits<3> SizeFlag = SZ.Value;
131 bits<2> IndexModeBits = IM.Value;
134 bits<5> Form = F.Value;
137 // Attributes specific to ARM instructions...
139 bit isUnaryDataProc = 0;
140 bit canXformTo16Bit = 0;
142 let Constraints = cstr;
145 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
146 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
147 let OutOperandList = oops;
148 let InOperandList = iops;
150 let Pattern = pattern;
153 // Almost all ARM instructions are predicable.
154 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
155 IndexMode im, Format f, string opc, string asm, string cstr,
157 : InstARM<am, sz, im, f, cstr> {
158 let OutOperandList = oops;
159 let InOperandList = !con(iops, (ops pred:$p));
160 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
161 let Pattern = pattern;
162 list<Predicate> Predicates = [IsARM];
165 // Same as I except it can optionally modify CPSR. Note it's modeled as
166 // an input operand since by default it's a zero register. It will
167 // become an implicit def once it's "flipped".
168 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
169 IndexMode im, Format f, string opc, string asm, string cstr,
171 : InstARM<am, sz, im, f, cstr> {
172 let OutOperandList = oops;
173 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
174 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
175 let Pattern = pattern;
176 list<Predicate> Predicates = [IsARM];
180 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
181 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
182 : InstARM<am, sz, im, f, cstr> {
183 let OutOperandList = oops;
184 let InOperandList = iops;
186 let Pattern = pattern;
187 list<Predicate> Predicates = [IsARM];
190 class AI<dag oops, dag iops, Format f, string opc,
191 string asm, list<dag> pattern>
192 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
194 class AsI<dag oops, dag iops, Format f, string opc,
195 string asm, list<dag> pattern>
196 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
198 class AXI<dag oops, dag iops, Format f, string asm,
200 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
203 // Ctrl flow instructions
204 class ABI<bits<4> opcod, dag oops, dag iops, string opc,
205 string asm, list<dag> pattern>
206 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
208 let Inst{27-24} = opcod;
210 class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
211 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
213 let Inst{27-24} = opcod;
215 class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
216 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
219 // BR_JT instructions
220 class JTI<dag oops, dag iops, string asm, list<dag> pattern>
221 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
224 // addrmode1 instructions
225 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
226 string asm, list<dag> pattern>
227 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
229 let Inst{24-21} = opcod;
230 let Inst{27-26} = {0,0};
232 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
233 string asm, list<dag> pattern>
234 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
236 let Inst{24-21} = opcod;
237 let Inst{27-26} = {0,0};
239 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
241 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
243 let Inst{24-21} = opcod;
244 let Inst{27-26} = {0,0};
246 class AI1x2<dag oops, dag iops, Format f, string opc,
247 string asm, list<dag> pattern>
248 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
252 // addrmode2 loads and stores
253 class AI2<dag oops, dag iops, Format f, string opc,
254 string asm, list<dag> pattern>
255 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
257 let Inst{27-26} = {0,1};
261 class AI2ldw<dag oops, dag iops, Format f, string opc,
262 string asm, list<dag> pattern>
263 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
265 let Inst{20} = 1; // L bit
266 let Inst{21} = 0; // W bit
267 let Inst{22} = 0; // B bit
268 let Inst{24} = 1; // P bit
269 let Inst{27-26} = {0,1};
271 class AXI2ldw<dag oops, dag iops, Format f, string asm,
273 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
275 let Inst{20} = 1; // L bit
276 let Inst{21} = 0; // W bit
277 let Inst{22} = 0; // B bit
278 let Inst{24} = 1; // P bit
279 let Inst{27-26} = {0,1};
281 class AI2ldb<dag oops, dag iops, Format f, string opc,
282 string asm, list<dag> pattern>
283 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
285 let Inst{20} = 1; // L bit
286 let Inst{21} = 0; // W bit
287 let Inst{22} = 1; // B bit
288 let Inst{24} = 1; // P bit
289 let Inst{27-26} = {0,1};
291 class AXI2ldb<dag oops, dag iops, Format f, string asm,
293 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
295 let Inst{20} = 1; // L bit
296 let Inst{21} = 0; // W bit
297 let Inst{22} = 1; // B bit
298 let Inst{24} = 1; // P bit
299 let Inst{27-26} = {0,1};
303 class AI2stw<dag oops, dag iops, Format f, string opc,
304 string asm, list<dag> pattern>
305 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
307 let Inst{20} = 0; // L bit
308 let Inst{21} = 0; // W bit
309 let Inst{22} = 0; // B bit
310 let Inst{24} = 1; // P bit
311 let Inst{27-26} = {0,1};
313 class AXI2stw<dag oops, dag iops, Format f, string asm,
315 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
317 let Inst{20} = 0; // L bit
318 let Inst{21} = 0; // W bit
319 let Inst{22} = 0; // B bit
320 let Inst{24} = 1; // P bit
321 let Inst{27-26} = {0,1};
323 class AI2stb<dag oops, dag iops, Format f, string opc,
324 string asm, list<dag> pattern>
325 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
327 let Inst{20} = 0; // L bit
328 let Inst{21} = 0; // W bit
329 let Inst{22} = 1; // B bit
330 let Inst{24} = 1; // P bit
331 let Inst{27-26} = {0,1};
333 class AXI2stb<dag oops, dag iops, Format f, string asm,
335 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
337 let Inst{20} = 0; // L bit
338 let Inst{21} = 0; // W bit
339 let Inst{22} = 1; // B bit
340 let Inst{24} = 1; // P bit
341 let Inst{27-26} = {0,1};
345 class AI2ldwpr<dag oops, dag iops, Format f, string opc,
346 string asm, string cstr, list<dag> pattern>
347 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
348 asm, cstr, pattern> {
349 let Inst{20} = 1; // L bit
350 let Inst{21} = 1; // W bit
351 let Inst{22} = 0; // B bit
352 let Inst{24} = 1; // P bit
353 let Inst{27-26} = {0,1};
355 class AI2ldbpr<dag oops, dag iops, Format f, string opc,
356 string asm, string cstr, list<dag> pattern>
357 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
358 asm, cstr, pattern> {
359 let Inst{20} = 1; // L bit
360 let Inst{21} = 1; // W bit
361 let Inst{22} = 1; // B bit
362 let Inst{24} = 1; // P bit
363 let Inst{27-26} = {0,1};
366 // Pre-indexed stores
367 class AI2stwpr<dag oops, dag iops, Format f, string opc,
368 string asm, string cstr, list<dag> pattern>
369 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
370 asm, cstr, pattern> {
371 let Inst{20} = 0; // L bit
372 let Inst{21} = 1; // W bit
373 let Inst{22} = 0; // B bit
374 let Inst{24} = 1; // P bit
375 let Inst{27-26} = {0,1};
377 class AI2stbpr<dag oops, dag iops, Format f, string opc,
378 string asm, string cstr, list<dag> pattern>
379 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
380 asm, cstr, pattern> {
381 let Inst{20} = 0; // L bit
382 let Inst{21} = 1; // W bit
383 let Inst{22} = 1; // B bit
384 let Inst{24} = 1; // P bit
385 let Inst{27-26} = {0,1};
388 // Post-indexed loads
389 class AI2ldwpo<dag oops, dag iops, Format f, string opc,
390 string asm, string cstr, list<dag> pattern>
391 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
393 let Inst{20} = 1; // L bit
394 let Inst{21} = 0; // W bit
395 let Inst{22} = 0; // B bit
396 let Inst{24} = 0; // P bit
397 let Inst{27-26} = {0,1};
399 class AI2ldbpo<dag oops, dag iops, Format f, string opc,
400 string asm, string cstr, list<dag> pattern>
401 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
403 let Inst{20} = 1; // L bit
404 let Inst{21} = 0; // W bit
405 let Inst{22} = 1; // B bit
406 let Inst{24} = 0; // P bit
407 let Inst{27-26} = {0,1};
410 // Post-indexed stores
411 class AI2stwpo<dag oops, dag iops, Format f, string opc,
412 string asm, string cstr, list<dag> pattern>
413 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
415 let Inst{20} = 0; // L bit
416 let Inst{21} = 0; // W bit
417 let Inst{22} = 0; // B bit
418 let Inst{24} = 0; // P bit
419 let Inst{27-26} = {0,1};
421 class AI2stbpo<dag oops, dag iops, Format f, string opc,
422 string asm, string cstr, list<dag> pattern>
423 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
425 let Inst{20} = 0; // L bit
426 let Inst{21} = 0; // W bit
427 let Inst{22} = 1; // B bit
428 let Inst{24} = 0; // P bit
429 let Inst{27-26} = {0,1};
432 // addrmode3 instructions
433 class AI3<dag oops, dag iops, Format f, string opc,
434 string asm, list<dag> pattern>
435 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
437 class AXI3<dag oops, dag iops, Format f, string asm,
439 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
443 class AI3ldh<dag oops, dag iops, Format f, string opc,
444 string asm, list<dag> pattern>
445 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
448 let Inst{5} = 1; // H bit
449 let Inst{6} = 0; // S bit
451 let Inst{20} = 1; // L bit
452 let Inst{21} = 0; // W bit
453 let Inst{24} = 1; // P bit
454 let Inst{27-25} = 0b000;
456 class AXI3ldh<dag oops, dag iops, Format f, string asm,
458 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
461 let Inst{5} = 1; // H bit
462 let Inst{6} = 0; // S bit
464 let Inst{20} = 1; // L bit
465 let Inst{21} = 0; // W bit
466 let Inst{24} = 1; // P bit
468 class AI3ldsh<dag oops, dag iops, Format f, string opc,
469 string asm, list<dag> pattern>
470 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
473 let Inst{5} = 1; // H bit
474 let Inst{6} = 1; // S bit
476 let Inst{20} = 1; // L bit
477 let Inst{21} = 0; // W bit
478 let Inst{24} = 1; // P bit
479 let Inst{27-25} = 0b000;
481 class AXI3ldsh<dag oops, dag iops, Format f, string asm,
483 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
486 let Inst{5} = 1; // H bit
487 let Inst{6} = 1; // S bit
489 let Inst{20} = 1; // L bit
490 let Inst{21} = 0; // W bit
491 let Inst{24} = 1; // P bit
493 class AI3ldsb<dag oops, dag iops, Format f, string opc,
494 string asm, list<dag> pattern>
495 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
498 let Inst{5} = 0; // H bit
499 let Inst{6} = 1; // S bit
501 let Inst{20} = 1; // L bit
502 let Inst{21} = 0; // W bit
503 let Inst{24} = 1; // P bit
504 let Inst{27-25} = 0b000;
506 class AXI3ldsb<dag oops, dag iops, Format f, string asm,
508 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
511 let Inst{5} = 0; // H bit
512 let Inst{6} = 1; // S bit
514 let Inst{20} = 1; // L bit
515 let Inst{21} = 0; // W bit
516 let Inst{24} = 1; // P bit
518 class AI3ldd<dag oops, dag iops, Format f, string opc,
519 string asm, list<dag> pattern>
520 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
523 let Inst{5} = 0; // H bit
524 let Inst{6} = 1; // S bit
526 let Inst{20} = 0; // L bit
527 let Inst{21} = 0; // W bit
528 let Inst{24} = 1; // P bit
529 let Inst{27-25} = 0b000;
533 class AI3sth<dag oops, dag iops, Format f, string opc,
534 string asm, list<dag> pattern>
535 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
538 let Inst{5} = 1; // H bit
539 let Inst{6} = 0; // S bit
541 let Inst{20} = 0; // L bit
542 let Inst{21} = 0; // W bit
543 let Inst{24} = 1; // P bit
544 let Inst{27-25} = 0b000;
546 class AXI3sth<dag oops, dag iops, Format f, string asm,
548 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
551 let Inst{5} = 1; // H bit
552 let Inst{6} = 0; // S bit
554 let Inst{20} = 0; // L bit
555 let Inst{21} = 0; // W bit
556 let Inst{24} = 1; // P bit
558 class AI3std<dag oops, dag iops, Format f, string opc,
559 string asm, list<dag> pattern>
560 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
563 let Inst{5} = 1; // H bit
564 let Inst{6} = 1; // S bit
566 let Inst{20} = 0; // L bit
567 let Inst{21} = 0; // W bit
568 let Inst{24} = 1; // P bit
569 let Inst{27-25} = 0b000;
573 class AI3ldhpr<dag oops, dag iops, Format f, string opc,
574 string asm, string cstr, list<dag> pattern>
575 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
576 asm, cstr, pattern> {
578 let Inst{5} = 1; // H bit
579 let Inst{6} = 0; // S bit
581 let Inst{20} = 1; // L bit
582 let Inst{21} = 1; // W bit
583 let Inst{24} = 1; // P bit
584 let Inst{27-25} = 0b000;
586 class AI3ldshpr<dag oops, dag iops, Format f, string opc,
587 string asm, string cstr, list<dag> pattern>
588 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
589 asm, cstr, pattern> {
591 let Inst{5} = 1; // H bit
592 let Inst{6} = 1; // S bit
594 let Inst{20} = 1; // L bit
595 let Inst{21} = 1; // W bit
596 let Inst{24} = 1; // P bit
597 let Inst{27-25} = 0b000;
599 class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
600 string asm, string cstr, list<dag> pattern>
601 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
602 asm, cstr, pattern> {
604 let Inst{5} = 0; // H bit
605 let Inst{6} = 1; // S bit
607 let Inst{20} = 1; // L bit
608 let Inst{21} = 1; // W bit
609 let Inst{24} = 1; // P bit
610 let Inst{27-25} = 0b000;
613 // Pre-indexed stores
614 class AI3sthpr<dag oops, dag iops, Format f, string opc,
615 string asm, string cstr, list<dag> pattern>
616 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
617 asm, cstr, pattern> {
619 let Inst{5} = 1; // H bit
620 let Inst{6} = 0; // S bit
622 let Inst{20} = 0; // L bit
623 let Inst{21} = 1; // W bit
624 let Inst{24} = 1; // P bit
625 let Inst{27-25} = 0b000;
628 // Post-indexed loads
629 class AI3ldhpo<dag oops, dag iops, Format f, string opc,
630 string asm, string cstr, list<dag> pattern>
631 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
634 let Inst{5} = 1; // H bit
635 let Inst{6} = 0; // S bit
637 let Inst{20} = 1; // L bit
638 let Inst{21} = 1; // W bit
639 let Inst{24} = 0; // P bit
640 let Inst{27-25} = 0b000;
642 class AI3ldshpo<dag oops, dag iops, Format f, string opc,
643 string asm, string cstr, list<dag> pattern>
644 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
647 let Inst{5} = 1; // H bit
648 let Inst{6} = 1; // S bit
650 let Inst{20} = 1; // L bit
651 let Inst{21} = 1; // W bit
652 let Inst{24} = 0; // P bit
653 let Inst{27-25} = 0b000;
655 class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
656 string asm, string cstr, list<dag> pattern>
657 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
660 let Inst{5} = 0; // H bit
661 let Inst{6} = 1; // S bit
663 let Inst{20} = 1; // L bit
664 let Inst{21} = 1; // W bit
665 let Inst{24} = 0; // P bit
666 let Inst{27-25} = 0b000;
669 // Post-indexed stores
670 class AI3sthpo<dag oops, dag iops, Format f, string opc,
671 string asm, string cstr, list<dag> pattern>
672 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
675 let Inst{5} = 1; // H bit
676 let Inst{6} = 0; // S bit
678 let Inst{20} = 0; // L bit
679 let Inst{21} = 1; // W bit
680 let Inst{24} = 0; // P bit
681 let Inst{27-25} = 0b000;
685 // addrmode4 instructions
686 class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
687 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
689 let Inst{20} = 1; // L bit
690 let Inst{22} = 0; // S bit
691 let Inst{27-25} = 0b100;
693 class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
694 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
696 let Inst{20} = 0; // L bit
697 let Inst{22} = 0; // S bit
698 let Inst{27-25} = 0b100;
701 // Unsigned multiply, multiply-accumulate instructions.
702 class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
703 string asm, list<dag> pattern>
704 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
706 let Inst{7-4} = 0b1001;
707 let Inst{20} = 0; // S bit
708 let Inst{27-21} = opcod;
710 class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
711 string asm, list<dag> pattern>
712 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
714 let Inst{7-4} = 0b1001;
715 let Inst{27-21} = opcod;
718 // Most significant word multiply
719 class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
720 string asm, list<dag> pattern>
721 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
723 let Inst{7-4} = 0b1001;
725 let Inst{27-21} = opcod;
728 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
729 class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
730 string asm, list<dag> pattern>
731 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
736 let Inst{27-21} = opcod;
739 // Extend instructions.
740 class AExtI<bits<8> opcod, dag oops, dag iops, string opc,
741 string asm, list<dag> pattern>
742 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc,
744 let Inst{7-4} = 0b0111;
745 let Inst{27-20} = opcod;
748 // Misc Arithmetic instructions.
749 class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc,
750 string asm, list<dag> pattern>
751 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc,
753 let Inst{27-20} = opcod;
756 //===----------------------------------------------------------------------===//
758 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
759 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
760 list<Predicate> Predicates = [IsARM];
762 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
763 list<Predicate> Predicates = [IsARM, HasV5TE];
765 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
766 list<Predicate> Predicates = [IsARM, HasV6];
769 //===----------------------------------------------------------------------===//
771 // Thumb Instruction Format Definitions.
774 // TI - Thumb instruction.
776 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
777 string asm, string cstr, list<dag> pattern>
778 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
779 let OutOperandList = outs;
780 let InOperandList = ins;
782 let Pattern = pattern;
783 list<Predicate> Predicates = [IsThumb];
786 class TI<dag outs, dag ins, string asm, list<dag> pattern>
787 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
789 // BL, BLX(1) are translated by assembler into two instructions
790 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
791 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
793 // BR_JT instructions
794 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
795 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
797 // TPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
798 class TPat<dag pattern, dag result> : Pat<pattern, result> {
799 list<Predicate> Predicates = [IsThumb];
802 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
803 list<Predicate> Predicates = [IsThumb, HasV5T];
807 class Thumb1I<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
808 string asm, string cstr, list<dag> pattern>
809 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
810 let OutOperandList = outs;
811 let InOperandList = ins;
813 let Pattern = pattern;
814 list<Predicate> Predicates = [IsThumb1Only];
817 class T1I<dag outs, dag ins, string asm, list<dag> pattern>
818 : Thumb1I<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
819 class T1I1<dag outs, dag ins, string asm, list<dag> pattern>
820 : Thumb1I<outs, ins, AddrModeT1_1, Size2Bytes, asm, "", pattern>;
821 class T1I2<dag outs, dag ins, string asm, list<dag> pattern>
822 : Thumb1I<outs, ins, AddrModeT1_2, Size2Bytes, asm, "", pattern>;
823 class T1I4<dag outs, dag ins, string asm, list<dag> pattern>
824 : Thumb1I<outs, ins, AddrModeT1_4, Size2Bytes, asm, "", pattern>;
825 class T1Is<dag outs, dag ins, string asm, list<dag> pattern>
826 : Thumb1I<outs, ins, AddrModeT1_s, Size2Bytes, asm, "", pattern>;
827 class T1Ix2<dag outs, dag ins, string asm, list<dag> pattern>
828 : Thumb1I<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
829 class T1JTI<dag outs, dag ins, string asm, list<dag> pattern>
830 : Thumb1I<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
832 // Two-address instructions
833 class T1It<dag outs, dag ins, string asm, list<dag> pattern>
834 : Thumb1I<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
836 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
837 list<Predicate> Predicates = [IsThumb1Only];
840 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
841 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
842 string opc, string asm, string cstr, list<dag> pattern>
843 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
844 let OutOperandList = oops;
845 let InOperandList = !con(iops, (ops pred:$p));
846 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
847 let Pattern = pattern;
848 list<Predicate> Predicates = [IsThumb2];
851 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
852 // an input operand since by default it's a zero register. It will
853 // become an implicit def once it's "flipped".
854 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
856 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
857 string opc, string asm, string cstr, list<dag> pattern>
858 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
859 let OutOperandList = oops;
860 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
861 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
862 let Pattern = pattern;
863 list<Predicate> Predicates = [IsThumb2];
867 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
868 string asm, string cstr, list<dag> pattern>
869 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
870 let OutOperandList = oops;
871 let InOperandList = iops;
873 let Pattern = pattern;
874 list<Predicate> Predicates = [IsThumb2];
877 class T2I<dag oops, dag iops, string opc, string asm, list<dag> pattern>
878 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>;
879 class T2Ii12<dag oops, dag iops, string opc, string asm, list<dag> pattern>
880 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, opc, asm, "", pattern>;
881 class T2Ii8<dag oops, dag iops, string opc, string asm, list<dag> pattern>
882 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, opc, asm, "", pattern>;
883 class T2Iso<dag oops, dag iops, string opc, string asm, list<dag> pattern>
884 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, opc, asm, "", pattern>;
885 class T2Ipc<dag oops, dag iops, string opc, string asm, list<dag> pattern>
886 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, opc, asm, "", pattern>;
887 class T2Ii8s4<dag oops, dag iops, string opc, string asm, list<dag> pattern>
888 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, opc, asm, "", pattern>;
890 class T2sI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
891 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>;
893 class T2XI<dag oops, dag iops, string asm, list<dag> pattern>
894 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, asm, "", pattern>;
895 class T2JTI<dag oops, dag iops, string asm, list<dag> pattern>
896 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, asm, "", pattern>;
898 // T2Iidxldst - Thumb2 indexed load / store instructions.
899 class T2Iidxldst<dag oops, dag iops, AddrMode am, IndexMode im,
900 string opc, string asm, string cstr, list<dag> pattern>
901 : InstARM<am, Size4Bytes, im, ThumbFrm, cstr> {
902 let OutOperandList = oops;
903 let InOperandList = !con(iops, (ops pred:$p));
904 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
905 let Pattern = pattern;
906 list<Predicate> Predicates = [IsThumb2];
910 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
911 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
912 list<Predicate> Predicates = [IsThumb2];
915 //===----------------------------------------------------------------------===//
917 //===----------------------------------------------------------------------===//
918 // ARM VFP Instruction templates.
921 // Almost all VFP instructions are predicable.
922 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
923 IndexMode im, Format f, string opc, string asm, string cstr,
925 : InstARM<am, sz, im, f, cstr> {
926 let OutOperandList = oops;
927 let InOperandList = !con(iops, (ops pred:$p));
928 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
929 let Pattern = pattern;
930 list<Predicate> Predicates = [HasVFP2];
934 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
935 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
936 : InstARM<am, sz, im, f, cstr> {
937 let OutOperandList = oops;
938 let InOperandList = iops;
940 let Pattern = pattern;
941 list<Predicate> Predicates = [HasVFP2];
944 class VFPAI<dag oops, dag iops, Format f, string opc,
945 string asm, list<dag> pattern>
946 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
949 // ARM VFP addrmode5 loads and stores
950 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
951 string opc, string asm, list<dag> pattern>
952 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
953 VFPLdStFrm, opc, asm, "", pattern> {
954 // TODO: Mark the instructions with the appropriate subtarget info.
955 let Inst{27-24} = opcod1;
956 let Inst{21-20} = opcod2;
957 let Inst{11-8} = 0b1011;
960 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
961 string opc, string asm, list<dag> pattern>
962 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
963 VFPLdStFrm, opc, asm, "", pattern> {
964 // TODO: Mark the instructions with the appropriate subtarget info.
965 let Inst{27-24} = opcod1;
966 let Inst{21-20} = opcod2;
967 let Inst{11-8} = 0b1010;
970 // Load / store multiple
971 class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
972 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
973 VFPLdStMulFrm, asm, "", pattern> {
974 // TODO: Mark the instructions with the appropriate subtarget info.
975 let Inst{27-25} = 0b110;
976 let Inst{11-8} = 0b1011;
979 class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
980 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
981 VFPLdStMulFrm, asm, "", pattern> {
982 // TODO: Mark the instructions with the appropriate subtarget info.
983 let Inst{27-25} = 0b110;
984 let Inst{11-8} = 0b1010;
988 // Double precision, unary
989 class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
990 string opc, string asm, list<dag> pattern>
991 : VFPAI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
992 let Inst{27-20} = opcod1;
993 let Inst{19-16} = opcod2;
994 let Inst{11-8} = 0b1011;
995 let Inst{7-4} = opcod3;
998 // Double precision, binary
999 class ADbI<bits<8> opcod, dag oops, dag iops, string opc,
1000 string asm, list<dag> pattern>
1001 : VFPAI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
1002 let Inst{27-20} = opcod;
1003 let Inst{11-8} = 0b1011;
1006 // Single precision, unary
1007 class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
1008 string opc, string asm, list<dag> pattern>
1009 : VFPAI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
1010 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding.
1011 let Inst{27-20} = opcod1;
1012 let Inst{19-16} = opcod2;
1013 let Inst{11-8} = 0b1010;
1014 let Inst{7-4} = opcod3;
1017 // Single precision, binary
1018 class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
1019 string asm, list<dag> pattern>
1020 : VFPAI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
1021 // Bit 22 (D bit) can be changed during instruction encoding.
1022 let Inst{27-20} = opcod;
1023 let Inst{11-8} = 0b1010;
1026 // VFP conversion instructions
1027 class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
1028 dag oops, dag iops, string opc, string asm, list<dag> pattern>
1029 : VFPAI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
1030 let Inst{27-20} = opcod1;
1031 let Inst{19-16} = opcod2;
1032 let Inst{11-8} = opcod3;
1036 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1037 string opc, string asm, list<dag> pattern>
1038 : VFPAI<oops, iops, f, opc, asm, pattern> {
1039 let Inst{27-20} = opcod1;
1040 let Inst{11-8} = opcod2;
1044 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
1045 string asm, list<dag> pattern>
1046 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>;
1048 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
1049 string asm, list<dag> pattern>
1050 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>;
1052 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
1053 string asm, list<dag> pattern>
1054 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>;
1056 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
1057 string asm, list<dag> pattern>
1058 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>;
1060 //===----------------------------------------------------------------------===//
1062 //===----------------------------------------------------------------------===//
1063 // ARM NEON Instruction templates.
1066 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, string asm,
1067 string cstr, list<dag> pattern>
1068 : InstARM<am, Size4Bytes, im, NEONFrm, cstr> {
1069 let OutOperandList = oops;
1070 let InOperandList = iops;
1071 let AsmString = asm;
1072 let Pattern = pattern;
1073 list<Predicate> Predicates = [HasNEON];
1076 class NI<dag oops, dag iops, string asm, list<dag> pattern>
1077 : NeonI<oops, iops, AddrModeNone, IndexModeNone, asm, "", pattern> {
1080 class NLdSt<dag oops, dag iops, string asm, list<dag> pattern>
1081 : NeonI<oops, iops, AddrMode6, IndexModeNone, asm, "", pattern> {
1082 let Inst{31-24} = 0b11110100;
1085 class NDataI<dag oops, dag iops, string asm, string cstr, list<dag> pattern>
1086 : NeonI<oops, iops, AddrModeNone, IndexModeNone, asm, cstr, pattern> {
1087 let Inst{31-25} = 0b1111001;
1090 // NEON "one register and a modified immediate" format.
1091 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1093 dag oops, dag iops, string asm, string cstr, list<dag> pattern>
1094 : NDataI<oops, iops, asm, cstr, pattern> {
1095 let Inst{23} = op23;
1096 let Inst{21-19} = op21_19;
1097 let Inst{11-8} = op11_8;
1104 // NEON 2 vector register format.
1105 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1106 bits<5> op11_7, bit op6, bit op4,
1107 dag oops, dag iops, string asm, string cstr, list<dag> pattern>
1108 : NDataI<oops, iops, asm, cstr, pattern> {
1109 let Inst{24-23} = op24_23;
1110 let Inst{21-20} = op21_20;
1111 let Inst{19-18} = op19_18;
1112 let Inst{17-16} = op17_16;
1113 let Inst{11-7} = op11_7;
1118 // NEON 2 vector register with immediate.
1119 class N2VImm<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
1121 dag oops, dag iops, string asm, string cstr, list<dag> pattern>
1122 : NDataI<oops, iops, asm, cstr, pattern> {
1123 let Inst{24} = op24;
1124 let Inst{23} = op23;
1125 let Inst{21-16} = op21_16;
1126 let Inst{11-8} = op11_8;
1132 // NEON 3 vector register format.
1133 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1134 dag oops, dag iops, string asm, string cstr, list<dag> pattern>
1135 : NDataI<oops, iops, asm, cstr, pattern> {
1136 let Inst{24} = op24;
1137 let Inst{23} = op23;
1138 let Inst{21-20} = op21_20;
1139 let Inst{11-8} = op11_8;
1144 // NEON VMOVs between scalar and core registers.
1145 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1146 dag oops, dag iops, Format f, string opc, string asm,
1148 : AI<oops, iops, f, opc, asm, pattern> {
1149 let Inst{27-20} = opcod1;
1150 let Inst{11-8} = opcod2;
1151 let Inst{6-5} = opcod3;
1153 list<Predicate> Predicates = [HasNEON];
1155 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1156 dag oops, dag iops, string opc, string asm, list<dag> pattern>
1157 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, opc, asm,
1159 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1160 dag oops, dag iops, string opc, string asm, list<dag> pattern>
1161 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, opc, asm,
1163 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1164 dag oops, dag iops, string opc, string asm, list<dag> pattern>
1165 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, opc, asm, pattern>;