1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
155 let DecoderMethod = "DecodePredicateOperand";
158 // Selectable predicate operand for CMOV instructions. We can't use a normal
159 // predicate because the default values interfere with instruction selection. In
160 // all other respects it is identical though: pseudo-instruction expansion
161 // relies on the MachineOperands being compatible.
162 def cmovpred : Operand<i32>, PredicateOp,
163 ComplexPattern<i32, 2, "SelectCMOVPred"> {
164 let MIOperandInfo = (ops i32imm, i32imm);
165 let PrintMethod = "printPredicateOperand";
168 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
169 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
170 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
171 let EncoderMethod = "getCCOutOpValue";
172 let PrintMethod = "printSBitModifierOperand";
173 let ParserMatchClass = CCOutOperand;
174 let DecoderMethod = "DecodeCCOutOperand";
177 // Same as cc_out except it defaults to setting CPSR.
178 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
179 let EncoderMethod = "getCCOutOpValue";
180 let PrintMethod = "printSBitModifierOperand";
181 let ParserMatchClass = CCOutOperand;
182 let DecoderMethod = "DecodeCCOutOperand";
185 // ARM special operands for disassembly only.
187 def SetEndAsmOperand : ImmAsmOperand {
188 let Name = "SetEndImm";
189 let ParserMethod = "parseSetEndImm";
191 def setend_op : Operand<i32> {
192 let PrintMethod = "printSetendOperand";
193 let ParserMatchClass = SetEndAsmOperand;
196 def MSRMaskOperand : AsmOperandClass {
197 let Name = "MSRMask";
198 let ParserMethod = "parseMSRMaskOperand";
200 def msr_mask : Operand<i32> {
201 let PrintMethod = "printMSRMaskOperand";
202 let DecoderMethod = "DecodeMSRMask";
203 let ParserMatchClass = MSRMaskOperand;
206 // Shift Right Immediate - A shift right immediate is encoded differently from
207 // other shift immediates. The imm6 field is encoded like so:
210 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
211 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
212 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
213 // 64 64 - <imm> is encoded in imm6<5:0>
214 def shr_imm8_asm_operand : ImmAsmOperand { let Name = "ShrImm8"; }
215 def shr_imm8 : Operand<i32> {
216 let EncoderMethod = "getShiftRight8Imm";
217 let DecoderMethod = "DecodeShiftRight8Imm";
218 let ParserMatchClass = shr_imm8_asm_operand;
220 def shr_imm16_asm_operand : ImmAsmOperand { let Name = "ShrImm16"; }
221 def shr_imm16 : Operand<i32> {
222 let EncoderMethod = "getShiftRight16Imm";
223 let DecoderMethod = "DecodeShiftRight16Imm";
224 let ParserMatchClass = shr_imm16_asm_operand;
226 def shr_imm32_asm_operand : ImmAsmOperand { let Name = "ShrImm32"; }
227 def shr_imm32 : Operand<i32> {
228 let EncoderMethod = "getShiftRight32Imm";
229 let DecoderMethod = "DecodeShiftRight32Imm";
230 let ParserMatchClass = shr_imm32_asm_operand;
232 def shr_imm64_asm_operand : ImmAsmOperand { let Name = "ShrImm64"; }
233 def shr_imm64 : Operand<i32> {
234 let EncoderMethod = "getShiftRight64Imm";
235 let DecoderMethod = "DecodeShiftRight64Imm";
236 let ParserMatchClass = shr_imm64_asm_operand;
239 //===----------------------------------------------------------------------===//
240 // ARM Assembler alias templates.
242 class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
243 : InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
244 class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
245 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
246 class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
247 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
248 class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
249 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
250 class VFP2DPInstAlias<string Asm, dag Result, bit Emit = 0b1>
251 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP2,HasDPVFP]>;
252 class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
253 : InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
254 class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
255 : InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
258 class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
260 class NEONMnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
263 //===----------------------------------------------------------------------===//
264 // ARM Instruction templates.
268 class InstTemplate<AddrMode am, int sz, IndexMode im,
269 Format f, Domain d, string cstr, InstrItinClass itin>
271 let Namespace = "ARM";
276 bits<2> IndexModeBits = IM.Value;
278 bits<6> Form = F.Value;
280 bit isUnaryDataProc = 0;
281 bit canXformTo16Bit = 0;
282 // The instruction is a 16-bit flag setting Thumb instruction. Used
283 // by the parser to determine whether to require the 'S' suffix on the
284 // mnemonic (when not in an IT block) or preclude it (when in an IT block).
285 bit thumbArithFlagSetting = 0;
287 // If this is a pseudo instruction, mark it isCodeGenOnly.
288 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
290 // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
291 let TSFlags{4-0} = AM.Value;
292 let TSFlags{6-5} = IndexModeBits;
293 let TSFlags{12-7} = Form;
294 let TSFlags{13} = isUnaryDataProc;
295 let TSFlags{14} = canXformTo16Bit;
296 let TSFlags{17-15} = D.Value;
297 let TSFlags{18} = thumbArithFlagSetting;
299 let Constraints = cstr;
300 let Itinerary = itin;
305 // Mask of bits that cause an encoding to be UNPREDICTABLE.
306 // If a bit is set, then if the corresponding bit in the
307 // target encoding differs from its value in the "Inst" field,
308 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
309 field bits<32> Unpredictable = 0;
310 // SoftFail is the generic name for this field, but we alias it so
311 // as to make it more obvious what it means in ARM-land.
312 field bits<32> SoftFail = Unpredictable;
315 class InstARM<AddrMode am, int sz, IndexMode im,
316 Format f, Domain d, string cstr, InstrItinClass itin>
317 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
318 let DecoderNamespace = "ARM";
321 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
322 // on by adding flavors to specific instructions.
323 class InstThumb<AddrMode am, int sz, IndexMode im,
324 Format f, Domain d, string cstr, InstrItinClass itin>
325 : InstTemplate<am, sz, im, f, d, cstr, itin> {
326 let DecoderNamespace = "Thumb";
329 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
330 // These are aliases that require C++ handling to convert to the target
331 // instruction, while InstAliases can be handled directly by tblgen.
332 class AsmPseudoInst<string asm, dag iops>
333 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
335 let OutOperandList = (outs);
336 let InOperandList = iops;
338 let isCodeGenOnly = 0; // So we get asm matcher for it.
343 class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
345 class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
347 class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
348 Requires<[IsThumb2]>;
349 class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
351 class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
354 // Pseudo instructions for the code generator.
355 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
356 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
357 GenericDomain, "", itin> {
358 let OutOperandList = oops;
359 let InOperandList = iops;
360 let Pattern = pattern;
361 let isCodeGenOnly = 1;
365 // PseudoInst that's ARM-mode only.
366 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
368 : PseudoInst<oops, iops, itin, pattern> {
370 list<Predicate> Predicates = [IsARM];
373 // PseudoInst that's Thumb-mode only.
374 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
376 : PseudoInst<oops, iops, itin, pattern> {
378 list<Predicate> Predicates = [IsThumb];
381 // PseudoInst that's Thumb2-mode only.
382 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
384 : PseudoInst<oops, iops, itin, pattern> {
386 list<Predicate> Predicates = [IsThumb2];
389 class ARMPseudoExpand<dag oops, dag iops, int sz,
390 InstrItinClass itin, list<dag> pattern,
392 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
393 PseudoInstExpansion<Result>;
395 class tPseudoExpand<dag oops, dag iops, int sz,
396 InstrItinClass itin, list<dag> pattern,
398 : tPseudoInst<oops, iops, sz, itin, pattern>,
399 PseudoInstExpansion<Result>;
401 class t2PseudoExpand<dag oops, dag iops, int sz,
402 InstrItinClass itin, list<dag> pattern,
404 : t2PseudoInst<oops, iops, sz, itin, pattern>,
405 PseudoInstExpansion<Result>;
407 // Almost all ARM instructions are predicable.
408 class I<dag oops, dag iops, AddrMode am, int sz,
409 IndexMode im, Format f, InstrItinClass itin,
410 string opc, string asm, string cstr,
412 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
415 let OutOperandList = oops;
416 let InOperandList = !con(iops, (ins pred:$p));
417 let AsmString = !strconcat(opc, "${p}", asm);
418 let Pattern = pattern;
419 list<Predicate> Predicates = [IsARM];
422 // A few are not predicable
423 class InoP<dag oops, dag iops, AddrMode am, int sz,
424 IndexMode im, Format f, InstrItinClass itin,
425 string opc, string asm, string cstr,
427 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
428 let OutOperandList = oops;
429 let InOperandList = iops;
430 let AsmString = !strconcat(opc, asm);
431 let Pattern = pattern;
432 let isPredicable = 0;
433 list<Predicate> Predicates = [IsARM];
436 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
437 // operand since by default it's a zero register. It will become an implicit def
438 // once it's "flipped".
439 class sI<dag oops, dag iops, AddrMode am, int sz,
440 IndexMode im, Format f, InstrItinClass itin,
441 string opc, string asm, string cstr,
443 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
444 bits<4> p; // Predicate operand
445 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
449 let OutOperandList = oops;
450 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
451 let AsmString = !strconcat(opc, "${s}${p}", asm);
452 let Pattern = pattern;
453 list<Predicate> Predicates = [IsARM];
457 class XI<dag oops, dag iops, AddrMode am, int sz,
458 IndexMode im, Format f, InstrItinClass itin,
459 string asm, string cstr, list<dag> pattern>
460 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
461 let OutOperandList = oops;
462 let InOperandList = iops;
464 let Pattern = pattern;
465 list<Predicate> Predicates = [IsARM];
468 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
471 opc, asm, "", pattern>;
472 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
473 string opc, string asm, list<dag> pattern>
474 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
475 opc, asm, "", pattern>;
476 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
477 string asm, list<dag> pattern>
478 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
480 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
481 string opc, string asm, list<dag> pattern>
482 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
483 opc, asm, "", pattern>;
485 // Ctrl flow instructions
486 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
487 string opc, string asm, list<dag> pattern>
488 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
489 opc, asm, "", pattern> {
490 let Inst{27-24} = opcod;
492 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
493 string asm, list<dag> pattern>
494 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
496 let Inst{27-24} = opcod;
499 // BR_JT instructions
500 class JTI<dag oops, dag iops, InstrItinClass itin,
501 string asm, list<dag> pattern>
502 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
505 class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
506 string opc, string asm, list<dag> pattern>
507 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
508 opc, asm, "", pattern> {
511 let Inst{27-23} = 0b00011;
512 let Inst{22-21} = opcod;
514 let Inst{19-16} = addr;
515 let Inst{15-12} = Rt;
516 let Inst{11-10} = 0b11;
517 let Inst{9-8} = opcod2;
518 let Inst{7-0} = 0b10011111;
520 class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
521 string opc, string asm, list<dag> pattern>
522 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
523 opc, asm, "", pattern> {
526 let Inst{27-23} = 0b00011;
527 let Inst{22-21} = opcod;
529 let Inst{19-16} = addr;
530 let Inst{11-10} = 0b11;
531 let Inst{9-8} = opcod2;
532 let Inst{7-4} = 0b1001;
535 // Atomic load/store instructions
536 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
537 string opc, string asm, list<dag> pattern>
538 : AIldr_ex_or_acq<opcod, 0b11, oops, iops, itin, opc, asm, pattern>;
540 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
541 string opc, string asm, list<dag> pattern>
542 : AIstr_ex_or_rel<opcod, 0b11, oops, iops, itin, opc, asm, pattern> {
544 let Inst{15-12} = Rd;
547 // Exclusive load/store instructions
549 class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
550 string opc, string asm, list<dag> pattern>
551 : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
552 Requires<[IsARM, HasV8]>;
554 class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
555 string opc, string asm, list<dag> pattern>
556 : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
557 Requires<[IsARM, HasV8]> {
559 let Inst{15-12} = Rd;
562 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
563 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
567 let Inst{27-23} = 0b00010;
569 let Inst{21-20} = 0b00;
570 let Inst{19-16} = addr;
571 let Inst{15-12} = Rt;
572 let Inst{11-4} = 0b00001001;
575 let Unpredictable{11-8} = 0b1111;
576 let DecoderMethod = "DecodeSwap";
578 // Acquire/Release load/store instructions
579 class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
580 string opc, string asm, list<dag> pattern>
581 : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
582 Requires<[IsARM, HasV8]>;
584 class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
585 string opc, string asm, list<dag> pattern>
586 : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
587 Requires<[IsARM, HasV8]> {
588 let Inst{15-12} = 0b1111;
591 // addrmode1 instructions
592 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
593 string opc, string asm, list<dag> pattern>
594 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
595 opc, asm, "", pattern> {
596 let Inst{24-21} = opcod;
597 let Inst{27-26} = 0b00;
599 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
600 string opc, string asm, list<dag> pattern>
601 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
602 opc, asm, "", pattern> {
603 let Inst{24-21} = opcod;
604 let Inst{27-26} = 0b00;
606 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
607 string asm, list<dag> pattern>
608 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
610 let Inst{24-21} = opcod;
611 let Inst{27-26} = 0b00;
616 // LDR/LDRB/STR/STRB/...
617 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
618 Format f, InstrItinClass itin, string opc, string asm,
620 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
622 let Inst{27-25} = op;
623 let Inst{24} = 1; // 24 == P
625 let Inst{22} = isByte;
626 let Inst{21} = 0; // 21 == W
629 // Indexed load/stores
630 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
631 IndexMode im, Format f, InstrItinClass itin, string opc,
632 string asm, string cstr, list<dag> pattern>
633 : I<oops, iops, AddrMode2, 4, im, f, itin,
634 opc, asm, cstr, pattern> {
636 let Inst{27-26} = 0b01;
637 let Inst{24} = isPre; // P bit
638 let Inst{22} = isByte; // B bit
639 let Inst{21} = isPre; // W bit
640 let Inst{20} = isLd; // L bit
641 let Inst{15-12} = Rt;
643 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
644 IndexMode im, Format f, InstrItinClass itin, string opc,
645 string asm, string cstr, list<dag> pattern>
646 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
648 // AM2 store w/ two operands: (GPR, am2offset)
654 let Inst{23} = offset{12};
655 let Inst{19-16} = Rn;
656 let Inst{11-5} = offset{11-5};
658 let Inst{3-0} = offset{3-0};
661 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
662 IndexMode im, Format f, InstrItinClass itin, string opc,
663 string asm, string cstr, list<dag> pattern>
664 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
666 // AM2 store w/ two operands: (GPR, am2offset)
672 let Inst{23} = offset{12};
673 let Inst{19-16} = Rn;
674 let Inst{11-0} = offset{11-0};
678 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
679 // but for now use this class for STRT and STRBT.
680 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
681 IndexMode im, Format f, InstrItinClass itin, string opc,
682 string asm, string cstr, list<dag> pattern>
683 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
685 // AM2 store w/ two operands: (GPR, am2offset)
687 // {13} 1 == Rm, 0 == imm12
691 let Inst{25} = addr{13};
692 let Inst{23} = addr{12};
693 let Inst{19-16} = addr{17-14};
694 let Inst{11-0} = addr{11-0};
697 // addrmode3 instructions
698 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
699 InstrItinClass itin, string opc, string asm, list<dag> pattern>
700 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
701 opc, asm, "", pattern> {
704 let Inst{27-25} = 0b000;
705 let Inst{24} = 1; // P bit
706 let Inst{23} = addr{8}; // U bit
707 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
708 let Inst{21} = 0; // W bit
709 let Inst{20} = op20; // L bit
710 let Inst{19-16} = addr{12-9}; // Rn
711 let Inst{15-12} = Rt; // Rt
712 let Inst{11-8} = addr{7-4}; // imm7_4/zero
714 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
716 let DecoderMethod = "DecodeAddrMode3Instruction";
719 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
720 IndexMode im, Format f, InstrItinClass itin, string opc,
721 string asm, string cstr, list<dag> pattern>
722 : I<oops, iops, AddrMode3, 4, im, f, itin,
723 opc, asm, cstr, pattern> {
725 let Inst{27-25} = 0b000;
726 let Inst{24} = isPre; // P bit
727 let Inst{21} = isPre; // W bit
728 let Inst{20} = op20; // L bit
729 let Inst{15-12} = Rt; // Rt
733 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
734 // but for now use this class for LDRSBT, LDRHT, LDSHT.
735 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
736 IndexMode im, Format f, InstrItinClass itin, string opc,
737 string asm, string cstr, list<dag> pattern>
738 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
739 // {13} 1 == imm8, 0 == Rm
746 let Inst{27-25} = 0b000;
747 let Inst{24} = 0; // P bit
749 let Inst{20} = isLoad; // L bit
750 let Inst{19-16} = addr; // Rn
751 let Inst{15-12} = Rt; // Rt
756 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
757 string opc, string asm, list<dag> pattern>
758 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
759 opc, asm, "", pattern> {
762 let Inst{27-25} = 0b000;
763 let Inst{24} = 1; // P bit
764 let Inst{23} = addr{8}; // U bit
765 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
766 let Inst{21} = 0; // W bit
767 let Inst{20} = 0; // L bit
768 let Inst{19-16} = addr{12-9}; // Rn
769 let Inst{15-12} = Rt; // Rt
770 let Inst{11-8} = addr{7-4}; // imm7_4/zero
772 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
773 let DecoderMethod = "DecodeAddrMode3Instruction";
776 // addrmode4 instructions
777 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
778 string asm, string cstr, list<dag> pattern>
779 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
784 let Inst{27-25} = 0b100;
785 let Inst{22} = 0; // S bit
786 let Inst{19-16} = Rn;
787 let Inst{15-0} = regs;
790 // Unsigned multiply, multiply-accumulate instructions.
791 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
792 string opc, string asm, list<dag> pattern>
793 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
794 opc, asm, "", pattern> {
795 let Inst{7-4} = 0b1001;
796 let Inst{20} = 0; // S bit
797 let Inst{27-21} = opcod;
799 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
800 string opc, string asm, list<dag> pattern>
801 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
802 opc, asm, "", pattern> {
803 let Inst{7-4} = 0b1001;
804 let Inst{27-21} = opcod;
807 // Most significant word multiply
808 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
809 InstrItinClass itin, string opc, string asm, list<dag> pattern>
810 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
811 opc, asm, "", pattern> {
815 let Inst{7-4} = opc7_4;
817 let Inst{27-21} = opcod;
818 let Inst{19-16} = Rd;
822 // MSW multiple w/ Ra operand
823 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
824 InstrItinClass itin, string opc, string asm, list<dag> pattern>
825 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
827 let Inst{15-12} = Ra;
830 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
831 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
832 InstrItinClass itin, string opc, string asm, list<dag> pattern>
833 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
834 opc, asm, "", pattern> {
840 let Inst{27-21} = opcod;
841 let Inst{6-5} = bit6_5;
845 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
846 InstrItinClass itin, string opc, string asm, list<dag> pattern>
847 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
849 let Inst{19-16} = Rd;
852 // AMulxyI with Ra operand
853 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
854 InstrItinClass itin, string opc, string asm, list<dag> pattern>
855 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
857 let Inst{15-12} = Ra;
860 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
861 InstrItinClass itin, string opc, string asm, list<dag> pattern>
862 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
865 let Inst{19-16} = RdHi;
866 let Inst{15-12} = RdLo;
869 // Extend instructions.
870 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
871 string opc, string asm, list<dag> pattern>
872 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
873 opc, asm, "", pattern> {
874 // All AExtI instructions have Rd and Rm register operands.
877 let Inst{15-12} = Rd;
879 let Inst{7-4} = 0b0111;
880 let Inst{9-8} = 0b00;
881 let Inst{27-20} = opcod;
883 let Unpredictable{9-8} = 0b11;
886 // Misc Arithmetic instructions.
887 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
888 InstrItinClass itin, string opc, string asm, list<dag> pattern>
889 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
890 opc, asm, "", pattern> {
893 let Inst{27-20} = opcod;
894 let Inst{19-16} = 0b1111;
895 let Inst{15-12} = Rd;
896 let Inst{11-8} = 0b1111;
897 let Inst{7-4} = opc7_4;
901 // Division instructions.
902 class ADivA1I<bits<3> opcod, dag oops, dag iops,
903 InstrItinClass itin, string opc, string asm, list<dag> pattern>
904 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
905 opc, asm, "", pattern> {
909 let Inst{27-23} = 0b01110;
910 let Inst{22-20} = opcod;
911 let Inst{19-16} = Rd;
912 let Inst{15-12} = 0b1111;
914 let Inst{7-4} = 0b0001;
919 def PKHLSLAsmOperand : ImmAsmOperand {
920 let Name = "PKHLSLImm";
921 let ParserMethod = "parsePKHLSLImm";
923 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
924 let PrintMethod = "printPKHLSLShiftImm";
925 let ParserMatchClass = PKHLSLAsmOperand;
927 def PKHASRAsmOperand : AsmOperandClass {
928 let Name = "PKHASRImm";
929 let ParserMethod = "parsePKHASRImm";
931 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
932 let PrintMethod = "printPKHASRShiftImm";
933 let ParserMatchClass = PKHASRAsmOperand;
936 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
937 string opc, string asm, list<dag> pattern>
938 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
939 opc, asm, "", pattern> {
944 let Inst{27-20} = opcod;
945 let Inst{19-16} = Rn;
946 let Inst{15-12} = Rd;
949 let Inst{5-4} = 0b01;
953 //===----------------------------------------------------------------------===//
955 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
956 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
957 list<Predicate> Predicates = [IsARM];
959 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
960 list<Predicate> Predicates = [IsARM, HasV5T];
962 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
963 list<Predicate> Predicates = [IsARM, HasV5TE];
965 // ARMV5MOPat - Same as ARMV5TEPat with UseMulOps.
966 class ARMV5MOPat<dag pattern, dag result> : Pat<pattern, result> {
967 list<Predicate> Predicates = [IsARM, HasV5TE, UseMulOps];
969 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
970 list<Predicate> Predicates = [IsARM, HasV6];
973 //===----------------------------------------------------------------------===//
974 // Thumb Instruction Format Definitions.
977 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
978 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
979 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
980 let OutOperandList = oops;
981 let InOperandList = iops;
983 let Pattern = pattern;
984 list<Predicate> Predicates = [IsThumb];
987 // TI - Thumb instruction.
988 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
989 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
991 // Two-address instructions
992 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
994 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
997 // tBL, tBX 32-bit instructions
998 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
999 dag oops, dag iops, InstrItinClass itin, string asm,
1001 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
1003 let Inst{31-27} = opcod1;
1004 let Inst{15-14} = opcod2;
1005 let Inst{12} = opcod3;
1008 // BR_JT instructions
1009 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1011 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1014 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
1015 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1016 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1017 let OutOperandList = oops;
1018 let InOperandList = iops;
1019 let AsmString = asm;
1020 let Pattern = pattern;
1021 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1024 class T1I<dag oops, dag iops, InstrItinClass itin,
1025 string asm, list<dag> pattern>
1026 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
1027 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1028 string asm, list<dag> pattern>
1029 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1031 // Two-address instructions
1032 class T1It<dag oops, dag iops, InstrItinClass itin,
1033 string asm, string cstr, list<dag> pattern>
1034 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
1035 asm, cstr, pattern>;
1037 // Thumb1 instruction that can either be predicated or set CPSR.
1038 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
1039 InstrItinClass itin,
1040 string opc, string asm, string cstr, list<dag> pattern>
1041 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1042 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1043 let InOperandList = !con(iops, (ins pred:$p));
1044 let AsmString = !strconcat(opc, "${s}${p}", asm);
1045 let Pattern = pattern;
1046 let thumbArithFlagSetting = 1;
1047 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1048 let DecoderNamespace = "ThumbSBit";
1051 class T1sI<dag oops, dag iops, InstrItinClass itin,
1052 string opc, string asm, list<dag> pattern>
1053 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1055 // Two-address instructions
1056 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1057 string opc, string asm, list<dag> pattern>
1058 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1059 "$Rn = $Rdn", pattern>;
1061 // Thumb1 instruction that can be predicated.
1062 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
1063 InstrItinClass itin,
1064 string opc, string asm, string cstr, list<dag> pattern>
1065 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1066 let OutOperandList = oops;
1067 let InOperandList = !con(iops, (ins pred:$p));
1068 let AsmString = !strconcat(opc, "${p}", asm);
1069 let Pattern = pattern;
1070 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1073 class T1pI<dag oops, dag iops, InstrItinClass itin,
1074 string opc, string asm, list<dag> pattern>
1075 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
1077 // Two-address instructions
1078 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1079 string opc, string asm, list<dag> pattern>
1080 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
1081 "$Rn = $Rdn", pattern>;
1083 class T1pIs<dag oops, dag iops,
1084 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1085 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
1087 class Encoding16 : Encoding {
1088 let Inst{31-16} = 0x0000;
1091 // A6.2 16-bit Thumb instruction encoding
1092 class T1Encoding<bits<6> opcode> : Encoding16 {
1093 let Inst{15-10} = opcode;
1096 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1097 class T1General<bits<5> opcode> : Encoding16 {
1098 let Inst{15-14} = 0b00;
1099 let Inst{13-9} = opcode;
1102 // A6.2.2 Data-processing encoding.
1103 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1104 let Inst{15-10} = 0b010000;
1105 let Inst{9-6} = opcode;
1108 // A6.2.3 Special data instructions and branch and exchange encoding.
1109 class T1Special<bits<4> opcode> : Encoding16 {
1110 let Inst{15-10} = 0b010001;
1111 let Inst{9-6} = opcode;
1114 // A6.2.4 Load/store single data item encoding.
1115 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1116 let Inst{15-12} = opA;
1117 let Inst{11-9} = opB;
1119 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1121 class T1BranchCond<bits<4> opcode> : Encoding16 {
1122 let Inst{15-12} = opcode;
1125 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1126 // following bits are used for "opA" (see A6.2.4):
1128 // 0b0110 => Immediate, 4 bytes
1129 // 0b1000 => Immediate, 2 bytes
1130 // 0b0111 => Immediate, 1 byte
1131 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1132 InstrItinClass itin, string opc, string asm,
1134 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1135 T1LoadStore<0b0101, opcode> {
1138 let Inst{8-6} = addr{5-3}; // Rm
1139 let Inst{5-3} = addr{2-0}; // Rn
1142 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1143 InstrItinClass itin, string opc, string asm,
1145 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1146 T1LoadStore<opA, {opB,?,?}> {
1149 let Inst{10-6} = addr{7-3}; // imm5
1150 let Inst{5-3} = addr{2-0}; // Rn
1154 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1155 class T1Misc<bits<7> opcode> : Encoding16 {
1156 let Inst{15-12} = 0b1011;
1157 let Inst{11-5} = opcode;
1160 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1161 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1162 InstrItinClass itin,
1163 string opc, string asm, string cstr, list<dag> pattern>
1164 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1165 let OutOperandList = oops;
1166 let InOperandList = !con(iops, (ins pred:$p));
1167 let AsmString = !strconcat(opc, "${p}", asm);
1168 let Pattern = pattern;
1169 list<Predicate> Predicates = [IsThumb2];
1170 let DecoderNamespace = "Thumb2";
1173 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1174 // input operand since by default it's a zero register. It will become an
1175 // implicit def once it's "flipped".
1177 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1179 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1180 InstrItinClass itin,
1181 string opc, string asm, string cstr, list<dag> pattern>
1182 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1183 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1186 let OutOperandList = oops;
1187 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1188 let AsmString = !strconcat(opc, "${s}${p}", asm);
1189 let Pattern = pattern;
1190 list<Predicate> Predicates = [IsThumb2];
1191 let DecoderNamespace = "Thumb2";
1195 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1196 InstrItinClass itin,
1197 string asm, string cstr, list<dag> pattern>
1198 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1199 let OutOperandList = oops;
1200 let InOperandList = iops;
1201 let AsmString = asm;
1202 let Pattern = pattern;
1203 list<Predicate> Predicates = [IsThumb2];
1204 let DecoderNamespace = "Thumb2";
1207 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1208 InstrItinClass itin,
1209 string asm, string cstr, list<dag> pattern>
1210 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1211 let OutOperandList = oops;
1212 let InOperandList = iops;
1213 let AsmString = asm;
1214 let Pattern = pattern;
1215 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1216 let DecoderNamespace = "Thumb";
1219 class T2I<dag oops, dag iops, InstrItinClass itin,
1220 string opc, string asm, list<dag> pattern>
1221 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1222 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1223 string opc, string asm, list<dag> pattern>
1224 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1225 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1226 string opc, string asm, list<dag> pattern>
1227 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1228 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1229 string opc, string asm, list<dag> pattern>
1230 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1231 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1232 string opc, string asm, list<dag> pattern>
1233 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1234 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1235 string opc, string asm, string cstr, list<dag> pattern>
1236 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1241 let Inst{31-25} = 0b1110100;
1243 let Inst{23} = addr{8};
1246 let Inst{20} = isLoad;
1247 let Inst{19-16} = addr{12-9};
1248 let Inst{15-12} = Rt{3-0};
1249 let Inst{11-8} = Rt2{3-0};
1250 let Inst{7-0} = addr{7-0};
1252 class T2Ii8s4post<bit P, bit W, bit isLoad, dag oops, dag iops,
1253 InstrItinClass itin, string opc, string asm, string cstr,
1255 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, cstr,
1261 let Inst{31-25} = 0b1110100;
1263 let Inst{23} = imm{8};
1266 let Inst{20} = isLoad;
1267 let Inst{19-16} = addr;
1268 let Inst{15-12} = Rt{3-0};
1269 let Inst{11-8} = Rt2{3-0};
1270 let Inst{7-0} = imm{7-0};
1273 class T2sI<dag oops, dag iops, InstrItinClass itin,
1274 string opc, string asm, list<dag> pattern>
1275 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1277 class T2XI<dag oops, dag iops, InstrItinClass itin,
1278 string asm, list<dag> pattern>
1279 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1280 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1281 string asm, list<dag> pattern>
1282 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1284 // Move to/from coprocessor instructions
1285 class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
1287 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
1288 let Inst{31-28} = opc;
1291 // Two-address instructions
1292 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1293 string asm, string cstr, list<dag> pattern>
1294 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1296 // T2Ipreldst - Thumb2 pre-indexed load / store instructions.
1297 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1299 AddrMode am, IndexMode im, InstrItinClass itin,
1300 string opc, string asm, string cstr, list<dag> pattern>
1301 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1302 let OutOperandList = oops;
1303 let InOperandList = !con(iops, (ins pred:$p));
1304 let AsmString = !strconcat(opc, "${p}", asm);
1305 let Pattern = pattern;
1306 list<Predicate> Predicates = [IsThumb2];
1307 let DecoderNamespace = "Thumb2";
1311 let Inst{31-27} = 0b11111;
1312 let Inst{26-25} = 0b00;
1313 let Inst{24} = signed;
1315 let Inst{22-21} = opcod;
1316 let Inst{20} = load;
1317 let Inst{19-16} = addr{12-9};
1318 let Inst{15-12} = Rt{3-0};
1320 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1321 let Inst{10} = pre; // The P bit.
1322 let Inst{9} = addr{8}; // Sign bit
1323 let Inst{8} = 1; // The W bit.
1324 let Inst{7-0} = addr{7-0};
1326 let DecoderMethod = "DecodeT2LdStPre";
1329 // T2Ipostldst - Thumb2 post-indexed load / store instructions.
1330 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1332 AddrMode am, IndexMode im, InstrItinClass itin,
1333 string opc, string asm, string cstr, list<dag> pattern>
1334 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1335 let OutOperandList = oops;
1336 let InOperandList = !con(iops, (ins pred:$p));
1337 let AsmString = !strconcat(opc, "${p}", asm);
1338 let Pattern = pattern;
1339 list<Predicate> Predicates = [IsThumb2];
1340 let DecoderNamespace = "Thumb2";
1345 let Inst{31-27} = 0b11111;
1346 let Inst{26-25} = 0b00;
1347 let Inst{24} = signed;
1349 let Inst{22-21} = opcod;
1350 let Inst{20} = load;
1351 let Inst{19-16} = Rn;
1352 let Inst{15-12} = Rt{3-0};
1354 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1355 let Inst{10} = pre; // The P bit.
1356 let Inst{9} = offset{8}; // Sign bit
1357 let Inst{8} = 1; // The W bit.
1358 let Inst{7-0} = offset{7-0};
1360 let DecoderMethod = "DecodeT2LdStPre";
1363 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1364 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1365 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1368 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1369 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1370 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1373 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1374 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1375 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1378 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1379 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1380 list<Predicate> Predicates = [IsThumb2];
1383 //===----------------------------------------------------------------------===//
1385 //===----------------------------------------------------------------------===//
1386 // ARM VFP Instruction templates.
1389 // Almost all VFP instructions are predicable.
1390 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1391 IndexMode im, Format f, InstrItinClass itin,
1392 string opc, string asm, string cstr, list<dag> pattern>
1393 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1395 let Inst{31-28} = p;
1396 let OutOperandList = oops;
1397 let InOperandList = !con(iops, (ins pred:$p));
1398 let AsmString = !strconcat(opc, "${p}", asm);
1399 let Pattern = pattern;
1400 let PostEncoderMethod = "VFPThumb2PostEncoder";
1401 let DecoderNamespace = "VFP";
1402 list<Predicate> Predicates = [HasVFP2];
1406 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1407 IndexMode im, Format f, InstrItinClass itin,
1408 string asm, string cstr, list<dag> pattern>
1409 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1411 let Inst{31-28} = p;
1412 let OutOperandList = oops;
1413 let InOperandList = iops;
1414 let AsmString = asm;
1415 let Pattern = pattern;
1416 let PostEncoderMethod = "VFPThumb2PostEncoder";
1417 let DecoderNamespace = "VFP";
1418 list<Predicate> Predicates = [HasVFP2];
1421 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1422 string opc, string asm, list<dag> pattern>
1423 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1424 opc, asm, "", pattern> {
1425 let PostEncoderMethod = "VFPThumb2PostEncoder";
1428 // ARM VFP addrmode5 loads and stores
1429 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1430 InstrItinClass itin,
1431 string opc, string asm, list<dag> pattern>
1432 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1433 VFPLdStFrm, itin, opc, asm, "", pattern> {
1434 // Instruction operands.
1438 // Encode instruction operands.
1439 let Inst{23} = addr{8}; // U (add = (U == '1'))
1440 let Inst{22} = Dd{4};
1441 let Inst{19-16} = addr{12-9}; // Rn
1442 let Inst{15-12} = Dd{3-0};
1443 let Inst{7-0} = addr{7-0}; // imm8
1445 let Inst{27-24} = opcod1;
1446 let Inst{21-20} = opcod2;
1447 let Inst{11-9} = 0b101;
1448 let Inst{8} = 1; // Double precision
1450 // Loads & stores operate on both NEON and VFP pipelines.
1451 let D = VFPNeonDomain;
1454 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1455 InstrItinClass itin,
1456 string opc, string asm, list<dag> pattern>
1457 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1458 VFPLdStFrm, itin, opc, asm, "", pattern> {
1459 // Instruction operands.
1463 // Encode instruction operands.
1464 let Inst{23} = addr{8}; // U (add = (U == '1'))
1465 let Inst{22} = Sd{0};
1466 let Inst{19-16} = addr{12-9}; // Rn
1467 let Inst{15-12} = Sd{4-1};
1468 let Inst{7-0} = addr{7-0}; // imm8
1470 let Inst{27-24} = opcod1;
1471 let Inst{21-20} = opcod2;
1472 let Inst{11-9} = 0b101;
1473 let Inst{8} = 0; // Single precision
1475 // Loads & stores operate on both NEON and VFP pipelines.
1476 let D = VFPNeonDomain;
1479 // VFP Load / store multiple pseudo instructions.
1480 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1482 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1484 let OutOperandList = oops;
1485 let InOperandList = !con(iops, (ins pred:$p));
1486 let Pattern = pattern;
1487 list<Predicate> Predicates = [HasVFP2];
1490 // Load / store multiple
1492 // Unknown precision
1493 class AXXI4<dag oops, dag iops, IndexMode im,
1494 string asm, string cstr, list<dag> pattern>
1495 : VFPXI<oops, iops, AddrMode4, 4, im,
1496 VFPLdStFrm, NoItinerary, asm, cstr, pattern> {
1497 // Instruction operands.
1501 // Encode instruction operands.
1502 let Inst{19-16} = Rn;
1504 let Inst{15-12} = regs{11-8};
1505 let Inst{7-1} = regs{7-1};
1507 let Inst{27-25} = 0b110;
1508 let Inst{11-8} = 0b1011;
1513 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1514 string asm, string cstr, list<dag> pattern>
1515 : VFPXI<oops, iops, AddrMode4, 4, im,
1516 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1517 // Instruction operands.
1521 // Encode instruction operands.
1522 let Inst{19-16} = Rn;
1523 let Inst{22} = regs{12};
1524 let Inst{15-12} = regs{11-8};
1525 let Inst{7-1} = regs{7-1};
1527 let Inst{27-25} = 0b110;
1528 let Inst{11-9} = 0b101;
1529 let Inst{8} = 1; // Double precision
1534 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1535 string asm, string cstr, list<dag> pattern>
1536 : VFPXI<oops, iops, AddrMode4, 4, im,
1537 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1538 // Instruction operands.
1542 // Encode instruction operands.
1543 let Inst{19-16} = Rn;
1544 let Inst{22} = regs{8};
1545 let Inst{15-12} = regs{12-9};
1546 let Inst{7-0} = regs{7-0};
1548 let Inst{27-25} = 0b110;
1549 let Inst{11-9} = 0b101;
1550 let Inst{8} = 0; // Single precision
1553 // Double precision, unary
1554 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1555 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1556 string asm, list<dag> pattern>
1557 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1558 // Instruction operands.
1562 // Encode instruction operands.
1563 let Inst{3-0} = Dm{3-0};
1564 let Inst{5} = Dm{4};
1565 let Inst{15-12} = Dd{3-0};
1566 let Inst{22} = Dd{4};
1568 let Inst{27-23} = opcod1;
1569 let Inst{21-20} = opcod2;
1570 let Inst{19-16} = opcod3;
1571 let Inst{11-9} = 0b101;
1572 let Inst{8} = 1; // Double precision
1573 let Inst{7-6} = opcod4;
1574 let Inst{4} = opcod5;
1576 let Predicates = [HasVFP2, HasDPVFP];
1579 // Double precision, unary, not-predicated
1580 class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1581 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1582 string asm, list<dag> pattern>
1583 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPUnaryFrm, itin, asm, "", pattern> {
1584 // Instruction operands.
1588 let Inst{31-28} = 0b1111;
1590 // Encode instruction operands.
1591 let Inst{3-0} = Dm{3-0};
1592 let Inst{5} = Dm{4};
1593 let Inst{15-12} = Dd{3-0};
1594 let Inst{22} = Dd{4};
1596 let Inst{27-23} = opcod1;
1597 let Inst{21-20} = opcod2;
1598 let Inst{19-16} = opcod3;
1599 let Inst{11-9} = 0b101;
1600 let Inst{8} = 1; // Double precision
1601 let Inst{7-6} = opcod4;
1602 let Inst{4} = opcod5;
1605 // Double precision, binary
1606 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1607 dag iops, InstrItinClass itin, string opc, string asm,
1609 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1610 // Instruction operands.
1615 // Encode instruction operands.
1616 let Inst{3-0} = Dm{3-0};
1617 let Inst{5} = Dm{4};
1618 let Inst{19-16} = Dn{3-0};
1619 let Inst{7} = Dn{4};
1620 let Inst{15-12} = Dd{3-0};
1621 let Inst{22} = Dd{4};
1623 let Inst{27-23} = opcod1;
1624 let Inst{21-20} = opcod2;
1625 let Inst{11-9} = 0b101;
1626 let Inst{8} = 1; // Double precision
1630 let Predicates = [HasVFP2, HasDPVFP];
1633 // FP, binary, not predicated
1634 class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1635 InstrItinClass itin, string asm, list<dag> pattern>
1636 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone, VFPBinaryFrm, itin,
1639 // Instruction operands.
1644 let Inst{31-28} = 0b1111;
1646 // Encode instruction operands.
1647 let Inst{3-0} = Dm{3-0};
1648 let Inst{5} = Dm{4};
1649 let Inst{19-16} = Dn{3-0};
1650 let Inst{7} = Dn{4};
1651 let Inst{15-12} = Dd{3-0};
1652 let Inst{22} = Dd{4};
1654 let Inst{27-23} = opcod1;
1655 let Inst{21-20} = opcod2;
1656 let Inst{11-9} = 0b101;
1657 let Inst{8} = 1; // double precision
1658 let Inst{6} = opcod3;
1661 let Predicates = [HasVFP2, HasDPVFP];
1664 // Single precision, unary, predicated
1665 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1666 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1667 string asm, list<dag> pattern>
1668 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1669 // Instruction operands.
1673 // Encode instruction operands.
1674 let Inst{3-0} = Sm{4-1};
1675 let Inst{5} = Sm{0};
1676 let Inst{15-12} = Sd{4-1};
1677 let Inst{22} = Sd{0};
1679 let Inst{27-23} = opcod1;
1680 let Inst{21-20} = opcod2;
1681 let Inst{19-16} = opcod3;
1682 let Inst{11-9} = 0b101;
1683 let Inst{8} = 0; // Single precision
1684 let Inst{7-6} = opcod4;
1685 let Inst{4} = opcod5;
1688 // Single precision, unary, non-predicated
1689 class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1690 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1691 string asm, list<dag> pattern>
1692 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1693 VFPUnaryFrm, itin, asm, "", pattern> {
1694 // Instruction operands.
1698 let Inst{31-28} = 0b1111;
1700 // Encode instruction operands.
1701 let Inst{3-0} = Sm{4-1};
1702 let Inst{5} = Sm{0};
1703 let Inst{15-12} = Sd{4-1};
1704 let Inst{22} = Sd{0};
1706 let Inst{27-23} = opcod1;
1707 let Inst{21-20} = opcod2;
1708 let Inst{19-16} = opcod3;
1709 let Inst{11-9} = 0b101;
1710 let Inst{8} = 0; // Single precision
1711 let Inst{7-6} = opcod4;
1712 let Inst{4} = opcod5;
1715 // Single precision unary, if no NEON. Same as ASuI except not available if
1717 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1718 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1719 string asm, list<dag> pattern>
1720 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1722 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1725 // Single precision, binary
1726 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1727 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1728 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1729 // Instruction operands.
1734 // Encode instruction operands.
1735 let Inst{3-0} = Sm{4-1};
1736 let Inst{5} = Sm{0};
1737 let Inst{19-16} = Sn{4-1};
1738 let Inst{7} = Sn{0};
1739 let Inst{15-12} = Sd{4-1};
1740 let Inst{22} = Sd{0};
1742 let Inst{27-23} = opcod1;
1743 let Inst{21-20} = opcod2;
1744 let Inst{11-9} = 0b101;
1745 let Inst{8} = 0; // Single precision
1750 // Single precision, binary, not predicated
1751 class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1752 InstrItinClass itin, string asm, list<dag> pattern>
1753 : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
1754 VFPBinaryFrm, itin, asm, "", pattern>
1756 // Instruction operands.
1761 let Inst{31-28} = 0b1111;
1763 // Encode instruction operands.
1764 let Inst{3-0} = Sm{4-1};
1765 let Inst{5} = Sm{0};
1766 let Inst{19-16} = Sn{4-1};
1767 let Inst{7} = Sn{0};
1768 let Inst{15-12} = Sd{4-1};
1769 let Inst{22} = Sd{0};
1771 let Inst{27-23} = opcod1;
1772 let Inst{21-20} = opcod2;
1773 let Inst{11-9} = 0b101;
1774 let Inst{8} = 0; // Single precision
1775 let Inst{6} = opcod3;
1779 // Single precision binary, if no NEON. Same as ASbI except not available if
1781 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1782 dag iops, InstrItinClass itin, string opc, string asm,
1784 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1785 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1787 // Instruction operands.
1792 // Encode instruction operands.
1793 let Inst{3-0} = Sm{4-1};
1794 let Inst{5} = Sm{0};
1795 let Inst{19-16} = Sn{4-1};
1796 let Inst{7} = Sn{0};
1797 let Inst{15-12} = Sd{4-1};
1798 let Inst{22} = Sd{0};
1801 // VFP conversion instructions
1802 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1803 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1805 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1806 let Inst{27-23} = opcod1;
1807 let Inst{21-20} = opcod2;
1808 let Inst{19-16} = opcod3;
1809 let Inst{11-8} = opcod4;
1814 // VFP conversion between floating-point and fixed-point
1815 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1816 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1818 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1820 // size (fixed-point number): sx == 0 ? 16 : 32
1821 let Inst{7} = op5; // sx
1822 let Inst{5} = fbits{0};
1823 let Inst{3-0} = fbits{4-1};
1826 // VFP conversion instructions, if no NEON
1827 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1828 dag oops, dag iops, InstrItinClass itin,
1829 string opc, string asm, list<dag> pattern>
1830 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1832 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1835 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1836 InstrItinClass itin,
1837 string opc, string asm, list<dag> pattern>
1838 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1839 let Inst{27-20} = opcod1;
1840 let Inst{11-8} = opcod2;
1844 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1845 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1846 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1848 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1849 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1850 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1852 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1853 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1854 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1856 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1857 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1858 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1860 //===----------------------------------------------------------------------===//
1862 //===----------------------------------------------------------------------===//
1863 // ARM NEON Instruction templates.
1866 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1867 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1869 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1870 let OutOperandList = oops;
1871 let InOperandList = !con(iops, (ins pred:$p));
1872 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1873 let Pattern = pattern;
1874 list<Predicate> Predicates = [HasNEON];
1875 let DecoderNamespace = "NEON";
1878 // Same as NeonI except it does not have a "data type" specifier.
1879 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1880 InstrItinClass itin, string opc, string asm, string cstr,
1882 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1883 let OutOperandList = oops;
1884 let InOperandList = !con(iops, (ins pred:$p));
1885 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1886 let Pattern = pattern;
1887 list<Predicate> Predicates = [HasNEON];
1888 let DecoderNamespace = "NEON";
1891 // Same as NeonI except it is not predicated
1892 class NeonInp<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1893 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1895 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1896 let OutOperandList = oops;
1897 let InOperandList = iops;
1898 let AsmString = !strconcat(opc, ".", dt, "\t", asm);
1899 let Pattern = pattern;
1900 list<Predicate> Predicates = [HasNEON];
1901 let DecoderNamespace = "NEON";
1903 let Inst{31-28} = 0b1111;
1906 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1907 dag oops, dag iops, InstrItinClass itin,
1908 string opc, string dt, string asm, string cstr, list<dag> pattern>
1909 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1911 let Inst{31-24} = 0b11110100;
1912 let Inst{23} = op23;
1913 let Inst{21-20} = op21_20;
1914 let Inst{11-8} = op11_8;
1915 let Inst{7-4} = op7_4;
1917 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1918 let DecoderNamespace = "NEONLoadStore";
1924 let Inst{22} = Vd{4};
1925 let Inst{15-12} = Vd{3-0};
1926 let Inst{19-16} = Rn{3-0};
1927 let Inst{3-0} = Rm{3-0};
1930 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1931 dag oops, dag iops, InstrItinClass itin,
1932 string opc, string dt, string asm, string cstr, list<dag> pattern>
1933 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1934 dt, asm, cstr, pattern> {
1938 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1939 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1941 let OutOperandList = oops;
1942 let InOperandList = !con(iops, (ins pred:$p));
1943 list<Predicate> Predicates = [HasNEON];
1946 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1948 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1950 let OutOperandList = oops;
1951 let InOperandList = !con(iops, (ins pred:$p));
1952 let Pattern = pattern;
1953 list<Predicate> Predicates = [HasNEON];
1956 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1957 string opc, string dt, string asm, string cstr, list<dag> pattern>
1958 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1960 let Inst{31-25} = 0b1111001;
1961 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1962 let DecoderNamespace = "NEONData";
1965 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1966 string opc, string asm, string cstr, list<dag> pattern>
1967 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1969 let Inst{31-25} = 0b1111001;
1970 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1971 let DecoderNamespace = "NEONData";
1974 // NEON "one register and a modified immediate" format.
1975 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1977 dag oops, dag iops, InstrItinClass itin,
1978 string opc, string dt, string asm, string cstr,
1980 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1981 let Inst{23} = op23;
1982 let Inst{21-19} = op21_19;
1983 let Inst{11-8} = op11_8;
1989 // Instruction operands.
1993 let Inst{15-12} = Vd{3-0};
1994 let Inst{22} = Vd{4};
1995 let Inst{24} = SIMM{7};
1996 let Inst{18-16} = SIMM{6-4};
1997 let Inst{3-0} = SIMM{3-0};
1998 let DecoderMethod = "DecodeNEONModImmInstruction";
2001 // NEON 2 vector register format.
2002 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2003 bits<5> op11_7, bit op6, bit op4,
2004 dag oops, dag iops, InstrItinClass itin,
2005 string opc, string dt, string asm, string cstr, list<dag> pattern>
2006 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
2007 let Inst{24-23} = op24_23;
2008 let Inst{21-20} = op21_20;
2009 let Inst{19-18} = op19_18;
2010 let Inst{17-16} = op17_16;
2011 let Inst{11-7} = op11_7;
2015 // Instruction operands.
2019 let Inst{15-12} = Vd{3-0};
2020 let Inst{22} = Vd{4};
2021 let Inst{3-0} = Vm{3-0};
2022 let Inst{5} = Vm{4};
2025 // Same as N2V but not predicated.
2026 class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
2027 dag oops, dag iops, InstrItinClass itin, string OpcodeStr,
2028 string Dt, ValueType ResTy, ValueType OpTy, list<dag> pattern>
2029 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin,
2030 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
2034 // Encode instruction operands
2035 let Inst{22} = Vd{4};
2036 let Inst{15-12} = Vd{3-0};
2037 let Inst{5} = Vm{4};
2038 let Inst{3-0} = Vm{3-0};
2040 // Encode constant bits
2041 let Inst{27-23} = 0b00111;
2042 let Inst{21-20} = 0b11;
2043 let Inst{19-18} = op19_18;
2044 let Inst{17-16} = op17_16;
2046 let Inst{10-8} = op10_8;
2051 let DecoderNamespace = "NEON";
2054 // Same as N2V except it doesn't have a datatype suffix.
2055 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2056 bits<5> op11_7, bit op6, bit op4,
2057 dag oops, dag iops, InstrItinClass itin,
2058 string opc, string asm, string cstr, list<dag> pattern>
2059 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
2060 let Inst{24-23} = op24_23;
2061 let Inst{21-20} = op21_20;
2062 let Inst{19-18} = op19_18;
2063 let Inst{17-16} = op17_16;
2064 let Inst{11-7} = op11_7;
2068 // Instruction operands.
2072 let Inst{15-12} = Vd{3-0};
2073 let Inst{22} = Vd{4};
2074 let Inst{3-0} = Vm{3-0};
2075 let Inst{5} = Vm{4};
2078 // NEON 2 vector register with immediate.
2079 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2080 dag oops, dag iops, Format f, InstrItinClass itin,
2081 string opc, string dt, string asm, string cstr, list<dag> pattern>
2082 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2083 let Inst{24} = op24;
2084 let Inst{23} = op23;
2085 let Inst{11-8} = op11_8;
2090 // Instruction operands.
2095 let Inst{15-12} = Vd{3-0};
2096 let Inst{22} = Vd{4};
2097 let Inst{3-0} = Vm{3-0};
2098 let Inst{5} = Vm{4};
2099 let Inst{21-16} = SIMM{5-0};
2102 // NEON 3 vector register format.
2104 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2105 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2106 string opc, string dt, string asm, string cstr,
2108 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2109 let Inst{24} = op24;
2110 let Inst{23} = op23;
2111 let Inst{21-20} = op21_20;
2112 let Inst{11-8} = op11_8;
2117 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
2118 dag oops, dag iops, Format f, InstrItinClass itin,
2119 string opc, string dt, string asm, string cstr, list<dag> pattern>
2120 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2121 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2122 // Instruction operands.
2127 let Inst{15-12} = Vd{3-0};
2128 let Inst{22} = Vd{4};
2129 let Inst{19-16} = Vn{3-0};
2130 let Inst{7} = Vn{4};
2131 let Inst{3-0} = Vm{3-0};
2132 let Inst{5} = Vm{4};
2135 class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2136 bit op4, dag oops, dag iops,Format f, InstrItinClass itin,
2137 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2138 SDPatternOperator IntOp, bit Commutable, list<dag> pattern>
2139 : NeonInp<oops, iops, AddrModeNone, IndexModeNone, f, itin, OpcodeStr,
2140 Dt, "$Vd, $Vn, $Vm", "", pattern> {
2145 // Encode instruction operands
2146 let Inst{22} = Vd{4};
2147 let Inst{15-12} = Vd{3-0};
2148 let Inst{19-16} = Vn{3-0};
2149 let Inst{7} = Vn{4};
2150 let Inst{5} = Vm{4};
2151 let Inst{3-0} = Vm{3-0};
2153 // Encode constant bits
2154 let Inst{27-23} = op27_23;
2155 let Inst{21-20} = op21_20;
2156 let Inst{11-8} = op11_8;
2161 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2162 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2163 string opc, string dt, string asm, string cstr,
2165 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2166 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2168 // Instruction operands.
2174 let Inst{15-12} = Vd{3-0};
2175 let Inst{22} = Vd{4};
2176 let Inst{19-16} = Vn{3-0};
2177 let Inst{7} = Vn{4};
2178 let Inst{3-0} = Vm{3-0};
2182 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2183 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
2184 string opc, string dt, string asm, string cstr,
2186 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
2187 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
2189 // Instruction operands.
2195 let Inst{15-12} = Vd{3-0};
2196 let Inst{22} = Vd{4};
2197 let Inst{19-16} = Vn{3-0};
2198 let Inst{7} = Vn{4};
2199 let Inst{2-0} = Vm{2-0};
2200 let Inst{5} = lane{1};
2201 let Inst{3} = lane{0};
2204 // Same as N3V except it doesn't have a data type suffix.
2205 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2207 dag oops, dag iops, Format f, InstrItinClass itin,
2208 string opc, string asm, string cstr, list<dag> pattern>
2209 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
2210 let Inst{24} = op24;
2211 let Inst{23} = op23;
2212 let Inst{21-20} = op21_20;
2213 let Inst{11-8} = op11_8;
2217 // Instruction operands.
2222 let Inst{15-12} = Vd{3-0};
2223 let Inst{22} = Vd{4};
2224 let Inst{19-16} = Vn{3-0};
2225 let Inst{7} = Vn{4};
2226 let Inst{3-0} = Vm{3-0};
2227 let Inst{5} = Vm{4};
2230 // NEON VMOVs between scalar and core registers.
2231 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2232 dag oops, dag iops, Format f, InstrItinClass itin,
2233 string opc, string dt, string asm, list<dag> pattern>
2234 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
2236 let Inst{27-20} = opcod1;
2237 let Inst{11-8} = opcod2;
2238 let Inst{6-5} = opcod3;
2240 // A8.6.303, A8.6.328, A8.6.329
2241 let Inst{3-0} = 0b0000;
2243 let OutOperandList = oops;
2244 let InOperandList = !con(iops, (ins pred:$p));
2245 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
2246 let Pattern = pattern;
2247 list<Predicate> Predicates = [HasNEON];
2249 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
2250 let DecoderNamespace = "NEONDup";
2257 let Inst{31-28} = p{3-0};
2259 let Inst{19-16} = V{3-0};
2260 let Inst{15-12} = R{3-0};
2262 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2263 dag oops, dag iops, InstrItinClass itin,
2264 string opc, string dt, string asm, list<dag> pattern>
2265 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
2266 opc, dt, asm, pattern>;
2267 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2268 dag oops, dag iops, InstrItinClass itin,
2269 string opc, string dt, string asm, list<dag> pattern>
2270 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
2271 opc, dt, asm, pattern>;
2272 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2273 dag oops, dag iops, InstrItinClass itin,
2274 string opc, string dt, string asm, list<dag> pattern>
2275 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
2276 opc, dt, asm, pattern>;
2278 // Vector Duplicate Lane (from scalar to all elements)
2279 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2280 InstrItinClass itin, string opc, string dt, string asm,
2282 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2283 let Inst{24-23} = 0b11;
2284 let Inst{21-20} = 0b11;
2285 let Inst{19-16} = op19_16;
2286 let Inst{11-7} = 0b11000;
2293 let Inst{22} = Vd{4};
2294 let Inst{15-12} = Vd{3-0};
2295 let Inst{5} = Vm{4};
2296 let Inst{3-0} = Vm{3-0};
2299 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2300 // for single-precision FP.
2301 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2302 list<Predicate> Predicates = [HasNEON,UseNEONForFP];
2305 // VFP/NEON Instruction aliases for type suffices.
2306 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
2307 InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
2309 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
2310 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2311 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2312 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2313 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2316 multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> {
2317 let Predicates = [HasNEON] in {
2318 def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
2319 def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
2320 def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
2321 def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
2325 // The same alias classes using AsmPseudo instead, for the more complex
2326 // stuff in NEON that InstAlias can't quite handle.
2327 // Note that we can't use anonymous defm references here like we can
2328 // above, as we care about the ultimate instruction enum names generated, unlike
2329 // for instalias defs.
2330 class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
2331 AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
2333 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
2334 def : TokenAlias<".s8", ".i8">;
2335 def : TokenAlias<".u8", ".i8">;
2336 def : TokenAlias<".s16", ".i16">;
2337 def : TokenAlias<".u16", ".i16">;
2338 def : TokenAlias<".s32", ".i32">;
2339 def : TokenAlias<".u32", ".i32">;
2340 def : TokenAlias<".s64", ".i64">;
2341 def : TokenAlias<".u64", ".i64">;
2343 def : TokenAlias<".i8", ".8">;
2344 def : TokenAlias<".i16", ".16">;
2345 def : TokenAlias<".i32", ".32">;
2346 def : TokenAlias<".i64", ".64">;
2348 def : TokenAlias<".p8", ".8">;
2349 def : TokenAlias<".p16", ".16">;
2351 def : TokenAlias<".f32", ".32">;
2352 def : TokenAlias<".f64", ".64">;
2353 def : TokenAlias<".f", ".f32">;
2354 def : TokenAlias<".d", ".f64">;