1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<5> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
107 def AddrMode_i12 : AddrMode<16>;
110 class SizeFlagVal<bits<3> val> {
113 def SizeInvalid : SizeFlagVal<0>; // Unset.
114 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
115 def Size8Bytes : SizeFlagVal<2>;
116 def Size4Bytes : SizeFlagVal<3>;
117 def Size2Bytes : SizeFlagVal<4>;
119 // Load / store index mode.
120 class IndexMode<bits<2> val> {
123 def IndexModeNone : IndexMode<0>;
124 def IndexModePre : IndexMode<1>;
125 def IndexModePost : IndexMode<2>;
126 def IndexModeUpd : IndexMode<3>;
128 // Instruction execution domain.
129 class Domain<bits<2> val> {
132 def GenericDomain : Domain<0>;
133 def VFPDomain : Domain<1>; // Instructions in VFP domain only
134 def NeonDomain : Domain<2>; // Instructions in Neon domain only
135 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
148 // register whose default is 0 (no register).
149 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
150 (ops (i32 14), (i32 zero_reg))> {
151 let PrintMethod = "printPredicateOperand";
152 let ParserMatchClass = CondCodeOperand;
155 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
156 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
157 string EncoderMethod = "getCCOutOpValue";
158 let PrintMethod = "printSBitModifierOperand";
161 // Same as cc_out except it defaults to setting CPSR.
162 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
163 string EncoderMethod = "getCCOutOpValue";
164 let PrintMethod = "printSBitModifierOperand";
167 // ARM special operands for disassembly only.
169 def setend_op : Operand<i32> {
170 let PrintMethod = "printSetendOperand";
173 def cps_opt : Operand<i32> {
174 let PrintMethod = "printCPSOptionOperand";
177 def msr_mask : Operand<i32> {
178 let PrintMethod = "printMSRMaskOperand";
181 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
182 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
183 def neg_zero : Operand<i32> {
184 let PrintMethod = "printNegZeroOperand";
187 //===----------------------------------------------------------------------===//
189 // ARM Instruction templates.
192 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
193 Format f, Domain d, string cstr, InstrItinClass itin>
195 let Namespace = "ARM";
200 bits<2> IndexModeBits = IM.Value;
202 bits<6> Form = F.Value;
204 bit isUnaryDataProc = 0;
205 bit canXformTo16Bit = 0;
207 // If this is a pseudo instruction, mark it isCodeGenOnly.
208 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
210 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
211 let TSFlags{4-0} = AM.Value;
212 let TSFlags{7-5} = SZ.Value;
213 let TSFlags{9-8} = IndexModeBits;
214 let TSFlags{15-10} = Form;
215 let TSFlags{16} = isUnaryDataProc;
216 let TSFlags{17} = canXformTo16Bit;
217 let TSFlags{19-18} = D.Value;
219 let Constraints = cstr;
220 let Itinerary = itin;
227 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
228 Format f, Domain d, string cstr, InstrItinClass itin>
229 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
231 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
232 // on by adding flavors to specific instructions.
233 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
234 Format f, Domain d, string cstr, InstrItinClass itin>
235 : InstTemplate<am, sz, im, f, d, cstr, itin>;
237 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
238 string asm, list<dag> pattern>
239 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
241 let OutOperandList = oops;
242 let InOperandList = iops;
244 let Pattern = pattern;
247 // Almost all ARM instructions are predicable.
248 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
249 IndexMode im, Format f, InstrItinClass itin,
250 string opc, string asm, string cstr,
252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
255 let OutOperandList = oops;
256 let InOperandList = !con(iops, (ins pred:$p));
257 let AsmString = !strconcat(opc, "${p}", asm);
258 let Pattern = pattern;
259 list<Predicate> Predicates = [IsARM];
262 // A few are not predicable
263 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
264 IndexMode im, Format f, InstrItinClass itin,
265 string opc, string asm, string cstr,
267 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
268 let OutOperandList = oops;
269 let InOperandList = iops;
270 let AsmString = !strconcat(opc, asm);
271 let Pattern = pattern;
272 let isPredicable = 0;
273 list<Predicate> Predicates = [IsARM];
276 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
277 // operand since by default it's a zero register. It will become an implicit def
278 // once it's "flipped".
279 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
280 IndexMode im, Format f, InstrItinClass itin,
281 string opc, string asm, string cstr,
283 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
284 bits<4> p; // Predicate operand
285 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
289 let OutOperandList = oops;
290 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
291 let AsmString = !strconcat(opc, "${s}${p}", asm);
292 let Pattern = pattern;
293 list<Predicate> Predicates = [IsARM];
297 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
298 IndexMode im, Format f, InstrItinClass itin,
299 string asm, string cstr, list<dag> pattern>
300 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
301 let OutOperandList = oops;
302 let InOperandList = iops;
304 let Pattern = pattern;
305 list<Predicate> Predicates = [IsARM];
308 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
311 opc, asm, "", pattern>;
312 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
313 string opc, string asm, list<dag> pattern>
314 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
315 opc, asm, "", pattern>;
316 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
317 string asm, list<dag> pattern>
318 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
320 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
323 opc, asm, "", pattern>;
325 // Ctrl flow instructions
326 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
327 string opc, string asm, list<dag> pattern>
328 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
329 opc, asm, "", pattern> {
330 let Inst{27-24} = opcod;
332 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
333 string asm, list<dag> pattern>
334 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
336 let Inst{27-24} = opcod;
338 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
339 string asm, list<dag> pattern>
340 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
343 // BR_JT instructions
344 class JTI<dag oops, dag iops, InstrItinClass itin,
345 string asm, list<dag> pattern>
346 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
349 // Atomic load/store instructions
350 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
353 opc, asm, "", pattern> {
356 let Inst{27-23} = 0b00011;
357 let Inst{22-21} = opcod;
359 let Inst{19-16} = Rn;
360 let Inst{15-12} = Rt;
361 let Inst{11-0} = 0b111110011111;
363 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
364 string opc, string asm, list<dag> pattern>
365 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
366 opc, asm, "", pattern> {
370 let Inst{27-23} = 0b00011;
371 let Inst{22-21} = opcod;
373 let Inst{19-16} = Rn;
374 let Inst{15-12} = Rd;
375 let Inst{11-4} = 0b11111001;
378 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
379 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
383 let Inst{27-23} = 0b00010;
385 let Inst{21-20} = 0b00;
386 let Inst{19-16} = Rn;
387 let Inst{15-12} = Rt;
388 let Inst{11-4} = 0b00001001;
392 // addrmode1 instructions
393 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
394 string opc, string asm, list<dag> pattern>
395 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
396 opc, asm, "", pattern> {
397 let Inst{24-21} = opcod;
398 let Inst{27-26} = 0b00;
400 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
401 string opc, string asm, list<dag> pattern>
402 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
403 opc, asm, "", pattern> {
404 let Inst{24-21} = opcod;
405 let Inst{27-26} = 0b00;
407 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
408 string asm, list<dag> pattern>
409 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
411 let Inst{24-21} = opcod;
412 let Inst{27-26} = 0b00;
414 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
417 opc, asm, "", pattern>;
423 class AIldst1<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
424 Format f, InstrItinClass itin, string opc, string asm,
426 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
428 let Inst{27-25} = op;
429 let Inst{24} = 1; // 24 == P
431 let Inst{22} = isByte;
432 let Inst{21} = 0; // 21 == W
435 // Indexed load/stores
436 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
437 IndexMode im, Format f, InstrItinClass itin, string opc,
438 string asm, string cstr, list<dag> pattern>
439 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
440 opc, asm, cstr, pattern> {
441 let Inst{27-26} = 0b01;
442 let Inst{24} = isPre; // P bit
443 let Inst{22} = isByte; // B bit
444 let Inst{21} = isPre; // W bit
445 let Inst{20} = isLd; // L bit
448 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
449 string asm, list<dag> pattern>
450 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
452 let Inst{20} = 1; // L bit
453 let Inst{21} = 0; // W bit
454 let Inst{22} = 0; // B bit
455 let Inst{24} = 1; // P bit
456 let Inst{27-26} = 0b01;
458 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
459 string asm, list<dag> pattern>
460 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
462 let Inst{20} = 1; // L bit
463 let Inst{21} = 0; // W bit
464 let Inst{22} = 1; // B bit
465 let Inst{24} = 1; // P bit
466 let Inst{27-26} = 0b01;
470 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
471 string asm, list<dag> pattern>
472 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
474 let Inst{20} = 0; // L bit
475 let Inst{21} = 0; // W bit
476 let Inst{22} = 0; // B bit
477 let Inst{24} = 1; // P bit
478 let Inst{27-26} = 0b01;
480 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
481 string asm, list<dag> pattern>
482 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
484 let Inst{20} = 0; // L bit
485 let Inst{21} = 0; // W bit
486 let Inst{22} = 1; // B bit
487 let Inst{24} = 1; // P bit
488 let Inst{27-26} = 0b01;
491 // addrmode3 instructions
492 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
493 string opc, string asm, list<dag> pattern>
494 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
495 opc, asm, "", pattern>;
496 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
497 string asm, list<dag> pattern>
498 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
502 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
503 string opc, string asm, list<dag> pattern>
504 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
505 opc, asm, "", pattern> {
507 let Inst{5} = 1; // H bit
508 let Inst{6} = 0; // S bit
510 let Inst{20} = 1; // L bit
511 let Inst{21} = 0; // W bit
512 let Inst{24} = 1; // P bit
513 let Inst{27-25} = 0b000;
515 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
516 string asm, list<dag> pattern>
517 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
520 let Inst{5} = 1; // H bit
521 let Inst{6} = 0; // S bit
523 let Inst{20} = 1; // L bit
524 let Inst{21} = 0; // W bit
525 let Inst{24} = 1; // P bit
527 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
528 string opc, string asm, list<dag> pattern>
529 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
530 opc, asm, "", pattern> {
533 let Inst{27-25} = 0b000;
534 let Inst{24} = 1; // P bit
535 let Inst{23} = addr{8}; // U bit
536 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
537 let Inst{21} = 0; // W bit
538 let Inst{20} = 1; // L bit
539 let Inst{19-16} = addr{12-9}; // Rn
540 let Inst{15-12} = Rt; // Rt
541 let Inst{11-8} = addr{7-4}; // imm7_4/zero
542 let Inst{7-4} = 0b1111;
543 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
545 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
546 string asm, list<dag> pattern>
547 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
550 let Inst{5} = 1; // H bit
551 let Inst{6} = 1; // S bit
553 let Inst{20} = 1; // L bit
554 let Inst{21} = 0; // W bit
555 let Inst{24} = 1; // P bit
557 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
558 string opc, string asm, list<dag> pattern>
559 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
560 opc, asm, "", pattern> {
563 let Inst{27-25} = 0b000;
564 let Inst{24} = 1; // P bit
565 let Inst{23} = addr{8}; // U bit
566 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
567 let Inst{21} = 0; // W bit
568 let Inst{20} = 1; // L bit
569 let Inst{19-16} = addr{12-9}; // Rn
570 let Inst{15-12} = Rt; // Rt
571 let Inst{11-8} = addr{7-4}; // imm7_4/zero
572 let Inst{7-4} = 0b1101;
573 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
575 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
576 string asm, list<dag> pattern>
577 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
580 let Inst{5} = 0; // H bit
581 let Inst{6} = 1; // S bit
583 let Inst{20} = 1; // L bit
584 let Inst{21} = 0; // W bit
585 let Inst{24} = 1; // P bit
587 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
588 string opc, string asm, list<dag> pattern>
589 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
590 opc, asm, "", pattern> {
592 let Inst{5} = 0; // H bit
593 let Inst{6} = 1; // S bit
595 let Inst{20} = 0; // L bit
596 let Inst{21} = 0; // W bit
597 let Inst{24} = 1; // P bit
598 let Inst{27-25} = 0b000;
602 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
603 string opc, string asm, list<dag> pattern>
604 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
605 opc, asm, "", pattern> {
608 let Inst{27-25} = 0b000;
609 let Inst{24} = 1; // P bit
610 let Inst{23} = addr{8}; // U bit
611 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
612 let Inst{21} = 0; // W bit
613 let Inst{20} = 0; // L bit
614 let Inst{19-16} = addr{12-9}; // Rn
615 let Inst{15-12} = Rt; // Rt
616 let Inst{11-8} = addr{7-4}; // imm7_4/zero
617 let Inst{7-4} = 0b1011;
618 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
620 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
621 string asm, list<dag> pattern>
622 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
625 let Inst{5} = 1; // H bit
626 let Inst{6} = 0; // S bit
628 let Inst{20} = 0; // L bit
629 let Inst{21} = 0; // W bit
630 let Inst{24} = 1; // P bit
632 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
633 string opc, string asm, list<dag> pattern>
634 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
635 opc, asm, "", pattern> {
637 let Inst{5} = 1; // H bit
638 let Inst{6} = 1; // S bit
640 let Inst{20} = 0; // L bit
641 let Inst{21} = 0; // W bit
642 let Inst{24} = 1; // P bit
643 let Inst{27-25} = 0b000;
647 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
648 string opc, string asm, string cstr, list<dag> pattern>
649 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
650 opc, asm, cstr, pattern> {
652 let Inst{5} = 1; // H bit
653 let Inst{6} = 0; // S bit
655 let Inst{20} = 1; // L bit
656 let Inst{21} = 1; // W bit
657 let Inst{24} = 1; // P bit
658 let Inst{27-25} = 0b000;
660 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
661 string opc, string asm, string cstr, list<dag> pattern>
662 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
663 opc, asm, cstr, pattern> {
666 let Inst{27-25} = 0b000;
667 let Inst{24} = 1; // P bit
668 let Inst{23} = addr{8}; // U bit
669 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
670 let Inst{21} = 1; // W bit
671 let Inst{20} = 1; // L bit
672 let Inst{19-16} = addr{12-9}; // Rn
673 let Inst{15-12} = Rt; // Rt
674 let Inst{11-8} = addr{7-4}; // imm7_4/zero
675 let Inst{7-4} = 0b1111;
676 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
678 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
679 string opc, string asm, string cstr, list<dag> pattern>
680 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
681 opc, asm, cstr, pattern> {
683 let Inst{5} = 0; // H bit
684 let Inst{6} = 1; // S bit
686 let Inst{20} = 1; // L bit
687 let Inst{21} = 1; // W bit
688 let Inst{24} = 1; // P bit
689 let Inst{27-25} = 0b000;
691 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
692 string opc, string asm, string cstr, list<dag> pattern>
693 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
694 opc, asm, cstr, pattern> {
696 let Inst{5} = 0; // H bit
697 let Inst{6} = 1; // S bit
699 let Inst{20} = 0; // L bit
700 let Inst{21} = 1; // W bit
701 let Inst{24} = 1; // P bit
702 let Inst{27-25} = 0b000;
706 // Pre-indexed stores
707 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
708 string opc, string asm, string cstr, list<dag> pattern>
709 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
710 opc, asm, cstr, pattern> {
712 let Inst{5} = 1; // H bit
713 let Inst{6} = 0; // S bit
715 let Inst{20} = 0; // L bit
716 let Inst{21} = 1; // W bit
717 let Inst{24} = 1; // P bit
718 let Inst{27-25} = 0b000;
720 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
721 string opc, string asm, string cstr, list<dag> pattern>
722 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
723 opc, asm, cstr, pattern> {
725 let Inst{5} = 1; // H bit
726 let Inst{6} = 1; // S bit
728 let Inst{20} = 0; // L bit
729 let Inst{21} = 1; // W bit
730 let Inst{24} = 1; // P bit
731 let Inst{27-25} = 0b000;
734 // Post-indexed loads
735 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
736 string opc, string asm, string cstr, list<dag> pattern>
737 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
738 opc, asm, cstr,pattern> {
740 let Inst{5} = 1; // H bit
741 let Inst{6} = 0; // S bit
743 let Inst{20} = 1; // L bit
744 let Inst{21} = 0; // W bit
745 let Inst{24} = 0; // P bit
746 let Inst{27-25} = 0b000;
748 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
749 string opc, string asm, string cstr, list<dag> pattern>
750 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
751 opc, asm, cstr,pattern> {
755 let Inst{27-25} = 0b000;
756 let Inst{24} = 0; // P bit
757 let Inst{23} = offset{8}; // U bit
758 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
759 let Inst{21} = 0; // W bit
760 let Inst{20} = 1; // L bit
761 let Inst{19-16} = Rn; // Rn
762 let Inst{15-12} = Rt; // Rt
763 let Inst{11-8} = offset{7-4}; // imm7_4/zero
764 let Inst{7-4} = 0b1111;
765 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
767 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
768 string opc, string asm, string cstr, list<dag> pattern>
769 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
770 opc, asm, cstr,pattern> {
772 let Inst{5} = 0; // H bit
773 let Inst{6} = 1; // S bit
775 let Inst{20} = 1; // L bit
776 let Inst{21} = 0; // W bit
777 let Inst{24} = 0; // P bit
778 let Inst{27-25} = 0b000;
780 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
781 string opc, string asm, string cstr, list<dag> pattern>
782 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
783 opc, asm, cstr, pattern> {
785 let Inst{5} = 0; // H bit
786 let Inst{6} = 1; // S bit
788 let Inst{20} = 0; // L bit
789 let Inst{21} = 0; // W bit
790 let Inst{24} = 0; // P bit
791 let Inst{27-25} = 0b000;
794 // Post-indexed stores
795 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
796 string opc, string asm, string cstr, list<dag> pattern>
797 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
798 opc, asm, cstr,pattern> {
800 let Inst{5} = 1; // H bit
801 let Inst{6} = 0; // S bit
803 let Inst{20} = 0; // L bit
804 let Inst{21} = 0; // W bit
805 let Inst{24} = 0; // P bit
806 let Inst{27-25} = 0b000;
808 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
809 string opc, string asm, string cstr, list<dag> pattern>
810 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
811 opc, asm, cstr, pattern> {
813 let Inst{5} = 1; // H bit
814 let Inst{6} = 1; // S bit
816 let Inst{20} = 0; // L bit
817 let Inst{21} = 0; // W bit
818 let Inst{24} = 0; // P bit
819 let Inst{27-25} = 0b000;
822 // addrmode4 instructions
823 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
824 string asm, string cstr, list<dag> pattern>
825 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
830 let Inst{27-25} = 0b100;
831 let Inst{22} = 0; // S bit
832 let Inst{19-16} = Rn;
833 let Inst{15-0} = regs;
835 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
836 string asm, string cstr, list<dag> pattern>
837 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
838 asm, cstr, pattern> {
844 let Inst{27-25} = 0b100;
845 let Inst{24-23} = amode;
846 let Inst{22} = 0; // S bit
847 let Inst{20} = 1; // L bit
848 let Inst{19-16} = Rn;
849 let Inst{15-0} = dsts;
851 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
852 string asm, string cstr, list<dag> pattern>
853 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
854 asm, cstr, pattern> {
860 let Inst{27-25} = 0b100;
861 let Inst{24-23} = amode;
862 let Inst{22} = 0; // S bit
863 let Inst{20} = 0; // L bit
864 let Inst{19-16} = Rn;
865 let Inst{15-0} = srcs;
868 // Unsigned multiply, multiply-accumulate instructions.
869 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
870 string opc, string asm, list<dag> pattern>
871 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
872 opc, asm, "", pattern> {
873 let Inst{7-4} = 0b1001;
874 let Inst{20} = 0; // S bit
875 let Inst{27-21} = opcod;
877 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
878 string opc, string asm, list<dag> pattern>
879 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
880 opc, asm, "", pattern> {
881 let Inst{7-4} = 0b1001;
882 let Inst{27-21} = opcod;
885 // Most significant word multiply
886 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
887 InstrItinClass itin, string opc, string asm, list<dag> pattern>
888 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
889 opc, asm, "", pattern> {
893 let Inst{7-4} = opc7_4;
895 let Inst{27-21} = opcod;
896 let Inst{19-16} = Rd;
900 // MSW multiple w/ Ra operand
901 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
902 InstrItinClass itin, string opc, string asm, list<dag> pattern>
903 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
905 let Inst{15-12} = Ra;
908 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
909 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
910 InstrItinClass itin, string opc, string asm, list<dag> pattern>
911 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
912 opc, asm, "", pattern> {
918 let Inst{27-21} = opcod;
919 let Inst{6-5} = bit6_5;
923 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
924 InstrItinClass itin, string opc, string asm, list<dag> pattern>
925 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
927 let Inst{19-16} = Rd;
930 // AMulxyI with Ra operand
931 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
932 InstrItinClass itin, string opc, string asm, list<dag> pattern>
933 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
935 let Inst{15-12} = Ra;
938 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
939 InstrItinClass itin, string opc, string asm, list<dag> pattern>
940 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
943 let Inst{19-16} = RdHi;
944 let Inst{15-12} = RdLo;
947 // Extend instructions.
948 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
949 string opc, string asm, list<dag> pattern>
950 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
951 opc, asm, "", pattern> {
952 // All AExtI instructions have Rd and Rm register operands.
955 let Inst{15-12} = Rd;
957 let Inst{7-4} = 0b0111;
958 let Inst{9-8} = 0b00;
959 let Inst{27-20} = opcod;
962 // Misc Arithmetic instructions.
963 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
964 InstrItinClass itin, string opc, string asm, list<dag> pattern>
965 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
966 opc, asm, "", pattern> {
969 let Inst{27-20} = opcod;
970 let Inst{19-16} = 0b1111;
971 let Inst{15-12} = Rd;
972 let Inst{11-8} = 0b1111;
973 let Inst{7-4} = opc7_4;
978 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
979 string opc, string asm, list<dag> pattern>
980 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
981 opc, asm, "", pattern> {
986 let Inst{27-20} = opcod;
987 let Inst{19-16} = Rn;
988 let Inst{15-12} = Rd;
989 let Inst{11-7} = sh{7-3};
991 let Inst{5-4} = 0b01;
995 //===----------------------------------------------------------------------===//
997 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
998 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
999 list<Predicate> Predicates = [IsARM];
1001 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
1002 list<Predicate> Predicates = [IsARM, HasV5TE];
1004 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
1005 list<Predicate> Predicates = [IsARM, HasV6];
1008 //===----------------------------------------------------------------------===//
1010 // Thumb Instruction Format Definitions.
1013 // TI - Thumb instruction.
1015 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1016 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1017 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1018 let OutOperandList = oops;
1019 let InOperandList = iops;
1020 let AsmString = asm;
1021 let Pattern = pattern;
1022 list<Predicate> Predicates = [IsThumb];
1025 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
1026 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1028 // Two-address instructions
1029 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1031 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
1034 // tBL, tBX 32-bit instructions
1035 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1036 dag oops, dag iops, InstrItinClass itin, string asm,
1038 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
1040 let Inst{31-27} = opcod1;
1041 let Inst{15-14} = opcod2;
1042 let Inst{12} = opcod3;
1045 // BR_JT instructions
1046 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1048 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1051 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1052 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1053 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1054 let OutOperandList = oops;
1055 let InOperandList = iops;
1056 let AsmString = asm;
1057 let Pattern = pattern;
1058 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1061 class T1I<dag oops, dag iops, InstrItinClass itin,
1062 string asm, list<dag> pattern>
1063 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1064 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1065 string asm, list<dag> pattern>
1066 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1067 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1068 string asm, list<dag> pattern>
1069 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1071 // Two-address instructions
1072 class T1It<dag oops, dag iops, InstrItinClass itin,
1073 string asm, string cstr, list<dag> pattern>
1074 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1075 asm, cstr, pattern>;
1077 // Thumb1 instruction that can either be predicated or set CPSR.
1078 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1079 InstrItinClass itin,
1080 string opc, string asm, string cstr, list<dag> pattern>
1081 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1082 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1083 let InOperandList = !con(iops, (ins pred:$p));
1084 let AsmString = !strconcat(opc, "${s}${p}", asm);
1085 let Pattern = pattern;
1086 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1089 class T1sI<dag oops, dag iops, InstrItinClass itin,
1090 string opc, string asm, list<dag> pattern>
1091 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1093 // Two-address instructions
1094 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1095 string opc, string asm, list<dag> pattern>
1096 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1097 "$lhs = $dst", pattern>;
1099 // Thumb1 instruction that can be predicated.
1100 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1101 InstrItinClass itin,
1102 string opc, string asm, string cstr, list<dag> pattern>
1103 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1104 let OutOperandList = oops;
1105 let InOperandList = !con(iops, (ins pred:$p));
1106 let AsmString = !strconcat(opc, "${p}", asm);
1107 let Pattern = pattern;
1108 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1111 class T1pI<dag oops, dag iops, InstrItinClass itin,
1112 string opc, string asm, list<dag> pattern>
1113 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1115 // Two-address instructions
1116 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1117 string opc, string asm, list<dag> pattern>
1118 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1119 "$lhs = $dst", pattern>;
1121 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1122 string opc, string asm, list<dag> pattern>
1123 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1124 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1125 string opc, string asm, list<dag> pattern>
1126 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1127 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1128 string opc, string asm, list<dag> pattern>
1129 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1130 class T1pIs<dag oops, dag iops,
1131 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1132 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1134 class Encoding16 : Encoding {
1135 let Inst{31-16} = 0x0000;
1138 // A6.2 16-bit Thumb instruction encoding
1139 class T1Encoding<bits<6> opcode> : Encoding16 {
1140 let Inst{15-10} = opcode;
1143 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1144 class T1General<bits<5> opcode> : Encoding16 {
1145 let Inst{15-14} = 0b00;
1146 let Inst{13-9} = opcode;
1149 // A6.2.2 Data-processing encoding.
1150 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1151 let Inst{15-10} = 0b010000;
1152 let Inst{9-6} = opcode;
1155 // A6.2.3 Special data instructions and branch and exchange encoding.
1156 class T1Special<bits<4> opcode> : Encoding16 {
1157 let Inst{15-10} = 0b010001;
1158 let Inst{9-6} = opcode;
1161 // A6.2.4 Load/store single data item encoding.
1162 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1163 let Inst{15-12} = opA;
1164 let Inst{11-9} = opB;
1166 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1167 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1168 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1169 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1170 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1172 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1173 class T1Misc<bits<7> opcode> : Encoding16 {
1174 let Inst{15-12} = 0b1011;
1175 let Inst{11-5} = opcode;
1178 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1179 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1180 InstrItinClass itin,
1181 string opc, string asm, string cstr, list<dag> pattern>
1182 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1183 let OutOperandList = oops;
1184 let InOperandList = !con(iops, (ins pred:$p));
1185 let AsmString = !strconcat(opc, "${p}", asm);
1186 let Pattern = pattern;
1187 list<Predicate> Predicates = [IsThumb2];
1190 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1191 // input operand since by default it's a zero register. It will become an
1192 // implicit def once it's "flipped".
1194 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1196 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1197 InstrItinClass itin,
1198 string opc, string asm, string cstr, list<dag> pattern>
1199 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1200 let OutOperandList = oops;
1201 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1202 let AsmString = !strconcat(opc, "${s}${p}", asm);
1203 let Pattern = pattern;
1204 list<Predicate> Predicates = [IsThumb2];
1208 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1209 InstrItinClass itin,
1210 string asm, string cstr, list<dag> pattern>
1211 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1212 let OutOperandList = oops;
1213 let InOperandList = iops;
1214 let AsmString = asm;
1215 let Pattern = pattern;
1216 list<Predicate> Predicates = [IsThumb2];
1219 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1220 InstrItinClass itin,
1221 string asm, string cstr, list<dag> pattern>
1222 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1223 let OutOperandList = oops;
1224 let InOperandList = iops;
1225 let AsmString = asm;
1226 let Pattern = pattern;
1227 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1230 class T2I<dag oops, dag iops, InstrItinClass itin,
1231 string opc, string asm, list<dag> pattern>
1232 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1233 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1234 string opc, string asm, list<dag> pattern>
1235 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1236 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1237 string opc, string asm, list<dag> pattern>
1238 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1239 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1240 string opc, string asm, list<dag> pattern>
1241 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1242 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1243 string opc, string asm, list<dag> pattern>
1244 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1245 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1246 string opc, string asm, list<dag> pattern>
1247 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1249 let Inst{31-27} = 0b11101;
1250 let Inst{26-25} = 0b00;
1252 let Inst{23} = ?; // The U bit.
1255 let Inst{20} = load;
1258 class T2sI<dag oops, dag iops, InstrItinClass itin,
1259 string opc, string asm, list<dag> pattern>
1260 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1262 class T2XI<dag oops, dag iops, InstrItinClass itin,
1263 string asm, list<dag> pattern>
1264 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1265 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1266 string asm, list<dag> pattern>
1267 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1269 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1270 string opc, string asm, list<dag> pattern>
1271 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1273 // Two-address instructions
1274 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1275 string asm, string cstr, list<dag> pattern>
1276 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1278 // T2Iidxldst - Thumb2 indexed load / store instructions.
1279 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1281 AddrMode am, IndexMode im, InstrItinClass itin,
1282 string opc, string asm, string cstr, list<dag> pattern>
1283 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1284 let OutOperandList = oops;
1285 let InOperandList = !con(iops, (ins pred:$p));
1286 let AsmString = !strconcat(opc, "${p}", asm);
1287 let Pattern = pattern;
1288 list<Predicate> Predicates = [IsThumb2];
1289 let Inst{31-27} = 0b11111;
1290 let Inst{26-25} = 0b00;
1291 let Inst{24} = signed;
1293 let Inst{22-21} = opcod;
1294 let Inst{20} = load;
1296 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1297 let Inst{10} = pre; // The P bit.
1298 let Inst{8} = 1; // The W bit.
1301 // Helper class for disassembly only
1302 // A6.3.16 & A6.3.17
1303 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1304 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1305 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1306 : T2I<oops, iops, itin, opc, asm, pattern> {
1307 let Inst{31-27} = 0b11111;
1308 let Inst{26-24} = 0b011;
1309 let Inst{23} = long;
1310 let Inst{22-20} = op22_20;
1311 let Inst{7-4} = op7_4;
1314 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1315 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1316 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1319 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1320 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1321 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1324 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1325 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1326 list<Predicate> Predicates = [IsThumb2];
1329 //===----------------------------------------------------------------------===//
1331 //===----------------------------------------------------------------------===//
1332 // ARM VFP Instruction templates.
1335 // Almost all VFP instructions are predicable.
1336 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1337 IndexMode im, Format f, InstrItinClass itin,
1338 string opc, string asm, string cstr, list<dag> pattern>
1339 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1341 let Inst{31-28} = p;
1342 let OutOperandList = oops;
1343 let InOperandList = !con(iops, (ins pred:$p));
1344 let AsmString = !strconcat(opc, "${p}", asm);
1345 let Pattern = pattern;
1346 list<Predicate> Predicates = [HasVFP2];
1350 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1351 IndexMode im, Format f, InstrItinClass itin,
1352 string asm, string cstr, list<dag> pattern>
1353 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1354 let OutOperandList = oops;
1355 let InOperandList = iops;
1356 let AsmString = asm;
1357 let Pattern = pattern;
1358 list<Predicate> Predicates = [HasVFP2];
1361 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1362 string opc, string asm, list<dag> pattern>
1363 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1364 opc, asm, "", pattern>;
1366 // ARM VFP addrmode5 loads and stores
1367 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1368 InstrItinClass itin,
1369 string opc, string asm, list<dag> pattern>
1370 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1371 VFPLdStFrm, itin, opc, asm, "", pattern> {
1372 // Instruction operands.
1376 // Encode instruction operands.
1377 let Inst{23} = addr{8}; // U (add = (U == '1'))
1378 let Inst{22} = Dd{4};
1379 let Inst{19-16} = addr{12-9}; // Rn
1380 let Inst{15-12} = Dd{3-0};
1381 let Inst{7-0} = addr{7-0}; // imm8
1383 // TODO: Mark the instructions with the appropriate subtarget info.
1384 let Inst{27-24} = opcod1;
1385 let Inst{21-20} = opcod2;
1386 let Inst{11-9} = 0b101;
1387 let Inst{8} = 1; // Double precision
1389 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1390 let D = VFPNeonDomain;
1393 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1394 InstrItinClass itin,
1395 string opc, string asm, list<dag> pattern>
1396 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1397 VFPLdStFrm, itin, opc, asm, "", pattern> {
1398 // Instruction operands.
1402 // Encode instruction operands.
1403 let Inst{23} = addr{8}; // U (add = (U == '1'))
1404 let Inst{22} = Sd{0};
1405 let Inst{19-16} = addr{12-9}; // Rn
1406 let Inst{15-12} = Sd{4-1};
1407 let Inst{7-0} = addr{7-0}; // imm8
1409 // TODO: Mark the instructions with the appropriate subtarget info.
1410 let Inst{27-24} = opcod1;
1411 let Inst{21-20} = opcod2;
1412 let Inst{11-9} = 0b101;
1413 let Inst{8} = 0; // Single precision
1416 // VFP Load / store multiple pseudo instructions.
1417 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1419 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1421 let OutOperandList = oops;
1422 let InOperandList = !con(iops, (ins pred:$p));
1423 let Pattern = pattern;
1424 list<Predicate> Predicates = [HasVFP2];
1427 // Load / store multiple
1428 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1429 string asm, string cstr, list<dag> pattern>
1430 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1431 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1432 // TODO: Mark the instructions with the appropriate subtarget info.
1433 let Inst{27-25} = 0b110;
1434 let Inst{11-9} = 0b101;
1435 let Inst{8} = 1; // Double precision
1437 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1438 let D = VFPNeonDomain;
1441 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1442 string asm, string cstr, list<dag> pattern>
1443 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1444 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1445 // TODO: Mark the instructions with the appropriate subtarget info.
1446 let Inst{27-25} = 0b110;
1447 let Inst{11-9} = 0b101;
1448 let Inst{8} = 0; // Single precision
1451 // Double precision, unary
1452 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1453 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1454 string asm, list<dag> pattern>
1455 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1456 // Instruction operands.
1460 // Encode instruction operands.
1461 let Inst{3-0} = Dm{3-0};
1462 let Inst{5} = Dm{4};
1463 let Inst{15-12} = Dd{3-0};
1464 let Inst{22} = Dd{4};
1466 let Inst{27-23} = opcod1;
1467 let Inst{21-20} = opcod2;
1468 let Inst{19-16} = opcod3;
1469 let Inst{11-9} = 0b101;
1470 let Inst{8} = 1; // Double precision
1471 let Inst{7-6} = opcod4;
1472 let Inst{4} = opcod5;
1475 // Double precision, binary
1476 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1477 dag iops, InstrItinClass itin, string opc, string asm,
1479 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1480 // Instruction operands.
1485 // Encode instruction operands.
1486 let Inst{3-0} = Dm{3-0};
1487 let Inst{5} = Dm{4};
1488 let Inst{19-16} = Dn{3-0};
1489 let Inst{7} = Dn{4};
1490 let Inst{15-12} = Dd{3-0};
1491 let Inst{22} = Dd{4};
1493 let Inst{27-23} = opcod1;
1494 let Inst{21-20} = opcod2;
1495 let Inst{11-9} = 0b101;
1496 let Inst{8} = 1; // Double precision
1501 // Single precision, unary
1502 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1503 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1504 string asm, list<dag> pattern>
1505 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1506 // Instruction operands.
1510 // Encode instruction operands.
1511 let Inst{3-0} = Sm{4-1};
1512 let Inst{5} = Sm{0};
1513 let Inst{15-12} = Sd{4-1};
1514 let Inst{22} = Sd{0};
1516 let Inst{27-23} = opcod1;
1517 let Inst{21-20} = opcod2;
1518 let Inst{19-16} = opcod3;
1519 let Inst{11-9} = 0b101;
1520 let Inst{8} = 0; // Single precision
1521 let Inst{7-6} = opcod4;
1522 let Inst{4} = opcod5;
1525 // Single precision unary, if no NEON
1526 // Same as ASuI except not available if NEON is enabled
1527 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1528 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1529 string asm, list<dag> pattern>
1530 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1532 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1535 // Single precision, binary
1536 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1537 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1538 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1539 // Instruction operands.
1544 // Encode instruction operands.
1545 let Inst{3-0} = Sm{4-1};
1546 let Inst{5} = Sm{0};
1547 let Inst{19-16} = Sn{4-1};
1548 let Inst{7} = Sn{0};
1549 let Inst{15-12} = Sd{4-1};
1550 let Inst{22} = Sd{0};
1552 let Inst{27-23} = opcod1;
1553 let Inst{21-20} = opcod2;
1554 let Inst{11-9} = 0b101;
1555 let Inst{8} = 0; // Single precision
1560 // Single precision binary, if no NEON
1561 // Same as ASbI except not available if NEON is enabled
1562 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1563 dag iops, InstrItinClass itin, string opc, string asm,
1565 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1566 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1568 // Instruction operands.
1573 // Encode instruction operands.
1574 let Inst{3-0} = Sm{4-1};
1575 let Inst{5} = Sm{0};
1576 let Inst{19-16} = Sn{4-1};
1577 let Inst{7} = Sn{0};
1578 let Inst{15-12} = Sd{4-1};
1579 let Inst{22} = Sd{0};
1582 // VFP conversion instructions
1583 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1584 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1586 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1587 let Inst{27-23} = opcod1;
1588 let Inst{21-20} = opcod2;
1589 let Inst{19-16} = opcod3;
1590 let Inst{11-8} = opcod4;
1595 // VFP conversion between floating-point and fixed-point
1596 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1597 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1599 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1600 // size (fixed-point number): sx == 0 ? 16 : 32
1601 let Inst{7} = op5; // sx
1604 // VFP conversion instructions, if no NEON
1605 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1606 dag oops, dag iops, InstrItinClass itin,
1607 string opc, string asm, list<dag> pattern>
1608 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1610 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1613 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1614 InstrItinClass itin,
1615 string opc, string asm, list<dag> pattern>
1616 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1617 let Inst{27-20} = opcod1;
1618 let Inst{11-8} = opcod2;
1622 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1623 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1624 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1626 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1627 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1628 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1630 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1631 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1632 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1634 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1635 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1636 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1638 //===----------------------------------------------------------------------===//
1640 //===----------------------------------------------------------------------===//
1641 // ARM NEON Instruction templates.
1644 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1645 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1647 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1648 let OutOperandList = oops;
1649 let InOperandList = !con(iops, (ins pred:$p));
1650 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1651 let Pattern = pattern;
1652 list<Predicate> Predicates = [HasNEON];
1655 // Same as NeonI except it does not have a "data type" specifier.
1656 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1657 InstrItinClass itin, string opc, string asm, string cstr,
1659 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1660 let OutOperandList = oops;
1661 let InOperandList = !con(iops, (ins pred:$p));
1662 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1663 let Pattern = pattern;
1664 list<Predicate> Predicates = [HasNEON];
1667 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1668 dag oops, dag iops, InstrItinClass itin,
1669 string opc, string dt, string asm, string cstr, list<dag> pattern>
1670 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1672 let Inst{31-24} = 0b11110100;
1673 let Inst{23} = op23;
1674 let Inst{21-20} = op21_20;
1675 let Inst{11-8} = op11_8;
1676 let Inst{7-4} = op7_4;
1678 string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1684 let Inst{22} = Vd{4};
1685 let Inst{15-12} = Vd{3-0};
1686 let Inst{19-16} = Rn{3-0};
1687 let Inst{3-0} = Rm{3-0};
1690 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1691 dag oops, dag iops, InstrItinClass itin,
1692 string opc, string dt, string asm, string cstr, list<dag> pattern>
1693 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1694 dt, asm, cstr, pattern> {
1698 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1699 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1701 let OutOperandList = oops;
1702 let InOperandList = !con(iops, (ins pred:$p));
1703 list<Predicate> Predicates = [HasNEON];
1706 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1708 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1710 let OutOperandList = oops;
1711 let InOperandList = !con(iops, (ins pred:$p));
1712 let Pattern = pattern;
1713 list<Predicate> Predicates = [HasNEON];
1716 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1717 string opc, string dt, string asm, string cstr, list<dag> pattern>
1718 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1720 let Inst{31-25} = 0b1111001;
1721 string PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1724 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1725 string opc, string asm, string cstr, list<dag> pattern>
1726 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1728 let Inst{31-25} = 0b1111001;
1731 // NEON "one register and a modified immediate" format.
1732 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1734 dag oops, dag iops, InstrItinClass itin,
1735 string opc, string dt, string asm, string cstr,
1737 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1738 let Inst{23} = op23;
1739 let Inst{21-19} = op21_19;
1740 let Inst{11-8} = op11_8;
1746 // Instruction operands.
1750 let Inst{15-12} = Vd{3-0};
1751 let Inst{22} = Vd{4};
1752 let Inst{24} = SIMM{7};
1753 let Inst{18-16} = SIMM{6-4};
1754 let Inst{3-0} = SIMM{3-0};
1757 // NEON 2 vector register format.
1758 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1759 bits<5> op11_7, bit op6, bit op4,
1760 dag oops, dag iops, InstrItinClass itin,
1761 string opc, string dt, string asm, string cstr, list<dag> pattern>
1762 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1763 let Inst{24-23} = op24_23;
1764 let Inst{21-20} = op21_20;
1765 let Inst{19-18} = op19_18;
1766 let Inst{17-16} = op17_16;
1767 let Inst{11-7} = op11_7;
1771 // Instruction operands.
1775 let Inst{15-12} = Vd{3-0};
1776 let Inst{22} = Vd{4};
1777 let Inst{3-0} = Vm{3-0};
1778 let Inst{5} = Vm{4};
1781 // Same as N2V except it doesn't have a datatype suffix.
1782 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1783 bits<5> op11_7, bit op6, bit op4,
1784 dag oops, dag iops, InstrItinClass itin,
1785 string opc, string asm, string cstr, list<dag> pattern>
1786 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1787 let Inst{24-23} = op24_23;
1788 let Inst{21-20} = op21_20;
1789 let Inst{19-18} = op19_18;
1790 let Inst{17-16} = op17_16;
1791 let Inst{11-7} = op11_7;
1795 // Instruction operands.
1799 let Inst{15-12} = Vd{3-0};
1800 let Inst{22} = Vd{4};
1801 let Inst{3-0} = Vm{3-0};
1802 let Inst{5} = Vm{4};
1805 // NEON 2 vector register with immediate.
1806 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1807 dag oops, dag iops, Format f, InstrItinClass itin,
1808 string opc, string dt, string asm, string cstr, list<dag> pattern>
1809 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1810 let Inst{24} = op24;
1811 let Inst{23} = op23;
1812 let Inst{11-8} = op11_8;
1817 // Instruction operands.
1822 let Inst{15-12} = Vd{3-0};
1823 let Inst{22} = Vd{4};
1824 let Inst{3-0} = Vm{3-0};
1825 let Inst{5} = Vm{4};
1826 let Inst{21-16} = SIMM{5-0};
1829 // NEON 3 vector register format.
1830 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1831 dag oops, dag iops, Format f, InstrItinClass itin,
1832 string opc, string dt, string asm, string cstr, list<dag> pattern>
1833 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1834 let Inst{24} = op24;
1835 let Inst{23} = op23;
1836 let Inst{21-20} = op21_20;
1837 let Inst{11-8} = op11_8;
1841 // Instruction operands.
1846 let Inst{15-12} = Vd{3-0};
1847 let Inst{22} = Vd{4};
1848 let Inst{19-16} = Vn{3-0};
1849 let Inst{7} = Vn{4};
1850 let Inst{3-0} = Vm{3-0};
1851 let Inst{5} = Vm{4};
1854 // Same as N3V except it doesn't have a data type suffix.
1855 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1857 dag oops, dag iops, Format f, InstrItinClass itin,
1858 string opc, string asm, string cstr, list<dag> pattern>
1859 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1860 let Inst{24} = op24;
1861 let Inst{23} = op23;
1862 let Inst{21-20} = op21_20;
1863 let Inst{11-8} = op11_8;
1867 // Instruction operands.
1872 let Inst{15-12} = Vd{3-0};
1873 let Inst{22} = Vd{4};
1874 let Inst{19-16} = Vn{3-0};
1875 let Inst{7} = Vn{4};
1876 let Inst{3-0} = Vm{3-0};
1877 let Inst{5} = Vm{4};
1880 // NEON VMOVs between scalar and core registers.
1881 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1882 dag oops, dag iops, Format f, InstrItinClass itin,
1883 string opc, string dt, string asm, list<dag> pattern>
1884 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1886 let Inst{27-20} = opcod1;
1887 let Inst{11-8} = opcod2;
1888 let Inst{6-5} = opcod3;
1891 let OutOperandList = oops;
1892 let InOperandList = !con(iops, (ins pred:$p));
1893 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1894 let Pattern = pattern;
1895 list<Predicate> Predicates = [HasNEON];
1897 string PostEncoderMethod = "NEONThumb2DupPostEncoder";
1904 let Inst{31-28} = p{3-0};
1906 let Inst{19-16} = V{3-0};
1907 let Inst{15-12} = R{3-0};
1909 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1910 dag oops, dag iops, InstrItinClass itin,
1911 string opc, string dt, string asm, list<dag> pattern>
1912 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1913 opc, dt, asm, pattern>;
1914 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1915 dag oops, dag iops, InstrItinClass itin,
1916 string opc, string dt, string asm, list<dag> pattern>
1917 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1918 opc, dt, asm, pattern>;
1919 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1920 dag oops, dag iops, InstrItinClass itin,
1921 string opc, string dt, string asm, list<dag> pattern>
1922 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1923 opc, dt, asm, pattern>;
1925 // Vector Duplicate Lane (from scalar to all elements)
1926 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1927 InstrItinClass itin, string opc, string dt, string asm,
1929 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1930 let Inst{24-23} = 0b11;
1931 let Inst{21-20} = 0b11;
1932 let Inst{19-16} = op19_16;
1933 let Inst{11-7} = 0b11000;
1941 let Inst{22} = Vd{4};
1942 let Inst{15-12} = Vd{3-0};
1943 let Inst{5} = Vm{4};
1944 let Inst{3-0} = Vm{3-0};
1947 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1948 // for single-precision FP.
1949 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1950 list<Predicate> Predicates = [HasNEON,UseNEONForFP];