1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def ExtFrm : Format<13>;
41 def VFPUnaryFrm : Format<14>;
42 def VFPBinaryFrm : Format<15>;
43 def VFPConv1Frm : Format<16>;
44 def VFPConv2Frm : Format<17>;
45 def VFPConv3Frm : Format<18>;
46 def VFPConv4Frm : Format<19>;
47 def VFPConv5Frm : Format<20>;
48 def VFPLdStFrm : Format<21>;
49 def VFPLdStMulFrm : Format<22>;
50 def VFPMiscFrm : Format<23>;
52 def ThumbFrm : Format<24>;
54 def NEONFrm : Format<25>;
55 def NEONGetLnFrm : Format<26>;
56 def NEONSetLnFrm : Format<27>;
57 def NEONDupFrm : Format<28>;
59 def MiscFrm : Format<29>;
60 def ThumbMiscFrm : Format<30>;
62 def NLdStFrm : Format<31>;
63 def NVdImmFrm : Format<32>;
64 def NVdVmImmFrm : Format<33>;
65 def NVdVmVCVTFrm : Format<34>;
69 // the instruction has a Rn register operand.
70 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
71 // it doesn't have a Rn operand.
72 class UnaryDP { bit isUnaryDataProc = 1; }
74 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
75 // a 16-bit Thumb instruction if certain conditions are met.
76 class Xform16Bit { bit canXformTo16Bit = 1; }
78 //===----------------------------------------------------------------------===//
79 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
83 class AddrMode<bits<4> val> {
86 def AddrModeNone : AddrMode<0>;
87 def AddrMode1 : AddrMode<1>;
88 def AddrMode2 : AddrMode<2>;
89 def AddrMode3 : AddrMode<3>;
90 def AddrMode4 : AddrMode<4>;
91 def AddrMode5 : AddrMode<5>;
92 def AddrMode6 : AddrMode<6>;
93 def AddrModeT1_1 : AddrMode<7>;
94 def AddrModeT1_2 : AddrMode<8>;
95 def AddrModeT1_4 : AddrMode<9>;
96 def AddrModeT1_s : AddrMode<10>;
97 def AddrModeT2_i12: AddrMode<11>;
98 def AddrModeT2_i8 : AddrMode<12>;
99 def AddrModeT2_so : AddrMode<13>;
100 def AddrModeT2_pc : AddrMode<14>;
101 def AddrModeT2_i8s4 : AddrMode<15>;
104 class SizeFlagVal<bits<3> val> {
107 def SizeInvalid : SizeFlagVal<0>; // Unset.
108 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
109 def Size8Bytes : SizeFlagVal<2>;
110 def Size4Bytes : SizeFlagVal<3>;
111 def Size2Bytes : SizeFlagVal<4>;
113 // Load / store index mode.
114 class IndexMode<bits<2> val> {
117 def IndexModeNone : IndexMode<0>;
118 def IndexModePre : IndexMode<1>;
119 def IndexModePost : IndexMode<2>;
120 def IndexModeUpd : IndexMode<3>;
122 // Instruction execution domain.
123 class Domain<bits<2> val> {
126 def GenericDomain : Domain<0>;
127 def VFPDomain : Domain<1>; // Instructions in VFP domain only
128 def NeonDomain : Domain<2>; // Instructions in Neon domain only
129 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
131 //===----------------------------------------------------------------------===//
133 // ARM special operands.
136 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
137 // register whose default is 0 (no register).
138 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
139 (ops (i32 14), (i32 zero_reg))> {
140 let PrintMethod = "printPredicateOperand";
143 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
144 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
145 let PrintMethod = "printSBitModifierOperand";
148 // Same as cc_out except it defaults to setting CPSR.
149 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
150 let PrintMethod = "printSBitModifierOperand";
153 // ARM special operands for disassembly only.
156 def cps_opt : Operand<i32> {
157 let PrintMethod = "printCPSOptionOperand";
160 def msr_mask : Operand<i32> {
161 let PrintMethod = "printMSRMaskOperand";
164 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
165 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
166 def neg_zero : Operand<i32> {
167 let PrintMethod = "printNegZeroOperand";
170 //===----------------------------------------------------------------------===//
172 // ARM Instruction templates.
175 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
176 Format f, Domain d, string cstr, InstrItinClass itin>
178 let Namespace = "ARM";
182 bits<4> AddrModeBits = AM.Value;
185 bits<3> SizeFlag = SZ.Value;
188 bits<2> IndexModeBits = IM.Value;
191 bits<6> Form = F.Value;
194 bits<2> Dom = D.Value;
197 // Attributes specific to ARM instructions...
199 bit isUnaryDataProc = 0;
200 bit canXformTo16Bit = 0;
202 let Constraints = cstr;
203 let Itinerary = itin;
210 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
211 Format f, Domain d, string cstr, InstrItinClass itin>
212 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
214 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
215 // on by adding flavors to specific instructions.
216 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
217 Format f, Domain d, string cstr, InstrItinClass itin>
218 : InstTemplate<am, sz, im, f, d, cstr, itin>;
220 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
221 string asm, list<dag> pattern>
222 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
224 let OutOperandList = oops;
225 let InOperandList = iops;
227 let Pattern = pattern;
230 // Almost all ARM instructions are predicable.
231 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
232 IndexMode im, Format f, InstrItinClass itin,
233 string opc, string asm, string cstr,
235 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
236 let OutOperandList = oops;
237 let InOperandList = !con(iops, (ins pred:$p));
238 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
239 let Pattern = pattern;
240 list<Predicate> Predicates = [IsARM];
242 // A few are not predicable
243 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
244 IndexMode im, Format f, InstrItinClass itin,
245 string opc, string asm, string cstr,
247 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
248 let OutOperandList = oops;
249 let InOperandList = iops;
250 let AsmString = !strconcat(opc, asm);
251 let Pattern = pattern;
252 let isPredicable = 0;
253 list<Predicate> Predicates = [IsARM];
256 // Same as I except it can optionally modify CPSR. Note it's modeled as
257 // an input operand since by default it's a zero register. It will
258 // become an implicit def once it's "flipped".
259 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
260 IndexMode im, Format f, InstrItinClass itin,
261 string opc, string asm, string cstr,
263 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
264 let OutOperandList = oops;
265 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
266 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
267 let Pattern = pattern;
268 list<Predicate> Predicates = [IsARM];
272 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
273 IndexMode im, Format f, InstrItinClass itin,
274 string asm, string cstr, list<dag> pattern>
275 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
276 let OutOperandList = oops;
277 let InOperandList = iops;
279 let Pattern = pattern;
280 list<Predicate> Predicates = [IsARM];
283 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
284 string opc, string asm, list<dag> pattern>
285 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
286 opc, asm, "", pattern>;
287 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
288 string opc, string asm, list<dag> pattern>
289 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
290 opc, asm, "", pattern>;
291 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
292 string asm, list<dag> pattern>
293 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
295 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
296 string opc, string asm, list<dag> pattern>
297 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
298 opc, asm, "", pattern>;
300 // Ctrl flow instructions
301 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
302 string opc, string asm, list<dag> pattern>
303 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
304 opc, asm, "", pattern> {
305 let Inst{27-24} = opcod;
307 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
308 string asm, list<dag> pattern>
309 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
311 let Inst{27-24} = opcod;
313 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
314 string asm, list<dag> pattern>
315 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
318 // BR_JT instructions
319 class JTI<dag oops, dag iops, InstrItinClass itin,
320 string asm, list<dag> pattern>
321 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
325 // Atomic load/store instructions
327 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
328 string opc, string asm, list<dag> pattern>
329 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
330 opc, asm, "", pattern> {
331 let Inst{27-23} = 0b00011;
332 let Inst{22-21} = opcod;
334 let Inst{11-0} = 0b111110011111;
336 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
337 string opc, string asm, list<dag> pattern>
338 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
339 opc, asm, "", pattern> {
340 let Inst{27-23} = 0b00011;
341 let Inst{22-21} = opcod;
343 let Inst{11-4} = 0b11111001;
346 // addrmode1 instructions
347 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
348 string opc, string asm, list<dag> pattern>
349 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
350 opc, asm, "", pattern> {
351 let Inst{24-21} = opcod;
352 let Inst{27-26} = {0,0};
354 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
355 string opc, string asm, list<dag> pattern>
356 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
357 opc, asm, "", pattern> {
358 let Inst{24-21} = opcod;
359 let Inst{27-26} = {0,0};
361 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
362 string asm, list<dag> pattern>
363 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
365 let Inst{24-21} = opcod;
366 let Inst{27-26} = {0,0};
368 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
369 string opc, string asm, list<dag> pattern>
370 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
371 opc, asm, "", pattern>;
374 // addrmode2 loads and stores
375 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
378 opc, asm, "", pattern> {
379 let Inst{27-26} = {0,1};
383 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
384 string opc, string asm, list<dag> pattern>
385 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
386 opc, asm, "", pattern> {
387 let Inst{20} = 1; // L bit
388 let Inst{21} = 0; // W bit
389 let Inst{22} = 0; // B bit
390 let Inst{24} = 1; // P bit
391 let Inst{27-26} = {0,1};
393 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
394 string asm, list<dag> pattern>
395 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
397 let Inst{20} = 1; // L bit
398 let Inst{21} = 0; // W bit
399 let Inst{22} = 0; // B bit
400 let Inst{24} = 1; // P bit
401 let Inst{27-26} = {0,1};
403 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
404 string opc, string asm, list<dag> pattern>
405 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
406 opc, asm, "", pattern> {
407 let Inst{20} = 1; // L bit
408 let Inst{21} = 0; // W bit
409 let Inst{22} = 1; // B bit
410 let Inst{24} = 1; // P bit
411 let Inst{27-26} = {0,1};
413 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
414 string asm, list<dag> pattern>
415 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
417 let Inst{20} = 1; // L bit
418 let Inst{21} = 0; // W bit
419 let Inst{22} = 1; // B bit
420 let Inst{24} = 1; // P bit
421 let Inst{27-26} = {0,1};
425 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
426 string opc, string asm, list<dag> pattern>
427 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
428 opc, asm, "", pattern> {
429 let Inst{20} = 0; // L bit
430 let Inst{21} = 0; // W bit
431 let Inst{22} = 0; // B bit
432 let Inst{24} = 1; // P bit
433 let Inst{27-26} = {0,1};
435 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
436 string asm, list<dag> pattern>
437 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
439 let Inst{20} = 0; // L bit
440 let Inst{21} = 0; // W bit
441 let Inst{22} = 0; // B bit
442 let Inst{24} = 1; // P bit
443 let Inst{27-26} = {0,1};
445 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
446 string opc, string asm, list<dag> pattern>
447 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
448 opc, asm, "", pattern> {
449 let Inst{20} = 0; // L bit
450 let Inst{21} = 0; // W bit
451 let Inst{22} = 1; // B bit
452 let Inst{24} = 1; // P bit
453 let Inst{27-26} = {0,1};
455 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
456 string asm, list<dag> pattern>
457 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
459 let Inst{20} = 0; // L bit
460 let Inst{21} = 0; // W bit
461 let Inst{22} = 1; // B bit
462 let Inst{24} = 1; // P bit
463 let Inst{27-26} = {0,1};
467 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
468 string opc, string asm, string cstr, list<dag> pattern>
469 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
470 opc, asm, cstr, pattern> {
471 let Inst{20} = 1; // L bit
472 let Inst{21} = 1; // W bit
473 let Inst{22} = 0; // B bit
474 let Inst{24} = 1; // P bit
475 let Inst{27-26} = {0,1};
477 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
478 string opc, string asm, string cstr, list<dag> pattern>
479 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
480 opc, asm, cstr, pattern> {
481 let Inst{20} = 1; // L bit
482 let Inst{21} = 1; // W bit
483 let Inst{22} = 1; // B bit
484 let Inst{24} = 1; // P bit
485 let Inst{27-26} = {0,1};
488 // Pre-indexed stores
489 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
490 string opc, string asm, string cstr, list<dag> pattern>
491 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
492 opc, asm, cstr, pattern> {
493 let Inst{20} = 0; // L bit
494 let Inst{21} = 1; // W bit
495 let Inst{22} = 0; // B bit
496 let Inst{24} = 1; // P bit
497 let Inst{27-26} = {0,1};
499 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
500 string opc, string asm, string cstr, list<dag> pattern>
501 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
502 opc, asm, cstr, pattern> {
503 let Inst{20} = 0; // L bit
504 let Inst{21} = 1; // W bit
505 let Inst{22} = 1; // B bit
506 let Inst{24} = 1; // P bit
507 let Inst{27-26} = {0,1};
510 // Post-indexed loads
511 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
512 string opc, string asm, string cstr, list<dag> pattern>
513 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
514 opc, asm, cstr,pattern> {
515 let Inst{20} = 1; // L bit
516 let Inst{21} = 0; // W bit
517 let Inst{22} = 0; // B bit
518 let Inst{24} = 0; // P bit
519 let Inst{27-26} = {0,1};
521 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
522 string opc, string asm, string cstr, list<dag> pattern>
523 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
524 opc, asm, cstr,pattern> {
525 let Inst{20} = 1; // L bit
526 let Inst{21} = 0; // W bit
527 let Inst{22} = 1; // B bit
528 let Inst{24} = 0; // P bit
529 let Inst{27-26} = {0,1};
532 // Post-indexed stores
533 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
534 string opc, string asm, string cstr, list<dag> pattern>
535 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
536 opc, asm, cstr,pattern> {
537 let Inst{20} = 0; // L bit
538 let Inst{21} = 0; // W bit
539 let Inst{22} = 0; // B bit
540 let Inst{24} = 0; // P bit
541 let Inst{27-26} = {0,1};
543 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
544 string opc, string asm, string cstr, list<dag> pattern>
545 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
546 opc, asm, cstr,pattern> {
547 let Inst{20} = 0; // L bit
548 let Inst{21} = 0; // W bit
549 let Inst{22} = 1; // B bit
550 let Inst{24} = 0; // P bit
551 let Inst{27-26} = {0,1};
554 // addrmode3 instructions
555 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
556 string opc, string asm, list<dag> pattern>
557 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
558 opc, asm, "", pattern>;
559 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
560 string asm, list<dag> pattern>
561 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
565 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
566 string opc, string asm, list<dag> pattern>
567 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
568 opc, asm, "", pattern> {
570 let Inst{5} = 1; // H bit
571 let Inst{6} = 0; // S bit
573 let Inst{20} = 1; // L bit
574 let Inst{21} = 0; // W bit
575 let Inst{24} = 1; // P bit
576 let Inst{27-25} = 0b000;
578 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
579 string asm, list<dag> pattern>
580 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
583 let Inst{5} = 1; // H bit
584 let Inst{6} = 0; // S bit
586 let Inst{20} = 1; // L bit
587 let Inst{21} = 0; // W bit
588 let Inst{24} = 1; // P bit
590 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
591 string opc, string asm, list<dag> pattern>
592 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
593 opc, asm, "", pattern> {
595 let Inst{5} = 1; // H bit
596 let Inst{6} = 1; // S bit
598 let Inst{20} = 1; // L bit
599 let Inst{21} = 0; // W bit
600 let Inst{24} = 1; // P bit
601 let Inst{27-25} = 0b000;
603 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
604 string asm, list<dag> pattern>
605 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
608 let Inst{5} = 1; // H bit
609 let Inst{6} = 1; // S bit
611 let Inst{20} = 1; // L bit
612 let Inst{21} = 0; // W bit
613 let Inst{24} = 1; // P bit
615 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
616 string opc, string asm, list<dag> pattern>
617 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
618 opc, asm, "", pattern> {
620 let Inst{5} = 0; // H bit
621 let Inst{6} = 1; // S bit
623 let Inst{20} = 1; // L bit
624 let Inst{21} = 0; // W bit
625 let Inst{24} = 1; // P bit
626 let Inst{27-25} = 0b000;
628 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
629 string asm, list<dag> pattern>
630 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
633 let Inst{5} = 0; // H bit
634 let Inst{6} = 1; // S bit
636 let Inst{20} = 1; // L bit
637 let Inst{21} = 0; // W bit
638 let Inst{24} = 1; // P bit
640 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
641 string opc, string asm, list<dag> pattern>
642 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
643 opc, asm, "", pattern> {
645 let Inst{5} = 0; // H bit
646 let Inst{6} = 1; // S bit
648 let Inst{20} = 0; // L bit
649 let Inst{21} = 0; // W bit
650 let Inst{24} = 1; // P bit
651 let Inst{27-25} = 0b000;
655 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
656 string opc, string asm, list<dag> pattern>
657 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
658 opc, asm, "", pattern> {
660 let Inst{5} = 1; // H bit
661 let Inst{6} = 0; // S bit
663 let Inst{20} = 0; // L bit
664 let Inst{21} = 0; // W bit
665 let Inst{24} = 1; // P bit
666 let Inst{27-25} = 0b000;
668 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
669 string asm, list<dag> pattern>
670 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
673 let Inst{5} = 1; // H bit
674 let Inst{6} = 0; // S bit
676 let Inst{20} = 0; // L bit
677 let Inst{21} = 0; // W bit
678 let Inst{24} = 1; // P bit
680 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
681 string opc, string asm, list<dag> pattern>
682 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
683 opc, asm, "", pattern> {
685 let Inst{5} = 1; // H bit
686 let Inst{6} = 1; // S bit
688 let Inst{20} = 0; // L bit
689 let Inst{21} = 0; // W bit
690 let Inst{24} = 1; // P bit
691 let Inst{27-25} = 0b000;
695 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
696 string opc, string asm, string cstr, list<dag> pattern>
697 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
698 opc, asm, cstr, pattern> {
700 let Inst{5} = 1; // H bit
701 let Inst{6} = 0; // S bit
703 let Inst{20} = 1; // L bit
704 let Inst{21} = 1; // W bit
705 let Inst{24} = 1; // P bit
706 let Inst{27-25} = 0b000;
708 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
709 string opc, string asm, string cstr, list<dag> pattern>
710 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
711 opc, asm, cstr, pattern> {
713 let Inst{5} = 1; // H bit
714 let Inst{6} = 1; // S bit
716 let Inst{20} = 1; // L bit
717 let Inst{21} = 1; // W bit
718 let Inst{24} = 1; // P bit
719 let Inst{27-25} = 0b000;
721 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
722 string opc, string asm, string cstr, list<dag> pattern>
723 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
724 opc, asm, cstr, pattern> {
726 let Inst{5} = 0; // H bit
727 let Inst{6} = 1; // S bit
729 let Inst{20} = 1; // L bit
730 let Inst{21} = 1; // W bit
731 let Inst{24} = 1; // P bit
732 let Inst{27-25} = 0b000;
734 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
735 string opc, string asm, string cstr, list<dag> pattern>
736 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
737 opc, asm, cstr, pattern> {
739 let Inst{5} = 0; // H bit
740 let Inst{6} = 1; // S bit
742 let Inst{20} = 0; // L bit
743 let Inst{21} = 1; // W bit
744 let Inst{24} = 1; // P bit
745 let Inst{27-25} = 0b000;
749 // Pre-indexed stores
750 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
751 string opc, string asm, string cstr, list<dag> pattern>
752 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
753 opc, asm, cstr, pattern> {
755 let Inst{5} = 1; // H bit
756 let Inst{6} = 0; // S bit
758 let Inst{20} = 0; // L bit
759 let Inst{21} = 1; // W bit
760 let Inst{24} = 1; // P bit
761 let Inst{27-25} = 0b000;
763 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
764 string opc, string asm, string cstr, list<dag> pattern>
765 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
766 opc, asm, cstr, pattern> {
768 let Inst{5} = 1; // H bit
769 let Inst{6} = 1; // S bit
771 let Inst{20} = 0; // L bit
772 let Inst{21} = 1; // W bit
773 let Inst{24} = 1; // P bit
774 let Inst{27-25} = 0b000;
777 // Post-indexed loads
778 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
779 string opc, string asm, string cstr, list<dag> pattern>
780 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
781 opc, asm, cstr,pattern> {
783 let Inst{5} = 1; // H bit
784 let Inst{6} = 0; // S bit
786 let Inst{20} = 1; // L bit
787 let Inst{21} = 0; // W bit
788 let Inst{24} = 0; // P bit
789 let Inst{27-25} = 0b000;
791 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
792 string opc, string asm, string cstr, list<dag> pattern>
793 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
794 opc, asm, cstr,pattern> {
796 let Inst{5} = 1; // H bit
797 let Inst{6} = 1; // S bit
799 let Inst{20} = 1; // L bit
800 let Inst{21} = 0; // W bit
801 let Inst{24} = 0; // P bit
802 let Inst{27-25} = 0b000;
804 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
805 string opc, string asm, string cstr, list<dag> pattern>
806 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
807 opc, asm, cstr,pattern> {
809 let Inst{5} = 0; // H bit
810 let Inst{6} = 1; // S bit
812 let Inst{20} = 1; // L bit
813 let Inst{21} = 0; // W bit
814 let Inst{24} = 0; // P bit
815 let Inst{27-25} = 0b000;
817 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
818 string opc, string asm, string cstr, list<dag> pattern>
819 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
820 opc, asm, cstr, pattern> {
822 let Inst{5} = 0; // H bit
823 let Inst{6} = 1; // S bit
825 let Inst{20} = 0; // L bit
826 let Inst{21} = 0; // W bit
827 let Inst{24} = 0; // P bit
828 let Inst{27-25} = 0b000;
831 // Post-indexed stores
832 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
833 string opc, string asm, string cstr, list<dag> pattern>
834 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
835 opc, asm, cstr,pattern> {
837 let Inst{5} = 1; // H bit
838 let Inst{6} = 0; // S bit
840 let Inst{20} = 0; // L bit
841 let Inst{21} = 0; // W bit
842 let Inst{24} = 0; // P bit
843 let Inst{27-25} = 0b000;
845 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
846 string opc, string asm, string cstr, list<dag> pattern>
847 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
848 opc, asm, cstr, pattern> {
850 let Inst{5} = 1; // H bit
851 let Inst{6} = 1; // S bit
853 let Inst{20} = 0; // L bit
854 let Inst{21} = 0; // W bit
855 let Inst{24} = 0; // P bit
856 let Inst{27-25} = 0b000;
859 // addrmode4 instructions
860 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
861 string asm, string cstr, list<dag> pattern>
862 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
863 asm, cstr, pattern> {
864 let Inst{20} = 1; // L bit
865 let Inst{22} = 0; // S bit
866 let Inst{27-25} = 0b100;
868 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
869 string asm, string cstr, list<dag> pattern>
870 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
871 asm, cstr, pattern> {
872 let Inst{20} = 0; // L bit
873 let Inst{22} = 0; // S bit
874 let Inst{27-25} = 0b100;
877 // Unsigned multiply, multiply-accumulate instructions.
878 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
879 string opc, string asm, list<dag> pattern>
880 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
881 opc, asm, "", pattern> {
882 let Inst{7-4} = 0b1001;
883 let Inst{20} = 0; // S bit
884 let Inst{27-21} = opcod;
886 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
887 string opc, string asm, list<dag> pattern>
888 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
889 opc, asm, "", pattern> {
890 let Inst{7-4} = 0b1001;
891 let Inst{27-21} = opcod;
894 // Most significant word multiply
895 class AMul2I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
896 string opc, string asm, list<dag> pattern>
897 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
898 opc, asm, "", pattern> {
899 let Inst{7-4} = 0b1001;
901 let Inst{27-21} = opcod;
904 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
905 class AMulxyI<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
906 string opc, string asm, list<dag> pattern>
907 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
908 opc, asm, "", pattern> {
912 let Inst{27-21} = opcod;
915 // Extend instructions.
916 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
917 string opc, string asm, list<dag> pattern>
918 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
919 opc, asm, "", pattern> {
920 let Inst{7-4} = 0b0111;
921 let Inst{27-20} = opcod;
924 // Misc Arithmetic instructions.
925 class AMiscA1I<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
926 string opc, string asm, list<dag> pattern>
927 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
928 opc, asm, "", pattern> {
929 let Inst{27-20} = opcod;
932 //===----------------------------------------------------------------------===//
934 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
935 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
936 list<Predicate> Predicates = [IsARM];
938 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
939 list<Predicate> Predicates = [IsARM, HasV5TE];
941 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
942 list<Predicate> Predicates = [IsARM, HasV6];
945 //===----------------------------------------------------------------------===//
947 // Thumb Instruction Format Definitions.
950 // TI - Thumb instruction.
952 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
953 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
954 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
955 let OutOperandList = oops;
956 let InOperandList = iops;
958 let Pattern = pattern;
959 list<Predicate> Predicates = [IsThumb];
962 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
963 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
965 // Two-address instructions
966 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
968 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
971 // tBL, tBX 32-bit instructions
972 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
973 dag oops, dag iops, InstrItinClass itin, string asm,
975 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
977 let Inst{31-27} = opcod1;
978 let Inst{15-14} = opcod2;
979 let Inst{12} = opcod3;
982 // BR_JT instructions
983 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
985 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
988 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
989 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
990 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
991 let OutOperandList = oops;
992 let InOperandList = iops;
994 let Pattern = pattern;
995 list<Predicate> Predicates = [IsThumb1Only];
998 class T1I<dag oops, dag iops, InstrItinClass itin,
999 string asm, list<dag> pattern>
1000 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1001 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1002 string asm, list<dag> pattern>
1003 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1004 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1005 string asm, list<dag> pattern>
1006 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1008 // Two-address instructions
1009 class T1It<dag oops, dag iops, InstrItinClass itin,
1010 string asm, string cstr, list<dag> pattern>
1011 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1012 asm, cstr, pattern>;
1014 // Thumb1 instruction that can either be predicated or set CPSR.
1015 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1016 InstrItinClass itin,
1017 string opc, string asm, string cstr, list<dag> pattern>
1018 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1019 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1020 let InOperandList = !con(iops, (ins pred:$p));
1021 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1022 let Pattern = pattern;
1023 list<Predicate> Predicates = [IsThumb1Only];
1026 class T1sI<dag oops, dag iops, InstrItinClass itin,
1027 string opc, string asm, list<dag> pattern>
1028 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1030 // Two-address instructions
1031 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1032 string opc, string asm, list<dag> pattern>
1033 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1034 "$lhs = $dst", pattern>;
1036 // Thumb1 instruction that can be predicated.
1037 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1038 InstrItinClass itin,
1039 string opc, string asm, string cstr, list<dag> pattern>
1040 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1041 let OutOperandList = oops;
1042 let InOperandList = !con(iops, (ins pred:$p));
1043 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1044 let Pattern = pattern;
1045 list<Predicate> Predicates = [IsThumb1Only];
1048 class T1pI<dag oops, dag iops, InstrItinClass itin,
1049 string opc, string asm, list<dag> pattern>
1050 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1052 // Two-address instructions
1053 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1054 string opc, string asm, list<dag> pattern>
1055 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1056 "$lhs = $dst", pattern>;
1058 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1059 string opc, string asm, list<dag> pattern>
1060 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1061 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1062 string opc, string asm, list<dag> pattern>
1063 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1064 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1065 string opc, string asm, list<dag> pattern>
1066 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1067 class T1pIs<dag oops, dag iops,
1068 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1069 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1071 class Encoding16 : Encoding {
1072 let Inst{31-16} = 0x0000;
1075 // A6.2 16-bit Thumb instruction encoding
1076 class T1Encoding<bits<6> opcode> : Encoding16 {
1077 let Inst{15-10} = opcode;
1080 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1081 class T1General<bits<5> opcode> : Encoding16 {
1082 let Inst{15-14} = 0b00;
1083 let Inst{13-9} = opcode;
1086 // A6.2.2 Data-processing encoding.
1087 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1088 let Inst{15-10} = 0b010000;
1089 let Inst{9-6} = opcode;
1092 // A6.2.3 Special data instructions and branch and exchange encoding.
1093 class T1Special<bits<4> opcode> : Encoding16 {
1094 let Inst{15-10} = 0b010001;
1095 let Inst{9-6} = opcode;
1098 // A6.2.4 Load/store single data item encoding.
1099 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1100 let Inst{15-12} = opA;
1101 let Inst{11-9} = opB;
1103 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1104 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1105 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1106 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1107 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1109 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1110 class T1Misc<bits<7> opcode> : Encoding16 {
1111 let Inst{15-12} = 0b1011;
1112 let Inst{11-5} = opcode;
1115 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1116 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1117 InstrItinClass itin,
1118 string opc, string asm, string cstr, list<dag> pattern>
1119 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1120 let OutOperandList = oops;
1121 let InOperandList = !con(iops, (ins pred:$p));
1122 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1123 let Pattern = pattern;
1124 list<Predicate> Predicates = [IsThumb2];
1127 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as
1128 // an input operand since by default it's a zero register. It will
1129 // become an implicit def once it's "flipped".
1130 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1132 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1133 InstrItinClass itin,
1134 string opc, string asm, string cstr, list<dag> pattern>
1135 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1136 let OutOperandList = oops;
1137 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1138 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm));
1139 let Pattern = pattern;
1140 list<Predicate> Predicates = [IsThumb2];
1144 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1145 InstrItinClass itin,
1146 string asm, string cstr, list<dag> pattern>
1147 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1148 let OutOperandList = oops;
1149 let InOperandList = iops;
1150 let AsmString = asm;
1151 let Pattern = pattern;
1152 list<Predicate> Predicates = [IsThumb2];
1155 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1156 InstrItinClass itin,
1157 string asm, string cstr, list<dag> pattern>
1158 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1159 let OutOperandList = oops;
1160 let InOperandList = iops;
1161 let AsmString = asm;
1162 let Pattern = pattern;
1163 list<Predicate> Predicates = [IsThumb1Only];
1166 class T2I<dag oops, dag iops, InstrItinClass itin,
1167 string opc, string asm, list<dag> pattern>
1168 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1169 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1170 string opc, string asm, list<dag> pattern>
1171 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1172 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1173 string opc, string asm, list<dag> pattern>
1174 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1175 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1176 string opc, string asm, list<dag> pattern>
1177 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1178 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1179 string opc, string asm, list<dag> pattern>
1180 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1181 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1182 string opc, string asm, list<dag> pattern>
1183 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1185 let Inst{31-27} = 0b11101;
1186 let Inst{26-25} = 0b00;
1188 let Inst{23} = ?; // The U bit.
1191 let Inst{20} = load;
1194 class T2sI<dag oops, dag iops, InstrItinClass itin,
1195 string opc, string asm, list<dag> pattern>
1196 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1198 class T2XI<dag oops, dag iops, InstrItinClass itin,
1199 string asm, list<dag> pattern>
1200 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1201 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1202 string asm, list<dag> pattern>
1203 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1205 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1206 string opc, string asm, list<dag> pattern>
1207 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1209 // Two-address instructions
1210 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1211 string asm, string cstr, list<dag> pattern>
1212 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1214 // T2Iidxldst - Thumb2 indexed load / store instructions.
1215 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1217 AddrMode am, IndexMode im, InstrItinClass itin,
1218 string opc, string asm, string cstr, list<dag> pattern>
1219 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1220 let OutOperandList = oops;
1221 let InOperandList = !con(iops, (ins pred:$p));
1222 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1223 let Pattern = pattern;
1224 list<Predicate> Predicates = [IsThumb2];
1225 let Inst{31-27} = 0b11111;
1226 let Inst{26-25} = 0b00;
1227 let Inst{24} = signed;
1229 let Inst{22-21} = opcod;
1230 let Inst{20} = load;
1232 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1233 let Inst{10} = pre; // The P bit.
1234 let Inst{8} = 1; // The W bit.
1237 // Helper class for disassembly only
1238 // A6.3.16 & A6.3.17
1239 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1240 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1241 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1242 : T2I<oops, iops, itin, opc, asm, pattern> {
1243 let Inst{31-27} = 0b11111;
1244 let Inst{26-24} = 0b011;
1245 let Inst{23} = long;
1246 let Inst{22-20} = op22_20;
1247 let Inst{7-4} = op7_4;
1250 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1251 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1252 list<Predicate> Predicates = [IsThumb1Only, HasV5T];
1255 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1256 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1257 list<Predicate> Predicates = [IsThumb1Only];
1260 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1261 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1262 list<Predicate> Predicates = [IsThumb2];
1265 //===----------------------------------------------------------------------===//
1267 //===----------------------------------------------------------------------===//
1268 // ARM VFP Instruction templates.
1271 // Almost all VFP instructions are predicable.
1272 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1273 IndexMode im, Format f, InstrItinClass itin,
1274 string opc, string asm, string cstr, list<dag> pattern>
1275 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1276 let OutOperandList = oops;
1277 let InOperandList = !con(iops, (ins pred:$p));
1278 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
1279 let Pattern = pattern;
1280 list<Predicate> Predicates = [HasVFP2];
1284 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1285 IndexMode im, Format f, InstrItinClass itin,
1286 string asm, string cstr, list<dag> pattern>
1287 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1288 let OutOperandList = oops;
1289 let InOperandList = iops;
1290 let AsmString = asm;
1291 let Pattern = pattern;
1292 list<Predicate> Predicates = [HasVFP2];
1295 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1296 string opc, string asm, list<dag> pattern>
1297 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1298 opc, asm, "", pattern>;
1300 // ARM VFP addrmode5 loads and stores
1301 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1302 InstrItinClass itin,
1303 string opc, string asm, list<dag> pattern>
1304 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1305 VFPLdStFrm, itin, opc, asm, "", pattern> {
1306 // TODO: Mark the instructions with the appropriate subtarget info.
1307 let Inst{27-24} = opcod1;
1308 let Inst{21-20} = opcod2;
1309 let Inst{11-8} = 0b1011;
1311 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1312 let Dom = VFPNeonDomain.Value;
1315 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1316 InstrItinClass itin,
1317 string opc, string asm, list<dag> pattern>
1318 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1319 VFPLdStFrm, itin, opc, asm, "", pattern> {
1320 // TODO: Mark the instructions with the appropriate subtarget info.
1321 let Inst{27-24} = opcod1;
1322 let Inst{21-20} = opcod2;
1323 let Inst{11-8} = 0b1010;
1326 // Load / store multiple
1327 class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1328 string asm, string cstr, list<dag> pattern>
1329 : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
1330 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1331 // TODO: Mark the instructions with the appropriate subtarget info.
1332 let Inst{27-25} = 0b110;
1333 let Inst{11-8} = 0b1011;
1335 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1336 let Dom = VFPNeonDomain.Value;
1339 class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1340 string asm, string cstr, list<dag> pattern>
1341 : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
1342 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1343 // TODO: Mark the instructions with the appropriate subtarget info.
1344 let Inst{27-25} = 0b110;
1345 let Inst{11-8} = 0b1010;
1348 // Double precision, unary
1349 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1350 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1351 string asm, list<dag> pattern>
1352 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1353 let Inst{27-23} = opcod1;
1354 let Inst{21-20} = opcod2;
1355 let Inst{19-16} = opcod3;
1356 let Inst{11-8} = 0b1011;
1357 let Inst{7-6} = opcod4;
1358 let Inst{4} = opcod5;
1361 // Double precision, binary
1362 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1363 dag iops, InstrItinClass itin, string opc, string asm,
1365 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1366 let Inst{27-23} = opcod1;
1367 let Inst{21-20} = opcod2;
1368 let Inst{11-8} = 0b1011;
1373 // Single precision, unary
1374 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1375 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1376 string asm, list<dag> pattern>
1377 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1378 let Inst{27-23} = opcod1;
1379 let Inst{21-20} = opcod2;
1380 let Inst{19-16} = opcod3;
1381 let Inst{11-8} = 0b1010;
1382 let Inst{7-6} = opcod4;
1383 let Inst{4} = opcod5;
1386 // Single precision unary, if no NEON
1387 // Same as ASuI except not available if NEON is enabled
1388 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1389 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1390 string asm, list<dag> pattern>
1391 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1393 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1396 // Single precision, binary
1397 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1398 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1399 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1400 let Inst{27-23} = opcod1;
1401 let Inst{21-20} = opcod2;
1402 let Inst{11-8} = 0b1010;
1407 // Single precision binary, if no NEON
1408 // Same as ASbI except not available if NEON is enabled
1409 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1410 dag iops, InstrItinClass itin, string opc, string asm,
1412 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1413 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1416 // VFP conversion instructions
1417 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1418 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1420 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1421 let Inst{27-23} = opcod1;
1422 let Inst{21-20} = opcod2;
1423 let Inst{19-16} = opcod3;
1424 let Inst{11-8} = opcod4;
1429 // VFP conversion between floating-point and fixed-point
1430 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1431 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1433 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1434 // size (fixed-point number): sx == 0 ? 16 : 32
1435 let Inst{7} = op5; // sx
1438 // VFP conversion instructions, if no NEON
1439 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1440 dag oops, dag iops, InstrItinClass itin,
1441 string opc, string asm, list<dag> pattern>
1442 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1444 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1447 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1448 InstrItinClass itin,
1449 string opc, string asm, list<dag> pattern>
1450 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1451 let Inst{27-20} = opcod1;
1452 let Inst{11-8} = opcod2;
1456 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1457 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1458 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1460 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1461 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1462 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1464 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1465 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1466 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1468 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1469 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1470 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1472 //===----------------------------------------------------------------------===//
1474 //===----------------------------------------------------------------------===//
1475 // ARM NEON Instruction templates.
1478 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1479 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1481 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1482 let OutOperandList = oops;
1483 let InOperandList = !con(iops, (ins pred:$p));
1484 let AsmString = !strconcat(
1485 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1486 !strconcat("\t", asm));
1487 let Pattern = pattern;
1488 list<Predicate> Predicates = [HasNEON];
1491 // Same as NeonI except it does not have a "data type" specifier.
1492 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1493 InstrItinClass itin, string opc, string asm, string cstr,
1495 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1496 let OutOperandList = oops;
1497 let InOperandList = !con(iops, (ins pred:$p));
1498 let AsmString = !strconcat(!strconcat(opc, "${p}"), !strconcat("\t", asm));
1499 let Pattern = pattern;
1500 list<Predicate> Predicates = [HasNEON];
1503 class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1505 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, NEONFrm, itin, opc, asm, "",
1509 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1510 dag oops, dag iops, InstrItinClass itin,
1511 string opc, string dt, string asm, string cstr, list<dag> pattern>
1512 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1514 let Inst{31-24} = 0b11110100;
1515 let Inst{23} = op23;
1516 let Inst{21-20} = op21_20;
1517 let Inst{11-8} = op11_8;
1518 let Inst{7-4} = op7_4;
1521 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1522 string opc, string dt, string asm, string cstr, list<dag> pattern>
1523 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1525 let Inst{31-25} = 0b1111001;
1528 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1529 string opc, string asm, string cstr, list<dag> pattern>
1530 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1532 let Inst{31-25} = 0b1111001;
1535 // NEON "one register and a modified immediate" format.
1536 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1538 dag oops, dag iops, InstrItinClass itin,
1539 string opc, string dt, string asm, string cstr,
1541 : NDataI<oops, iops, NVdImmFrm, itin, opc, dt, asm, cstr, pattern> {
1542 let Inst{23} = op23;
1543 let Inst{21-19} = op21_19;
1544 let Inst{11-8} = op11_8;
1551 // NEON 2 vector register format.
1552 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1553 bits<5> op11_7, bit op6, bit op4,
1554 dag oops, dag iops, InstrItinClass itin,
1555 string opc, string dt, string asm, string cstr, list<dag> pattern>
1556 : NDataI<oops, iops, NVdVmImmFrm, itin, opc, dt, asm, cstr, pattern> {
1557 let Inst{24-23} = op24_23;
1558 let Inst{21-20} = op21_20;
1559 let Inst{19-18} = op19_18;
1560 let Inst{17-16} = op17_16;
1561 let Inst{11-7} = op11_7;
1566 // Same as N2V except it doesn't have a datatype suffix.
1567 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1568 bits<5> op11_7, bit op6, bit op4,
1569 dag oops, dag iops, InstrItinClass itin,
1570 string opc, string asm, string cstr, list<dag> pattern>
1571 : NDataXI<oops, iops, NVdVmImmFrm, itin, opc, asm, cstr, pattern> {
1572 let Inst{24-23} = op24_23;
1573 let Inst{21-20} = op21_20;
1574 let Inst{19-18} = op19_18;
1575 let Inst{17-16} = op17_16;
1576 let Inst{11-7} = op11_7;
1581 // NEON 2 vector register with immediate.
1582 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1583 dag oops, dag iops, InstrItinClass itin,
1584 string opc, string dt, string asm, string cstr, list<dag> pattern>
1585 : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
1586 let Inst{24} = op24;
1587 let Inst{23} = op23;
1588 let Inst{11-8} = op11_8;
1594 // NEON 3 vector register format.
1595 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1596 dag oops, dag iops, InstrItinClass itin,
1597 string opc, string dt, string asm, string cstr, list<dag> pattern>
1598 : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
1599 let Inst{24} = op24;
1600 let Inst{23} = op23;
1601 let Inst{21-20} = op21_20;
1602 let Inst{11-8} = op11_8;
1607 // Same as N3V except it doesn't have a data type suffix.
1608 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1610 dag oops, dag iops, InstrItinClass itin,
1611 string opc, string asm, string cstr, list<dag> pattern>
1612 : NDataXI<oops, iops, NEONFrm, itin, opc, asm, cstr, pattern> {
1613 let Inst{24} = op24;
1614 let Inst{23} = op23;
1615 let Inst{21-20} = op21_20;
1616 let Inst{11-8} = op11_8;
1621 // NEON VMOVs between scalar and core registers.
1622 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1623 dag oops, dag iops, Format f, InstrItinClass itin,
1624 string opc, string dt, string asm, list<dag> pattern>
1625 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
1627 let Inst{27-20} = opcod1;
1628 let Inst{11-8} = opcod2;
1629 let Inst{6-5} = opcod3;
1632 let OutOperandList = oops;
1633 let InOperandList = !con(iops, (ins pred:$p));
1634 let AsmString = !strconcat(
1635 !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
1636 !strconcat("\t", asm));
1637 let Pattern = pattern;
1638 list<Predicate> Predicates = [HasNEON];
1640 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1641 dag oops, dag iops, InstrItinClass itin,
1642 string opc, string dt, string asm, list<dag> pattern>
1643 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, itin,
1644 opc, dt, asm, pattern>;
1645 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1646 dag oops, dag iops, InstrItinClass itin,
1647 string opc, string dt, string asm, list<dag> pattern>
1648 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, itin,
1649 opc, dt, asm, pattern>;
1650 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1651 dag oops, dag iops, InstrItinClass itin,
1652 string opc, string dt, string asm, list<dag> pattern>
1653 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, itin,
1654 opc, dt, asm, pattern>;
1656 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1657 // for single-precision FP.
1658 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1659 list<Predicate> Predicates = [HasNEON,UseNEONForFP];