1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // The instruction has an Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
87 // FIXME: Once the JIT is MC-ized, these can go away.
89 class AddrMode<bits<5> val> {
92 def AddrModeNone : AddrMode<0>;
93 def AddrMode1 : AddrMode<1>;
94 def AddrMode2 : AddrMode<2>;
95 def AddrMode3 : AddrMode<3>;
96 def AddrMode4 : AddrMode<4>;
97 def AddrMode5 : AddrMode<5>;
98 def AddrMode6 : AddrMode<6>;
99 def AddrModeT1_1 : AddrMode<7>;
100 def AddrModeT1_2 : AddrMode<8>;
101 def AddrModeT1_4 : AddrMode<9>;
102 def AddrModeT1_s : AddrMode<10>;
103 def AddrModeT2_i12 : AddrMode<11>;
104 def AddrModeT2_i8 : AddrMode<12>;
105 def AddrModeT2_so : AddrMode<13>;
106 def AddrModeT2_pc : AddrMode<14>;
107 def AddrModeT2_i8s4 : AddrMode<15>;
108 def AddrMode_i12 : AddrMode<16>;
111 class SizeFlagVal<bits<3> val> {
114 def SizeInvalid : SizeFlagVal<0>; // Unset.
115 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
116 def Size8Bytes : SizeFlagVal<2>;
117 def Size4Bytes : SizeFlagVal<3>;
118 def Size2Bytes : SizeFlagVal<4>;
120 // Load / store index mode.
121 class IndexMode<bits<2> val> {
124 def IndexModeNone : IndexMode<0>;
125 def IndexModePre : IndexMode<1>;
126 def IndexModePost : IndexMode<2>;
127 def IndexModeUpd : IndexMode<3>;
129 // Instruction execution domain.
130 class Domain<bits<3> val> {
133 def GenericDomain : Domain<0>;
134 def VFPDomain : Domain<1>; // Instructions in VFP domain only
135 def NeonDomain : Domain<2>; // Instructions in Neon domain only
136 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
139 //===----------------------------------------------------------------------===//
140 // ARM special operands.
143 def CondCodeOperand : AsmOperandClass {
144 let Name = "CondCode";
145 let SuperClasses = [];
148 def CCOutOperand : AsmOperandClass {
150 let SuperClasses = [];
153 def MemBarrierOptOperand : AsmOperandClass {
154 let Name = "MemBarrierOpt";
155 let SuperClasses = [];
156 let ParserMethod = "tryParseMemBarrierOptOperand";
159 def ProcIFlagsOperand : AsmOperandClass {
160 let Name = "ProcIFlags";
161 let SuperClasses = [];
162 let ParserMethod = "tryParseProcIFlagsOperand";
165 def MSRMaskOperand : AsmOperandClass {
166 let Name = "MSRMask";
167 let SuperClasses = [];
168 let ParserMethod = "tryParseMSRMaskOperand";
171 // ARM imod and iflag operands, used only by the CPS instruction.
172 def imod_op : Operand<i32> {
173 let PrintMethod = "printCPSIMod";
176 def iflags_op : Operand<i32> {
177 let PrintMethod = "printCPSIFlag";
178 let ParserMatchClass = ProcIFlagsOperand;
181 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
182 // register whose default is 0 (no register).
183 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
184 (ops (i32 14), (i32 zero_reg))> {
185 let PrintMethod = "printPredicateOperand";
186 let ParserMatchClass = CondCodeOperand;
189 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
190 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
191 let EncoderMethod = "getCCOutOpValue";
192 let PrintMethod = "printSBitModifierOperand";
193 let ParserMatchClass = CCOutOperand;
196 // Same as cc_out except it defaults to setting CPSR.
197 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
198 let EncoderMethod = "getCCOutOpValue";
199 let PrintMethod = "printSBitModifierOperand";
200 let ParserMatchClass = CCOutOperand;
203 // ARM special operands for disassembly only.
205 def setend_op : Operand<i32> {
206 let PrintMethod = "printSetendOperand";
209 def msr_mask : Operand<i32> {
210 let PrintMethod = "printMSRMaskOperand";
211 let ParserMatchClass = MSRMaskOperand;
214 // Shift Right Immediate - A shift right immediate is encoded differently from
215 // other shift immediates. The imm6 field is encoded like so:
218 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
219 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
220 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
221 // 64 64 - <imm> is encoded in imm6<5:0>
222 def shr_imm8 : Operand<i32> {
223 let EncoderMethod = "getShiftRight8Imm";
225 def shr_imm16 : Operand<i32> {
226 let EncoderMethod = "getShiftRight16Imm";
228 def shr_imm32 : Operand<i32> {
229 let EncoderMethod = "getShiftRight32Imm";
231 def shr_imm64 : Operand<i32> {
232 let EncoderMethod = "getShiftRight64Imm";
235 //===----------------------------------------------------------------------===//
236 // ARM Instruction templates.
239 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
240 Format f, Domain d, string cstr, InstrItinClass itin>
242 let Namespace = "ARM";
247 bits<2> IndexModeBits = IM.Value;
249 bits<6> Form = F.Value;
251 bit isUnaryDataProc = 0;
252 bit canXformTo16Bit = 0;
254 // If this is a pseudo instruction, mark it isCodeGenOnly.
255 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
257 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
258 let TSFlags{4-0} = AM.Value;
259 let TSFlags{7-5} = SZ.Value;
260 let TSFlags{9-8} = IndexModeBits;
261 let TSFlags{15-10} = Form;
262 let TSFlags{16} = isUnaryDataProc;
263 let TSFlags{17} = canXformTo16Bit;
264 let TSFlags{20-18} = D.Value;
266 let Constraints = cstr;
267 let Itinerary = itin;
274 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
275 Format f, Domain d, string cstr, InstrItinClass itin>
276 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
278 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
279 // on by adding flavors to specific instructions.
280 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
281 Format f, Domain d, string cstr, InstrItinClass itin>
282 : InstTemplate<am, sz, im, f, d, cstr, itin>;
284 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
285 // FIXME: This really should derive from InstTemplate instead, as pseudos
286 // don't need encoding information. TableGen doesn't like that
287 // currently. Need to figure out why and fix it.
288 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
290 let OutOperandList = oops;
291 let InOperandList = iops;
292 let Pattern = pattern;
293 let isCodeGenOnly = 1;
296 // PseudoInst that's ARM-mode only.
297 class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
299 : PseudoInst<oops, iops, itin, pattern> {
301 list<Predicate> Predicates = [IsARM];
304 // PseudoInst that's Thumb-mode only.
305 class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
307 : PseudoInst<oops, iops, itin, pattern> {
309 list<Predicate> Predicates = [IsThumb];
312 // PseudoInst that's Thumb2-mode only.
313 class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
315 : PseudoInst<oops, iops, itin, pattern> {
317 list<Predicate> Predicates = [IsThumb2];
319 // Almost all ARM instructions are predicable.
320 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
321 IndexMode im, Format f, InstrItinClass itin,
322 string opc, string asm, string cstr,
324 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
327 let OutOperandList = oops;
328 let InOperandList = !con(iops, (ins pred:$p));
329 let AsmString = !strconcat(opc, "${p}", asm);
330 let Pattern = pattern;
331 list<Predicate> Predicates = [IsARM];
334 // A few are not predicable
335 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
336 IndexMode im, Format f, InstrItinClass itin,
337 string opc, string asm, string cstr,
339 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
340 let OutOperandList = oops;
341 let InOperandList = iops;
342 let AsmString = !strconcat(opc, asm);
343 let Pattern = pattern;
344 let isPredicable = 0;
345 list<Predicate> Predicates = [IsARM];
348 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
349 // operand since by default it's a zero register. It will become an implicit def
350 // once it's "flipped".
351 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
352 IndexMode im, Format f, InstrItinClass itin,
353 string opc, string asm, string cstr,
355 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
356 bits<4> p; // Predicate operand
357 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
361 let OutOperandList = oops;
362 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
363 let AsmString = !strconcat(opc, "${s}${p}", asm);
364 let Pattern = pattern;
365 list<Predicate> Predicates = [IsARM];
369 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
370 IndexMode im, Format f, InstrItinClass itin,
371 string asm, string cstr, list<dag> pattern>
372 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
373 let OutOperandList = oops;
374 let InOperandList = iops;
376 let Pattern = pattern;
377 list<Predicate> Predicates = [IsARM];
380 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
381 string opc, string asm, list<dag> pattern>
382 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
383 opc, asm, "", pattern>;
384 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
385 string opc, string asm, list<dag> pattern>
386 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
387 opc, asm, "", pattern>;
388 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
389 string asm, list<dag> pattern>
390 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
392 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
393 string opc, string asm, list<dag> pattern>
394 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
395 opc, asm, "", pattern>;
397 // Ctrl flow instructions
398 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
401 opc, asm, "", pattern> {
402 let Inst{27-24} = opcod;
404 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
405 string asm, list<dag> pattern>
406 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
408 let Inst{27-24} = opcod;
411 // BR_JT instructions
412 class JTI<dag oops, dag iops, InstrItinClass itin,
413 string asm, list<dag> pattern>
414 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
417 // Atomic load/store instructions
418 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
419 string opc, string asm, list<dag> pattern>
420 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
421 opc, asm, "", pattern> {
424 let Inst{27-23} = 0b00011;
425 let Inst{22-21} = opcod;
427 let Inst{19-16} = Rn;
428 let Inst{15-12} = Rt;
429 let Inst{11-0} = 0b111110011111;
431 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
432 string opc, string asm, list<dag> pattern>
433 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
434 opc, asm, "", pattern> {
438 let Inst{27-23} = 0b00011;
439 let Inst{22-21} = opcod;
441 let Inst{19-16} = addr;
442 let Inst{15-12} = Rd;
443 let Inst{11-4} = 0b11111001;
446 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
447 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
451 let Inst{27-23} = 0b00010;
453 let Inst{21-20} = 0b00;
454 let Inst{19-16} = Rn;
455 let Inst{15-12} = Rt;
456 let Inst{11-4} = 0b00001001;
460 // addrmode1 instructions
461 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
462 string opc, string asm, list<dag> pattern>
463 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
464 opc, asm, "", pattern> {
465 let Inst{24-21} = opcod;
466 let Inst{27-26} = 0b00;
468 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
469 string opc, string asm, list<dag> pattern>
470 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
471 opc, asm, "", pattern> {
472 let Inst{24-21} = opcod;
473 let Inst{27-26} = 0b00;
475 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
476 string asm, list<dag> pattern>
477 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
479 let Inst{24-21} = opcod;
480 let Inst{27-26} = 0b00;
485 // LDR/LDRB/STR/STRB/...
486 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
487 Format f, InstrItinClass itin, string opc, string asm,
489 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
491 let Inst{27-25} = op;
492 let Inst{24} = 1; // 24 == P
494 let Inst{22} = isByte;
495 let Inst{21} = 0; // 21 == W
498 // Indexed load/stores
499 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
500 IndexMode im, Format f, InstrItinClass itin, string opc,
501 string asm, string cstr, list<dag> pattern>
502 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
503 opc, asm, cstr, pattern> {
505 let Inst{27-26} = 0b01;
506 let Inst{24} = isPre; // P bit
507 let Inst{22} = isByte; // B bit
508 let Inst{21} = isPre; // W bit
509 let Inst{20} = isLd; // L bit
510 let Inst{15-12} = Rt;
512 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
513 IndexMode im, Format f, InstrItinClass itin, string opc,
514 string asm, string cstr, list<dag> pattern>
515 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
517 // AM2 store w/ two operands: (GPR, am2offset)
518 // {13} 1 == Rm, 0 == imm12
523 let Inst{25} = offset{13};
524 let Inst{23} = offset{12};
525 let Inst{19-16} = Rn;
526 let Inst{11-0} = offset{11-0};
529 // addrmode3 instructions
530 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
531 InstrItinClass itin, string opc, string asm, list<dag> pattern>
532 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
533 opc, asm, "", pattern> {
536 let Inst{27-25} = 0b000;
537 let Inst{24} = 1; // P bit
538 let Inst{23} = addr{8}; // U bit
539 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
540 let Inst{21} = 0; // W bit
541 let Inst{20} = op20; // L bit
542 let Inst{19-16} = addr{12-9}; // Rn
543 let Inst{15-12} = Rt; // Rt
544 let Inst{11-8} = addr{7-4}; // imm7_4/zero
546 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
549 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
550 IndexMode im, Format f, InstrItinClass itin, string opc,
551 string asm, string cstr, list<dag> pattern>
552 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
553 opc, asm, cstr, pattern> {
555 let Inst{27-25} = 0b000;
556 let Inst{24} = isPre; // P bit
557 let Inst{21} = isPre; // W bit
558 let Inst{20} = op20; // L bit
559 let Inst{15-12} = Rt; // Rt
562 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
563 IndexMode im, Format f, InstrItinClass itin, string opc,
564 string asm, string cstr, list<dag> pattern>
565 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
567 // AM3 store w/ two operands: (GPR, am3offset)
571 let Inst{27-25} = 0b000;
572 let Inst{23} = offset{8};
573 let Inst{22} = offset{9};
574 let Inst{19-16} = Rn;
575 let Inst{15-12} = Rt; // Rt
576 let Inst{11-8} = offset{7-4}; // imm7_4/zero
578 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
582 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
583 string opc, string asm, list<dag> pattern>
584 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
585 opc, asm, "", pattern> {
588 let Inst{27-25} = 0b000;
589 let Inst{24} = 1; // P bit
590 let Inst{23} = addr{8}; // U bit
591 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
592 let Inst{21} = 0; // W bit
593 let Inst{20} = 0; // L bit
594 let Inst{19-16} = addr{12-9}; // Rn
595 let Inst{15-12} = Rt; // Rt
596 let Inst{11-8} = addr{7-4}; // imm7_4/zero
598 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
601 // Pre-indexed stores
602 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
603 string opc, string asm, string cstr, list<dag> pattern>
604 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
605 opc, asm, cstr, pattern> {
607 let Inst{5} = 1; // H bit
608 let Inst{6} = 0; // S bit
610 let Inst{20} = 0; // L bit
611 let Inst{21} = 1; // W bit
612 let Inst{24} = 1; // P bit
613 let Inst{27-25} = 0b000;
615 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
616 string opc, string asm, string cstr, list<dag> pattern>
617 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
618 opc, asm, cstr, pattern> {
620 let Inst{5} = 1; // H bit
621 let Inst{6} = 1; // S bit
623 let Inst{20} = 0; // L bit
624 let Inst{21} = 1; // W bit
625 let Inst{24} = 1; // P bit
626 let Inst{27-25} = 0b000;
629 // Post-indexed stores
630 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
631 string opc, string asm, string cstr, list<dag> pattern>
632 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
633 opc, asm, cstr,pattern> {
635 let Inst{5} = 1; // H bit
636 let Inst{6} = 0; // S bit
638 let Inst{20} = 0; // L bit
639 let Inst{21} = 0; // W bit
640 let Inst{24} = 0; // P bit
641 let Inst{27-25} = 0b000;
643 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
644 string opc, string asm, string cstr, list<dag> pattern>
645 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
646 opc, asm, cstr, pattern> {
648 let Inst{5} = 1; // H bit
649 let Inst{6} = 1; // S bit
651 let Inst{20} = 0; // L bit
652 let Inst{21} = 0; // W bit
653 let Inst{24} = 0; // P bit
654 let Inst{27-25} = 0b000;
657 // addrmode4 instructions
658 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
659 string asm, string cstr, list<dag> pattern>
660 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
665 let Inst{27-25} = 0b100;
666 let Inst{22} = 0; // S bit
667 let Inst{19-16} = Rn;
668 let Inst{15-0} = regs;
671 // Unsigned multiply, multiply-accumulate instructions.
672 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
673 string opc, string asm, list<dag> pattern>
674 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
675 opc, asm, "", pattern> {
676 let Inst{7-4} = 0b1001;
677 let Inst{20} = 0; // S bit
678 let Inst{27-21} = opcod;
680 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
681 string opc, string asm, list<dag> pattern>
682 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
683 opc, asm, "", pattern> {
684 let Inst{7-4} = 0b1001;
685 let Inst{27-21} = opcod;
688 // Most significant word multiply
689 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
690 InstrItinClass itin, string opc, string asm, list<dag> pattern>
691 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
692 opc, asm, "", pattern> {
696 let Inst{7-4} = opc7_4;
698 let Inst{27-21} = opcod;
699 let Inst{19-16} = Rd;
703 // MSW multiple w/ Ra operand
704 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
705 InstrItinClass itin, string opc, string asm, list<dag> pattern>
706 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
708 let Inst{15-12} = Ra;
711 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
712 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
713 InstrItinClass itin, string opc, string asm, list<dag> pattern>
714 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
715 opc, asm, "", pattern> {
721 let Inst{27-21} = opcod;
722 let Inst{6-5} = bit6_5;
726 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
727 InstrItinClass itin, string opc, string asm, list<dag> pattern>
728 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
730 let Inst{19-16} = Rd;
733 // AMulxyI with Ra operand
734 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
735 InstrItinClass itin, string opc, string asm, list<dag> pattern>
736 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
738 let Inst{15-12} = Ra;
741 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
742 InstrItinClass itin, string opc, string asm, list<dag> pattern>
743 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
746 let Inst{19-16} = RdHi;
747 let Inst{15-12} = RdLo;
750 // Extend instructions.
751 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
752 string opc, string asm, list<dag> pattern>
753 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
754 opc, asm, "", pattern> {
755 // All AExtI instructions have Rd and Rm register operands.
758 let Inst{15-12} = Rd;
760 let Inst{7-4} = 0b0111;
761 let Inst{9-8} = 0b00;
762 let Inst{27-20} = opcod;
765 // Misc Arithmetic instructions.
766 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
767 InstrItinClass itin, string opc, string asm, list<dag> pattern>
768 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
769 opc, asm, "", pattern> {
772 let Inst{27-20} = opcod;
773 let Inst{19-16} = 0b1111;
774 let Inst{15-12} = Rd;
775 let Inst{11-8} = 0b1111;
776 let Inst{7-4} = opc7_4;
781 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
782 string opc, string asm, list<dag> pattern>
783 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
784 opc, asm, "", pattern> {
789 let Inst{27-20} = opcod;
790 let Inst{19-16} = Rn;
791 let Inst{15-12} = Rd;
792 let Inst{11-7} = sh{7-3};
794 let Inst{5-4} = 0b01;
798 //===----------------------------------------------------------------------===//
800 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
801 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
802 list<Predicate> Predicates = [IsARM];
804 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
805 list<Predicate> Predicates = [IsARM, HasV5TE];
807 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
808 list<Predicate> Predicates = [IsARM, HasV6];
811 //===----------------------------------------------------------------------===//
812 // Thumb Instruction Format Definitions.
815 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
816 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
817 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
818 let OutOperandList = oops;
819 let InOperandList = iops;
821 let Pattern = pattern;
822 list<Predicate> Predicates = [IsThumb];
825 // TI - Thumb instruction.
826 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
827 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
829 // Two-address instructions
830 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
832 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
835 // tBL, tBX 32-bit instructions
836 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
837 dag oops, dag iops, InstrItinClass itin, string asm,
839 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
841 let Inst{31-27} = opcod1;
842 let Inst{15-14} = opcod2;
843 let Inst{12} = opcod3;
846 // Move to/from coprocessor instructions
847 class T1Cop<dag oops, dag iops, string asm, list<dag> pattern>
848 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>,
849 Encoding, Requires<[IsThumb, HasV6]> {
850 let Inst{31-28} = 0b1110;
853 // BR_JT instructions
854 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
856 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
859 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
860 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
861 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
862 let OutOperandList = oops;
863 let InOperandList = iops;
865 let Pattern = pattern;
866 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
869 class T1I<dag oops, dag iops, InstrItinClass itin,
870 string asm, list<dag> pattern>
871 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
872 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
873 string asm, list<dag> pattern>
874 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
876 // Two-address instructions
877 class T1It<dag oops, dag iops, InstrItinClass itin,
878 string asm, string cstr, list<dag> pattern>
879 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
882 // Thumb1 instruction that can either be predicated or set CPSR.
883 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
885 string opc, string asm, string cstr, list<dag> pattern>
886 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
887 let OutOperandList = !con(oops, (outs s_cc_out:$s));
888 let InOperandList = !con(iops, (ins pred:$p));
889 let AsmString = !strconcat(opc, "${s}${p}", asm);
890 let Pattern = pattern;
891 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
894 class T1sI<dag oops, dag iops, InstrItinClass itin,
895 string opc, string asm, list<dag> pattern>
896 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
898 // Two-address instructions
899 class T1sIt<dag oops, dag iops, InstrItinClass itin,
900 string opc, string asm, list<dag> pattern>
901 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
902 "$Rn = $Rdn", pattern>;
904 // Thumb1 instruction that can be predicated.
905 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
907 string opc, string asm, string cstr, list<dag> pattern>
908 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
909 let OutOperandList = oops;
910 let InOperandList = !con(iops, (ins pred:$p));
911 let AsmString = !strconcat(opc, "${p}", asm);
912 let Pattern = pattern;
913 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
916 class T1pI<dag oops, dag iops, InstrItinClass itin,
917 string opc, string asm, list<dag> pattern>
918 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
920 // Two-address instructions
921 class T1pIt<dag oops, dag iops, InstrItinClass itin,
922 string opc, string asm, list<dag> pattern>
923 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
924 "$Rn = $Rdn", pattern>;
926 class T1pIs<dag oops, dag iops,
927 InstrItinClass itin, string opc, string asm, list<dag> pattern>
928 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
930 class Encoding16 : Encoding {
931 let Inst{31-16} = 0x0000;
934 // A6.2 16-bit Thumb instruction encoding
935 class T1Encoding<bits<6> opcode> : Encoding16 {
936 let Inst{15-10} = opcode;
939 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
940 class T1General<bits<5> opcode> : Encoding16 {
941 let Inst{15-14} = 0b00;
942 let Inst{13-9} = opcode;
945 // A6.2.2 Data-processing encoding.
946 class T1DataProcessing<bits<4> opcode> : Encoding16 {
947 let Inst{15-10} = 0b010000;
948 let Inst{9-6} = opcode;
951 // A6.2.3 Special data instructions and branch and exchange encoding.
952 class T1Special<bits<4> opcode> : Encoding16 {
953 let Inst{15-10} = 0b010001;
954 let Inst{9-6} = opcode;
957 // A6.2.4 Load/store single data item encoding.
958 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
959 let Inst{15-12} = opA;
960 let Inst{11-9} = opB;
962 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
964 // Helper classes to encode Thumb1 loads and stores. For immediates, the
965 // following bits are used for "opA" (see A6.2.4):
967 // 0b0110 => Immediate, 4 bytes
968 // 0b1000 => Immediate, 2 bytes
969 // 0b0111 => Immediate, 1 byte
970 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
971 InstrItinClass itin, string opc, string asm,
973 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
974 T1LoadStore<0b0101, opcode> {
977 let Inst{8-6} = addr{5-3}; // Rm
978 let Inst{5-3} = addr{2-0}; // Rn
981 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
982 InstrItinClass itin, string opc, string asm,
984 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
985 T1LoadStore<opA, {opB,?,?}> {
988 let Inst{10-6} = addr{7-3}; // imm5
989 let Inst{5-3} = addr{2-0}; // Rn
993 // A6.2.5 Miscellaneous 16-bit instructions encoding.
994 class T1Misc<bits<7> opcode> : Encoding16 {
995 let Inst{15-12} = 0b1011;
996 let Inst{11-5} = opcode;
999 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1000 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1001 InstrItinClass itin,
1002 string opc, string asm, string cstr, list<dag> pattern>
1003 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1004 let OutOperandList = oops;
1005 let InOperandList = !con(iops, (ins pred:$p));
1006 let AsmString = !strconcat(opc, "${p}", asm);
1007 let Pattern = pattern;
1008 list<Predicate> Predicates = [IsThumb2];
1011 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1012 // input operand since by default it's a zero register. It will become an
1013 // implicit def once it's "flipped".
1015 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1017 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1018 InstrItinClass itin,
1019 string opc, string asm, string cstr, list<dag> pattern>
1020 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1021 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1024 let OutOperandList = oops;
1025 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1026 let AsmString = !strconcat(opc, "${s}${p}", asm);
1027 let Pattern = pattern;
1028 list<Predicate> Predicates = [IsThumb2];
1032 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1033 InstrItinClass itin,
1034 string asm, string cstr, list<dag> pattern>
1035 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1036 let OutOperandList = oops;
1037 let InOperandList = iops;
1038 let AsmString = asm;
1039 let Pattern = pattern;
1040 list<Predicate> Predicates = [IsThumb2];
1043 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1044 InstrItinClass itin,
1045 string asm, string cstr, list<dag> pattern>
1046 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1047 let OutOperandList = oops;
1048 let InOperandList = iops;
1049 let AsmString = asm;
1050 let Pattern = pattern;
1051 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1054 class T2I<dag oops, dag iops, InstrItinClass itin,
1055 string opc, string asm, list<dag> pattern>
1056 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1057 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1058 string opc, string asm, list<dag> pattern>
1059 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1060 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1061 string opc, string asm, list<dag> pattern>
1062 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1063 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1064 string opc, string asm, list<dag> pattern>
1065 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1066 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1067 string opc, string asm, list<dag> pattern>
1068 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1069 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1070 string opc, string asm, list<dag> pattern>
1071 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1076 let Inst{31-25} = 0b1110100;
1078 let Inst{23} = addr{8};
1081 let Inst{20} = isLoad;
1082 let Inst{19-16} = addr{12-9};
1083 let Inst{15-12} = Rt{3-0};
1084 let Inst{11-8} = Rt2{3-0};
1085 let Inst{7-0} = addr{7-0};
1088 class T2sI<dag oops, dag iops, InstrItinClass itin,
1089 string opc, string asm, list<dag> pattern>
1090 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1092 class T2XI<dag oops, dag iops, InstrItinClass itin,
1093 string asm, list<dag> pattern>
1094 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1095 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1096 string asm, list<dag> pattern>
1097 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1099 // Move to/from coprocessor instructions
1100 class T2Cop<dag oops, dag iops, string asm, list<dag> pattern>
1101 : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> {
1102 let Inst{31-28} = 0b1111;
1105 // Two-address instructions
1106 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1107 string asm, string cstr, list<dag> pattern>
1108 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1110 // T2Iidxldst - Thumb2 indexed load / store instructions.
1111 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1113 AddrMode am, IndexMode im, InstrItinClass itin,
1114 string opc, string asm, string cstr, list<dag> pattern>
1115 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1116 let OutOperandList = oops;
1117 let InOperandList = !con(iops, (ins pred:$p));
1118 let AsmString = !strconcat(opc, "${p}", asm);
1119 let Pattern = pattern;
1120 list<Predicate> Predicates = [IsThumb2];
1121 let Inst{31-27} = 0b11111;
1122 let Inst{26-25} = 0b00;
1123 let Inst{24} = signed;
1125 let Inst{22-21} = opcod;
1126 let Inst{20} = load;
1128 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1129 let Inst{10} = pre; // The P bit.
1130 let Inst{8} = 1; // The W bit.
1133 let Inst{7-0} = addr{7-0};
1134 let Inst{9} = addr{8}; // Sign bit
1138 let Inst{15-12} = Rt{3-0};
1139 let Inst{19-16} = Rn{3-0};
1142 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1143 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1144 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1147 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1148 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1149 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1152 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1153 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1154 list<Predicate> Predicates = [IsThumb2];
1157 //===----------------------------------------------------------------------===//
1159 //===----------------------------------------------------------------------===//
1160 // ARM VFP Instruction templates.
1163 // Almost all VFP instructions are predicable.
1164 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1165 IndexMode im, Format f, InstrItinClass itin,
1166 string opc, string asm, string cstr, list<dag> pattern>
1167 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1169 let Inst{31-28} = p;
1170 let OutOperandList = oops;
1171 let InOperandList = !con(iops, (ins pred:$p));
1172 let AsmString = !strconcat(opc, "${p}", asm);
1173 let Pattern = pattern;
1174 let PostEncoderMethod = "VFPThumb2PostEncoder";
1175 list<Predicate> Predicates = [HasVFP2];
1179 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1180 IndexMode im, Format f, InstrItinClass itin,
1181 string asm, string cstr, list<dag> pattern>
1182 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1184 let Inst{31-28} = p;
1185 let OutOperandList = oops;
1186 let InOperandList = iops;
1187 let AsmString = asm;
1188 let Pattern = pattern;
1189 let PostEncoderMethod = "VFPThumb2PostEncoder";
1190 list<Predicate> Predicates = [HasVFP2];
1193 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1194 string opc, string asm, list<dag> pattern>
1195 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1196 opc, asm, "", pattern> {
1197 let PostEncoderMethod = "VFPThumb2PostEncoder";
1200 // ARM VFP addrmode5 loads and stores
1201 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1202 InstrItinClass itin,
1203 string opc, string asm, list<dag> pattern>
1204 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1205 VFPLdStFrm, itin, opc, asm, "", pattern> {
1206 // Instruction operands.
1210 // Encode instruction operands.
1211 let Inst{23} = addr{8}; // U (add = (U == '1'))
1212 let Inst{22} = Dd{4};
1213 let Inst{19-16} = addr{12-9}; // Rn
1214 let Inst{15-12} = Dd{3-0};
1215 let Inst{7-0} = addr{7-0}; // imm8
1217 // TODO: Mark the instructions with the appropriate subtarget info.
1218 let Inst{27-24} = opcod1;
1219 let Inst{21-20} = opcod2;
1220 let Inst{11-9} = 0b101;
1221 let Inst{8} = 1; // Double precision
1223 // Loads & stores operate on both NEON and VFP pipelines.
1224 let D = VFPNeonDomain;
1227 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1228 InstrItinClass itin,
1229 string opc, string asm, list<dag> pattern>
1230 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1231 VFPLdStFrm, itin, opc, asm, "", pattern> {
1232 // Instruction operands.
1236 // Encode instruction operands.
1237 let Inst{23} = addr{8}; // U (add = (U == '1'))
1238 let Inst{22} = Sd{0};
1239 let Inst{19-16} = addr{12-9}; // Rn
1240 let Inst{15-12} = Sd{4-1};
1241 let Inst{7-0} = addr{7-0}; // imm8
1243 // TODO: Mark the instructions with the appropriate subtarget info.
1244 let Inst{27-24} = opcod1;
1245 let Inst{21-20} = opcod2;
1246 let Inst{11-9} = 0b101;
1247 let Inst{8} = 0; // Single precision
1249 // Loads & stores operate on both NEON and VFP pipelines.
1250 let D = VFPNeonDomain;
1253 // VFP Load / store multiple pseudo instructions.
1254 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1256 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1258 let OutOperandList = oops;
1259 let InOperandList = !con(iops, (ins pred:$p));
1260 let Pattern = pattern;
1261 list<Predicate> Predicates = [HasVFP2];
1264 // Load / store multiple
1265 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1266 string asm, string cstr, list<dag> pattern>
1267 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1268 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1269 // Instruction operands.
1273 // Encode instruction operands.
1274 let Inst{19-16} = Rn;
1275 let Inst{22} = regs{12};
1276 let Inst{15-12} = regs{11-8};
1277 let Inst{7-0} = regs{7-0};
1279 // TODO: Mark the instructions with the appropriate subtarget info.
1280 let Inst{27-25} = 0b110;
1281 let Inst{11-9} = 0b101;
1282 let Inst{8} = 1; // Double precision
1285 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1286 string asm, string cstr, list<dag> pattern>
1287 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1288 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1289 // Instruction operands.
1293 // Encode instruction operands.
1294 let Inst{19-16} = Rn;
1295 let Inst{22} = regs{8};
1296 let Inst{15-12} = regs{12-9};
1297 let Inst{7-0} = regs{7-0};
1299 // TODO: Mark the instructions with the appropriate subtarget info.
1300 let Inst{27-25} = 0b110;
1301 let Inst{11-9} = 0b101;
1302 let Inst{8} = 0; // Single precision
1305 // Double precision, unary
1306 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1307 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1308 string asm, list<dag> pattern>
1309 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1310 // Instruction operands.
1314 // Encode instruction operands.
1315 let Inst{3-0} = Dm{3-0};
1316 let Inst{5} = Dm{4};
1317 let Inst{15-12} = Dd{3-0};
1318 let Inst{22} = Dd{4};
1320 let Inst{27-23} = opcod1;
1321 let Inst{21-20} = opcod2;
1322 let Inst{19-16} = opcod3;
1323 let Inst{11-9} = 0b101;
1324 let Inst{8} = 1; // Double precision
1325 let Inst{7-6} = opcod4;
1326 let Inst{4} = opcod5;
1329 // Double precision, binary
1330 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1331 dag iops, InstrItinClass itin, string opc, string asm,
1333 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1334 // Instruction operands.
1339 // Encode instruction operands.
1340 let Inst{3-0} = Dm{3-0};
1341 let Inst{5} = Dm{4};
1342 let Inst{19-16} = Dn{3-0};
1343 let Inst{7} = Dn{4};
1344 let Inst{15-12} = Dd{3-0};
1345 let Inst{22} = Dd{4};
1347 let Inst{27-23} = opcod1;
1348 let Inst{21-20} = opcod2;
1349 let Inst{11-9} = 0b101;
1350 let Inst{8} = 1; // Double precision
1355 // Single precision, unary
1356 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1357 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1358 string asm, list<dag> pattern>
1359 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1360 // Instruction operands.
1364 // Encode instruction operands.
1365 let Inst{3-0} = Sm{4-1};
1366 let Inst{5} = Sm{0};
1367 let Inst{15-12} = Sd{4-1};
1368 let Inst{22} = Sd{0};
1370 let Inst{27-23} = opcod1;
1371 let Inst{21-20} = opcod2;
1372 let Inst{19-16} = opcod3;
1373 let Inst{11-9} = 0b101;
1374 let Inst{8} = 0; // Single precision
1375 let Inst{7-6} = opcod4;
1376 let Inst{4} = opcod5;
1379 // Single precision unary, if no NEON. Same as ASuI except not available if
1381 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1382 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1383 string asm, list<dag> pattern>
1384 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1386 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1389 // Single precision, binary
1390 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1391 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1392 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1393 // Instruction operands.
1398 // Encode instruction operands.
1399 let Inst{3-0} = Sm{4-1};
1400 let Inst{5} = Sm{0};
1401 let Inst{19-16} = Sn{4-1};
1402 let Inst{7} = Sn{0};
1403 let Inst{15-12} = Sd{4-1};
1404 let Inst{22} = Sd{0};
1406 let Inst{27-23} = opcod1;
1407 let Inst{21-20} = opcod2;
1408 let Inst{11-9} = 0b101;
1409 let Inst{8} = 0; // Single precision
1414 // Single precision binary, if no NEON. Same as ASbI except not available if
1416 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1417 dag iops, InstrItinClass itin, string opc, string asm,
1419 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1420 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1422 // Instruction operands.
1427 // Encode instruction operands.
1428 let Inst{3-0} = Sm{4-1};
1429 let Inst{5} = Sm{0};
1430 let Inst{19-16} = Sn{4-1};
1431 let Inst{7} = Sn{0};
1432 let Inst{15-12} = Sd{4-1};
1433 let Inst{22} = Sd{0};
1436 // VFP conversion instructions
1437 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1438 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1440 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1441 let Inst{27-23} = opcod1;
1442 let Inst{21-20} = opcod2;
1443 let Inst{19-16} = opcod3;
1444 let Inst{11-8} = opcod4;
1449 // VFP conversion between floating-point and fixed-point
1450 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1451 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1453 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1454 // size (fixed-point number): sx == 0 ? 16 : 32
1455 let Inst{7} = op5; // sx
1458 // VFP conversion instructions, if no NEON
1459 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1460 dag oops, dag iops, InstrItinClass itin,
1461 string opc, string asm, list<dag> pattern>
1462 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1464 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1467 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1468 InstrItinClass itin,
1469 string opc, string asm, list<dag> pattern>
1470 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1471 let Inst{27-20} = opcod1;
1472 let Inst{11-8} = opcod2;
1476 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1477 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1478 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1480 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1481 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1482 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1484 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1485 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1486 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1488 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1489 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1490 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1492 //===----------------------------------------------------------------------===//
1494 //===----------------------------------------------------------------------===//
1495 // ARM NEON Instruction templates.
1498 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1499 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1501 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1502 let OutOperandList = oops;
1503 let InOperandList = !con(iops, (ins pred:$p));
1504 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1505 let Pattern = pattern;
1506 list<Predicate> Predicates = [HasNEON];
1509 // Same as NeonI except it does not have a "data type" specifier.
1510 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1511 InstrItinClass itin, string opc, string asm, string cstr,
1513 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1514 let OutOperandList = oops;
1515 let InOperandList = !con(iops, (ins pred:$p));
1516 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1517 let Pattern = pattern;
1518 list<Predicate> Predicates = [HasNEON];
1521 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1522 dag oops, dag iops, InstrItinClass itin,
1523 string opc, string dt, string asm, string cstr, list<dag> pattern>
1524 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1526 let Inst{31-24} = 0b11110100;
1527 let Inst{23} = op23;
1528 let Inst{21-20} = op21_20;
1529 let Inst{11-8} = op11_8;
1530 let Inst{7-4} = op7_4;
1532 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1538 let Inst{22} = Vd{4};
1539 let Inst{15-12} = Vd{3-0};
1540 let Inst{19-16} = Rn{3-0};
1541 let Inst{3-0} = Rm{3-0};
1544 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1545 dag oops, dag iops, InstrItinClass itin,
1546 string opc, string dt, string asm, string cstr, list<dag> pattern>
1547 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1548 dt, asm, cstr, pattern> {
1552 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1553 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1555 let OutOperandList = oops;
1556 let InOperandList = !con(iops, (ins pred:$p));
1557 list<Predicate> Predicates = [HasNEON];
1560 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1562 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1564 let OutOperandList = oops;
1565 let InOperandList = !con(iops, (ins pred:$p));
1566 let Pattern = pattern;
1567 list<Predicate> Predicates = [HasNEON];
1570 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1571 string opc, string dt, string asm, string cstr, list<dag> pattern>
1572 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1574 let Inst{31-25} = 0b1111001;
1575 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1578 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1579 string opc, string asm, string cstr, list<dag> pattern>
1580 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1582 let Inst{31-25} = 0b1111001;
1583 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1586 // NEON "one register and a modified immediate" format.
1587 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1589 dag oops, dag iops, InstrItinClass itin,
1590 string opc, string dt, string asm, string cstr,
1592 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1593 let Inst{23} = op23;
1594 let Inst{21-19} = op21_19;
1595 let Inst{11-8} = op11_8;
1601 // Instruction operands.
1605 let Inst{15-12} = Vd{3-0};
1606 let Inst{22} = Vd{4};
1607 let Inst{24} = SIMM{7};
1608 let Inst{18-16} = SIMM{6-4};
1609 let Inst{3-0} = SIMM{3-0};
1612 // NEON 2 vector register format.
1613 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1614 bits<5> op11_7, bit op6, bit op4,
1615 dag oops, dag iops, InstrItinClass itin,
1616 string opc, string dt, string asm, string cstr, list<dag> pattern>
1617 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1618 let Inst{24-23} = op24_23;
1619 let Inst{21-20} = op21_20;
1620 let Inst{19-18} = op19_18;
1621 let Inst{17-16} = op17_16;
1622 let Inst{11-7} = op11_7;
1626 // Instruction operands.
1630 let Inst{15-12} = Vd{3-0};
1631 let Inst{22} = Vd{4};
1632 let Inst{3-0} = Vm{3-0};
1633 let Inst{5} = Vm{4};
1636 // Same as N2V except it doesn't have a datatype suffix.
1637 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1638 bits<5> op11_7, bit op6, bit op4,
1639 dag oops, dag iops, InstrItinClass itin,
1640 string opc, string asm, string cstr, list<dag> pattern>
1641 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1642 let Inst{24-23} = op24_23;
1643 let Inst{21-20} = op21_20;
1644 let Inst{19-18} = op19_18;
1645 let Inst{17-16} = op17_16;
1646 let Inst{11-7} = op11_7;
1650 // Instruction operands.
1654 let Inst{15-12} = Vd{3-0};
1655 let Inst{22} = Vd{4};
1656 let Inst{3-0} = Vm{3-0};
1657 let Inst{5} = Vm{4};
1660 // NEON 2 vector register with immediate.
1661 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1662 dag oops, dag iops, Format f, InstrItinClass itin,
1663 string opc, string dt, string asm, string cstr, list<dag> pattern>
1664 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1665 let Inst{24} = op24;
1666 let Inst{23} = op23;
1667 let Inst{11-8} = op11_8;
1672 // Instruction operands.
1677 let Inst{15-12} = Vd{3-0};
1678 let Inst{22} = Vd{4};
1679 let Inst{3-0} = Vm{3-0};
1680 let Inst{5} = Vm{4};
1681 let Inst{21-16} = SIMM{5-0};
1684 // NEON 3 vector register format.
1686 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1687 dag oops, dag iops, Format f, InstrItinClass itin,
1688 string opc, string dt, string asm, string cstr, list<dag> pattern>
1689 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1690 let Inst{24} = op24;
1691 let Inst{23} = op23;
1692 let Inst{21-20} = op21_20;
1693 let Inst{11-8} = op11_8;
1698 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1699 dag oops, dag iops, Format f, InstrItinClass itin,
1700 string opc, string dt, string asm, string cstr, list<dag> pattern>
1701 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1702 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1704 // Instruction operands.
1709 let Inst{15-12} = Vd{3-0};
1710 let Inst{22} = Vd{4};
1711 let Inst{19-16} = Vn{3-0};
1712 let Inst{7} = Vn{4};
1713 let Inst{3-0} = Vm{3-0};
1714 let Inst{5} = Vm{4};
1717 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1718 dag oops, dag iops, Format f, InstrItinClass itin,
1719 string opc, string dt, string asm, string cstr, list<dag> pattern>
1720 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1721 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1723 // Instruction operands.
1729 let Inst{15-12} = Vd{3-0};
1730 let Inst{22} = Vd{4};
1731 let Inst{19-16} = Vn{3-0};
1732 let Inst{7} = Vn{4};
1733 let Inst{3-0} = Vm{3-0};
1737 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1738 dag oops, dag iops, Format f, InstrItinClass itin,
1739 string opc, string dt, string asm, string cstr, list<dag> pattern>
1740 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1741 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1743 // Instruction operands.
1749 let Inst{15-12} = Vd{3-0};
1750 let Inst{22} = Vd{4};
1751 let Inst{19-16} = Vn{3-0};
1752 let Inst{7} = Vn{4};
1753 let Inst{2-0} = Vm{2-0};
1754 let Inst{5} = lane{1};
1755 let Inst{3} = lane{0};
1758 // Same as N3V except it doesn't have a data type suffix.
1759 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1761 dag oops, dag iops, Format f, InstrItinClass itin,
1762 string opc, string asm, string cstr, list<dag> pattern>
1763 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1764 let Inst{24} = op24;
1765 let Inst{23} = op23;
1766 let Inst{21-20} = op21_20;
1767 let Inst{11-8} = op11_8;
1771 // Instruction operands.
1776 let Inst{15-12} = Vd{3-0};
1777 let Inst{22} = Vd{4};
1778 let Inst{19-16} = Vn{3-0};
1779 let Inst{7} = Vn{4};
1780 let Inst{3-0} = Vm{3-0};
1781 let Inst{5} = Vm{4};
1784 // NEON VMOVs between scalar and core registers.
1785 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1786 dag oops, dag iops, Format f, InstrItinClass itin,
1787 string opc, string dt, string asm, list<dag> pattern>
1788 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1790 let Inst{27-20} = opcod1;
1791 let Inst{11-8} = opcod2;
1792 let Inst{6-5} = opcod3;
1795 let OutOperandList = oops;
1796 let InOperandList = !con(iops, (ins pred:$p));
1797 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1798 let Pattern = pattern;
1799 list<Predicate> Predicates = [HasNEON];
1801 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1808 let Inst{31-28} = p{3-0};
1810 let Inst{19-16} = V{3-0};
1811 let Inst{15-12} = R{3-0};
1813 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1814 dag oops, dag iops, InstrItinClass itin,
1815 string opc, string dt, string asm, list<dag> pattern>
1816 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1817 opc, dt, asm, pattern>;
1818 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1819 dag oops, dag iops, InstrItinClass itin,
1820 string opc, string dt, string asm, list<dag> pattern>
1821 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1822 opc, dt, asm, pattern>;
1823 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1824 dag oops, dag iops, InstrItinClass itin,
1825 string opc, string dt, string asm, list<dag> pattern>
1826 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1827 opc, dt, asm, pattern>;
1829 // Vector Duplicate Lane (from scalar to all elements)
1830 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1831 InstrItinClass itin, string opc, string dt, string asm,
1833 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1834 let Inst{24-23} = 0b11;
1835 let Inst{21-20} = 0b11;
1836 let Inst{19-16} = op19_16;
1837 let Inst{11-7} = 0b11000;
1845 let Inst{22} = Vd{4};
1846 let Inst{15-12} = Vd{3-0};
1847 let Inst{5} = Vm{4};
1848 let Inst{3-0} = Vm{3-0};
1851 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1852 // for single-precision FP.
1853 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1854 list<Predicate> Predicates = [HasNEON,UseNEONForFP];