1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // the instruction has a Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 class AddrMode<bits<5> val> {
91 def AddrModeNone : AddrMode<0>;
92 def AddrMode1 : AddrMode<1>;
93 def AddrMode2 : AddrMode<2>;
94 def AddrMode3 : AddrMode<3>;
95 def AddrMode4 : AddrMode<4>;
96 def AddrMode5 : AddrMode<5>;
97 def AddrMode6 : AddrMode<6>;
98 def AddrModeT1_1 : AddrMode<7>;
99 def AddrModeT1_2 : AddrMode<8>;
100 def AddrModeT1_4 : AddrMode<9>;
101 def AddrModeT1_s : AddrMode<10>;
102 def AddrModeT2_i12 : AddrMode<11>;
103 def AddrModeT2_i8 : AddrMode<12>;
104 def AddrModeT2_so : AddrMode<13>;
105 def AddrModeT2_pc : AddrMode<14>;
106 def AddrModeT2_i8s4 : AddrMode<15>;
107 def AddrMode_i12 : AddrMode<16>;
110 class SizeFlagVal<bits<3> val> {
113 def SizeInvalid : SizeFlagVal<0>; // Unset.
114 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
115 def Size8Bytes : SizeFlagVal<2>;
116 def Size4Bytes : SizeFlagVal<3>;
117 def Size2Bytes : SizeFlagVal<4>;
119 // Load / store index mode.
120 class IndexMode<bits<2> val> {
123 def IndexModeNone : IndexMode<0>;
124 def IndexModePre : IndexMode<1>;
125 def IndexModePost : IndexMode<2>;
126 def IndexModeUpd : IndexMode<3>;
128 // Instruction execution domain.
129 class Domain<bits<2> val> {
132 def GenericDomain : Domain<0>;
133 def VFPDomain : Domain<1>; // Instructions in VFP domain only
134 def NeonDomain : Domain<2>; // Instructions in Neon domain only
135 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
137 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
148 // register whose default is 0 (no register).
149 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
150 (ops (i32 14), (i32 zero_reg))> {
151 let PrintMethod = "printPredicateOperand";
152 let ParserMatchClass = CondCodeOperand;
155 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
156 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
157 string EncoderMethod = "getCCOutOpValue";
158 let PrintMethod = "printSBitModifierOperand";
161 // Same as cc_out except it defaults to setting CPSR.
162 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
163 string EncoderMethod = "getCCOutOpValue";
164 let PrintMethod = "printSBitModifierOperand";
167 // ARM special operands for disassembly only.
169 def setend_op : Operand<i32> {
170 let PrintMethod = "printSetendOperand";
173 def cps_opt : Operand<i32> {
174 let PrintMethod = "printCPSOptionOperand";
177 def msr_mask : Operand<i32> {
178 let PrintMethod = "printMSRMaskOperand";
181 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
182 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
183 def neg_zero : Operand<i32> {
184 let PrintMethod = "printNegZeroOperand";
187 //===----------------------------------------------------------------------===//
189 // ARM Instruction templates.
192 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
193 Format f, Domain d, string cstr, InstrItinClass itin>
195 let Namespace = "ARM";
200 bits<2> IndexModeBits = IM.Value;
202 bits<6> Form = F.Value;
204 bit isUnaryDataProc = 0;
205 bit canXformTo16Bit = 0;
207 // If this is a pseudo instruction, mark it isCodeGenOnly.
208 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
210 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
211 let TSFlags{4-0} = AM.Value;
212 let TSFlags{7-5} = SZ.Value;
213 let TSFlags{9-8} = IndexModeBits;
214 let TSFlags{15-10} = Form;
215 let TSFlags{16} = isUnaryDataProc;
216 let TSFlags{17} = canXformTo16Bit;
217 let TSFlags{19-18} = D.Value;
219 let Constraints = cstr;
220 let Itinerary = itin;
227 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
228 Format f, Domain d, string cstr, InstrItinClass itin>
229 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
231 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
232 // on by adding flavors to specific instructions.
233 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
234 Format f, Domain d, string cstr, InstrItinClass itin>
235 : InstTemplate<am, sz, im, f, d, cstr, itin>;
237 class PseudoInst<dag oops, dag iops, InstrItinClass itin,
238 string asm, list<dag> pattern>
239 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
241 let OutOperandList = oops;
242 let InOperandList = iops;
244 let Pattern = pattern;
247 // Almost all ARM instructions are predicable.
248 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
249 IndexMode im, Format f, InstrItinClass itin,
250 string opc, string asm, string cstr,
252 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
255 let OutOperandList = oops;
256 let InOperandList = !con(iops, (ins pred:$p));
257 let AsmString = !strconcat(opc, "${p}", asm);
258 let Pattern = pattern;
259 list<Predicate> Predicates = [IsARM];
262 // A few are not predicable
263 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
264 IndexMode im, Format f, InstrItinClass itin,
265 string opc, string asm, string cstr,
267 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
268 let OutOperandList = oops;
269 let InOperandList = iops;
270 let AsmString = !strconcat(opc, asm);
271 let Pattern = pattern;
272 let isPredicable = 0;
273 list<Predicate> Predicates = [IsARM];
276 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
277 // operand since by default it's a zero register. It will become an implicit def
278 // once it's "flipped".
279 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
280 IndexMode im, Format f, InstrItinClass itin,
281 string opc, string asm, string cstr,
283 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
284 bits<4> p; // Predicate operand
285 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
289 let OutOperandList = oops;
290 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
291 let AsmString = !strconcat(opc, "${s}${p}", asm);
292 let Pattern = pattern;
293 list<Predicate> Predicates = [IsARM];
297 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
298 IndexMode im, Format f, InstrItinClass itin,
299 string asm, string cstr, list<dag> pattern>
300 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
301 let OutOperandList = oops;
302 let InOperandList = iops;
304 let Pattern = pattern;
305 list<Predicate> Predicates = [IsARM];
308 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
309 string opc, string asm, list<dag> pattern>
310 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
311 opc, asm, "", pattern>;
312 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
313 string opc, string asm, list<dag> pattern>
314 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
315 opc, asm, "", pattern>;
316 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
317 string asm, list<dag> pattern>
318 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
320 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
321 string opc, string asm, list<dag> pattern>
322 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
323 opc, asm, "", pattern>;
325 // Ctrl flow instructions
326 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
327 string opc, string asm, list<dag> pattern>
328 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
329 opc, asm, "", pattern> {
330 let Inst{27-24} = opcod;
332 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
333 string asm, list<dag> pattern>
334 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
336 let Inst{27-24} = opcod;
338 class ABXIx2<dag oops, dag iops, InstrItinClass itin,
339 string asm, list<dag> pattern>
340 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
343 // BR_JT instructions
344 class JTI<dag oops, dag iops, InstrItinClass itin,
345 string asm, list<dag> pattern>
346 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
349 // Atomic load/store instructions
350 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
353 opc, asm, "", pattern> {
356 let Inst{27-23} = 0b00011;
357 let Inst{22-21} = opcod;
359 let Inst{19-16} = Rn;
360 let Inst{15-12} = Rt;
361 let Inst{11-0} = 0b111110011111;
363 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
364 string opc, string asm, list<dag> pattern>
365 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
366 opc, asm, "", pattern> {
370 let Inst{27-23} = 0b00011;
371 let Inst{22-21} = opcod;
373 let Inst{19-16} = Rn;
374 let Inst{15-12} = Rd;
375 let Inst{11-4} = 0b11111001;
378 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
379 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
383 let Inst{27-23} = 0b00010;
385 let Inst{21-20} = 0b00;
386 let Inst{19-16} = Rn;
387 let Inst{15-12} = Rt;
388 let Inst{11-4} = 0b00001001;
392 // addrmode1 instructions
393 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
394 string opc, string asm, list<dag> pattern>
395 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
396 opc, asm, "", pattern> {
397 let Inst{24-21} = opcod;
398 let Inst{27-26} = 0b00;
400 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
401 string opc, string asm, list<dag> pattern>
402 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
403 opc, asm, "", pattern> {
404 let Inst{24-21} = opcod;
405 let Inst{27-26} = 0b00;
407 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
408 string asm, list<dag> pattern>
409 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
411 let Inst{24-21} = opcod;
412 let Inst{27-26} = 0b00;
414 class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
417 opc, asm, "", pattern>;
420 // addrmode2 loads and stores
421 class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
422 string opc, string asm, list<dag> pattern>
423 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
424 opc, asm, "", pattern> {
425 let Inst{27-26} = 0b01;
431 class AIldst1<bits<3> op, bit opc22, bit isLd, dag oops, dag iops, AddrMode am,
432 Format f, InstrItinClass itin, string opc, string asm,
434 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
436 let Inst{27-25} = op;
437 let Inst{24} = 1; // 24 == P
439 let Inst{22} = opc22;
440 let Inst{21} = 0; // 21 == W
443 // LDRH/LDRSB/LDRSH/LDRD
444 class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
445 Format f, InstrItinClass itin, string opc, string asm,
447 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
449 let Inst{27-25} = 0b000;
450 let Inst{24} = 1; // 24 == P
452 let Inst{22} = opc22;
453 let Inst{21} = 0; // 21 == W
454 let Inst{20} = opc20;
462 class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
463 string opc, string asm, list<dag> pattern>
464 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
465 opc, asm, "", pattern> {
466 let Inst{20} = 1; // L bit
467 let Inst{21} = 0; // W bit
468 let Inst{22} = 0; // B bit
469 let Inst{24} = 1; // P bit
470 let Inst{27-26} = 0b01;
472 class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
473 string asm, list<dag> pattern>
474 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
476 let Inst{20} = 1; // L bit
477 let Inst{21} = 0; // W bit
478 let Inst{22} = 0; // B bit
479 let Inst{24} = 1; // P bit
480 let Inst{27-26} = 0b01;
482 class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
483 string opc, string asm, list<dag> pattern>
484 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
485 opc, asm, "", pattern> {
486 let Inst{20} = 1; // L bit
487 let Inst{21} = 0; // W bit
488 let Inst{22} = 1; // B bit
489 let Inst{24} = 1; // P bit
490 let Inst{27-26} = 0b01;
492 class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
493 string asm, list<dag> pattern>
494 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
496 let Inst{20} = 1; // L bit
497 let Inst{21} = 0; // W bit
498 let Inst{22} = 1; // B bit
499 let Inst{24} = 1; // P bit
500 let Inst{27-26} = 0b01;
504 class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
505 string opc, string asm, list<dag> pattern>
506 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
507 opc, asm, "", pattern> {
508 let Inst{20} = 0; // L bit
509 let Inst{21} = 0; // W bit
510 let Inst{22} = 0; // B bit
511 let Inst{24} = 1; // P bit
512 let Inst{27-26} = 0b01;
514 class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
515 string asm, list<dag> pattern>
516 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
518 let Inst{20} = 0; // L bit
519 let Inst{21} = 0; // W bit
520 let Inst{22} = 0; // B bit
521 let Inst{24} = 1; // P bit
522 let Inst{27-26} = 0b01;
524 class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
525 string opc, string asm, list<dag> pattern>
526 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
527 opc, asm, "", pattern> {
528 let Inst{20} = 0; // L bit
529 let Inst{21} = 0; // W bit
530 let Inst{22} = 1; // B bit
531 let Inst{24} = 1; // P bit
532 let Inst{27-26} = 0b01;
534 class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
535 string asm, list<dag> pattern>
536 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
538 let Inst{20} = 0; // L bit
539 let Inst{21} = 0; // W bit
540 let Inst{22} = 1; // B bit
541 let Inst{24} = 1; // P bit
542 let Inst{27-26} = 0b01;
546 class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
547 string opc, string asm, string cstr, list<dag> pattern>
548 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
549 opc, asm, cstr, pattern> {
550 let Inst{20} = 1; // L bit
551 let Inst{21} = 1; // W bit
552 let Inst{22} = 0; // B bit
553 let Inst{24} = 1; // P bit
554 let Inst{27-26} = 0b01;
556 class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
557 string opc, string asm, string cstr, list<dag> pattern>
558 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
559 opc, asm, cstr, pattern> {
560 let Inst{20} = 1; // L bit
561 let Inst{21} = 1; // W bit
562 let Inst{22} = 1; // B bit
563 let Inst{24} = 1; // P bit
564 let Inst{27-26} = 0b01;
567 // Pre-indexed stores
568 class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
569 string opc, string asm, string cstr, list<dag> pattern>
570 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
571 opc, asm, cstr, pattern> {
572 let Inst{20} = 0; // L bit
573 let Inst{21} = 1; // W bit
574 let Inst{22} = 0; // B bit
575 let Inst{24} = 1; // P bit
576 let Inst{27-26} = 0b01;
578 class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
579 string opc, string asm, string cstr, list<dag> pattern>
580 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
581 opc, asm, cstr, pattern> {
582 let Inst{20} = 0; // L bit
583 let Inst{21} = 1; // W bit
584 let Inst{22} = 1; // B bit
585 let Inst{24} = 1; // P bit
586 let Inst{27-26} = 0b01;
589 // Post-indexed loads
590 class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
591 string opc, string asm, string cstr, list<dag> pattern>
592 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
593 opc, asm, cstr,pattern> {
594 let Inst{20} = 1; // L bit
595 let Inst{21} = 0; // W bit
596 let Inst{22} = 0; // B bit
597 let Inst{24} = 0; // P bit
598 let Inst{27-26} = 0b01;
600 class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
601 string opc, string asm, string cstr, list<dag> pattern>
602 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
603 opc, asm, cstr,pattern> {
604 let Inst{20} = 1; // L bit
605 let Inst{21} = 0; // W bit
606 let Inst{22} = 1; // B bit
607 let Inst{24} = 0; // P bit
608 let Inst{27-26} = 0b01;
611 // Post-indexed stores
612 class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
613 string opc, string asm, string cstr, list<dag> pattern>
614 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
615 opc, asm, cstr,pattern> {
616 let Inst{20} = 0; // L bit
617 let Inst{21} = 0; // W bit
618 let Inst{22} = 0; // B bit
619 let Inst{24} = 0; // P bit
620 let Inst{27-26} = 0b01;
622 class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
623 string opc, string asm, string cstr, list<dag> pattern>
624 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
625 opc, asm, cstr,pattern> {
626 let Inst{20} = 0; // L bit
627 let Inst{21} = 0; // W bit
628 let Inst{22} = 1; // B bit
629 let Inst{24} = 0; // P bit
630 let Inst{27-26} = 0b01;
633 // addrmode3 instructions
634 class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
635 string opc, string asm, list<dag> pattern>
636 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
637 opc, asm, "", pattern>;
638 class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
639 string asm, list<dag> pattern>
640 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
644 class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
645 string opc, string asm, list<dag> pattern>
646 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
647 opc, asm, "", pattern> {
649 let Inst{5} = 1; // H bit
650 let Inst{6} = 0; // S bit
652 let Inst{20} = 1; // L bit
653 let Inst{21} = 0; // W bit
654 let Inst{24} = 1; // P bit
655 let Inst{27-25} = 0b000;
657 class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
658 string asm, list<dag> pattern>
659 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
662 let Inst{5} = 1; // H bit
663 let Inst{6} = 0; // S bit
665 let Inst{20} = 1; // L bit
666 let Inst{21} = 0; // W bit
667 let Inst{24} = 1; // P bit
669 class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
670 string opc, string asm, list<dag> pattern>
671 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
672 opc, asm, "", pattern> {
674 let Inst{5} = 1; // H bit
675 let Inst{6} = 1; // S bit
677 let Inst{20} = 1; // L bit
678 let Inst{21} = 0; // W bit
679 let Inst{24} = 1; // P bit
680 let Inst{27-25} = 0b000;
682 class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
683 string asm, list<dag> pattern>
684 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
687 let Inst{5} = 1; // H bit
688 let Inst{6} = 1; // S bit
690 let Inst{20} = 1; // L bit
691 let Inst{21} = 0; // W bit
692 let Inst{24} = 1; // P bit
694 class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
695 string opc, string asm, list<dag> pattern>
696 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
697 opc, asm, "", pattern> {
699 let Inst{5} = 0; // H bit
700 let Inst{6} = 1; // S bit
702 let Inst{20} = 1; // L bit
703 let Inst{21} = 0; // W bit
704 let Inst{24} = 1; // P bit
705 let Inst{27-25} = 0b000;
707 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
708 string asm, list<dag> pattern>
709 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
712 let Inst{5} = 0; // H bit
713 let Inst{6} = 1; // S bit
715 let Inst{20} = 1; // L bit
716 let Inst{21} = 0; // W bit
717 let Inst{24} = 1; // P bit
719 class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
720 string opc, string asm, list<dag> pattern>
721 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
722 opc, asm, "", pattern> {
724 let Inst{5} = 0; // H bit
725 let Inst{6} = 1; // S bit
727 let Inst{20} = 0; // L bit
728 let Inst{21} = 0; // W bit
729 let Inst{24} = 1; // P bit
730 let Inst{27-25} = 0b000;
734 class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
735 string opc, string asm, list<dag> pattern>
736 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
737 opc, asm, "", pattern> {
739 let Inst{5} = 1; // H bit
740 let Inst{6} = 0; // S bit
742 let Inst{20} = 0; // L bit
743 let Inst{21} = 0; // W bit
744 let Inst{24} = 1; // P bit
745 let Inst{27-25} = 0b000;
747 class AXI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
748 string asm, list<dag> pattern>
749 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
752 let Inst{5} = 1; // H bit
753 let Inst{6} = 0; // S bit
755 let Inst{20} = 0; // L bit
756 let Inst{21} = 0; // W bit
757 let Inst{24} = 1; // P bit
759 class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
760 string opc, string asm, list<dag> pattern>
761 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
762 opc, asm, "", pattern> {
764 let Inst{5} = 1; // H bit
765 let Inst{6} = 1; // S bit
767 let Inst{20} = 0; // L bit
768 let Inst{21} = 0; // W bit
769 let Inst{24} = 1; // P bit
770 let Inst{27-25} = 0b000;
774 class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
775 string opc, string asm, string cstr, list<dag> pattern>
776 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
777 opc, asm, cstr, pattern> {
779 let Inst{5} = 1; // H bit
780 let Inst{6} = 0; // S bit
782 let Inst{20} = 1; // L bit
783 let Inst{21} = 1; // W bit
784 let Inst{24} = 1; // P bit
785 let Inst{27-25} = 0b000;
787 class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
788 string opc, string asm, string cstr, list<dag> pattern>
789 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
790 opc, asm, cstr, pattern> {
792 let Inst{5} = 1; // H bit
793 let Inst{6} = 1; // S bit
795 let Inst{20} = 1; // L bit
796 let Inst{21} = 1; // W bit
797 let Inst{24} = 1; // P bit
798 let Inst{27-25} = 0b000;
800 class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
801 string opc, string asm, string cstr, list<dag> pattern>
802 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
803 opc, asm, cstr, pattern> {
805 let Inst{5} = 0; // H bit
806 let Inst{6} = 1; // S bit
808 let Inst{20} = 1; // L bit
809 let Inst{21} = 1; // W bit
810 let Inst{24} = 1; // P bit
811 let Inst{27-25} = 0b000;
813 class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
814 string opc, string asm, string cstr, list<dag> pattern>
815 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
816 opc, asm, cstr, pattern> {
818 let Inst{5} = 0; // H bit
819 let Inst{6} = 1; // S bit
821 let Inst{20} = 0; // L bit
822 let Inst{21} = 1; // W bit
823 let Inst{24} = 1; // P bit
824 let Inst{27-25} = 0b000;
828 // Pre-indexed stores
829 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
830 string opc, string asm, string cstr, list<dag> pattern>
831 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
832 opc, asm, cstr, pattern> {
834 let Inst{5} = 1; // H bit
835 let Inst{6} = 0; // S bit
837 let Inst{20} = 0; // L bit
838 let Inst{21} = 1; // W bit
839 let Inst{24} = 1; // P bit
840 let Inst{27-25} = 0b000;
842 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
843 string opc, string asm, string cstr, list<dag> pattern>
844 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
845 opc, asm, cstr, pattern> {
847 let Inst{5} = 1; // H bit
848 let Inst{6} = 1; // S bit
850 let Inst{20} = 0; // L bit
851 let Inst{21} = 1; // W bit
852 let Inst{24} = 1; // P bit
853 let Inst{27-25} = 0b000;
856 // Post-indexed loads
857 class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
858 string opc, string asm, string cstr, list<dag> pattern>
859 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
860 opc, asm, cstr,pattern> {
862 let Inst{5} = 1; // H bit
863 let Inst{6} = 0; // S bit
865 let Inst{20} = 1; // L bit
866 let Inst{21} = 0; // W bit
867 let Inst{24} = 0; // P bit
868 let Inst{27-25} = 0b000;
870 class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
871 string opc, string asm, string cstr, list<dag> pattern>
872 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
873 opc, asm, cstr,pattern> {
875 let Inst{5} = 1; // H bit
876 let Inst{6} = 1; // S bit
878 let Inst{20} = 1; // L bit
879 let Inst{21} = 0; // W bit
880 let Inst{24} = 0; // P bit
881 let Inst{27-25} = 0b000;
883 class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
884 string opc, string asm, string cstr, list<dag> pattern>
885 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
886 opc, asm, cstr,pattern> {
888 let Inst{5} = 0; // H bit
889 let Inst{6} = 1; // S bit
891 let Inst{20} = 1; // L bit
892 let Inst{21} = 0; // W bit
893 let Inst{24} = 0; // P bit
894 let Inst{27-25} = 0b000;
896 class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
897 string opc, string asm, string cstr, list<dag> pattern>
898 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
899 opc, asm, cstr, pattern> {
901 let Inst{5} = 0; // H bit
902 let Inst{6} = 1; // S bit
904 let Inst{20} = 0; // L bit
905 let Inst{21} = 0; // W bit
906 let Inst{24} = 0; // P bit
907 let Inst{27-25} = 0b000;
910 // Post-indexed stores
911 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
912 string opc, string asm, string cstr, list<dag> pattern>
913 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
914 opc, asm, cstr,pattern> {
916 let Inst{5} = 1; // H bit
917 let Inst{6} = 0; // S bit
919 let Inst{20} = 0; // L bit
920 let Inst{21} = 0; // W bit
921 let Inst{24} = 0; // P bit
922 let Inst{27-25} = 0b000;
924 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
925 string opc, string asm, string cstr, list<dag> pattern>
926 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
927 opc, asm, cstr, pattern> {
929 let Inst{5} = 1; // H bit
930 let Inst{6} = 1; // S bit
932 let Inst{20} = 0; // L bit
933 let Inst{21} = 0; // W bit
934 let Inst{24} = 0; // P bit
935 let Inst{27-25} = 0b000;
938 // addrmode4 instructions
939 class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
940 string asm, string cstr, list<dag> pattern>
941 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
942 asm, cstr, pattern> {
945 let Inst{27-25} = 0b100;
946 let Inst{24-22} = 0b010;
947 let Inst{20} = 1; // L bit
948 let Inst{19-16} = Rn;
949 let Inst{15-0} = dsts;
951 class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
952 string asm, string cstr, list<dag> pattern>
953 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
954 asm, cstr, pattern> {
956 let Inst{20} = 0; // L bit
957 let Inst{22} = 0; // S bit
958 let Inst{27-25} = 0b100;
959 let Inst{15-0} = srcs;
962 // Unsigned multiply, multiply-accumulate instructions.
963 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
964 string opc, string asm, list<dag> pattern>
965 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
966 opc, asm, "", pattern> {
967 let Inst{7-4} = 0b1001;
968 let Inst{20} = 0; // S bit
969 let Inst{27-21} = opcod;
971 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
972 string opc, string asm, list<dag> pattern>
973 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
974 opc, asm, "", pattern> {
975 let Inst{7-4} = 0b1001;
976 let Inst{27-21} = opcod;
979 // Most significant word multiply
980 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
981 InstrItinClass itin, string opc, string asm, list<dag> pattern>
982 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
983 opc, asm, "", pattern> {
987 let Inst{7-4} = opc7_4;
989 let Inst{27-21} = opcod;
990 let Inst{19-16} = Rd;
994 // MSW multiple w/ Ra operand
995 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
996 InstrItinClass itin, string opc, string asm, list<dag> pattern>
997 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
999 let Inst{15-12} = Ra;
1002 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
1003 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1004 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1005 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
1006 opc, asm, "", pattern> {
1012 let Inst{27-21} = opcod;
1013 let Inst{6-5} = bit6_5;
1014 let Inst{11-8} = Rm;
1017 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1018 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1019 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1021 let Inst{19-16} = Rd;
1024 // AMulxyI with Ra operand
1025 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1026 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1027 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1029 let Inst{15-12} = Ra;
1032 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
1033 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1034 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
1037 let Inst{19-16} = RdHi;
1038 let Inst{15-12} = RdLo;
1041 // Extend instructions.
1042 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
1043 string opc, string asm, list<dag> pattern>
1044 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
1045 opc, asm, "", pattern> {
1046 // All AExtI instructions have Rd and Rm register operands.
1049 let Inst{15-12} = Rd;
1051 let Inst{7-4} = 0b0111;
1052 let Inst{9-8} = 0b00;
1053 let Inst{27-20} = opcod;
1056 // Misc Arithmetic instructions.
1057 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
1058 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1059 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1060 opc, asm, "", pattern> {
1063 let Inst{27-20} = opcod;
1064 let Inst{19-16} = 0b1111;
1065 let Inst{15-12} = Rd;
1066 let Inst{11-8} = 0b1111;
1067 let Inst{7-4} = opc7_4;
1072 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
1073 string opc, string asm, list<dag> pattern>
1074 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
1075 opc, asm, "", pattern> {
1080 let Inst{27-20} = opcod;
1081 let Inst{19-16} = Rn;
1082 let Inst{15-12} = Rd;
1083 let Inst{11-7} = sh{7-3};
1085 let Inst{5-4} = 0b01;
1089 //===----------------------------------------------------------------------===//
1091 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
1092 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
1093 list<Predicate> Predicates = [IsARM];
1095 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
1096 list<Predicate> Predicates = [IsARM, HasV5TE];
1098 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
1099 list<Predicate> Predicates = [IsARM, HasV6];
1102 //===----------------------------------------------------------------------===//
1104 // Thumb Instruction Format Definitions.
1107 // TI - Thumb instruction.
1109 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1110 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1111 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1112 let OutOperandList = oops;
1113 let InOperandList = iops;
1114 let AsmString = asm;
1115 let Pattern = pattern;
1116 list<Predicate> Predicates = [IsThumb];
1119 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
1120 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1122 // Two-address instructions
1123 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
1125 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
1128 // tBL, tBX 32-bit instructions
1129 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1130 dag oops, dag iops, InstrItinClass itin, string asm,
1132 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
1134 let Inst{31-27} = opcod1;
1135 let Inst{15-14} = opcod2;
1136 let Inst{12} = opcod3;
1139 // BR_JT instructions
1140 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
1142 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1145 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1146 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
1147 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1148 let OutOperandList = oops;
1149 let InOperandList = iops;
1150 let AsmString = asm;
1151 let Pattern = pattern;
1152 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1155 class T1I<dag oops, dag iops, InstrItinClass itin,
1156 string asm, list<dag> pattern>
1157 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
1158 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
1159 string asm, list<dag> pattern>
1160 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1161 class T1JTI<dag oops, dag iops, InstrItinClass itin,
1162 string asm, list<dag> pattern>
1163 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1165 // Two-address instructions
1166 class T1It<dag oops, dag iops, InstrItinClass itin,
1167 string asm, string cstr, list<dag> pattern>
1168 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
1169 asm, cstr, pattern>;
1171 // Thumb1 instruction that can either be predicated or set CPSR.
1172 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1173 InstrItinClass itin,
1174 string opc, string asm, string cstr, list<dag> pattern>
1175 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1176 let OutOperandList = !con(oops, (outs s_cc_out:$s));
1177 let InOperandList = !con(iops, (ins pred:$p));
1178 let AsmString = !strconcat(opc, "${s}${p}", asm);
1179 let Pattern = pattern;
1180 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1183 class T1sI<dag oops, dag iops, InstrItinClass itin,
1184 string opc, string asm, list<dag> pattern>
1185 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1187 // Two-address instructions
1188 class T1sIt<dag oops, dag iops, InstrItinClass itin,
1189 string opc, string asm, list<dag> pattern>
1190 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1191 "$lhs = $dst", pattern>;
1193 // Thumb1 instruction that can be predicated.
1194 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1195 InstrItinClass itin,
1196 string opc, string asm, string cstr, list<dag> pattern>
1197 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1198 let OutOperandList = oops;
1199 let InOperandList = !con(iops, (ins pred:$p));
1200 let AsmString = !strconcat(opc, "${p}", asm);
1201 let Pattern = pattern;
1202 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1205 class T1pI<dag oops, dag iops, InstrItinClass itin,
1206 string opc, string asm, list<dag> pattern>
1207 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
1209 // Two-address instructions
1210 class T1pIt<dag oops, dag iops, InstrItinClass itin,
1211 string opc, string asm, list<dag> pattern>
1212 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
1213 "$lhs = $dst", pattern>;
1215 class T1pI1<dag oops, dag iops, InstrItinClass itin,
1216 string opc, string asm, list<dag> pattern>
1217 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, itin, opc, asm, "", pattern>;
1218 class T1pI2<dag oops, dag iops, InstrItinClass itin,
1219 string opc, string asm, list<dag> pattern>
1220 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, itin, opc, asm, "", pattern>;
1221 class T1pI4<dag oops, dag iops, InstrItinClass itin,
1222 string opc, string asm, list<dag> pattern>
1223 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
1224 class T1pIs<dag oops, dag iops,
1225 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1226 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
1228 class Encoding16 : Encoding {
1229 let Inst{31-16} = 0x0000;
1232 // A6.2 16-bit Thumb instruction encoding
1233 class T1Encoding<bits<6> opcode> : Encoding16 {
1234 let Inst{15-10} = opcode;
1237 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
1238 class T1General<bits<5> opcode> : Encoding16 {
1239 let Inst{15-14} = 0b00;
1240 let Inst{13-9} = opcode;
1243 // A6.2.2 Data-processing encoding.
1244 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1245 let Inst{15-10} = 0b010000;
1246 let Inst{9-6} = opcode;
1249 // A6.2.3 Special data instructions and branch and exchange encoding.
1250 class T1Special<bits<4> opcode> : Encoding16 {
1251 let Inst{15-10} = 0b010001;
1252 let Inst{9-6} = opcode;
1255 // A6.2.4 Load/store single data item encoding.
1256 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1257 let Inst{15-12} = opA;
1258 let Inst{11-9} = opB;
1260 class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
1261 class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
1262 class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
1263 class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
1264 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1266 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1267 class T1Misc<bits<7> opcode> : Encoding16 {
1268 let Inst{15-12} = 0b1011;
1269 let Inst{11-5} = opcode;
1272 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1273 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1274 InstrItinClass itin,
1275 string opc, string asm, string cstr, list<dag> pattern>
1276 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1277 let OutOperandList = oops;
1278 let InOperandList = !con(iops, (ins pred:$p));
1279 let AsmString = !strconcat(opc, "${p}", asm);
1280 let Pattern = pattern;
1281 list<Predicate> Predicates = [IsThumb2];
1284 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1285 // input operand since by default it's a zero register. It will become an
1286 // implicit def once it's "flipped".
1288 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1290 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1291 InstrItinClass itin,
1292 string opc, string asm, string cstr, list<dag> pattern>
1293 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1294 let OutOperandList = oops;
1295 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1296 let AsmString = !strconcat(opc, "${s}${p}", asm);
1297 let Pattern = pattern;
1298 list<Predicate> Predicates = [IsThumb2];
1302 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1303 InstrItinClass itin,
1304 string asm, string cstr, list<dag> pattern>
1305 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1306 let OutOperandList = oops;
1307 let InOperandList = iops;
1308 let AsmString = asm;
1309 let Pattern = pattern;
1310 list<Predicate> Predicates = [IsThumb2];
1313 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1314 InstrItinClass itin,
1315 string asm, string cstr, list<dag> pattern>
1316 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1317 let OutOperandList = oops;
1318 let InOperandList = iops;
1319 let AsmString = asm;
1320 let Pattern = pattern;
1321 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1324 class T2I<dag oops, dag iops, InstrItinClass itin,
1325 string opc, string asm, list<dag> pattern>
1326 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1327 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1328 string opc, string asm, list<dag> pattern>
1329 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1330 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1331 string opc, string asm, list<dag> pattern>
1332 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1333 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1334 string opc, string asm, list<dag> pattern>
1335 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1336 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1337 string opc, string asm, list<dag> pattern>
1338 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1339 class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
1340 string opc, string asm, list<dag> pattern>
1341 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1343 let Inst{31-27} = 0b11101;
1344 let Inst{26-25} = 0b00;
1346 let Inst{23} = ?; // The U bit.
1349 let Inst{20} = load;
1352 class T2sI<dag oops, dag iops, InstrItinClass itin,
1353 string opc, string asm, list<dag> pattern>
1354 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1356 class T2XI<dag oops, dag iops, InstrItinClass itin,
1357 string asm, list<dag> pattern>
1358 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1359 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1360 string asm, list<dag> pattern>
1361 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1363 class T2Ix2<dag oops, dag iops, InstrItinClass itin,
1364 string opc, string asm, list<dag> pattern>
1365 : Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
1367 // Two-address instructions
1368 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1369 string asm, string cstr, list<dag> pattern>
1370 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1372 // T2Iidxldst - Thumb2 indexed load / store instructions.
1373 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1375 AddrMode am, IndexMode im, InstrItinClass itin,
1376 string opc, string asm, string cstr, list<dag> pattern>
1377 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1378 let OutOperandList = oops;
1379 let InOperandList = !con(iops, (ins pred:$p));
1380 let AsmString = !strconcat(opc, "${p}", asm);
1381 let Pattern = pattern;
1382 list<Predicate> Predicates = [IsThumb2];
1383 let Inst{31-27} = 0b11111;
1384 let Inst{26-25} = 0b00;
1385 let Inst{24} = signed;
1387 let Inst{22-21} = opcod;
1388 let Inst{20} = load;
1390 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1391 let Inst{10} = pre; // The P bit.
1392 let Inst{8} = 1; // The W bit.
1395 // Helper class for disassembly only
1396 // A6.3.16 & A6.3.17
1397 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1398 class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
1399 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1400 : T2I<oops, iops, itin, opc, asm, pattern> {
1401 let Inst{31-27} = 0b11111;
1402 let Inst{26-24} = 0b011;
1403 let Inst{23} = long;
1404 let Inst{22-20} = op22_20;
1405 let Inst{7-4} = op7_4;
1408 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1409 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1410 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1413 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1414 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1415 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1418 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1419 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1420 list<Predicate> Predicates = [IsThumb2];
1423 //===----------------------------------------------------------------------===//
1425 //===----------------------------------------------------------------------===//
1426 // ARM VFP Instruction templates.
1429 // Almost all VFP instructions are predicable.
1430 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1431 IndexMode im, Format f, InstrItinClass itin,
1432 string opc, string asm, string cstr, list<dag> pattern>
1433 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1435 let Inst{31-28} = p;
1436 let OutOperandList = oops;
1437 let InOperandList = !con(iops, (ins pred:$p));
1438 let AsmString = !strconcat(opc, "${p}", asm);
1439 let Pattern = pattern;
1440 list<Predicate> Predicates = [HasVFP2];
1444 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1445 IndexMode im, Format f, InstrItinClass itin,
1446 string asm, string cstr, list<dag> pattern>
1447 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1448 let OutOperandList = oops;
1449 let InOperandList = iops;
1450 let AsmString = asm;
1451 let Pattern = pattern;
1452 list<Predicate> Predicates = [HasVFP2];
1455 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1456 string opc, string asm, list<dag> pattern>
1457 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1458 opc, asm, "", pattern>;
1460 // ARM VFP addrmode5 loads and stores
1461 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1462 InstrItinClass itin,
1463 string opc, string asm, list<dag> pattern>
1464 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1465 VFPLdStFrm, itin, opc, asm, "", pattern> {
1466 // Instruction operands.
1470 // Encode instruction operands.
1471 let Inst{23} = addr{8}; // U (add = (U == '1'))
1472 let Inst{22} = Dd{4};
1473 let Inst{19-16} = addr{12-9}; // Rn
1474 let Inst{15-12} = Dd{3-0};
1475 let Inst{7-0} = addr{7-0}; // imm8
1477 // TODO: Mark the instructions with the appropriate subtarget info.
1478 let Inst{27-24} = opcod1;
1479 let Inst{21-20} = opcod2;
1480 let Inst{11-9} = 0b101;
1481 let Inst{8} = 1; // Double precision
1483 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1484 let D = VFPNeonDomain;
1487 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1488 InstrItinClass itin,
1489 string opc, string asm, list<dag> pattern>
1490 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1491 VFPLdStFrm, itin, opc, asm, "", pattern> {
1492 // Instruction operands.
1496 // Encode instruction operands.
1497 let Inst{23} = addr{8}; // U (add = (U == '1'))
1498 let Inst{22} = Sd{0};
1499 let Inst{19-16} = addr{12-9}; // Rn
1500 let Inst{15-12} = Sd{4-1};
1501 let Inst{7-0} = addr{7-0}; // imm8
1503 // TODO: Mark the instructions with the appropriate subtarget info.
1504 let Inst{27-24} = opcod1;
1505 let Inst{21-20} = opcod2;
1506 let Inst{11-9} = 0b101;
1507 let Inst{8} = 0; // Single precision
1510 // VFP Load / store multiple pseudo instructions.
1511 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1513 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1515 let OutOperandList = oops;
1516 let InOperandList = !con(iops, (ins pred:$p));
1517 let Pattern = pattern;
1518 list<Predicate> Predicates = [HasVFP2];
1521 // Load / store multiple
1522 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1523 string asm, string cstr, list<dag> pattern>
1524 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1525 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1526 // TODO: Mark the instructions with the appropriate subtarget info.
1527 let Inst{27-25} = 0b110;
1528 let Inst{11-9} = 0b101;
1529 let Inst{8} = 1; // Double precision
1531 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1532 let D = VFPNeonDomain;
1535 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1536 string asm, string cstr, list<dag> pattern>
1537 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1538 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1539 // TODO: Mark the instructions with the appropriate subtarget info.
1540 let Inst{27-25} = 0b110;
1541 let Inst{11-9} = 0b101;
1542 let Inst{8} = 0; // Single precision
1545 // Double precision, unary
1546 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1547 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1548 string asm, list<dag> pattern>
1549 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1550 // Instruction operands.
1554 // Encode instruction operands.
1555 let Inst{3-0} = Dm{3-0};
1556 let Inst{5} = Dm{4};
1557 let Inst{15-12} = Dd{3-0};
1558 let Inst{22} = Dd{4};
1560 let Inst{27-23} = opcod1;
1561 let Inst{21-20} = opcod2;
1562 let Inst{19-16} = opcod3;
1563 let Inst{11-9} = 0b101;
1564 let Inst{8} = 1; // Double precision
1565 let Inst{7-6} = opcod4;
1566 let Inst{4} = opcod5;
1569 // Double precision, binary
1570 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1571 dag iops, InstrItinClass itin, string opc, string asm,
1573 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1574 // Instruction operands.
1579 // Encode instruction operands.
1580 let Inst{3-0} = Dm{3-0};
1581 let Inst{5} = Dm{4};
1582 let Inst{19-16} = Dn{3-0};
1583 let Inst{7} = Dn{4};
1584 let Inst{15-12} = Dd{3-0};
1585 let Inst{22} = Dd{4};
1587 let Inst{27-23} = opcod1;
1588 let Inst{21-20} = opcod2;
1589 let Inst{11-9} = 0b101;
1590 let Inst{8} = 1; // Double precision
1595 // Double precision, binary, VML[AS] (for additional predicate)
1596 class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1597 dag iops, InstrItinClass itin, string opc, string asm,
1599 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1600 // Instruction operands.
1605 // Encode instruction operands.
1606 let Inst{19-16} = Dn{3-0};
1607 let Inst{7} = Dn{4};
1608 let Inst{15-12} = Dd{3-0};
1609 let Inst{22} = Dd{4};
1610 let Inst{3-0} = Dm{3-0};
1611 let Inst{5} = Dm{4};
1613 let Inst{27-23} = opcod1;
1614 let Inst{21-20} = opcod2;
1615 let Inst{11-9} = 0b101;
1616 let Inst{8} = 1; // Double precision
1619 list<Predicate> Predicates = [HasVFP2, UseVMLx];
1622 // Single precision, unary
1623 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1624 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1625 string asm, list<dag> pattern>
1626 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1627 // Instruction operands.
1631 // Encode instruction operands.
1632 let Inst{3-0} = Sm{4-1};
1633 let Inst{5} = Sm{0};
1634 let Inst{15-12} = Sd{4-1};
1635 let Inst{22} = Sd{0};
1637 let Inst{27-23} = opcod1;
1638 let Inst{21-20} = opcod2;
1639 let Inst{19-16} = opcod3;
1640 let Inst{11-9} = 0b101;
1641 let Inst{8} = 0; // Single precision
1642 let Inst{7-6} = opcod4;
1643 let Inst{4} = opcod5;
1646 // Single precision unary, if no NEON
1647 // Same as ASuI except not available if NEON is enabled
1648 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1649 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1650 string asm, list<dag> pattern>
1651 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1653 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1656 // Single precision, binary
1657 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1658 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1659 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1660 // Instruction operands.
1665 // Encode instruction operands.
1666 let Inst{3-0} = Sm{4-1};
1667 let Inst{5} = Sm{0};
1668 let Inst{19-16} = Sn{4-1};
1669 let Inst{7} = Sn{0};
1670 let Inst{15-12} = Sd{4-1};
1671 let Inst{22} = Sd{0};
1673 let Inst{27-23} = opcod1;
1674 let Inst{21-20} = opcod2;
1675 let Inst{11-9} = 0b101;
1676 let Inst{8} = 0; // Single precision
1681 // Single precision binary, if no NEON
1682 // Same as ASbI except not available if NEON is enabled
1683 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1684 dag iops, InstrItinClass itin, string opc, string asm,
1686 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1687 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1689 // Instruction operands.
1694 // Encode instruction operands.
1695 let Inst{3-0} = Sm{4-1};
1696 let Inst{5} = Sm{0};
1697 let Inst{19-16} = Sn{4-1};
1698 let Inst{7} = Sn{0};
1699 let Inst{15-12} = Sd{4-1};
1700 let Inst{22} = Sd{0};
1703 // VFP conversion instructions
1704 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1705 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1707 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1708 let Inst{27-23} = opcod1;
1709 let Inst{21-20} = opcod2;
1710 let Inst{19-16} = opcod3;
1711 let Inst{11-8} = opcod4;
1716 // VFP conversion between floating-point and fixed-point
1717 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1718 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1720 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1721 // size (fixed-point number): sx == 0 ? 16 : 32
1722 let Inst{7} = op5; // sx
1725 // VFP conversion instructions, if no NEON
1726 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1727 dag oops, dag iops, InstrItinClass itin,
1728 string opc, string asm, list<dag> pattern>
1729 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1731 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1734 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1735 InstrItinClass itin,
1736 string opc, string asm, list<dag> pattern>
1737 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1738 let Inst{27-20} = opcod1;
1739 let Inst{11-8} = opcod2;
1743 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1744 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1745 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1747 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1748 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1749 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1751 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1752 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1753 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1755 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1756 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1757 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1759 //===----------------------------------------------------------------------===//
1761 //===----------------------------------------------------------------------===//
1762 // ARM NEON Instruction templates.
1765 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1766 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1768 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1769 let OutOperandList = oops;
1770 let InOperandList = !con(iops, (ins pred:$p));
1771 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1772 let Pattern = pattern;
1773 list<Predicate> Predicates = [HasNEON];
1776 // Same as NeonI except it does not have a "data type" specifier.
1777 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1778 InstrItinClass itin, string opc, string asm, string cstr,
1780 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1781 let OutOperandList = oops;
1782 let InOperandList = !con(iops, (ins pred:$p));
1783 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1784 let Pattern = pattern;
1785 list<Predicate> Predicates = [HasNEON];
1788 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1789 dag oops, dag iops, InstrItinClass itin,
1790 string opc, string dt, string asm, string cstr, list<dag> pattern>
1791 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1793 let Inst{31-24} = 0b11110100;
1794 let Inst{23} = op23;
1795 let Inst{21-20} = op21_20;
1796 let Inst{11-8} = op11_8;
1797 let Inst{7-4} = op7_4;
1803 let Inst{22} = Vd{4};
1804 let Inst{15-12} = Vd{3-0};
1805 let Inst{19-16} = Rn{3-0};
1806 let Inst{3-0} = Rm{3-0};
1809 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1810 dag oops, dag iops, InstrItinClass itin,
1811 string opc, string dt, string asm, string cstr, list<dag> pattern>
1812 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1813 dt, asm, cstr, pattern> {
1817 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1818 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1820 let OutOperandList = oops;
1821 let InOperandList = !con(iops, (ins pred:$p));
1822 list<Predicate> Predicates = [HasNEON];
1825 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1827 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1829 let OutOperandList = oops;
1830 let InOperandList = !con(iops, (ins pred:$p));
1831 let Pattern = pattern;
1832 list<Predicate> Predicates = [HasNEON];
1835 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1836 string opc, string dt, string asm, string cstr, list<dag> pattern>
1837 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1839 let Inst{31-25} = 0b1111001;
1842 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1843 string opc, string asm, string cstr, list<dag> pattern>
1844 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1846 let Inst{31-25} = 0b1111001;
1849 // NEON "one register and a modified immediate" format.
1850 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1852 dag oops, dag iops, InstrItinClass itin,
1853 string opc, string dt, string asm, string cstr,
1855 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1856 let Inst{23} = op23;
1857 let Inst{21-19} = op21_19;
1858 let Inst{11-8} = op11_8;
1864 // Instruction operands.
1868 let Inst{15-12} = Vd{3-0};
1869 let Inst{22} = Vd{4};
1870 let Inst{24} = SIMM{7};
1871 let Inst{18-16} = SIMM{6-4};
1872 let Inst{3-0} = SIMM{3-0};
1875 // NEON 2 vector register format.
1876 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1877 bits<5> op11_7, bit op6, bit op4,
1878 dag oops, dag iops, InstrItinClass itin,
1879 string opc, string dt, string asm, string cstr, list<dag> pattern>
1880 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1881 let Inst{24-23} = op24_23;
1882 let Inst{21-20} = op21_20;
1883 let Inst{19-18} = op19_18;
1884 let Inst{17-16} = op17_16;
1885 let Inst{11-7} = op11_7;
1889 // Instruction operands.
1893 let Inst{15-12} = Vd{3-0};
1894 let Inst{22} = Vd{4};
1895 let Inst{3-0} = Vm{3-0};
1896 let Inst{5} = Vm{4};
1899 // Same as N2V except it doesn't have a datatype suffix.
1900 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1901 bits<5> op11_7, bit op6, bit op4,
1902 dag oops, dag iops, InstrItinClass itin,
1903 string opc, string asm, string cstr, list<dag> pattern>
1904 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1905 let Inst{24-23} = op24_23;
1906 let Inst{21-20} = op21_20;
1907 let Inst{19-18} = op19_18;
1908 let Inst{17-16} = op17_16;
1909 let Inst{11-7} = op11_7;
1913 // Instruction operands.
1917 let Inst{15-12} = Vd{3-0};
1918 let Inst{22} = Vd{4};
1919 let Inst{3-0} = Vm{3-0};
1920 let Inst{5} = Vm{4};
1923 // NEON 2 vector register with immediate.
1924 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1925 dag oops, dag iops, Format f, InstrItinClass itin,
1926 string opc, string dt, string asm, string cstr, list<dag> pattern>
1927 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1928 let Inst{24} = op24;
1929 let Inst{23} = op23;
1930 let Inst{11-8} = op11_8;
1935 // Instruction operands.
1940 let Inst{15-12} = Vd{3-0};
1941 let Inst{22} = Vd{4};
1942 let Inst{3-0} = Vm{3-0};
1943 let Inst{5} = Vm{4};
1944 let Inst{21-16} = SIMM{5-0};
1947 // NEON 3 vector register format.
1948 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1949 dag oops, dag iops, Format f, InstrItinClass itin,
1950 string opc, string dt, string asm, string cstr, list<dag> pattern>
1951 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1952 let Inst{24} = op24;
1953 let Inst{23} = op23;
1954 let Inst{21-20} = op21_20;
1955 let Inst{11-8} = op11_8;
1959 // Instruction operands.
1964 let Inst{15-12} = Vd{3-0};
1965 let Inst{22} = Vd{4};
1966 let Inst{19-16} = Vn{3-0};
1967 let Inst{7} = Vn{4};
1968 let Inst{3-0} = Vm{3-0};
1969 let Inst{5} = Vm{4};
1972 // Same as N3V except it doesn't have a data type suffix.
1973 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1975 dag oops, dag iops, Format f, InstrItinClass itin,
1976 string opc, string asm, string cstr, list<dag> pattern>
1977 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1978 let Inst{24} = op24;
1979 let Inst{23} = op23;
1980 let Inst{21-20} = op21_20;
1981 let Inst{11-8} = op11_8;
1985 // Instruction operands.
1990 let Inst{15-12} = Vd{3-0};
1991 let Inst{22} = Vd{4};
1992 let Inst{19-16} = Vn{3-0};
1993 let Inst{7} = Vn{4};
1994 let Inst{3-0} = Vm{3-0};
1995 let Inst{5} = Vm{4};
1998 // NEON VMOVs between scalar and core registers.
1999 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2000 dag oops, dag iops, Format f, InstrItinClass itin,
2001 string opc, string dt, string asm, list<dag> pattern>
2002 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
2004 let Inst{27-20} = opcod1;
2005 let Inst{11-8} = opcod2;
2006 let Inst{6-5} = opcod3;
2009 let OutOperandList = oops;
2010 let InOperandList = !con(iops, (ins pred:$p));
2011 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
2012 let Pattern = pattern;
2013 list<Predicate> Predicates = [HasNEON];
2020 let Inst{31-28} = p{3-0};
2022 let Inst{19-16} = V{3-0};
2023 let Inst{15-12} = R{3-0};
2025 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2026 dag oops, dag iops, InstrItinClass itin,
2027 string opc, string dt, string asm, list<dag> pattern>
2028 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
2029 opc, dt, asm, pattern>;
2030 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2031 dag oops, dag iops, InstrItinClass itin,
2032 string opc, string dt, string asm, list<dag> pattern>
2033 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
2034 opc, dt, asm, pattern>;
2035 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2036 dag oops, dag iops, InstrItinClass itin,
2037 string opc, string dt, string asm, list<dag> pattern>
2038 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
2039 opc, dt, asm, pattern>;
2041 // Vector Duplicate Lane (from scalar to all elements)
2042 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2043 InstrItinClass itin, string opc, string dt, string asm,
2045 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
2046 let Inst{24-23} = 0b11;
2047 let Inst{21-20} = 0b11;
2048 let Inst{19-16} = op19_16;
2049 let Inst{11-7} = 0b11000;
2057 let Inst{22} = Vd{4};
2058 let Inst{15-12} = Vd{3-0};
2059 let Inst{5} = Vm{4};
2060 let Inst{3-0} = Vm{3-0};
2063 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
2064 // for single-precision FP.
2065 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
2066 list<Predicate> Predicates = [HasNEON,UseNEONForFP];