1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def MulSMLAW : Format<3>;
25 def MulSMULW : Format<4>;
26 def MulSMLA : Format<5>;
27 def MulSMUL : Format<6>;
28 def Branch : Format<7>;
29 def BranchMisc : Format<8>;
31 def DPFrm : Format<9>;
32 def DPSoRegFrm : Format<10>;
34 def LdFrm : Format<11>;
35 def StFrm : Format<12>;
36 def LdMiscFrm : Format<13>;
37 def StMiscFrm : Format<14>;
38 def LdMulFrm : Format<15>;
39 def StMulFrm : Format<16>;
41 def ArithMisc : Format<17>;
42 def ThumbFrm : Format<18>;
43 def VFPFrm : Format<19>;
45 // Misc flag for data processing instructions that indicates whether
46 // the instruction has a Rn register operand.
47 class UnaryDP { bit isUnaryDataProc = 1; }
49 //===----------------------------------------------------------------------===//
51 // ARM Instruction templates.
54 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
55 Format f, string cstr>
59 let Namespace = "ARM";
61 bits<4> Opcode = opcod;
65 bits<4> AddrModeBits = AM.Value;
68 bits<3> SizeFlag = SZ.Value;
71 bits<2> IndexModeBits = IM.Value;
74 bits<5> Form = F.Value;
77 // Attributes specific to ARM instructions...
79 bit isUnaryDataProc = 0;
81 let Constraints = cstr;
84 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
85 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
86 let OutOperandList = oops;
87 let InOperandList = iops;
89 let Pattern = pattern;
92 // Almost all ARM instructions are predicable.
93 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
94 IndexMode im, Format f, string opc, string asm, string cstr,
96 : InstARM<opcod, am, sz, im, f, cstr> {
97 let OutOperandList = oops;
98 let InOperandList = !con(iops, (ops pred:$p));
99 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
100 let Pattern = pattern;
101 list<Predicate> Predicates = [IsARM];
104 // Same as I except it can optionally modify CPSR. Note it's modeled as
105 // an input operand since by default it's a zero register. It will
106 // become an implicit def once it's "flipped".
107 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
108 IndexMode im, Format f, string opc, string asm, string cstr,
110 : InstARM<opcod, am, sz, im, f, cstr> {
111 let OutOperandList = oops;
112 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
113 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
114 let Pattern = pattern;
115 list<Predicate> Predicates = [IsARM];
119 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
120 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
121 : InstARM<opcod, am, sz, im, f, cstr> {
122 let OutOperandList = oops;
123 let InOperandList = iops;
125 let Pattern = pattern;
126 list<Predicate> Predicates = [IsARM];
129 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
130 string asm, list<dag> pattern>
131 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
133 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
134 string asm, list<dag> pattern>
135 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
137 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
139 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
142 // Ctrl flow instructions
143 class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
144 string asm, list<dag> pattern>
145 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
147 let Inst{27-24} = opcod;
149 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
151 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
153 let Inst{27-24} = opcod;
156 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
158 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
160 class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
162 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
164 let Inst{27-24} = opcod;
166 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
167 string asm, list<dag> pattern>
168 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
170 let Inst{27-24} = opcod;
173 // BR_JT instructions
175 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
176 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
178 let Inst{20} = 0; // S Bit
179 let Inst{24-21} = opcod;
180 let Inst{27-26} = {0,0};
183 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
184 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
186 let Inst{20} = 0; // S bit
187 let Inst{24-21} = opcod;
188 let Inst{27-26} = {0,0};
191 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
192 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
194 let Inst{20} = 1; // L bit
195 let Inst{21} = 0; // W bit
196 let Inst{22} = 0; // B bit
197 let Inst{24} = 1; // P bit
198 let Inst{27-26} = {0,1};
202 // addrmode1 instructions
203 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
204 string asm, list<dag> pattern>
205 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
207 let Inst{24-21} = opcod;
208 let Inst{27-26} = {0,0};
210 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
211 string asm, list<dag> pattern>
212 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
214 let Inst{24-21} = opcod;
215 let Inst{27-26} = {0,0};
217 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
219 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
221 let Inst{24-21} = opcod;
222 let Inst{27-26} = {0,0};
224 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
225 string asm, list<dag> pattern>
226 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
230 // addrmode2 loads and stores
231 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
232 string asm, list<dag> pattern>
233 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
235 let Inst{27-26} = {0,1};
239 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
240 string asm, list<dag> pattern>
241 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
243 let Inst{20} = 1; // L bit
244 let Inst{21} = 0; // W bit
245 let Inst{22} = 0; // B bit
246 let Inst{24} = 1; // P bit
247 let Inst{27-26} = {0,1};
249 class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
251 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
253 let Inst{20} = 1; // L bit
254 let Inst{21} = 0; // W bit
255 let Inst{22} = 0; // B bit
256 let Inst{24} = 1; // P bit
257 let Inst{27-26} = {0,1};
259 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
260 string asm, list<dag> pattern>
261 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
263 let Inst{20} = 1; // L bit
264 let Inst{21} = 0; // W bit
265 let Inst{22} = 1; // B bit
266 let Inst{24} = 1; // P bit
267 let Inst{27-26} = {0,1};
269 class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
271 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
273 let Inst{20} = 1; // L bit
274 let Inst{21} = 0; // W bit
275 let Inst{22} = 1; // B bit
276 let Inst{24} = 1; // P bit
277 let Inst{27-26} = {0,1};
281 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
282 string asm, list<dag> pattern>
283 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
285 let Inst{20} = 0; // L bit
286 let Inst{21} = 0; // W bit
287 let Inst{22} = 0; // B bit
288 let Inst{24} = 1; // P bit
289 let Inst{27-26} = {0,1};
291 class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
293 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
295 let Inst{20} = 0; // L bit
296 let Inst{21} = 0; // W bit
297 let Inst{22} = 0; // B bit
298 let Inst{24} = 1; // P bit
299 let Inst{27-26} = {0,1};
301 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
302 string asm, list<dag> pattern>
303 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
305 let Inst{20} = 0; // L bit
306 let Inst{21} = 0; // W bit
307 let Inst{22} = 1; // B bit
308 let Inst{24} = 1; // P bit
309 let Inst{27-26} = {0,1};
311 class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
313 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
315 let Inst{20} = 0; // L bit
316 let Inst{21} = 0; // W bit
317 let Inst{22} = 1; // B bit
318 let Inst{24} = 1; // P bit
319 let Inst{27-26} = {0,1};
323 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
324 string asm, string cstr, list<dag> pattern>
325 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
326 asm, cstr, pattern> {
327 let Inst{20} = 1; // L bit
328 let Inst{21} = 1; // W bit
329 let Inst{22} = 0; // B bit
330 let Inst{24} = 1; // P bit
331 let Inst{27-26} = {0,1};
333 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
334 string asm, string cstr, list<dag> pattern>
335 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
336 asm, cstr, pattern> {
337 let Inst{20} = 1; // L bit
338 let Inst{21} = 1; // W bit
339 let Inst{22} = 1; // B bit
340 let Inst{24} = 1; // P bit
341 let Inst{27-26} = {0,1};
344 // Pre-indexed stores
345 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
346 string asm, string cstr, list<dag> pattern>
347 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
348 asm, cstr, pattern> {
349 let Inst{20} = 0; // L bit
350 let Inst{21} = 1; // W bit
351 let Inst{22} = 0; // B bit
352 let Inst{24} = 1; // P bit
353 let Inst{27-26} = {0,1};
355 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
356 string asm, string cstr, list<dag> pattern>
357 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
358 asm, cstr, pattern> {
359 let Inst{20} = 0; // L bit
360 let Inst{21} = 1; // W bit
361 let Inst{22} = 1; // B bit
362 let Inst{24} = 1; // P bit
363 let Inst{27-26} = {0,1};
366 // Post-indexed loads
367 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
368 string asm, string cstr, list<dag> pattern>
369 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
371 let Inst{20} = 1; // L bit
372 let Inst{21} = 0; // W bit
373 let Inst{22} = 0; // B bit
374 let Inst{24} = 0; // P bit
375 let Inst{27-26} = {0,1};
377 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
378 string asm, string cstr, list<dag> pattern>
379 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
381 let Inst{20} = 1; // L bit
382 let Inst{21} = 0; // W bit
383 let Inst{22} = 1; // B bit
384 let Inst{24} = 0; // P bit
385 let Inst{27-26} = {0,1};
388 // Post-indexed stores
389 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
390 string asm, string cstr, list<dag> pattern>
391 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
393 let Inst{20} = 0; // L bit
394 let Inst{21} = 0; // W bit
395 let Inst{22} = 0; // B bit
396 let Inst{24} = 0; // P bit
397 let Inst{27-26} = {0,1};
399 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
400 string asm, string cstr, list<dag> pattern>
401 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
403 let Inst{20} = 0; // L bit
404 let Inst{21} = 0; // W bit
405 let Inst{22} = 1; // B bit
406 let Inst{24} = 0; // P bit
407 let Inst{27-26} = {0,1};
410 // addrmode3 instructions
411 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
412 string asm, list<dag> pattern>
413 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
415 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
417 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
421 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
422 string asm, list<dag> pattern>
423 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
426 let Inst{5} = 1; // H bit
427 let Inst{6} = 0; // S bit
429 let Inst{20} = 1; // L bit
430 let Inst{21} = 0; // W bit
431 let Inst{24} = 1; // P bit
433 class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
435 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
438 let Inst{5} = 1; // H bit
439 let Inst{6} = 0; // S bit
441 let Inst{20} = 1; // L bit
442 let Inst{21} = 0; // W bit
443 let Inst{24} = 1; // P bit
445 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
446 string asm, list<dag> pattern>
447 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
450 let Inst{5} = 1; // H bit
451 let Inst{6} = 1; // S bit
453 let Inst{20} = 1; // L bit
454 let Inst{21} = 0; // W bit
455 let Inst{24} = 1; // P bit
457 class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
459 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
462 let Inst{5} = 1; // H bit
463 let Inst{6} = 1; // S bit
465 let Inst{20} = 1; // L bit
466 let Inst{21} = 0; // W bit
467 let Inst{24} = 1; // P bit
469 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
470 string asm, list<dag> pattern>
471 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
474 let Inst{5} = 0; // H bit
475 let Inst{6} = 1; // S bit
477 let Inst{20} = 1; // L bit
478 let Inst{21} = 0; // W bit
479 let Inst{24} = 1; // P bit
481 class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
483 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
486 let Inst{5} = 0; // H bit
487 let Inst{6} = 1; // S bit
489 let Inst{20} = 1; // L bit
490 let Inst{21} = 0; // W bit
491 let Inst{24} = 1; // P bit
493 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
494 string asm, list<dag> pattern>
495 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
498 let Inst{5} = 0; // H bit
499 let Inst{6} = 1; // S bit
501 let Inst{20} = 0; // L bit
502 let Inst{21} = 0; // W bit
503 let Inst{24} = 1; // P bit
507 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
508 string asm, list<dag> pattern>
509 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
512 let Inst{5} = 1; // H bit
513 let Inst{6} = 0; // S bit
515 let Inst{20} = 0; // L bit
516 let Inst{21} = 0; // W bit
517 let Inst{24} = 1; // P bit
519 class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
521 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
524 let Inst{5} = 1; // H bit
525 let Inst{6} = 0; // S bit
527 let Inst{20} = 0; // L bit
528 let Inst{21} = 0; // W bit
529 let Inst{24} = 1; // P bit
531 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
532 string asm, list<dag> pattern>
533 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
536 let Inst{5} = 1; // H bit
537 let Inst{6} = 1; // S bit
539 let Inst{20} = 0; // L bit
540 let Inst{21} = 0; // W bit
541 let Inst{24} = 1; // P bit
545 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
546 string asm, string cstr, list<dag> pattern>
547 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
548 asm, cstr, pattern> {
550 let Inst{5} = 1; // H bit
551 let Inst{6} = 0; // S bit
553 let Inst{20} = 1; // L bit
554 let Inst{21} = 1; // W bit
555 let Inst{24} = 1; // P bit
557 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
558 string asm, string cstr, list<dag> pattern>
559 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
560 asm, cstr, pattern> {
562 let Inst{5} = 1; // H bit
563 let Inst{6} = 1; // S bit
565 let Inst{20} = 1; // L bit
566 let Inst{21} = 1; // W bit
567 let Inst{24} = 1; // P bit
569 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
570 string asm, string cstr, list<dag> pattern>
571 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
572 asm, cstr, pattern> {
574 let Inst{5} = 0; // H bit
575 let Inst{6} = 1; // S bit
577 let Inst{20} = 1; // L bit
578 let Inst{21} = 1; // W bit
579 let Inst{24} = 1; // P bit
582 // Pre-indexed stores
583 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
584 string asm, string cstr, list<dag> pattern>
585 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
586 asm, cstr, pattern> {
588 let Inst{5} = 1; // H bit
589 let Inst{6} = 0; // S bit
591 let Inst{20} = 0; // L bit
592 let Inst{21} = 1; // W bit
593 let Inst{24} = 1; // P bit
596 // Post-indexed loads
597 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
598 string asm, string cstr, list<dag> pattern>
599 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
602 let Inst{5} = 1; // H bit
603 let Inst{6} = 0; // S bit
605 let Inst{20} = 1; // L bit
606 let Inst{21} = 1; // W bit
607 let Inst{24} = 0; // P bit
609 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
610 string asm, string cstr, list<dag> pattern>
611 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
614 let Inst{5} = 1; // H bit
615 let Inst{6} = 1; // S bit
617 let Inst{20} = 1; // L bit
618 let Inst{21} = 1; // W bit
619 let Inst{24} = 0; // P bit
621 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
622 string asm, string cstr, list<dag> pattern>
623 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
626 let Inst{5} = 0; // H bit
627 let Inst{6} = 1; // S bit
629 let Inst{20} = 1; // L bit
630 let Inst{21} = 1; // W bit
631 let Inst{24} = 0; // P bit
634 // Post-indexed stores
635 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
636 string asm, string cstr, list<dag> pattern>
637 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
640 let Inst{5} = 1; // H bit
641 let Inst{6} = 0; // S bit
643 let Inst{20} = 0; // L bit
644 let Inst{21} = 1; // W bit
645 let Inst{24} = 0; // P bit
649 // addrmode4 instructions
650 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
651 string asm, list<dag> pattern>
652 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
654 let Inst{25-27} = {0,0,1};
656 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
658 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
660 let Inst{20} = 1; // L bit
661 let Inst{22} = 0; // S bit
662 let Inst{27-25} = 0b100;
664 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
666 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
668 let Inst{20} = 1; // L bit
669 let Inst{27-25} = 0b100;
671 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
673 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
675 let Inst{20} = 0; // L bit
676 let Inst{22} = 0; // S bit
677 let Inst{27-25} = 0b100;
680 // Unsigned multiply, multiply-accumulate instructions.
681 class AMul1I<bits<7> mulopc, dag oops, dag iops, string opc,
682 string asm, list<dag> pattern>
683 : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
685 let Inst{7-4} = 0b1001;
686 let Inst{20} = 0; // S bit
687 let Inst{27-21} = mulopc;
689 class AsMul1I<bits<7> mulopc, dag oops, dag iops, string opc,
690 string asm, list<dag> pattern>
691 : sI<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
693 let Inst{7-4} = 0b1001;
694 let Inst{27-21} = mulopc;
697 // Most significant word multiply
698 class AMul2I<bits<7> mulopc, dag oops, dag iops, string opc,
699 string asm, list<dag> pattern>
700 : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
702 let Inst{7-4} = 0b1001;
704 let Inst{27-21} = mulopc;
707 //===----------------------------------------------------------------------===//
709 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
710 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
711 list<Predicate> Predicates = [IsARM];
713 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
714 list<Predicate> Predicates = [IsARM, HasV5TE];
716 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
717 list<Predicate> Predicates = [IsARM, HasV6];
720 //===----------------------------------------------------------------------===//
722 // Thumb Instruction Format Definitions.
726 // TI - Thumb instruction.
728 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
729 string asm, string cstr, list<dag> pattern>
730 // FIXME: Set all opcodes to 0 for now.
731 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
732 let OutOperandList = outs;
733 let InOperandList = ins;
735 let Pattern = pattern;
736 list<Predicate> Predicates = [IsThumb];
739 class TI<dag outs, dag ins, string asm, list<dag> pattern>
740 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
741 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
742 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
743 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
744 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
745 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
746 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
747 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
748 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
750 // Two-address instructions
751 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
752 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
754 // BL, BLX(1) are translated by assembler into two instructions
755 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
756 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
758 // BR_JT instructions
759 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
760 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
763 //===----------------------------------------------------------------------===//
766 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
767 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
768 list<Predicate> Predicates = [IsThumb];
771 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
772 list<Predicate> Predicates = [IsThumb, HasV5T];