1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // The instruction has an Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
87 // FIXME: Once the JIT is MC-ized, these can go away.
89 class AddrMode<bits<5> val> {
92 def AddrModeNone : AddrMode<0>;
93 def AddrMode1 : AddrMode<1>;
94 def AddrMode2 : AddrMode<2>;
95 def AddrMode3 : AddrMode<3>;
96 def AddrMode4 : AddrMode<4>;
97 def AddrMode5 : AddrMode<5>;
98 def AddrMode6 : AddrMode<6>;
99 def AddrModeT1_1 : AddrMode<7>;
100 def AddrModeT1_2 : AddrMode<8>;
101 def AddrModeT1_4 : AddrMode<9>;
102 def AddrModeT1_s : AddrMode<10>;
103 def AddrModeT2_i12 : AddrMode<11>;
104 def AddrModeT2_i8 : AddrMode<12>;
105 def AddrModeT2_so : AddrMode<13>;
106 def AddrModeT2_pc : AddrMode<14>;
107 def AddrModeT2_i8s4 : AddrMode<15>;
108 def AddrMode_i12 : AddrMode<16>;
111 class SizeFlagVal<bits<3> val> {
114 def SizeInvalid : SizeFlagVal<0>; // Unset.
115 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
116 def Size8Bytes : SizeFlagVal<2>;
117 def Size4Bytes : SizeFlagVal<3>;
118 def Size2Bytes : SizeFlagVal<4>;
120 // Load / store index mode.
121 class IndexMode<bits<2> val> {
124 def IndexModeNone : IndexMode<0>;
125 def IndexModePre : IndexMode<1>;
126 def IndexModePost : IndexMode<2>;
127 def IndexModeUpd : IndexMode<3>;
129 // Instruction execution domain.
130 class Domain<bits<2> val> {
133 def GenericDomain : Domain<0>;
134 def VFPDomain : Domain<1>; // Instructions in VFP domain only
135 def NeonDomain : Domain<2>; // Instructions in Neon domain only
136 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
138 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 def CCOutOperand : AsmOperandClass {
149 let SuperClasses = [];
152 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
153 // register whose default is 0 (no register).
154 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
155 (ops (i32 14), (i32 zero_reg))> {
156 let PrintMethod = "printPredicateOperand";
157 let ParserMatchClass = CondCodeOperand;
160 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
161 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
162 let EncoderMethod = "getCCOutOpValue";
163 let PrintMethod = "printSBitModifierOperand";
164 let ParserMatchClass = CCOutOperand;
167 // Same as cc_out except it defaults to setting CPSR.
168 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
169 let EncoderMethod = "getCCOutOpValue";
170 let PrintMethod = "printSBitModifierOperand";
171 let ParserMatchClass = CCOutOperand;
174 // ARM special operands for disassembly only.
176 def setend_op : Operand<i32> {
177 let PrintMethod = "printSetendOperand";
180 def cps_opt : Operand<i32> {
181 let PrintMethod = "printCPSOptionOperand";
184 def msr_mask : Operand<i32> {
185 let PrintMethod = "printMSRMaskOperand";
188 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
189 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
190 def neg_zero : Operand<i32> {
191 let PrintMethod = "printNegZeroOperand";
194 //===----------------------------------------------------------------------===//
195 // ARM Instruction templates.
198 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
199 Format f, Domain d, string cstr, InstrItinClass itin>
201 let Namespace = "ARM";
206 bits<2> IndexModeBits = IM.Value;
208 bits<6> Form = F.Value;
210 bit isUnaryDataProc = 0;
211 bit canXformTo16Bit = 0;
213 // If this is a pseudo instruction, mark it isCodeGenOnly.
214 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
216 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
217 let TSFlags{4-0} = AM.Value;
218 let TSFlags{7-5} = SZ.Value;
219 let TSFlags{9-8} = IndexModeBits;
220 let TSFlags{15-10} = Form;
221 let TSFlags{16} = isUnaryDataProc;
222 let TSFlags{17} = canXformTo16Bit;
223 let TSFlags{19-18} = D.Value;
225 let Constraints = cstr;
226 let Itinerary = itin;
233 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
234 Format f, Domain d, string cstr, InstrItinClass itin>
235 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
237 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
238 // on by adding flavors to specific instructions.
239 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
240 Format f, Domain d, string cstr, InstrItinClass itin>
241 : InstTemplate<am, sz, im, f, d, cstr, itin>;
243 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
244 // FIXME: This really should derive from InstTemplate instead, as pseudos
245 // don't need encoding information. TableGen doesn't like that
246 // currently. Need to figure out why and fix it.
247 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
249 let OutOperandList = oops;
250 let InOperandList = iops;
251 let Pattern = pattern;
254 // PseudoInst that's ARM-mode only.
255 class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
257 : PseudoInst<oops, iops, itin, pattern> {
259 list<Predicate> Predicates = [IsARM];
262 // PseudoInst that's Thumb-mode only.
263 class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
265 : PseudoInst<oops, iops, itin, pattern> {
267 list<Predicate> Predicates = [IsThumb];
270 // PseudoInst that's Thumb2-mode only.
271 class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
273 : PseudoInst<oops, iops, itin, pattern> {
275 list<Predicate> Predicates = [IsThumb2];
277 // Almost all ARM instructions are predicable.
278 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
279 IndexMode im, Format f, InstrItinClass itin,
280 string opc, string asm, string cstr,
282 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
285 let OutOperandList = oops;
286 let InOperandList = !con(iops, (ins pred:$p));
287 let AsmString = !strconcat(opc, "${p}", asm);
288 let Pattern = pattern;
289 list<Predicate> Predicates = [IsARM];
292 // A few are not predicable
293 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
294 IndexMode im, Format f, InstrItinClass itin,
295 string opc, string asm, string cstr,
297 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
298 let OutOperandList = oops;
299 let InOperandList = iops;
300 let AsmString = !strconcat(opc, asm);
301 let Pattern = pattern;
302 let isPredicable = 0;
303 list<Predicate> Predicates = [IsARM];
306 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
307 // operand since by default it's a zero register. It will become an implicit def
308 // once it's "flipped".
309 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
310 IndexMode im, Format f, InstrItinClass itin,
311 string opc, string asm, string cstr,
313 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
314 bits<4> p; // Predicate operand
315 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
319 let OutOperandList = oops;
320 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
321 let AsmString = !strconcat(opc, "${s}${p}", asm);
322 let Pattern = pattern;
323 list<Predicate> Predicates = [IsARM];
327 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
328 IndexMode im, Format f, InstrItinClass itin,
329 string asm, string cstr, list<dag> pattern>
330 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
331 let OutOperandList = oops;
332 let InOperandList = iops;
334 let Pattern = pattern;
335 list<Predicate> Predicates = [IsARM];
338 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
339 string opc, string asm, list<dag> pattern>
340 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
341 opc, asm, "", pattern>;
342 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
343 string opc, string asm, list<dag> pattern>
344 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
345 opc, asm, "", pattern>;
346 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
347 string asm, list<dag> pattern>
348 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
350 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
353 opc, asm, "", pattern>;
355 // Ctrl flow instructions
356 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
357 string opc, string asm, list<dag> pattern>
358 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
359 opc, asm, "", pattern> {
360 let Inst{27-24} = opcod;
362 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
363 string asm, list<dag> pattern>
364 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
366 let Inst{27-24} = opcod;
369 // BR_JT instructions
370 class JTI<dag oops, dag iops, InstrItinClass itin,
371 string asm, list<dag> pattern>
372 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
375 // Atomic load/store instructions
376 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
377 string opc, string asm, list<dag> pattern>
378 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
379 opc, asm, "", pattern> {
382 let Inst{27-23} = 0b00011;
383 let Inst{22-21} = opcod;
385 let Inst{19-16} = Rn;
386 let Inst{15-12} = Rt;
387 let Inst{11-0} = 0b111110011111;
389 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
390 string opc, string asm, list<dag> pattern>
391 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
392 opc, asm, "", pattern> {
396 let Inst{27-23} = 0b00011;
397 let Inst{22-21} = opcod;
399 let Inst{19-16} = Rn;
400 let Inst{15-12} = Rd;
401 let Inst{11-4} = 0b11111001;
404 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
405 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
409 let Inst{27-23} = 0b00010;
411 let Inst{21-20} = 0b00;
412 let Inst{19-16} = Rn;
413 let Inst{15-12} = Rt;
414 let Inst{11-4} = 0b00001001;
418 // addrmode1 instructions
419 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
420 string opc, string asm, list<dag> pattern>
421 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
422 opc, asm, "", pattern> {
423 let Inst{24-21} = opcod;
424 let Inst{27-26} = 0b00;
426 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
427 string opc, string asm, list<dag> pattern>
428 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
429 opc, asm, "", pattern> {
430 let Inst{24-21} = opcod;
431 let Inst{27-26} = 0b00;
433 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
434 string asm, list<dag> pattern>
435 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
437 let Inst{24-21} = opcod;
438 let Inst{27-26} = 0b00;
443 // LDR/LDRB/STR/STRB/...
444 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
445 Format f, InstrItinClass itin, string opc, string asm,
447 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
449 let Inst{27-25} = op;
450 let Inst{24} = 1; // 24 == P
452 let Inst{22} = isByte;
453 let Inst{21} = 0; // 21 == W
456 // Indexed load/stores
457 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
458 IndexMode im, Format f, InstrItinClass itin, string opc,
459 string asm, string cstr, list<dag> pattern>
460 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
461 opc, asm, cstr, pattern> {
463 let Inst{27-26} = 0b01;
464 let Inst{24} = isPre; // P bit
465 let Inst{22} = isByte; // B bit
466 let Inst{21} = isPre; // W bit
467 let Inst{20} = isLd; // L bit
468 let Inst{15-12} = Rt;
470 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
471 IndexMode im, Format f, InstrItinClass itin, string opc,
472 string asm, string cstr, list<dag> pattern>
473 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
475 // AM2 store w/ two operands: (GPR, am2offset)
476 // {13} 1 == Rm, 0 == imm12
481 let Inst{25} = offset{13};
482 let Inst{23} = offset{12};
483 let Inst{19-16} = Rn;
484 let Inst{11-0} = offset{11-0};
487 // addrmode3 instructions
488 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
489 InstrItinClass itin, string opc, string asm, list<dag> pattern>
490 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
491 opc, asm, "", pattern> {
494 let Inst{27-25} = 0b000;
495 let Inst{24} = 1; // P bit
496 let Inst{23} = addr{8}; // U bit
497 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
498 let Inst{21} = 0; // W bit
499 let Inst{20} = op20; // L bit
500 let Inst{19-16} = addr{12-9}; // Rn
501 let Inst{15-12} = Rt; // Rt
502 let Inst{11-8} = addr{7-4}; // imm7_4/zero
504 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
507 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
508 IndexMode im, Format f, InstrItinClass itin, string opc,
509 string asm, string cstr, list<dag> pattern>
510 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
511 opc, asm, cstr, pattern> {
513 let Inst{27-25} = 0b000;
514 let Inst{24} = isPre; // P bit
515 let Inst{21} = isPre; // W bit
516 let Inst{20} = op20; // L bit
517 let Inst{15-12} = Rt; // Rt
520 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
521 IndexMode im, Format f, InstrItinClass itin, string opc,
522 string asm, string cstr, list<dag> pattern>
523 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
525 // AM3 store w/ two operands: (GPR, am3offset)
529 let Inst{27-25} = 0b000;
530 let Inst{23} = offset{8};
531 let Inst{22} = offset{9};
532 let Inst{19-16} = Rn;
533 let Inst{15-12} = Rt; // Rt
534 let Inst{11-8} = offset{7-4}; // imm7_4/zero
536 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
540 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
541 string opc, string asm, list<dag> pattern>
542 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
543 opc, asm, "", pattern> {
546 let Inst{27-25} = 0b000;
547 let Inst{24} = 1; // P bit
548 let Inst{23} = addr{8}; // U bit
549 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
550 let Inst{21} = 0; // W bit
551 let Inst{20} = 0; // L bit
552 let Inst{19-16} = addr{12-9}; // Rn
553 let Inst{15-12} = Rt; // Rt
554 let Inst{11-8} = addr{7-4}; // imm7_4/zero
556 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
559 // Pre-indexed stores
560 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
561 string opc, string asm, string cstr, list<dag> pattern>
562 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
563 opc, asm, cstr, pattern> {
565 let Inst{5} = 1; // H bit
566 let Inst{6} = 0; // S bit
568 let Inst{20} = 0; // L bit
569 let Inst{21} = 1; // W bit
570 let Inst{24} = 1; // P bit
571 let Inst{27-25} = 0b000;
573 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
574 string opc, string asm, string cstr, list<dag> pattern>
575 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
576 opc, asm, cstr, pattern> {
578 let Inst{5} = 1; // H bit
579 let Inst{6} = 1; // S bit
581 let Inst{20} = 0; // L bit
582 let Inst{21} = 1; // W bit
583 let Inst{24} = 1; // P bit
584 let Inst{27-25} = 0b000;
587 // Post-indexed stores
588 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
589 string opc, string asm, string cstr, list<dag> pattern>
590 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
591 opc, asm, cstr,pattern> {
593 let Inst{5} = 1; // H bit
594 let Inst{6} = 0; // S bit
596 let Inst{20} = 0; // L bit
597 let Inst{21} = 0; // W bit
598 let Inst{24} = 0; // P bit
599 let Inst{27-25} = 0b000;
601 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
602 string opc, string asm, string cstr, list<dag> pattern>
603 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
604 opc, asm, cstr, pattern> {
606 let Inst{5} = 1; // H bit
607 let Inst{6} = 1; // S bit
609 let Inst{20} = 0; // L bit
610 let Inst{21} = 0; // W bit
611 let Inst{24} = 0; // P bit
612 let Inst{27-25} = 0b000;
615 // addrmode4 instructions
616 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
617 string asm, string cstr, list<dag> pattern>
618 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
623 let Inst{27-25} = 0b100;
624 let Inst{22} = 0; // S bit
625 let Inst{19-16} = Rn;
626 let Inst{15-0} = regs;
629 // Unsigned multiply, multiply-accumulate instructions.
630 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
631 string opc, string asm, list<dag> pattern>
632 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
633 opc, asm, "", pattern> {
634 let Inst{7-4} = 0b1001;
635 let Inst{20} = 0; // S bit
636 let Inst{27-21} = opcod;
638 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
639 string opc, string asm, list<dag> pattern>
640 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
641 opc, asm, "", pattern> {
642 let Inst{7-4} = 0b1001;
643 let Inst{27-21} = opcod;
646 // Most significant word multiply
647 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
648 InstrItinClass itin, string opc, string asm, list<dag> pattern>
649 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
650 opc, asm, "", pattern> {
654 let Inst{7-4} = opc7_4;
656 let Inst{27-21} = opcod;
657 let Inst{19-16} = Rd;
661 // MSW multiple w/ Ra operand
662 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
663 InstrItinClass itin, string opc, string asm, list<dag> pattern>
664 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
666 let Inst{15-12} = Ra;
669 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
670 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
671 InstrItinClass itin, string opc, string asm, list<dag> pattern>
672 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
673 opc, asm, "", pattern> {
679 let Inst{27-21} = opcod;
680 let Inst{6-5} = bit6_5;
684 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
685 InstrItinClass itin, string opc, string asm, list<dag> pattern>
686 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
688 let Inst{19-16} = Rd;
691 // AMulxyI with Ra operand
692 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
693 InstrItinClass itin, string opc, string asm, list<dag> pattern>
694 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
696 let Inst{15-12} = Ra;
699 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
700 InstrItinClass itin, string opc, string asm, list<dag> pattern>
701 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
704 let Inst{19-16} = RdHi;
705 let Inst{15-12} = RdLo;
708 // Extend instructions.
709 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
710 string opc, string asm, list<dag> pattern>
711 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
712 opc, asm, "", pattern> {
713 // All AExtI instructions have Rd and Rm register operands.
716 let Inst{15-12} = Rd;
718 let Inst{7-4} = 0b0111;
719 let Inst{9-8} = 0b00;
720 let Inst{27-20} = opcod;
723 // Misc Arithmetic instructions.
724 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
725 InstrItinClass itin, string opc, string asm, list<dag> pattern>
726 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
727 opc, asm, "", pattern> {
730 let Inst{27-20} = opcod;
731 let Inst{19-16} = 0b1111;
732 let Inst{15-12} = Rd;
733 let Inst{11-8} = 0b1111;
734 let Inst{7-4} = opc7_4;
739 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
740 string opc, string asm, list<dag> pattern>
741 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
742 opc, asm, "", pattern> {
747 let Inst{27-20} = opcod;
748 let Inst{19-16} = Rn;
749 let Inst{15-12} = Rd;
750 let Inst{11-7} = sh{7-3};
752 let Inst{5-4} = 0b01;
756 //===----------------------------------------------------------------------===//
758 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
759 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
760 list<Predicate> Predicates = [IsARM];
762 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
763 list<Predicate> Predicates = [IsARM, HasV5TE];
765 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
766 list<Predicate> Predicates = [IsARM, HasV6];
769 //===----------------------------------------------------------------------===//
770 // Thumb Instruction Format Definitions.
773 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
774 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
775 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
776 let OutOperandList = oops;
777 let InOperandList = iops;
779 let Pattern = pattern;
780 list<Predicate> Predicates = [IsThumb];
783 // TI - Thumb instruction.
784 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
785 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
787 // Two-address instructions
788 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
790 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
793 // tBL, tBX 32-bit instructions
794 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
795 dag oops, dag iops, InstrItinClass itin, string asm,
797 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
799 let Inst{31-27} = opcod1;
800 let Inst{15-14} = opcod2;
801 let Inst{12} = opcod3;
804 // BR_JT instructions
805 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
807 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
810 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
811 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
812 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
813 let OutOperandList = oops;
814 let InOperandList = iops;
816 let Pattern = pattern;
817 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
820 class T1I<dag oops, dag iops, InstrItinClass itin,
821 string asm, list<dag> pattern>
822 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
823 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
824 string asm, list<dag> pattern>
825 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
827 // Two-address instructions
828 class T1It<dag oops, dag iops, InstrItinClass itin,
829 string asm, string cstr, list<dag> pattern>
830 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
833 // Thumb1 instruction that can either be predicated or set CPSR.
834 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
836 string opc, string asm, string cstr, list<dag> pattern>
837 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
838 let OutOperandList = !con(oops, (outs s_cc_out:$s));
839 let InOperandList = !con(iops, (ins pred:$p));
840 let AsmString = !strconcat(opc, "${s}${p}", asm);
841 let Pattern = pattern;
842 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
845 class T1sI<dag oops, dag iops, InstrItinClass itin,
846 string opc, string asm, list<dag> pattern>
847 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
849 // Two-address instructions
850 class T1sIt<dag oops, dag iops, InstrItinClass itin,
851 string opc, string asm, list<dag> pattern>
852 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
853 "$Rn = $Rdn", pattern>;
855 // Thumb1 instruction that can be predicated.
856 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
858 string opc, string asm, string cstr, list<dag> pattern>
859 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
860 let OutOperandList = oops;
861 let InOperandList = !con(iops, (ins pred:$p));
862 let AsmString = !strconcat(opc, "${p}", asm);
863 let Pattern = pattern;
864 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
867 class T1pI<dag oops, dag iops, InstrItinClass itin,
868 string opc, string asm, list<dag> pattern>
869 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
871 // Two-address instructions
872 class T1pIt<dag oops, dag iops, InstrItinClass itin,
873 string opc, string asm, list<dag> pattern>
874 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
875 "$Rn = $Rdn", pattern>;
877 class T1pIs<dag oops, dag iops,
878 InstrItinClass itin, string opc, string asm, list<dag> pattern>
879 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
881 class Encoding16 : Encoding {
882 let Inst{31-16} = 0x0000;
885 // A6.2 16-bit Thumb instruction encoding
886 class T1Encoding<bits<6> opcode> : Encoding16 {
887 let Inst{15-10} = opcode;
890 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
891 class T1General<bits<5> opcode> : Encoding16 {
892 let Inst{15-14} = 0b00;
893 let Inst{13-9} = opcode;
896 // A6.2.2 Data-processing encoding.
897 class T1DataProcessing<bits<4> opcode> : Encoding16 {
898 let Inst{15-10} = 0b010000;
899 let Inst{9-6} = opcode;
902 // A6.2.3 Special data instructions and branch and exchange encoding.
903 class T1Special<bits<4> opcode> : Encoding16 {
904 let Inst{15-10} = 0b010001;
905 let Inst{9-6} = opcode;
908 // A6.2.4 Load/store single data item encoding.
909 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
910 let Inst{15-12} = opA;
911 let Inst{11-9} = opB;
913 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
915 // Helper classes to encode Thumb1 loads and stores. For immediates, the
916 // following bits are used for "opA" (see A6.2.4):
918 // 0b0110 => Immediate, 4 bytes
919 // 0b1000 => Immediate, 2 bytes
920 // 0b0111 => Immediate, 1 byte
921 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
922 InstrItinClass itin, string opc, string asm,
924 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
925 T1LoadStore<0b0101, opcode> {
928 let Inst{8-6} = addr{5-3}; // Rm
929 let Inst{5-3} = addr{2-0}; // Rn
932 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
933 InstrItinClass itin, string opc, string asm,
935 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
936 T1LoadStore<opA, {opB,?,?}> {
939 let Inst{10-6} = addr{7-3}; // imm5
940 let Inst{5-3} = addr{2-0}; // Rn
944 // A6.2.5 Miscellaneous 16-bit instructions encoding.
945 class T1Misc<bits<7> opcode> : Encoding16 {
946 let Inst{15-12} = 0b1011;
947 let Inst{11-5} = opcode;
950 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
951 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
953 string opc, string asm, string cstr, list<dag> pattern>
954 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
955 let OutOperandList = oops;
956 let InOperandList = !con(iops, (ins pred:$p));
957 let AsmString = !strconcat(opc, "${p}", asm);
958 let Pattern = pattern;
959 list<Predicate> Predicates = [IsThumb2];
962 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
963 // input operand since by default it's a zero register. It will become an
964 // implicit def once it's "flipped".
966 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
968 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
970 string opc, string asm, string cstr, list<dag> pattern>
971 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
972 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
975 let OutOperandList = oops;
976 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
977 let AsmString = !strconcat(opc, "${s}${p}", asm);
978 let Pattern = pattern;
979 list<Predicate> Predicates = [IsThumb2];
983 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
985 string asm, string cstr, list<dag> pattern>
986 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
987 let OutOperandList = oops;
988 let InOperandList = iops;
990 let Pattern = pattern;
991 list<Predicate> Predicates = [IsThumb2];
994 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
996 string asm, string cstr, list<dag> pattern>
997 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
998 let OutOperandList = oops;
999 let InOperandList = iops;
1000 let AsmString = asm;
1001 let Pattern = pattern;
1002 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1005 class T2I<dag oops, dag iops, InstrItinClass itin,
1006 string opc, string asm, list<dag> pattern>
1007 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1008 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1009 string opc, string asm, list<dag> pattern>
1010 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1011 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1012 string opc, string asm, list<dag> pattern>
1013 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1014 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1015 string opc, string asm, list<dag> pattern>
1016 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1017 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1018 string opc, string asm, list<dag> pattern>
1019 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1020 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1021 string opc, string asm, list<dag> pattern>
1022 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1027 let Inst{31-25} = 0b1110100;
1029 let Inst{23} = addr{8};
1032 let Inst{20} = isLoad;
1033 let Inst{19-16} = addr{12-9};
1034 let Inst{15-12} = Rt{3-0};
1035 let Inst{11-8} = Rt2{3-0};
1036 let Inst{7-0} = addr{7-0};
1039 class T2sI<dag oops, dag iops, InstrItinClass itin,
1040 string opc, string asm, list<dag> pattern>
1041 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1043 class T2XI<dag oops, dag iops, InstrItinClass itin,
1044 string asm, list<dag> pattern>
1045 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1046 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1047 string asm, list<dag> pattern>
1048 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1050 // Two-address instructions
1051 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1052 string asm, string cstr, list<dag> pattern>
1053 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1055 // T2Iidxldst - Thumb2 indexed load / store instructions.
1056 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1058 AddrMode am, IndexMode im, InstrItinClass itin,
1059 string opc, string asm, string cstr, list<dag> pattern>
1060 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1061 let OutOperandList = oops;
1062 let InOperandList = !con(iops, (ins pred:$p));
1063 let AsmString = !strconcat(opc, "${p}", asm);
1064 let Pattern = pattern;
1065 list<Predicate> Predicates = [IsThumb2];
1066 let Inst{31-27} = 0b11111;
1067 let Inst{26-25} = 0b00;
1068 let Inst{24} = signed;
1070 let Inst{22-21} = opcod;
1071 let Inst{20} = load;
1073 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1074 let Inst{10} = pre; // The P bit.
1075 let Inst{8} = 1; // The W bit.
1078 let Inst{7-0} = addr{7-0};
1079 let Inst{9} = addr{8}; // Sign bit
1083 let Inst{15-12} = Rt{3-0};
1084 let Inst{19-16} = Rn{3-0};
1087 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1088 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1089 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1092 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1093 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1094 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1097 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1098 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1099 list<Predicate> Predicates = [IsThumb2];
1102 //===----------------------------------------------------------------------===//
1104 //===----------------------------------------------------------------------===//
1105 // ARM VFP Instruction templates.
1108 // Almost all VFP instructions are predicable.
1109 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1110 IndexMode im, Format f, InstrItinClass itin,
1111 string opc, string asm, string cstr, list<dag> pattern>
1112 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1114 let Inst{31-28} = p;
1115 let OutOperandList = oops;
1116 let InOperandList = !con(iops, (ins pred:$p));
1117 let AsmString = !strconcat(opc, "${p}", asm);
1118 let Pattern = pattern;
1119 let PostEncoderMethod = "VFPThumb2PostEncoder";
1120 list<Predicate> Predicates = [HasVFP2];
1124 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1125 IndexMode im, Format f, InstrItinClass itin,
1126 string asm, string cstr, list<dag> pattern>
1127 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1129 let Inst{31-28} = p;
1130 let OutOperandList = oops;
1131 let InOperandList = iops;
1132 let AsmString = asm;
1133 let Pattern = pattern;
1134 let PostEncoderMethod = "VFPThumb2PostEncoder";
1135 list<Predicate> Predicates = [HasVFP2];
1138 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1139 string opc, string asm, list<dag> pattern>
1140 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1141 opc, asm, "", pattern> {
1142 let PostEncoderMethod = "VFPThumb2PostEncoder";
1145 // ARM VFP addrmode5 loads and stores
1146 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1147 InstrItinClass itin,
1148 string opc, string asm, list<dag> pattern>
1149 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1150 VFPLdStFrm, itin, opc, asm, "", pattern> {
1151 // Instruction operands.
1155 // Encode instruction operands.
1156 let Inst{23} = addr{8}; // U (add = (U == '1'))
1157 let Inst{22} = Dd{4};
1158 let Inst{19-16} = addr{12-9}; // Rn
1159 let Inst{15-12} = Dd{3-0};
1160 let Inst{7-0} = addr{7-0}; // imm8
1162 // TODO: Mark the instructions with the appropriate subtarget info.
1163 let Inst{27-24} = opcod1;
1164 let Inst{21-20} = opcod2;
1165 let Inst{11-9} = 0b101;
1166 let Inst{8} = 1; // Double precision
1168 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1169 let D = VFPNeonDomain;
1172 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1173 InstrItinClass itin,
1174 string opc, string asm, list<dag> pattern>
1175 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1176 VFPLdStFrm, itin, opc, asm, "", pattern> {
1177 // Instruction operands.
1181 // Encode instruction operands.
1182 let Inst{23} = addr{8}; // U (add = (U == '1'))
1183 let Inst{22} = Sd{0};
1184 let Inst{19-16} = addr{12-9}; // Rn
1185 let Inst{15-12} = Sd{4-1};
1186 let Inst{7-0} = addr{7-0}; // imm8
1188 // TODO: Mark the instructions with the appropriate subtarget info.
1189 let Inst{27-24} = opcod1;
1190 let Inst{21-20} = opcod2;
1191 let Inst{11-9} = 0b101;
1192 let Inst{8} = 0; // Single precision
1195 // VFP Load / store multiple pseudo instructions.
1196 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1198 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1200 let OutOperandList = oops;
1201 let InOperandList = !con(iops, (ins pred:$p));
1202 let Pattern = pattern;
1203 list<Predicate> Predicates = [HasVFP2];
1206 // Load / store multiple
1207 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1208 string asm, string cstr, list<dag> pattern>
1209 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1210 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1211 // Instruction operands.
1215 // Encode instruction operands.
1216 let Inst{19-16} = Rn;
1217 let Inst{22} = regs{12};
1218 let Inst{15-12} = regs{11-8};
1219 let Inst{7-0} = regs{7-0};
1221 // TODO: Mark the instructions with the appropriate subtarget info.
1222 let Inst{27-25} = 0b110;
1223 let Inst{11-9} = 0b101;
1224 let Inst{8} = 1; // Double precision
1226 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1227 let D = VFPNeonDomain;
1230 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1231 string asm, string cstr, list<dag> pattern>
1232 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1233 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1234 // Instruction operands.
1238 // Encode instruction operands.
1239 let Inst{19-16} = Rn;
1240 let Inst{22} = regs{8};
1241 let Inst{15-12} = regs{12-9};
1242 let Inst{7-0} = regs{7-0};
1244 // TODO: Mark the instructions with the appropriate subtarget info.
1245 let Inst{27-25} = 0b110;
1246 let Inst{11-9} = 0b101;
1247 let Inst{8} = 0; // Single precision
1250 // Double precision, unary
1251 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1252 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1253 string asm, list<dag> pattern>
1254 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1255 // Instruction operands.
1259 // Encode instruction operands.
1260 let Inst{3-0} = Dm{3-0};
1261 let Inst{5} = Dm{4};
1262 let Inst{15-12} = Dd{3-0};
1263 let Inst{22} = Dd{4};
1265 let Inst{27-23} = opcod1;
1266 let Inst{21-20} = opcod2;
1267 let Inst{19-16} = opcod3;
1268 let Inst{11-9} = 0b101;
1269 let Inst{8} = 1; // Double precision
1270 let Inst{7-6} = opcod4;
1271 let Inst{4} = opcod5;
1274 // Double precision, binary
1275 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1276 dag iops, InstrItinClass itin, string opc, string asm,
1278 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1279 // Instruction operands.
1284 // Encode instruction operands.
1285 let Inst{3-0} = Dm{3-0};
1286 let Inst{5} = Dm{4};
1287 let Inst{19-16} = Dn{3-0};
1288 let Inst{7} = Dn{4};
1289 let Inst{15-12} = Dd{3-0};
1290 let Inst{22} = Dd{4};
1292 let Inst{27-23} = opcod1;
1293 let Inst{21-20} = opcod2;
1294 let Inst{11-9} = 0b101;
1295 let Inst{8} = 1; // Double precision
1300 // Single precision, unary
1301 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1302 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1303 string asm, list<dag> pattern>
1304 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1305 // Instruction operands.
1309 // Encode instruction operands.
1310 let Inst{3-0} = Sm{4-1};
1311 let Inst{5} = Sm{0};
1312 let Inst{15-12} = Sd{4-1};
1313 let Inst{22} = Sd{0};
1315 let Inst{27-23} = opcod1;
1316 let Inst{21-20} = opcod2;
1317 let Inst{19-16} = opcod3;
1318 let Inst{11-9} = 0b101;
1319 let Inst{8} = 0; // Single precision
1320 let Inst{7-6} = opcod4;
1321 let Inst{4} = opcod5;
1324 // Single precision unary, if no NEON. Same as ASuI except not available if
1326 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1327 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1328 string asm, list<dag> pattern>
1329 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1331 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1334 // Single precision, binary
1335 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1336 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1337 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1338 // Instruction operands.
1343 // Encode instruction operands.
1344 let Inst{3-0} = Sm{4-1};
1345 let Inst{5} = Sm{0};
1346 let Inst{19-16} = Sn{4-1};
1347 let Inst{7} = Sn{0};
1348 let Inst{15-12} = Sd{4-1};
1349 let Inst{22} = Sd{0};
1351 let Inst{27-23} = opcod1;
1352 let Inst{21-20} = opcod2;
1353 let Inst{11-9} = 0b101;
1354 let Inst{8} = 0; // Single precision
1359 // Single precision binary, if no NEON. Same as ASbI except not available if
1361 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1362 dag iops, InstrItinClass itin, string opc, string asm,
1364 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1365 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1367 // Instruction operands.
1372 // Encode instruction operands.
1373 let Inst{3-0} = Sm{4-1};
1374 let Inst{5} = Sm{0};
1375 let Inst{19-16} = Sn{4-1};
1376 let Inst{7} = Sn{0};
1377 let Inst{15-12} = Sd{4-1};
1378 let Inst{22} = Sd{0};
1381 // VFP conversion instructions
1382 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1383 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1385 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1386 let Inst{27-23} = opcod1;
1387 let Inst{21-20} = opcod2;
1388 let Inst{19-16} = opcod3;
1389 let Inst{11-8} = opcod4;
1394 // VFP conversion between floating-point and fixed-point
1395 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1396 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1398 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1399 // size (fixed-point number): sx == 0 ? 16 : 32
1400 let Inst{7} = op5; // sx
1403 // VFP conversion instructions, if no NEON
1404 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1405 dag oops, dag iops, InstrItinClass itin,
1406 string opc, string asm, list<dag> pattern>
1407 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1409 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1412 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1413 InstrItinClass itin,
1414 string opc, string asm, list<dag> pattern>
1415 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1416 let Inst{27-20} = opcod1;
1417 let Inst{11-8} = opcod2;
1421 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1422 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1423 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1425 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1426 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1427 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1429 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1430 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1431 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1433 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1434 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1435 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1437 //===----------------------------------------------------------------------===//
1439 //===----------------------------------------------------------------------===//
1440 // ARM NEON Instruction templates.
1443 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1444 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1446 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1447 let OutOperandList = oops;
1448 let InOperandList = !con(iops, (ins pred:$p));
1449 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1450 let Pattern = pattern;
1451 list<Predicate> Predicates = [HasNEON];
1454 // Same as NeonI except it does not have a "data type" specifier.
1455 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1456 InstrItinClass itin, string opc, string asm, string cstr,
1458 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1459 let OutOperandList = oops;
1460 let InOperandList = !con(iops, (ins pred:$p));
1461 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1462 let Pattern = pattern;
1463 list<Predicate> Predicates = [HasNEON];
1466 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1467 dag oops, dag iops, InstrItinClass itin,
1468 string opc, string dt, string asm, string cstr, list<dag> pattern>
1469 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1471 let Inst{31-24} = 0b11110100;
1472 let Inst{23} = op23;
1473 let Inst{21-20} = op21_20;
1474 let Inst{11-8} = op11_8;
1475 let Inst{7-4} = op7_4;
1477 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1483 let Inst{22} = Vd{4};
1484 let Inst{15-12} = Vd{3-0};
1485 let Inst{19-16} = Rn{3-0};
1486 let Inst{3-0} = Rm{3-0};
1489 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1490 dag oops, dag iops, InstrItinClass itin,
1491 string opc, string dt, string asm, string cstr, list<dag> pattern>
1492 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1493 dt, asm, cstr, pattern> {
1497 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1498 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1500 let OutOperandList = oops;
1501 let InOperandList = !con(iops, (ins pred:$p));
1502 list<Predicate> Predicates = [HasNEON];
1505 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1507 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1509 let OutOperandList = oops;
1510 let InOperandList = !con(iops, (ins pred:$p));
1511 let Pattern = pattern;
1512 list<Predicate> Predicates = [HasNEON];
1515 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1516 string opc, string dt, string asm, string cstr, list<dag> pattern>
1517 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1519 let Inst{31-25} = 0b1111001;
1520 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1523 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1524 string opc, string asm, string cstr, list<dag> pattern>
1525 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1527 let Inst{31-25} = 0b1111001;
1528 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1531 // NEON "one register and a modified immediate" format.
1532 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1534 dag oops, dag iops, InstrItinClass itin,
1535 string opc, string dt, string asm, string cstr,
1537 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1538 let Inst{23} = op23;
1539 let Inst{21-19} = op21_19;
1540 let Inst{11-8} = op11_8;
1546 // Instruction operands.
1550 let Inst{15-12} = Vd{3-0};
1551 let Inst{22} = Vd{4};
1552 let Inst{24} = SIMM{7};
1553 let Inst{18-16} = SIMM{6-4};
1554 let Inst{3-0} = SIMM{3-0};
1557 // NEON 2 vector register format.
1558 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1559 bits<5> op11_7, bit op6, bit op4,
1560 dag oops, dag iops, InstrItinClass itin,
1561 string opc, string dt, string asm, string cstr, list<dag> pattern>
1562 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1563 let Inst{24-23} = op24_23;
1564 let Inst{21-20} = op21_20;
1565 let Inst{19-18} = op19_18;
1566 let Inst{17-16} = op17_16;
1567 let Inst{11-7} = op11_7;
1571 // Instruction operands.
1575 let Inst{15-12} = Vd{3-0};
1576 let Inst{22} = Vd{4};
1577 let Inst{3-0} = Vm{3-0};
1578 let Inst{5} = Vm{4};
1581 // Same as N2V except it doesn't have a datatype suffix.
1582 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1583 bits<5> op11_7, bit op6, bit op4,
1584 dag oops, dag iops, InstrItinClass itin,
1585 string opc, string asm, string cstr, list<dag> pattern>
1586 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1587 let Inst{24-23} = op24_23;
1588 let Inst{21-20} = op21_20;
1589 let Inst{19-18} = op19_18;
1590 let Inst{17-16} = op17_16;
1591 let Inst{11-7} = op11_7;
1595 // Instruction operands.
1599 let Inst{15-12} = Vd{3-0};
1600 let Inst{22} = Vd{4};
1601 let Inst{3-0} = Vm{3-0};
1602 let Inst{5} = Vm{4};
1605 // NEON 2 vector register with immediate.
1606 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1607 dag oops, dag iops, Format f, InstrItinClass itin,
1608 string opc, string dt, string asm, string cstr, list<dag> pattern>
1609 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1610 let Inst{24} = op24;
1611 let Inst{23} = op23;
1612 let Inst{11-8} = op11_8;
1617 // Instruction operands.
1622 let Inst{15-12} = Vd{3-0};
1623 let Inst{22} = Vd{4};
1624 let Inst{3-0} = Vm{3-0};
1625 let Inst{5} = Vm{4};
1626 let Inst{21-16} = SIMM{5-0};
1629 // NEON 3 vector register format.
1630 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1631 dag oops, dag iops, Format f, InstrItinClass itin,
1632 string opc, string dt, string asm, string cstr, list<dag> pattern>
1633 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1634 let Inst{24} = op24;
1635 let Inst{23} = op23;
1636 let Inst{21-20} = op21_20;
1637 let Inst{11-8} = op11_8;
1641 // Instruction operands.
1646 let Inst{15-12} = Vd{3-0};
1647 let Inst{22} = Vd{4};
1648 let Inst{19-16} = Vn{3-0};
1649 let Inst{7} = Vn{4};
1650 let Inst{3-0} = Vm{3-0};
1651 let Inst{5} = Vm{4};
1654 // Same as N3V except it doesn't have a data type suffix.
1655 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1657 dag oops, dag iops, Format f, InstrItinClass itin,
1658 string opc, string asm, string cstr, list<dag> pattern>
1659 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1660 let Inst{24} = op24;
1661 let Inst{23} = op23;
1662 let Inst{21-20} = op21_20;
1663 let Inst{11-8} = op11_8;
1667 // Instruction operands.
1672 let Inst{15-12} = Vd{3-0};
1673 let Inst{22} = Vd{4};
1674 let Inst{19-16} = Vn{3-0};
1675 let Inst{7} = Vn{4};
1676 let Inst{3-0} = Vm{3-0};
1677 let Inst{5} = Vm{4};
1680 // NEON VMOVs between scalar and core registers.
1681 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1682 dag oops, dag iops, Format f, InstrItinClass itin,
1683 string opc, string dt, string asm, list<dag> pattern>
1684 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1686 let Inst{27-20} = opcod1;
1687 let Inst{11-8} = opcod2;
1688 let Inst{6-5} = opcod3;
1691 let OutOperandList = oops;
1692 let InOperandList = !con(iops, (ins pred:$p));
1693 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1694 let Pattern = pattern;
1695 list<Predicate> Predicates = [HasNEON];
1697 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1704 let Inst{31-28} = p{3-0};
1706 let Inst{19-16} = V{3-0};
1707 let Inst{15-12} = R{3-0};
1709 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1710 dag oops, dag iops, InstrItinClass itin,
1711 string opc, string dt, string asm, list<dag> pattern>
1712 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1713 opc, dt, asm, pattern>;
1714 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1715 dag oops, dag iops, InstrItinClass itin,
1716 string opc, string dt, string asm, list<dag> pattern>
1717 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1718 opc, dt, asm, pattern>;
1719 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1720 dag oops, dag iops, InstrItinClass itin,
1721 string opc, string dt, string asm, list<dag> pattern>
1722 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1723 opc, dt, asm, pattern>;
1725 // Vector Duplicate Lane (from scalar to all elements)
1726 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1727 InstrItinClass itin, string opc, string dt, string asm,
1729 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1730 let Inst{24-23} = 0b11;
1731 let Inst{21-20} = 0b11;
1732 let Inst{19-16} = op19_16;
1733 let Inst{11-7} = 0b11000;
1741 let Inst{22} = Vd{4};
1742 let Inst{15-12} = Vd{3-0};
1743 let Inst{5} = Vm{4};
1744 let Inst{3-0} = Vm{3-0};
1747 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1748 // for single-precision FP.
1749 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1750 list<Predicate> Predicates = [HasNEON,UseNEONForFP];