1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
28 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
41 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
46 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
47 return &ARM::GPRRegClass;
50 /// Return true if the instruction is a register to register move and
51 /// leave the source and dest operands in the passed parameters.
53 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
54 unsigned &SrcReg, unsigned &DstReg) const {
55 unsigned oc = MI.getOpcode();
61 SrcReg = MI.getOperand(1).getReg();
62 DstReg = MI.getOperand(0).getReg();
66 assert(MI.getDesc().getNumOperands() >= 2 &&
67 MI.getOperand(0).isRegister() &&
68 MI.getOperand(1).isRegister() &&
69 "Invalid ARM MOV instruction");
70 SrcReg = MI.getOperand(1).getReg();
71 DstReg = MI.getOperand(0).getReg();
76 unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
77 switch (MI->getOpcode()) {
80 if (MI->getOperand(1).isFrameIndex() &&
81 MI->getOperand(2).isRegister() &&
82 MI->getOperand(3).isImmediate() &&
83 MI->getOperand(2).getReg() == 0 &&
84 MI->getOperand(3).getImm() == 0) {
85 FrameIndex = MI->getOperand(1).getIndex();
86 return MI->getOperand(0).getReg();
91 if (MI->getOperand(1).isFrameIndex() &&
92 MI->getOperand(2).isImmediate() &&
93 MI->getOperand(2).getImm() == 0) {
94 FrameIndex = MI->getOperand(1).getIndex();
95 return MI->getOperand(0).getReg();
99 if (MI->getOperand(1).isFrameIndex() &&
100 MI->getOperand(2).isImmediate() &&
101 MI->getOperand(2).getImm() == 0) {
102 FrameIndex = MI->getOperand(1).getIndex();
103 return MI->getOperand(0).getReg();
110 unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
111 switch (MI->getOpcode()) {
114 if (MI->getOperand(1).isFrameIndex() &&
115 MI->getOperand(2).isRegister() &&
116 MI->getOperand(3).isImmediate() &&
117 MI->getOperand(2).getReg() == 0 &&
118 MI->getOperand(3).getImm() == 0) {
119 FrameIndex = MI->getOperand(1).getIndex();
120 return MI->getOperand(0).getReg();
125 if (MI->getOperand(1).isFrameIndex() &&
126 MI->getOperand(2).isImmediate() &&
127 MI->getOperand(2).getImm() == 0) {
128 FrameIndex = MI->getOperand(1).getIndex();
129 return MI->getOperand(0).getReg();
133 if (MI->getOperand(1).isFrameIndex() &&
134 MI->getOperand(2).isImmediate() &&
135 MI->getOperand(2).getImm() == 0) {
136 FrameIndex = MI->getOperand(1).getIndex();
137 return MI->getOperand(0).getReg();
144 static unsigned getUnindexedOpcode(unsigned Opc) {
157 case ARM::LDRSH_POST:
160 case ARM::LDRSB_POST:
176 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
177 MachineBasicBlock::iterator &MBBI,
178 LiveVariables &LV) const {
182 MachineInstr *MI = MBBI;
183 unsigned TSFlags = MI->getDesc().TSFlags;
185 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
186 default: return NULL;
187 case ARMII::IndexModePre:
190 case ARMII::IndexModePost:
194 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
196 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
200 MachineInstr *UpdateMI = NULL;
201 MachineInstr *MemMI = NULL;
202 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
203 const TargetInstrDesc &TID = MI->getDesc();
204 unsigned NumOps = TID.getNumOperands();
205 bool isLoad = !TID.mayStore();
206 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
207 const MachineOperand &Base = MI->getOperand(2);
208 const MachineOperand &Offset = MI->getOperand(NumOps-3);
209 unsigned WBReg = WB.getReg();
210 unsigned BaseReg = Base.getReg();
211 unsigned OffReg = Offset.getReg();
212 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
213 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
216 assert(false && "Unknown indexed op!");
218 case ARMII::AddrMode2: {
219 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
220 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
222 int SOImmVal = ARM_AM::getSOImmVal(Amt);
224 // Can't encode it in a so_imm operand. This transformation will
225 // add more than 1 instruction. Abandon!
227 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
228 .addReg(BaseReg).addImm(SOImmVal)
229 .addImm(Pred).addReg(0).addReg(0);
230 } else if (Amt != 0) {
231 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
232 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
233 UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
234 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
235 .addImm(Pred).addReg(0).addReg(0);
237 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
238 .addReg(BaseReg).addReg(OffReg)
239 .addImm(Pred).addReg(0).addReg(0);
242 case ARMII::AddrMode3 : {
243 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
244 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
246 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
247 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
248 .addReg(BaseReg).addImm(Amt)
249 .addImm(Pred).addReg(0).addReg(0);
251 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
252 .addReg(BaseReg).addReg(OffReg)
253 .addImm(Pred).addReg(0).addReg(0);
258 std::vector<MachineInstr*> NewMIs;
261 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
262 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
264 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
265 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
266 NewMIs.push_back(MemMI);
267 NewMIs.push_back(UpdateMI);
270 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
271 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
273 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
274 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
276 UpdateMI->getOperand(0).setIsDead();
277 NewMIs.push_back(UpdateMI);
278 NewMIs.push_back(MemMI);
281 // Transfer LiveVariables states, kill / dead info.
282 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
283 MachineOperand &MO = MI->getOperand(i);
284 if (MO.isRegister() && MO.getReg() &&
285 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
286 unsigned Reg = MO.getReg();
287 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
289 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
291 LV.addVirtualRegisterDead(Reg, NewMI);
293 if (MO.isUse() && MO.isKill()) {
294 for (unsigned j = 0; j < 2; ++j) {
295 // Look at the two new MI's in reverse order.
296 MachineInstr *NewMI = NewMIs[j];
297 if (!NewMI->readsRegister(Reg))
299 LV.addVirtualRegisterKilled(Reg, NewMI);
300 if (VI.removeKill(MI))
301 VI.Kills.push_back(NewMI);
308 MFI->insert(MBBI, NewMIs[1]);
309 MFI->insert(MBBI, NewMIs[0]);
314 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
315 MachineBasicBlock *&FBB,
316 std::vector<MachineOperand> &Cond) const {
317 // If the block has no terminators, it just falls into the block after it.
318 MachineBasicBlock::iterator I = MBB.end();
319 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
322 // Get the last instruction in the block.
323 MachineInstr *LastInst = I;
325 // If there is only one terminator instruction, process it.
326 unsigned LastOpc = LastInst->getOpcode();
327 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
328 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
329 TBB = LastInst->getOperand(0).getMBB();
332 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
333 // Block ends with fall-through condbranch.
334 TBB = LastInst->getOperand(0).getMBB();
335 Cond.push_back(LastInst->getOperand(1));
336 Cond.push_back(LastInst->getOperand(2));
339 return true; // Can't handle indirect branch.
342 // Get the instruction before it if it is a terminator.
343 MachineInstr *SecondLastInst = I;
345 // If there are three terminators, we don't know what sort of block this is.
346 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
349 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
350 unsigned SecondLastOpc = SecondLastInst->getOpcode();
351 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
352 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
353 TBB = SecondLastInst->getOperand(0).getMBB();
354 Cond.push_back(SecondLastInst->getOperand(1));
355 Cond.push_back(SecondLastInst->getOperand(2));
356 FBB = LastInst->getOperand(0).getMBB();
360 // If the block ends with two unconditional branches, handle it. The second
361 // one is not executed, so remove it.
362 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
363 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
364 TBB = SecondLastInst->getOperand(0).getMBB();
366 I->eraseFromParent();
370 // Likewise if it ends with a branch table followed by an unconditional branch.
371 // The branch folder can create these, and we must get rid of them for
372 // correctness of Thumb constant islands.
373 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
374 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
375 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
377 I->eraseFromParent();
381 // Otherwise, can't handle this.
386 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
387 MachineFunction &MF = *MBB.getParent();
388 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
389 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
390 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
392 MachineBasicBlock::iterator I = MBB.end();
393 if (I == MBB.begin()) return 0;
395 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
398 // Remove the branch.
399 I->eraseFromParent();
403 if (I == MBB.begin()) return 1;
405 if (I->getOpcode() != BccOpc)
408 // Remove the branch.
409 I->eraseFromParent();
413 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
414 MachineBasicBlock *FBB,
415 const std::vector<MachineOperand> &Cond) const {
416 MachineFunction &MF = *MBB.getParent();
417 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
418 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
419 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
421 // Shouldn't be a fall through.
422 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
423 assert((Cond.size() == 2 || Cond.size() == 0) &&
424 "ARM branch conditions have two components!");
427 if (Cond.empty()) // Unconditional branch?
428 BuildMI(&MBB, get(BOpc)).addMBB(TBB);
430 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
431 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
435 // Two-way conditional branch.
436 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
437 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
438 BuildMI(&MBB, get(BOpc)).addMBB(FBB);
442 void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
443 MachineBasicBlock::iterator I,
444 unsigned DestReg, unsigned SrcReg,
445 const TargetRegisterClass *DestRC,
446 const TargetRegisterClass *SrcRC) const {
447 if (DestRC != SrcRC) {
448 cerr << "Not yet supported!";
452 if (DestRC == ARM::GPRRegisterClass) {
453 MachineFunction &MF = *MBB.getParent();
454 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
455 if (AFI->isThumbFunction())
456 BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg);
458 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg)
460 } else if (DestRC == ARM::SPRRegisterClass)
461 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg)
463 else if (DestRC == ARM::DPRRegisterClass)
464 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
470 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
471 MachineOperand &MO) {
473 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
474 else if (MO.isImmediate())
475 MIB = MIB.addImm(MO.getImm());
476 else if (MO.isFrameIndex())
477 MIB = MIB.addFrameIndex(MO.getIndex());
479 assert(0 && "Unknown operand for ARMInstrAddOperand!");
485 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
486 unsigned SrcReg, bool isKill, int FI,
487 const TargetRegisterClass *RC) const {
488 if (RC == ARM::GPRRegisterClass) {
489 MachineFunction &MF = *MBB.getParent();
490 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
491 if (AFI->isThumbFunction())
492 BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
493 .addFrameIndex(FI).addImm(0);
495 AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
496 .addReg(SrcReg, false, false, isKill)
497 .addFrameIndex(FI).addReg(0).addImm(0));
498 } else if (RC == ARM::DPRRegisterClass) {
499 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
500 .addReg(SrcReg, false, false, isKill)
501 .addFrameIndex(FI).addImm(0));
503 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
504 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
505 .addReg(SrcReg, false, false, isKill)
506 .addFrameIndex(FI).addImm(0));
510 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
512 SmallVectorImpl<MachineOperand> &Addr,
513 const TargetRegisterClass *RC,
514 SmallVectorImpl<MachineInstr*> &NewMIs) const {
516 if (RC == ARM::GPRRegisterClass) {
517 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
518 if (AFI->isThumbFunction()) {
519 Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
520 MachineInstrBuilder MIB =
521 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
522 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
523 MIB = ARMInstrAddOperand(MIB, Addr[i]);
524 NewMIs.push_back(MIB);
528 } else if (RC == ARM::DPRRegisterClass) {
531 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
535 MachineInstrBuilder MIB =
536 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
537 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
538 MIB = ARMInstrAddOperand(MIB, Addr[i]);
540 NewMIs.push_back(MIB);
545 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
546 unsigned DestReg, int FI,
547 const TargetRegisterClass *RC) const {
548 if (RC == ARM::GPRRegisterClass) {
549 MachineFunction &MF = *MBB.getParent();
550 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
551 if (AFI->isThumbFunction())
552 BuildMI(MBB, I, get(ARM::tRestore), DestReg)
553 .addFrameIndex(FI).addImm(0);
555 AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
556 .addFrameIndex(FI).addReg(0).addImm(0));
557 } else if (RC == ARM::DPRRegisterClass) {
558 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
559 .addFrameIndex(FI).addImm(0));
561 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
562 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
563 .addFrameIndex(FI).addImm(0));
567 void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
568 SmallVectorImpl<MachineOperand> &Addr,
569 const TargetRegisterClass *RC,
570 SmallVectorImpl<MachineInstr*> &NewMIs) const {
572 if (RC == ARM::GPRRegisterClass) {
573 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
574 if (AFI->isThumbFunction()) {
575 Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
576 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
577 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
578 MIB = ARMInstrAddOperand(MIB, Addr[i]);
579 NewMIs.push_back(MIB);
583 } else if (RC == ARM::DPRRegisterClass) {
586 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
590 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
591 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
592 MIB = ARMInstrAddOperand(MIB, Addr[i]);
594 NewMIs.push_back(MIB);
598 bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
599 MachineBasicBlock::iterator MI,
600 const std::vector<CalleeSavedInfo> &CSI) const {
601 MachineFunction &MF = *MBB.getParent();
602 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
603 if (!AFI->isThumbFunction() || CSI.empty())
606 MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH));
607 for (unsigned i = CSI.size(); i != 0; --i) {
608 unsigned Reg = CSI[i-1].getReg();
609 // Add the callee-saved register as live-in. It's killed at the spill.
611 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
616 bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
617 MachineBasicBlock::iterator MI,
618 const std::vector<CalleeSavedInfo> &CSI) const {
619 MachineFunction &MF = *MBB.getParent();
620 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
621 if (!AFI->isThumbFunction() || CSI.empty())
624 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
625 MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP));
626 MBB.insert(MI, PopMI);
627 for (unsigned i = CSI.size(); i != 0; --i) {
628 unsigned Reg = CSI[i-1].getReg();
629 if (Reg == ARM::LR) {
630 // Special epilogue for vararg functions. See emitEpilogue
634 PopMI->setDesc(get(ARM::tPOP_RET));
637 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
642 MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF,
644 SmallVectorImpl<unsigned> &Ops,
646 if (Ops.size() != 1) return NULL;
648 unsigned OpNum = Ops[0];
649 unsigned Opc = MI->getOpcode();
650 MachineInstr *NewMI = NULL;
654 if (MI->getOperand(4).getReg() == ARM::CPSR)
655 // If it is updating CPSR, then it cannot be foled.
657 unsigned Pred = MI->getOperand(2).getImm();
658 unsigned PredReg = MI->getOperand(3).getReg();
659 if (OpNum == 0) { // move -> store
660 unsigned SrcReg = MI->getOperand(1).getReg();
661 NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
662 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
663 } else { // move -> load
664 unsigned DstReg = MI->getOperand(0).getReg();
665 NewMI = BuildMI(get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
666 .addImm(0).addImm(Pred).addReg(PredReg);
671 if (OpNum == 0) { // move -> store
672 unsigned SrcReg = MI->getOperand(1).getReg();
673 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
674 // tSpill cannot take a high register operand.
676 NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
678 } else { // move -> load
679 unsigned DstReg = MI->getOperand(0).getReg();
680 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
681 // tRestore cannot target a high register operand.
683 NewMI = BuildMI(get(ARM::tRestore), DstReg).addFrameIndex(FI)
689 unsigned Pred = MI->getOperand(2).getImm();
690 unsigned PredReg = MI->getOperand(3).getReg();
691 if (OpNum == 0) { // move -> store
692 unsigned SrcReg = MI->getOperand(1).getReg();
693 NewMI = BuildMI(get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
694 .addImm(0).addImm(Pred).addReg(PredReg);
695 } else { // move -> load
696 unsigned DstReg = MI->getOperand(0).getReg();
697 NewMI = BuildMI(get(ARM::FLDS), DstReg).addFrameIndex(FI)
698 .addImm(0).addImm(Pred).addReg(PredReg);
703 unsigned Pred = MI->getOperand(2).getImm();
704 unsigned PredReg = MI->getOperand(3).getReg();
705 if (OpNum == 0) { // move -> store
706 unsigned SrcReg = MI->getOperand(1).getReg();
707 NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
708 .addImm(0).addImm(Pred).addReg(PredReg);
709 } else { // move -> load
710 unsigned DstReg = MI->getOperand(0).getReg();
711 NewMI = BuildMI(get(ARM::FLDD), DstReg).addFrameIndex(FI)
712 .addImm(0).addImm(Pred).addReg(PredReg);
719 NewMI->copyKillDeadInfo(MI);
723 bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
724 SmallVectorImpl<unsigned> &Ops) const {
725 if (Ops.size() != 1) return false;
727 unsigned OpNum = Ops[0];
728 unsigned Opc = MI->getOpcode();
732 // If it is updating CPSR, then it cannot be foled.
733 return MI->getOperand(4).getReg() != ARM::CPSR;
735 if (OpNum == 0) { // move -> store
736 unsigned SrcReg = MI->getOperand(1).getReg();
737 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
738 // tSpill cannot take a high register operand.
740 } else { // move -> load
741 unsigned DstReg = MI->getOperand(0).getReg();
742 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
743 // tRestore cannot target a high register operand.
756 bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
757 if (MBB.empty()) return false;
759 switch (MBB.back().getOpcode()) {
760 case ARM::BX_RET: // Return.
763 case ARM::tBX_RET_vararg:
766 case ARM::tB: // Uncond branch.
768 case ARM::BR_JTr: // Jumptable branch.
769 case ARM::BR_JTm: // Jumptable branch through mem.
770 case ARM::BR_JTadd: // Jumptable branch add to pc.
772 default: return false;
777 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
778 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
779 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
783 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
784 int PIdx = MI->findFirstPredOperandIdx();
785 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
788 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
789 const std::vector<MachineOperand> &Pred) const {
790 unsigned Opc = MI->getOpcode();
791 if (Opc == ARM::B || Opc == ARM::tB) {
792 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
793 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
794 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
798 int PIdx = MI->findFirstPredOperandIdx();
800 MachineOperand &PMO = MI->getOperand(PIdx);
801 PMO.setImm(Pred[0].getImm());
802 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
809 ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
810 const std::vector<MachineOperand> &Pred2) const{
811 if (Pred1.size() > 2 || Pred2.size() > 2)
814 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
815 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
825 return CC2 == ARMCC::HI;
827 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
829 return CC2 == ARMCC::GT;
831 return CC2 == ARMCC::LT;
835 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
836 std::vector<MachineOperand> &Pred) const {
837 const TargetInstrDesc &TID = MI->getDesc();
838 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
842 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
843 const MachineOperand &MO = MI->getOperand(i);
844 if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
854 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
855 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
856 unsigned JTI) DISABLE_INLINE;
857 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
859 return JT[JTI].MBBs.size();
862 /// GetInstSize - Return the size of the specified MachineInstr.
864 unsigned ARM::GetInstSize(MachineInstr *MI) {
865 MachineBasicBlock &MBB = *MI->getParent();
866 const MachineFunction *MF = MBB.getParent();
867 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
869 // Basic size info comes from the TSFlags field.
870 const TargetInstrDesc &TID = MI->getDesc();
871 unsigned TSFlags = TID.TSFlags;
873 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
875 // If this machine instr is an inline asm, measure it.
876 if (MI->getOpcode() == ARM::INLINEASM)
877 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
878 if (MI->getOpcode() == ARM::LABEL)
880 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
882 assert(0 && "Unknown or unset size field for instr!");
884 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
885 case ARMII::Size4Bytes: return 4; // Arm instruction.
886 case ARMII::Size2Bytes: return 2; // Thumb instruction.
887 case ARMII::SizeSpecial: {
888 switch (MI->getOpcode()) {
889 case ARM::CONSTPOOL_ENTRY:
890 // If this machine instr is a constant pool entry, its size is recorded as
892 return MI->getOperand(2).getImm();
897 // These are jumptable branches, i.e. a branch followed by an inlined
898 // jumptable. The size is 4 + 4 * number of entries.
899 unsigned NumOps = TID.getNumOperands();
900 MachineOperand JTOP =
901 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
902 unsigned JTI = JTOP.getIndex();
903 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
904 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
905 assert(JTI < JT.size());
906 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
907 // 4 aligned. The assembler / linker may add 2 byte padding just before
908 // the JT entries. The size does not include this padding; the
909 // constant islands pass does separate bookkeeping for it.
910 // FIXME: If we know the size of the function is less than (1 << 16) *2
911 // bytes, we can use 16-bit entries instead. Then there won't be an
913 return getNumJTEntries(JT, JTI) * 4 +
914 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
917 // Otherwise, pseudo-instruction sizes are zero.
924 /// GetFunctionSize - Returns the size of the specified MachineFunction.
926 unsigned ARM::GetFunctionSize(MachineFunction &MF) {
928 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
930 MachineBasicBlock &MBB = *MBBI;
931 for (MachineBasicBlock::iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
932 FnSize += ARM::GetInstSize(I);