1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
28 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
41 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
46 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
47 return &ARM::GPRRegClass;
50 /// Return true if the instruction is a register to register move and
51 /// leave the source and dest operands in the passed parameters.
53 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
54 unsigned &SrcReg, unsigned &DstReg) const {
55 unsigned oc = MI.getOpcode();
61 SrcReg = MI.getOperand(1).getReg();
62 DstReg = MI.getOperand(0).getReg();
66 assert(MI.getDesc().getNumOperands() >= 2 &&
67 MI.getOperand(0).isRegister() &&
68 MI.getOperand(1).isRegister() &&
69 "Invalid ARM MOV instruction");
70 SrcReg = MI.getOperand(1).getReg();
71 DstReg = MI.getOperand(0).getReg();
76 unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
77 switch (MI->getOpcode()) {
80 if (MI->getOperand(1).isFrameIndex() &&
81 MI->getOperand(2).isRegister() &&
82 MI->getOperand(3).isImmediate() &&
83 MI->getOperand(2).getReg() == 0 &&
84 MI->getOperand(3).getImm() == 0) {
85 FrameIndex = MI->getOperand(1).getIndex();
86 return MI->getOperand(0).getReg();
91 if (MI->getOperand(1).isFrameIndex() &&
92 MI->getOperand(2).isImmediate() &&
93 MI->getOperand(2).getImm() == 0) {
94 FrameIndex = MI->getOperand(1).getIndex();
95 return MI->getOperand(0).getReg();
99 if (MI->getOperand(1).isFrameIndex() &&
100 MI->getOperand(2).isImmediate() &&
101 MI->getOperand(2).getImm() == 0) {
102 FrameIndex = MI->getOperand(1).getIndex();
103 return MI->getOperand(0).getReg();
110 unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
111 switch (MI->getOpcode()) {
114 if (MI->getOperand(1).isFrameIndex() &&
115 MI->getOperand(2).isRegister() &&
116 MI->getOperand(3).isImmediate() &&
117 MI->getOperand(2).getReg() == 0 &&
118 MI->getOperand(3).getImm() == 0) {
119 FrameIndex = MI->getOperand(1).getIndex();
120 return MI->getOperand(0).getReg();
125 if (MI->getOperand(1).isFrameIndex() &&
126 MI->getOperand(2).isImmediate() &&
127 MI->getOperand(2).getImm() == 0) {
128 FrameIndex = MI->getOperand(1).getIndex();
129 return MI->getOperand(0).getReg();
133 if (MI->getOperand(1).isFrameIndex() &&
134 MI->getOperand(2).isImmediate() &&
135 MI->getOperand(2).getImm() == 0) {
136 FrameIndex = MI->getOperand(1).getIndex();
137 return MI->getOperand(0).getReg();
144 static unsigned getUnindexedOpcode(unsigned Opc) {
157 case ARM::LDRSH_POST:
160 case ARM::LDRSB_POST:
176 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
177 MachineBasicBlock::iterator &MBBI,
178 LiveVariables &LV) const {
182 MachineInstr *MI = MBBI;
183 unsigned TSFlags = MI->getDesc().TSFlags;
185 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
186 default: return NULL;
187 case ARMII::IndexModePre:
190 case ARMII::IndexModePost:
194 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
196 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
200 MachineInstr *UpdateMI = NULL;
201 MachineInstr *MemMI = NULL;
202 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
203 const TargetInstrDesc &TID = MI->getDesc();
204 unsigned NumOps = TID.getNumOperands();
205 bool isLoad = TID.isSimpleLoad();
206 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
207 const MachineOperand &Base = MI->getOperand(2);
208 const MachineOperand &Offset = MI->getOperand(NumOps-3);
209 unsigned WBReg = WB.getReg();
210 unsigned BaseReg = Base.getReg();
211 unsigned OffReg = Offset.getReg();
212 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
213 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
216 assert(false && "Unknown indexed op!");
218 case ARMII::AddrMode2: {
219 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
220 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
222 int SOImmVal = ARM_AM::getSOImmVal(Amt);
224 // Can't encode it in a so_imm operand. This transformation will
225 // add more than 1 instruction. Abandon!
227 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
228 .addReg(BaseReg).addImm(SOImmVal)
229 .addImm(Pred).addReg(0).addReg(0);
230 } else if (Amt != 0) {
231 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
232 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
233 UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
234 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
235 .addImm(Pred).addReg(0).addReg(0);
237 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
238 .addReg(BaseReg).addReg(OffReg)
239 .addImm(Pred).addReg(0).addReg(0);
242 case ARMII::AddrMode3 : {
243 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
244 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
246 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
247 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
248 .addReg(BaseReg).addImm(Amt)
249 .addImm(Pred).addReg(0).addReg(0);
251 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
252 .addReg(BaseReg).addReg(OffReg)
253 .addImm(Pred).addReg(0).addReg(0);
258 std::vector<MachineInstr*> NewMIs;
261 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
262 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
264 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
265 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
266 NewMIs.push_back(MemMI);
267 NewMIs.push_back(UpdateMI);
270 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
271 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
273 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
274 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
276 UpdateMI->getOperand(0).setIsDead();
277 NewMIs.push_back(UpdateMI);
278 NewMIs.push_back(MemMI);
281 // Transfer LiveVariables states, kill / dead info.
282 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
283 MachineOperand &MO = MI->getOperand(i);
284 if (MO.isRegister() && MO.getReg() &&
285 MRegisterInfo::isVirtualRegister(MO.getReg())) {
286 unsigned Reg = MO.getReg();
287 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
289 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
291 LV.addVirtualRegisterDead(Reg, NewMI);
292 // Update the defining instruction.
293 if (VI.DefInst == MI)
296 if (MO.isUse() && MO.isKill()) {
297 for (unsigned j = 0; j < 2; ++j) {
298 // Look at the two new MI's in reverse order.
299 MachineInstr *NewMI = NewMIs[j];
300 int NIdx = NewMI->findRegisterUseOperandIdx(Reg);
303 LV.addVirtualRegisterKilled(Reg, NewMI);
304 if (VI.removeKill(MI))
305 VI.Kills.push_back(NewMI);
312 MFI->insert(MBBI, NewMIs[1]);
313 MFI->insert(MBBI, NewMIs[0]);
318 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
319 MachineBasicBlock *&FBB,
320 std::vector<MachineOperand> &Cond) const {
321 // If the block has no terminators, it just falls into the block after it.
322 MachineBasicBlock::iterator I = MBB.end();
323 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
326 // Get the last instruction in the block.
327 MachineInstr *LastInst = I;
329 // If there is only one terminator instruction, process it.
330 unsigned LastOpc = LastInst->getOpcode();
331 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
332 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
333 TBB = LastInst->getOperand(0).getMBB();
336 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
337 // Block ends with fall-through condbranch.
338 TBB = LastInst->getOperand(0).getMBB();
339 Cond.push_back(LastInst->getOperand(1));
340 Cond.push_back(LastInst->getOperand(2));
343 return true; // Can't handle indirect branch.
346 // Get the instruction before it if it is a terminator.
347 MachineInstr *SecondLastInst = I;
349 // If there are three terminators, we don't know what sort of block this is.
350 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
353 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
354 unsigned SecondLastOpc = SecondLastInst->getOpcode();
355 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
356 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
357 TBB = SecondLastInst->getOperand(0).getMBB();
358 Cond.push_back(SecondLastInst->getOperand(1));
359 Cond.push_back(SecondLastInst->getOperand(2));
360 FBB = LastInst->getOperand(0).getMBB();
364 // If the block ends with two unconditional branches, handle it. The second
365 // one is not executed, so remove it.
366 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
367 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
368 TBB = SecondLastInst->getOperand(0).getMBB();
370 I->eraseFromParent();
374 // Likewise if it ends with a branch table followed by an unconditional branch.
375 // The branch folder can create these, and we must get rid of them for
376 // correctness of Thumb constant islands.
377 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
378 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
379 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
381 I->eraseFromParent();
385 // Otherwise, can't handle this.
390 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
391 MachineFunction &MF = *MBB.getParent();
392 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
393 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
394 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
396 MachineBasicBlock::iterator I = MBB.end();
397 if (I == MBB.begin()) return 0;
399 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
402 // Remove the branch.
403 I->eraseFromParent();
407 if (I == MBB.begin()) return 1;
409 if (I->getOpcode() != BccOpc)
412 // Remove the branch.
413 I->eraseFromParent();
417 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
418 MachineBasicBlock *FBB,
419 const std::vector<MachineOperand> &Cond) const {
420 MachineFunction &MF = *MBB.getParent();
421 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
422 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
423 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
425 // Shouldn't be a fall through.
426 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
427 assert((Cond.size() == 2 || Cond.size() == 0) &&
428 "ARM branch conditions have two components!");
431 if (Cond.empty()) // Unconditional branch?
432 BuildMI(&MBB, get(BOpc)).addMBB(TBB);
434 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
435 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
439 // Two-way conditional branch.
440 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
441 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
442 BuildMI(&MBB, get(BOpc)).addMBB(FBB);
446 void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator I,
448 unsigned DestReg, unsigned SrcReg,
449 const TargetRegisterClass *DestRC,
450 const TargetRegisterClass *SrcRC) const {
451 if (DestRC != SrcRC) {
452 cerr << "Not yet supported!";
456 if (DestRC == ARM::GPRRegisterClass) {
457 MachineFunction &MF = *MBB.getParent();
458 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
459 if (AFI->isThumbFunction())
460 BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg);
462 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg)
464 } else if (DestRC == ARM::SPRRegisterClass)
465 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg)
467 else if (DestRC == ARM::DPRRegisterClass)
468 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
474 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
475 MachineOperand &MO) {
477 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
478 else if (MO.isImmediate())
479 MIB = MIB.addImm(MO.getImm());
480 else if (MO.isFrameIndex())
481 MIB = MIB.addFrameIndex(MO.getIndex());
483 assert(0 && "Unknown operand for ARMInstrAddOperand!");
489 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
490 unsigned SrcReg, bool isKill, int FI,
491 const TargetRegisterClass *RC) const {
492 if (RC == ARM::GPRRegisterClass) {
493 MachineFunction &MF = *MBB.getParent();
494 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
495 if (AFI->isThumbFunction())
496 BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
497 .addFrameIndex(FI).addImm(0);
499 AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
500 .addReg(SrcReg, false, false, isKill)
501 .addFrameIndex(FI).addReg(0).addImm(0));
502 } else if (RC == ARM::DPRRegisterClass) {
503 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
504 .addReg(SrcReg, false, false, isKill)
505 .addFrameIndex(FI).addImm(0));
507 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
508 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
509 .addReg(SrcReg, false, false, isKill)
510 .addFrameIndex(FI).addImm(0));
514 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
516 SmallVectorImpl<MachineOperand> &Addr,
517 const TargetRegisterClass *RC,
518 SmallVectorImpl<MachineInstr*> &NewMIs) const {
520 if (RC == ARM::GPRRegisterClass) {
521 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
522 if (AFI->isThumbFunction()) {
523 Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
524 MachineInstrBuilder MIB =
525 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
526 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
527 MIB = ARMInstrAddOperand(MIB, Addr[i]);
528 NewMIs.push_back(MIB);
532 } else if (RC == ARM::DPRRegisterClass) {
535 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
539 MachineInstrBuilder MIB =
540 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
541 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
542 MIB = ARMInstrAddOperand(MIB, Addr[i]);
544 NewMIs.push_back(MIB);
549 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
550 unsigned DestReg, int FI,
551 const TargetRegisterClass *RC) const {
552 if (RC == ARM::GPRRegisterClass) {
553 MachineFunction &MF = *MBB.getParent();
554 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
555 if (AFI->isThumbFunction())
556 BuildMI(MBB, I, get(ARM::tRestore), DestReg)
557 .addFrameIndex(FI).addImm(0);
559 AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
560 .addFrameIndex(FI).addReg(0).addImm(0));
561 } else if (RC == ARM::DPRRegisterClass) {
562 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
563 .addFrameIndex(FI).addImm(0));
565 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
566 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
567 .addFrameIndex(FI).addImm(0));
571 void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
572 SmallVectorImpl<MachineOperand> &Addr,
573 const TargetRegisterClass *RC,
574 SmallVectorImpl<MachineInstr*> &NewMIs) const {
576 if (RC == ARM::GPRRegisterClass) {
577 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
578 if (AFI->isThumbFunction()) {
579 Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
580 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
581 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
582 MIB = ARMInstrAddOperand(MIB, Addr[i]);
583 NewMIs.push_back(MIB);
587 } else if (RC == ARM::DPRRegisterClass) {
590 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
594 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
595 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
596 MIB = ARMInstrAddOperand(MIB, Addr[i]);
598 NewMIs.push_back(MIB);
602 bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
603 MachineBasicBlock::iterator MI,
604 const std::vector<CalleeSavedInfo> &CSI) const {
605 MachineFunction &MF = *MBB.getParent();
606 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
607 if (!AFI->isThumbFunction() || CSI.empty())
610 MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH));
611 for (unsigned i = CSI.size(); i != 0; --i) {
612 unsigned Reg = CSI[i-1].getReg();
613 // Add the callee-saved register as live-in. It's killed at the spill.
615 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
620 bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
621 MachineBasicBlock::iterator MI,
622 const std::vector<CalleeSavedInfo> &CSI) const {
623 MachineFunction &MF = *MBB.getParent();
624 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
625 if (!AFI->isThumbFunction() || CSI.empty())
628 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
629 MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP));
630 MBB.insert(MI, PopMI);
631 for (unsigned i = CSI.size(); i != 0; --i) {
632 unsigned Reg = CSI[i-1].getReg();
633 if (Reg == ARM::LR) {
634 // Special epilogue for vararg functions. See emitEpilogue
638 PopMI->setInstrDescriptor(get(ARM::tPOP_RET));
641 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
646 MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineInstr *MI,
647 SmallVectorImpl<unsigned> &Ops,
649 if (Ops.size() != 1) return NULL;
651 unsigned OpNum = Ops[0];
652 unsigned Opc = MI->getOpcode();
653 MachineInstr *NewMI = NULL;
657 if (MI->getOperand(4).getReg() == ARM::CPSR)
658 // If it is updating CPSR, then it cannot be foled.
660 unsigned Pred = MI->getOperand(2).getImm();
661 unsigned PredReg = MI->getOperand(3).getReg();
662 if (OpNum == 0) { // move -> store
663 unsigned SrcReg = MI->getOperand(1).getReg();
664 NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
665 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
666 } else { // move -> load
667 unsigned DstReg = MI->getOperand(0).getReg();
668 NewMI = BuildMI(get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
669 .addImm(0).addImm(Pred).addReg(PredReg);
674 if (OpNum == 0) { // move -> store
675 unsigned SrcReg = MI->getOperand(1).getReg();
676 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
677 // tSpill cannot take a high register operand.
679 NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
681 } else { // move -> load
682 unsigned DstReg = MI->getOperand(0).getReg();
683 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
684 // tRestore cannot target a high register operand.
686 NewMI = BuildMI(get(ARM::tRestore), DstReg).addFrameIndex(FI)
692 unsigned Pred = MI->getOperand(2).getImm();
693 unsigned PredReg = MI->getOperand(3).getReg();
694 if (OpNum == 0) { // move -> store
695 unsigned SrcReg = MI->getOperand(1).getReg();
696 NewMI = BuildMI(get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
697 .addImm(0).addImm(Pred).addReg(PredReg);
698 } else { // move -> load
699 unsigned DstReg = MI->getOperand(0).getReg();
700 NewMI = BuildMI(get(ARM::FLDS), DstReg).addFrameIndex(FI)
701 .addImm(0).addImm(Pred).addReg(PredReg);
706 unsigned Pred = MI->getOperand(2).getImm();
707 unsigned PredReg = MI->getOperand(3).getReg();
708 if (OpNum == 0) { // move -> store
709 unsigned SrcReg = MI->getOperand(1).getReg();
710 NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
711 .addImm(0).addImm(Pred).addReg(PredReg);
712 } else { // move -> load
713 unsigned DstReg = MI->getOperand(0).getReg();
714 NewMI = BuildMI(get(ARM::FLDD), DstReg).addFrameIndex(FI)
715 .addImm(0).addImm(Pred).addReg(PredReg);
722 NewMI->copyKillDeadInfo(MI);
726 bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
727 SmallVectorImpl<unsigned> &Ops) const {
728 if (Ops.size() != 1) return false;
730 unsigned OpNum = Ops[0];
731 unsigned Opc = MI->getOpcode();
735 // If it is updating CPSR, then it cannot be foled.
736 return MI->getOperand(4).getReg() != ARM::CPSR;
738 if (OpNum == 0) { // move -> store
739 unsigned SrcReg = MI->getOperand(1).getReg();
740 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
741 // tSpill cannot take a high register operand.
743 } else { // move -> load
744 unsigned DstReg = MI->getOperand(0).getReg();
745 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
746 // tRestore cannot target a high register operand.
759 bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
760 if (MBB.empty()) return false;
762 switch (MBB.back().getOpcode()) {
763 case ARM::BX_RET: // Return.
766 case ARM::tBX_RET_vararg:
769 case ARM::tB: // Uncond branch.
771 case ARM::BR_JTr: // Jumptable branch.
772 case ARM::BR_JTm: // Jumptable branch through mem.
773 case ARM::BR_JTadd: // Jumptable branch add to pc.
775 default: return false;
780 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
781 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
782 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
786 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
787 int PIdx = MI->findFirstPredOperandIdx();
788 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
791 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
792 const std::vector<MachineOperand> &Pred) const {
793 unsigned Opc = MI->getOpcode();
794 if (Opc == ARM::B || Opc == ARM::tB) {
795 MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
796 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
797 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
801 int PIdx = MI->findFirstPredOperandIdx();
803 MachineOperand &PMO = MI->getOperand(PIdx);
804 PMO.setImm(Pred[0].getImm());
805 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
812 ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
813 const std::vector<MachineOperand> &Pred2) const{
814 if (Pred1.size() > 2 || Pred2.size() > 2)
817 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
818 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
828 return CC2 == ARMCC::HI;
830 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
832 return CC2 == ARMCC::GT;
834 return CC2 == ARMCC::LT;
838 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
839 std::vector<MachineOperand> &Pred) const {
840 const TargetInstrDesc &TID = MI->getDesc();
841 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
845 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
846 const MachineOperand &MO = MI->getOperand(i);
847 if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
857 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
858 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
859 unsigned JTI) DISABLE_INLINE;
860 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
862 return JT[JTI].MBBs.size();
865 /// GetInstSize - Return the size of the specified MachineInstr.
867 unsigned ARM::GetInstSize(MachineInstr *MI) {
868 MachineBasicBlock &MBB = *MI->getParent();
869 const MachineFunction *MF = MBB.getParent();
870 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
872 // Basic size info comes from the TSFlags field.
873 const TargetInstrDesc &TID = MI->getDesc();
874 unsigned TSFlags = TID.TSFlags;
876 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
878 // If this machine instr is an inline asm, measure it.
879 if (MI->getOpcode() == ARM::INLINEASM)
880 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
881 if (MI->getOpcode() == ARM::LABEL)
883 assert(0 && "Unknown or unset size field for instr!");
885 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
886 case ARMII::Size4Bytes: return 4; // Arm instruction.
887 case ARMII::Size2Bytes: return 2; // Thumb instruction.
888 case ARMII::SizeSpecial: {
889 switch (MI->getOpcode()) {
890 case ARM::CONSTPOOL_ENTRY:
891 // If this machine instr is a constant pool entry, its size is recorded as
893 return MI->getOperand(2).getImm();
898 // These are jumptable branches, i.e. a branch followed by an inlined
899 // jumptable. The size is 4 + 4 * number of entries.
900 unsigned NumOps = TID.getNumOperands();
901 MachineOperand JTOP =
902 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
903 unsigned JTI = JTOP.getIndex();
904 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
905 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
906 assert(JTI < JT.size());
907 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
908 // 4 aligned. The assembler / linker may add 2 byte padding just before
909 // the JT entries. The size does not include this padding; the
910 // constant islands pass does separate bookkeeping for it.
911 // FIXME: If we know the size of the function is less than (1 << 16) *2
912 // bytes, we can use 16-bit entries instead. Then there won't be an
914 return getNumJTEntries(JT, JTI) * 4 +
915 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
918 // Otherwise, pseudo-instruction sizes are zero.
925 /// GetFunctionSize - Returns the size of the specified MachineFunction.
927 unsigned ARM::GetFunctionSize(MachineFunction &MF) {
929 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
931 MachineBasicBlock &MBB = *MBBI;
932 for (MachineBasicBlock::iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
933 FnSize += ARM::GetInstSize(I);