1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInst.h"
32 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI() {}
35 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
36 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
38 NopInst.setOpcode(ARM::HINT);
39 NopInst.addOperand(MCOperand::createImm(0));
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::createReg(0));
43 NopInst.setOpcode(ARM::MOVr);
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createReg(ARM::R0));
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
47 NopInst.addOperand(MCOperand::createReg(0));
48 NopInst.addOperand(MCOperand::createReg(0));
52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
55 case ARM::LDR_PRE_IMM:
56 case ARM::LDR_PRE_REG:
57 case ARM::LDR_POST_IMM:
58 case ARM::LDR_POST_REG:
63 case ARM::LDRB_PRE_IMM:
64 case ARM::LDRB_PRE_REG:
65 case ARM::LDRB_POST_IMM:
66 case ARM::LDRB_POST_REG:
74 case ARM::STR_PRE_IMM:
75 case ARM::STR_PRE_REG:
76 case ARM::STR_POST_IMM:
77 case ARM::STR_POST_REG:
82 case ARM::STRB_PRE_IMM:
83 case ARM::STRB_PRE_REG:
84 case ARM::STRB_POST_IMM:
85 case ARM::STRB_POST_REG:
92 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
93 Reloc::Model RM) const {
94 MachineFunction &MF = *MI->getParent()->getParent();
95 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
97 if (!Subtarget.useMovt(MF)) {
98 if (RM == Reloc::PIC_)
99 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12, RM);
101 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12, RM);
105 if (RM != Reloc::PIC_) {
106 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12, RM);
110 const GlobalValue *GV =
111 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
113 if (!Subtarget.GVIsIndirectSymbol(GV, RM)) {
114 expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12, RM);
118 MachineBasicBlock &MBB = *MI->getParent();
119 DebugLoc DL = MI->getDebugLoc();
120 unsigned Reg = MI->getOperand(0).getReg();
121 MachineInstrBuilder MIB;
123 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
124 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
125 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
126 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
127 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 4, 4);
128 MIB.addMemOperand(MMO);
129 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg);
130 MIB.addReg(Reg, RegState::Kill).addImm(0);
131 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
136 /// ARMCGBR - Create Global Base Reg pass. This initializes the PIC
137 /// global base register for ARM ELF.
138 struct ARMCGBR : public MachineFunctionPass {
140 ARMCGBR() : MachineFunctionPass(ID) {}
142 bool runOnMachineFunction(MachineFunction &MF) override {
143 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
144 if (AFI->getGlobalBaseReg() == 0)
146 const ARMSubtarget &STI =
147 static_cast<const ARMSubtarget &>(MF.getSubtarget());
148 // Don't do this for Thumb1.
149 if (STI.isThumb1Only())
152 const TargetMachine &TM = MF.getTarget();
153 if (TM.getRelocationModel() != Reloc::PIC_)
156 LLVMContext *Context = &MF.getFunction()->getContext();
157 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
158 unsigned PCAdj = STI.isThumb() ? 4 : 8;
159 ARMConstantPoolValue *CPV = ARMConstantPoolSymbol::Create(
160 *Context, "_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, PCAdj);
162 unsigned Align = MF.getDataLayout().getPrefTypeAlignment(
163 Type::getInt32PtrTy(*Context));
164 unsigned Idx = MF.getConstantPool()->getConstantPoolIndex(CPV, Align);
166 MachineBasicBlock &FirstMBB = MF.front();
167 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
168 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
170 MF.getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
171 unsigned Opc = STI.isThumb2() ? ARM::t2LDRpci : ARM::LDRcp;
172 const TargetInstrInfo &TII = *STI.getInstrInfo();
173 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
174 TII.get(Opc), TempReg)
175 .addConstantPoolIndex(Idx);
176 if (Opc == ARM::LDRcp)
180 // Fix the GOT address by adding pc.
181 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
182 Opc = STI.isThumb2() ? ARM::tPICADD : ARM::PICADD;
183 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
185 .addImm(ARMPCLabelIndex);
186 if (Opc == ARM::PICADD)
192 const char *getPassName() const override {
193 return "ARM PIC Global Base Reg Initialization";
196 void getAnalysisUsage(AnalysisUsage &AU) const override {
197 AU.setPreservesCFG();
198 MachineFunctionPass::getAnalysisUsage(AU);
203 char ARMCGBR::ID = 0;
205 llvm::createARMGlobalBaseRegPass() { return new ARMCGBR(); }