1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the TargetInstrInfo class.
13 //===----------------------------------------------------------------------===//
15 #include "ARMInstrInfo.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/Target/TargetAsmInfo.h"
24 #include "llvm/Support/CommandLine.h"
27 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
28 cl::desc("Enable ARM 2-addr to 3-addr conv"));
30 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
31 : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
35 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
36 return &ARM::GPRRegClass;
39 /// Return true if the instruction is a register to register move and
40 /// leave the source and dest operands in the passed parameters.
42 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
43 unsigned &SrcReg, unsigned &DstReg) const {
44 MachineOpCode oc = MI.getOpcode();
50 SrcReg = MI.getOperand(1).getReg();
51 DstReg = MI.getOperand(0).getReg();
55 assert(MI.getInstrDescriptor()->numOperands >= 2 &&
56 MI.getOperand(0).isRegister() &&
57 MI.getOperand(1).isRegister() &&
58 "Invalid ARM MOV instruction");
59 SrcReg = MI.getOperand(1).getReg();
60 DstReg = MI.getOperand(0).getReg();
65 unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
66 switch (MI->getOpcode()) {
69 if (MI->getOperand(1).isFrameIndex() &&
70 MI->getOperand(2).isReg() &&
71 MI->getOperand(3).isImmediate() &&
72 MI->getOperand(2).getReg() == 0 &&
73 MI->getOperand(3).getImmedValue() == 0) {
74 FrameIndex = MI->getOperand(1).getFrameIndex();
75 return MI->getOperand(0).getReg();
80 if (MI->getOperand(1).isFrameIndex() &&
81 MI->getOperand(2).isImmediate() &&
82 MI->getOperand(2).getImmedValue() == 0) {
83 FrameIndex = MI->getOperand(1).getFrameIndex();
84 return MI->getOperand(0).getReg();
88 if (MI->getOperand(1).isFrameIndex() &&
89 MI->getOperand(2).isImmediate() &&
90 MI->getOperand(2).getImmedValue() == 0) {
91 FrameIndex = MI->getOperand(1).getFrameIndex();
92 return MI->getOperand(0).getReg();
99 unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
100 switch (MI->getOpcode()) {
103 if (MI->getOperand(1).isFrameIndex() &&
104 MI->getOperand(2).isReg() &&
105 MI->getOperand(3).isImmediate() &&
106 MI->getOperand(2).getReg() == 0 &&
107 MI->getOperand(3).getImmedValue() == 0) {
108 FrameIndex = MI->getOperand(1).getFrameIndex();
109 return MI->getOperand(0).getReg();
114 if (MI->getOperand(1).isFrameIndex() &&
115 MI->getOperand(2).isImmediate() &&
116 MI->getOperand(2).getImmedValue() == 0) {
117 FrameIndex = MI->getOperand(1).getFrameIndex();
118 return MI->getOperand(0).getReg();
122 if (MI->getOperand(1).isFrameIndex() &&
123 MI->getOperand(2).isImmediate() &&
124 MI->getOperand(2).getImmedValue() == 0) {
125 FrameIndex = MI->getOperand(1).getFrameIndex();
126 return MI->getOperand(0).getReg();
133 static unsigned getUnindexedOpcode(unsigned Opc) {
146 case ARM::LDRSH_POST:
149 case ARM::LDRSB_POST:
165 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
166 MachineBasicBlock::iterator &MBBI,
167 LiveVariables &LV) const {
171 MachineInstr *MI = MBBI;
172 unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
174 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
175 default: return NULL;
176 case ARMII::IndexModePre:
179 case ARMII::IndexModePost:
183 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
185 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
189 MachineInstr *UpdateMI = NULL;
190 MachineInstr *MemMI = NULL;
191 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
192 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
193 unsigned NumOps = TID->numOperands;
194 bool isLoad = (TID->Flags & M_LOAD_FLAG) != 0;
195 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
196 const MachineOperand &Base = MI->getOperand(2);
197 const MachineOperand &Offset = MI->getOperand(NumOps-3);
198 unsigned WBReg = WB.getReg();
199 unsigned BaseReg = Base.getReg();
200 unsigned OffReg = Offset.getReg();
201 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
202 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
205 assert(false && "Unknown indexed op!");
207 case ARMII::AddrMode2: {
208 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
209 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
211 int SOImmVal = ARM_AM::getSOImmVal(Amt);
213 // Can't encode it in a so_imm operand. This transformation will
214 // add more than 1 instruction. Abandon!
216 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
217 .addReg(BaseReg).addImm(SOImmVal).addImm(Pred);
218 } else if (Amt != 0) {
219 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
220 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
221 UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
222 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc).addImm(Pred);
224 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
225 .addReg(BaseReg).addReg(OffReg).addImm(Pred);
228 case ARMII::AddrMode3 : {
229 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
230 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
232 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
233 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
234 .addReg(BaseReg).addImm(Amt).addImm(Pred);
236 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
237 .addReg(BaseReg).addReg(OffReg).addImm(Pred);
242 std::vector<MachineInstr*> NewMIs;
245 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
246 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
248 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
249 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
250 NewMIs.push_back(MemMI);
251 NewMIs.push_back(UpdateMI);
254 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
255 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
257 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
258 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
260 UpdateMI->getOperand(0).setIsDead();
261 NewMIs.push_back(UpdateMI);
262 NewMIs.push_back(MemMI);
265 // Transfer LiveVariables states, kill / dead info.
266 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
267 MachineOperand &MO = MI->getOperand(i);
268 if (MO.isRegister() && MO.getReg() &&
269 MRegisterInfo::isVirtualRegister(MO.getReg())) {
270 unsigned Reg = MO.getReg();
271 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
273 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
275 LV.addVirtualRegisterDead(Reg, NewMI);
276 // Update the defining instruction.
277 if (VI.DefInst == MI)
280 if (MO.isUse() && MO.isKill()) {
281 for (unsigned j = 0; j < 2; ++j) {
282 // Look at the two new MI's in reverse order.
283 MachineInstr *NewMI = NewMIs[j];
284 int NIdx = NewMI->findRegisterUseOperandIdx(Reg);
287 LV.addVirtualRegisterKilled(Reg, NewMI);
288 if (VI.removeKill(MI))
289 VI.Kills.push_back(NewMI);
296 MFI->insert(MBBI, NewMIs[1]);
297 MFI->insert(MBBI, NewMIs[0]);
302 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
303 MachineBasicBlock *&FBB,
304 std::vector<MachineOperand> &Cond) const {
305 // If the block has no terminators, it just falls into the block after it.
306 MachineBasicBlock::iterator I = MBB.end();
307 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
310 // Get the last instruction in the block.
311 MachineInstr *LastInst = I;
313 // If there is only one terminator instruction, process it.
314 unsigned LastOpc = LastInst->getOpcode();
315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
316 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
317 TBB = LastInst->getOperand(0).getMachineBasicBlock();
320 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
321 // Block ends with fall-through condbranch.
322 TBB = LastInst->getOperand(0).getMachineBasicBlock();
323 Cond.push_back(LastInst->getOperand(1));
324 Cond.push_back(LastInst->getOperand(2));
327 return true; // Can't handle indirect branch.
330 // Get the instruction before it if it is a terminator.
331 MachineInstr *SecondLastInst = I;
333 // If there are three terminators, we don't know what sort of block this is.
334 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
337 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
338 unsigned SecondLastOpc = SecondLastInst->getOpcode();
339 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
340 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
341 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
342 Cond.push_back(SecondLastInst->getOperand(1));
343 Cond.push_back(SecondLastInst->getOperand(2));
344 FBB = LastInst->getOperand(0).getMachineBasicBlock();
348 // If the block ends with two B's or tB's, handle it. The second one is not
349 // executed, so remove it.
350 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
351 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
352 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
354 I->eraseFromParent();
358 // Otherwise, can't handle this.
363 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
364 MachineFunction &MF = *MBB.getParent();
365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
366 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
367 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
369 MachineBasicBlock::iterator I = MBB.end();
370 if (I == MBB.begin()) return 0;
372 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
375 // Remove the branch.
376 I->eraseFromParent();
380 if (I == MBB.begin()) return 1;
382 if (I->getOpcode() != BccOpc)
385 // Remove the branch.
386 I->eraseFromParent();
390 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
391 MachineBasicBlock *FBB,
392 const std::vector<MachineOperand> &Cond) const {
393 MachineFunction &MF = *MBB.getParent();
394 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
395 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
396 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
398 // Shouldn't be a fall through.
399 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
400 assert((Cond.size() == 2 || Cond.size() == 0) &&
401 "ARM branch conditions have two components!");
404 if (Cond.empty()) // Unconditional branch?
405 BuildMI(&MBB, get(BOpc)).addMBB(TBB);
407 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
408 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
412 // Two-way conditional branch.
413 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
414 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
415 BuildMI(&MBB, get(BOpc)).addMBB(FBB);
419 bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
420 if (MBB.empty()) return false;
422 switch (MBB.back().getOpcode()) {
423 case ARM::BX_RET: // Return.
426 case ARM::tBX_RET_vararg:
429 case ARM::tB: // Uncond branch.
431 case ARM::BR_JTr: // Jumptable branch.
432 case ARM::BR_JTm: // Jumptable branch through mem.
433 case ARM::BR_JTadd: // Jumptable branch add to pc.
435 default: return false;
440 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
441 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
442 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
446 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
447 int PIdx = MI->findFirstPredOperandIdx();
448 return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
451 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
452 const std::vector<MachineOperand> &Pred) const {
453 unsigned Opc = MI->getOpcode();
454 if (Opc == ARM::B || Opc == ARM::tB) {
455 MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
456 MI->addImmOperand(Pred[0].getImmedValue());
457 MI->addRegOperand(Pred[1].getReg(), false);
461 int PIdx = MI->findFirstPredOperandIdx();
463 MachineOperand &PMO = MI->getOperand(PIdx);
464 PMO.setImm(Pred[0].getImmedValue());
465 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
472 ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
473 const std::vector<MachineOperand> &Pred2) const{
474 if (Pred1.size() > 2 || Pred2.size() > 2)
477 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
478 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
488 return CC2 == ARMCC::HI;
490 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
492 return CC2 == ARMCC::GT;
494 return CC2 == ARMCC::LT;
498 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
499 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
500 unsigned JTI) DISABLE_INLINE;
501 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
503 return JT[JTI].MBBs.size();
506 /// GetInstSize - Return the size of the specified MachineInstr.
508 unsigned ARM::GetInstSize(MachineInstr *MI) {
509 MachineBasicBlock &MBB = *MI->getParent();
510 const MachineFunction *MF = MBB.getParent();
511 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
513 // Basic size info comes from the TSFlags field.
514 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
515 unsigned TSFlags = TID->TSFlags;
517 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
519 // If this machine instr is an inline asm, measure it.
520 if (MI->getOpcode() == ARM::INLINEASM)
521 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
522 if (MI->getOpcode() == ARM::LABEL)
524 assert(0 && "Unknown or unset size field for instr!");
526 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
527 case ARMII::Size4Bytes: return 4; // Arm instruction.
528 case ARMII::Size2Bytes: return 2; // Thumb instruction.
529 case ARMII::SizeSpecial: {
530 switch (MI->getOpcode()) {
531 case ARM::CONSTPOOL_ENTRY:
532 // If this machine instr is a constant pool entry, its size is recorded as
534 return MI->getOperand(2).getImm();
539 // These are jumptable branches, i.e. a branch followed by an inlined
540 // jumptable. The size is 4 + 4 * number of entries.
541 unsigned NumOps = TID->numOperands;
542 MachineOperand JTOP =
543 MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2));
544 unsigned JTI = JTOP.getJumpTableIndex();
545 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
546 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
547 assert(JTI < JT.size());
548 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
549 // 4 aligned. The assembler / linker may add 2 byte padding just before
550 // the JT entries. The size does not include this padding; the
551 // constant islands pass does separate bookkeeping for it.
552 // FIXME: If we know the size of the function is less than (1 << 16) *2
553 // bytes, we can use 16-bit entries instead. Then there won't be an
555 return getNumJTEntries(JT, JTI) * 4 +
556 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
559 // Otherwise, pseudo-instruction sizes are zero.
566 /// GetFunctionSize - Returns the size of the specified MachineFunction.
568 unsigned ARM::GetFunctionSize(MachineFunction &MF) {
570 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
572 MachineBasicBlock &MBB = *MBBI;
573 for (MachineBasicBlock::iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
574 FnSize += ARM::GetInstSize(I);