1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/Target/TargetAsmInfo.h"
24 #include "llvm/Support/CommandLine.h"
27 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
28 cl::desc("Enable ARM 2-addr to 3-addr conv"));
30 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
31 : TargetInstrInfo(ARMInsts, array_lengthof(ARMInsts)),
35 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
36 return &ARM::GPRRegClass;
39 /// Return true if the instruction is a register to register move and
40 /// leave the source and dest operands in the passed parameters.
42 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
43 unsigned &SrcReg, unsigned &DstReg) const {
44 MachineOpCode oc = MI.getOpcode();
50 SrcReg = MI.getOperand(1).getReg();
51 DstReg = MI.getOperand(0).getReg();
55 assert(MI.getInstrDescriptor()->numOperands >= 2 &&
56 MI.getOperand(0).isRegister() &&
57 MI.getOperand(1).isRegister() &&
58 "Invalid ARM MOV instruction");
59 SrcReg = MI.getOperand(1).getReg();
60 DstReg = MI.getOperand(0).getReg();
65 unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
66 switch (MI->getOpcode()) {
69 if (MI->getOperand(1).isFrameIndex() &&
70 MI->getOperand(2).isRegister() &&
71 MI->getOperand(3).isImmediate() &&
72 MI->getOperand(2).getReg() == 0 &&
73 MI->getOperand(3).getImm() == 0) {
74 FrameIndex = MI->getOperand(1).getFrameIndex();
75 return MI->getOperand(0).getReg();
80 if (MI->getOperand(1).isFrameIndex() &&
81 MI->getOperand(2).isImmediate() &&
82 MI->getOperand(2).getImm() == 0) {
83 FrameIndex = MI->getOperand(1).getFrameIndex();
84 return MI->getOperand(0).getReg();
88 if (MI->getOperand(1).isFrameIndex() &&
89 MI->getOperand(2).isImmediate() &&
90 MI->getOperand(2).getImm() == 0) {
91 FrameIndex = MI->getOperand(1).getFrameIndex();
92 return MI->getOperand(0).getReg();
99 unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
100 switch (MI->getOpcode()) {
103 if (MI->getOperand(1).isFrameIndex() &&
104 MI->getOperand(2).isRegister() &&
105 MI->getOperand(3).isImmediate() &&
106 MI->getOperand(2).getReg() == 0 &&
107 MI->getOperand(3).getImm() == 0) {
108 FrameIndex = MI->getOperand(1).getFrameIndex();
109 return MI->getOperand(0).getReg();
114 if (MI->getOperand(1).isFrameIndex() &&
115 MI->getOperand(2).isImmediate() &&
116 MI->getOperand(2).getImm() == 0) {
117 FrameIndex = MI->getOperand(1).getFrameIndex();
118 return MI->getOperand(0).getReg();
122 if (MI->getOperand(1).isFrameIndex() &&
123 MI->getOperand(2).isImmediate() &&
124 MI->getOperand(2).getImm() == 0) {
125 FrameIndex = MI->getOperand(1).getFrameIndex();
126 return MI->getOperand(0).getReg();
133 static unsigned getUnindexedOpcode(unsigned Opc) {
146 case ARM::LDRSH_POST:
149 case ARM::LDRSB_POST:
165 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
166 MachineBasicBlock::iterator &MBBI,
167 LiveVariables &LV) const {
171 MachineInstr *MI = MBBI;
172 unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
174 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
175 default: return NULL;
176 case ARMII::IndexModePre:
179 case ARMII::IndexModePost:
183 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
185 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
189 MachineInstr *UpdateMI = NULL;
190 MachineInstr *MemMI = NULL;
191 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
192 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
193 unsigned NumOps = TID->numOperands;
194 bool isLoad = (TID->Flags & M_LOAD_FLAG) != 0;
195 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
196 const MachineOperand &Base = MI->getOperand(2);
197 const MachineOperand &Offset = MI->getOperand(NumOps-3);
198 unsigned WBReg = WB.getReg();
199 unsigned BaseReg = Base.getReg();
200 unsigned OffReg = Offset.getReg();
201 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
202 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
205 assert(false && "Unknown indexed op!");
207 case ARMII::AddrMode2: {
208 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
209 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
211 int SOImmVal = ARM_AM::getSOImmVal(Amt);
213 // Can't encode it in a so_imm operand. This transformation will
214 // add more than 1 instruction. Abandon!
216 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
217 .addReg(BaseReg).addImm(SOImmVal)
218 .addImm(Pred).addReg(0).addReg(0);
219 } else if (Amt != 0) {
220 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
221 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
222 UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
223 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
224 .addImm(Pred).addReg(0).addReg(0);
226 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
227 .addReg(BaseReg).addReg(OffReg)
228 .addImm(Pred).addReg(0).addReg(0);
231 case ARMII::AddrMode3 : {
232 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
233 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
235 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
236 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
237 .addReg(BaseReg).addImm(Amt)
238 .addImm(Pred).addReg(0).addReg(0);
240 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
241 .addReg(BaseReg).addReg(OffReg)
242 .addImm(Pred).addReg(0).addReg(0);
247 std::vector<MachineInstr*> NewMIs;
250 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
251 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
253 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
254 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
255 NewMIs.push_back(MemMI);
256 NewMIs.push_back(UpdateMI);
259 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
260 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
262 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
263 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
265 UpdateMI->getOperand(0).setIsDead();
266 NewMIs.push_back(UpdateMI);
267 NewMIs.push_back(MemMI);
270 // Transfer LiveVariables states, kill / dead info.
271 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
272 MachineOperand &MO = MI->getOperand(i);
273 if (MO.isRegister() && MO.getReg() &&
274 MRegisterInfo::isVirtualRegister(MO.getReg())) {
275 unsigned Reg = MO.getReg();
276 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
278 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
280 LV.addVirtualRegisterDead(Reg, NewMI);
281 // Update the defining instruction.
282 if (VI.DefInst == MI)
285 if (MO.isUse() && MO.isKill()) {
286 for (unsigned j = 0; j < 2; ++j) {
287 // Look at the two new MI's in reverse order.
288 MachineInstr *NewMI = NewMIs[j];
289 int NIdx = NewMI->findRegisterUseOperandIdx(Reg);
292 LV.addVirtualRegisterKilled(Reg, NewMI);
293 if (VI.removeKill(MI))
294 VI.Kills.push_back(NewMI);
301 MFI->insert(MBBI, NewMIs[1]);
302 MFI->insert(MBBI, NewMIs[0]);
307 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
308 MachineBasicBlock *&FBB,
309 std::vector<MachineOperand> &Cond) const {
310 // If the block has no terminators, it just falls into the block after it.
311 MachineBasicBlock::iterator I = MBB.end();
312 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
315 // Get the last instruction in the block.
316 MachineInstr *LastInst = I;
318 // If there is only one terminator instruction, process it.
319 unsigned LastOpc = LastInst->getOpcode();
320 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
321 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
322 TBB = LastInst->getOperand(0).getMachineBasicBlock();
325 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
326 // Block ends with fall-through condbranch.
327 TBB = LastInst->getOperand(0).getMachineBasicBlock();
328 Cond.push_back(LastInst->getOperand(1));
329 Cond.push_back(LastInst->getOperand(2));
332 return true; // Can't handle indirect branch.
335 // Get the instruction before it if it is a terminator.
336 MachineInstr *SecondLastInst = I;
338 // If there are three terminators, we don't know what sort of block this is.
339 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
342 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
343 unsigned SecondLastOpc = SecondLastInst->getOpcode();
344 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
345 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
346 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
347 Cond.push_back(SecondLastInst->getOperand(1));
348 Cond.push_back(SecondLastInst->getOperand(2));
349 FBB = LastInst->getOperand(0).getMachineBasicBlock();
353 // If the block ends with two unconditional branches, handle it. The second
354 // one is not executed, so remove it.
355 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
356 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
357 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
359 I->eraseFromParent();
363 // Likewise if it ends with a branch table followed by an unconditional branch.
364 // The branch folder can create these, and we must get rid of them for
365 // correctness of Thumb constant islands.
366 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
367 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
368 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
370 I->eraseFromParent();
374 // Otherwise, can't handle this.
379 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
380 MachineFunction &MF = *MBB.getParent();
381 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
382 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
383 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
385 MachineBasicBlock::iterator I = MBB.end();
386 if (I == MBB.begin()) return 0;
388 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
391 // Remove the branch.
392 I->eraseFromParent();
396 if (I == MBB.begin()) return 1;
398 if (I->getOpcode() != BccOpc)
401 // Remove the branch.
402 I->eraseFromParent();
406 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
407 MachineBasicBlock *FBB,
408 const std::vector<MachineOperand> &Cond) const {
409 MachineFunction &MF = *MBB.getParent();
410 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
411 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
412 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
414 // Shouldn't be a fall through.
415 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
416 assert((Cond.size() == 2 || Cond.size() == 0) &&
417 "ARM branch conditions have two components!");
420 if (Cond.empty()) // Unconditional branch?
421 BuildMI(&MBB, get(BOpc)).addMBB(TBB);
423 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
424 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
428 // Two-way conditional branch.
429 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
430 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
431 BuildMI(&MBB, get(BOpc)).addMBB(FBB);
435 bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
436 if (MBB.empty()) return false;
438 switch (MBB.back().getOpcode()) {
439 case ARM::BX_RET: // Return.
442 case ARM::tBX_RET_vararg:
445 case ARM::tB: // Uncond branch.
447 case ARM::BR_JTr: // Jumptable branch.
448 case ARM::BR_JTm: // Jumptable branch through mem.
449 case ARM::BR_JTadd: // Jumptable branch add to pc.
451 default: return false;
456 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
457 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
458 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
462 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
463 int PIdx = MI->findFirstPredOperandIdx();
464 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
467 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
468 const std::vector<MachineOperand> &Pred) const {
469 unsigned Opc = MI->getOpcode();
470 if (Opc == ARM::B || Opc == ARM::tB) {
471 MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
472 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
473 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
477 int PIdx = MI->findFirstPredOperandIdx();
479 MachineOperand &PMO = MI->getOperand(PIdx);
480 PMO.setImm(Pred[0].getImm());
481 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
488 ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
489 const std::vector<MachineOperand> &Pred2) const{
490 if (Pred1.size() > 2 || Pred2.size() > 2)
493 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
494 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
504 return CC2 == ARMCC::HI;
506 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
508 return CC2 == ARMCC::GT;
510 return CC2 == ARMCC::LT;
514 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
515 std::vector<MachineOperand> &Pred) const {
516 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
517 if (!TID->ImplicitDefs && (TID->Flags & M_HAS_OPTIONAL_DEF) == 0)
521 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
522 const MachineOperand &MO = MI->getOperand(i);
523 if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
533 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
534 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
535 unsigned JTI) DISABLE_INLINE;
536 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
538 return JT[JTI].MBBs.size();
541 /// GetInstSize - Return the size of the specified MachineInstr.
543 unsigned ARM::GetInstSize(MachineInstr *MI) {
544 MachineBasicBlock &MBB = *MI->getParent();
545 const MachineFunction *MF = MBB.getParent();
546 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
548 // Basic size info comes from the TSFlags field.
549 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
550 unsigned TSFlags = TID->TSFlags;
552 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
554 // If this machine instr is an inline asm, measure it.
555 if (MI->getOpcode() == ARM::INLINEASM)
556 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
557 if (MI->getOpcode() == ARM::LABEL)
559 assert(0 && "Unknown or unset size field for instr!");
561 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
562 case ARMII::Size4Bytes: return 4; // Arm instruction.
563 case ARMII::Size2Bytes: return 2; // Thumb instruction.
564 case ARMII::SizeSpecial: {
565 switch (MI->getOpcode()) {
566 case ARM::CONSTPOOL_ENTRY:
567 // If this machine instr is a constant pool entry, its size is recorded as
569 return MI->getOperand(2).getImm();
574 // These are jumptable branches, i.e. a branch followed by an inlined
575 // jumptable. The size is 4 + 4 * number of entries.
576 unsigned NumOps = TID->numOperands;
577 MachineOperand JTOP =
578 MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2));
579 unsigned JTI = JTOP.getJumpTableIndex();
580 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
581 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
582 assert(JTI < JT.size());
583 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
584 // 4 aligned. The assembler / linker may add 2 byte padding just before
585 // the JT entries. The size does not include this padding; the
586 // constant islands pass does separate bookkeeping for it.
587 // FIXME: If we know the size of the function is less than (1 << 16) *2
588 // bytes, we can use 16-bit entries instead. Then there won't be an
590 return getNumJTEntries(JT, JTI) * 4 +
591 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
594 // Otherwise, pseudo-instruction sizes are zero.
601 /// GetFunctionSize - Returns the size of the specified MachineFunction.
603 unsigned ARM::GetFunctionSize(MachineFunction &MF) {
605 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
607 MachineBasicBlock &MBB = *MBBI;
608 for (MachineBasicBlock::iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
609 FnSize += ARM::GetInstSize(I);