1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCInst.h"
31 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
32 : ARMBaseInstrInfo(STI), RI(STI) {
35 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
36 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
38 NopInst.setOpcode(ARM::HINT);
39 NopInst.addOperand(MCOperand::CreateImm(0));
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::CreateReg(0));
43 NopInst.setOpcode(ARM::MOVr);
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
47 NopInst.addOperand(MCOperand::CreateReg(0));
48 NopInst.addOperand(MCOperand::CreateReg(0));
52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
55 case ARM::LDR_PRE_IMM:
56 case ARM::LDR_PRE_REG:
57 case ARM::LDR_POST_IMM:
58 case ARM::LDR_POST_REG:
63 case ARM::LDRB_PRE_IMM:
64 case ARM::LDRB_PRE_REG:
65 case ARM::LDRB_POST_IMM:
66 case ARM::LDRB_POST_REG:
74 case ARM::STR_PRE_IMM:
75 case ARM::STR_PRE_REG:
76 case ARM::STR_POST_IMM:
77 case ARM::STR_POST_REG:
82 case ARM::STRB_PRE_IMM:
83 case ARM::STRB_PRE_REG:
84 case ARM::STRB_POST_IMM:
85 case ARM::STRB_POST_REG:
93 /// ARMCGBR - Create Global Base Reg pass. This initializes the PIC
94 /// global base register for ARM ELF.
95 struct ARMCGBR : public MachineFunctionPass {
97 ARMCGBR() : MachineFunctionPass(ID) {}
99 virtual bool runOnMachineFunction(MachineFunction &MF) {
100 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
101 if (AFI->getGlobalBaseReg() == 0)
104 const ARMTargetMachine *TM =
105 static_cast<const ARMTargetMachine *>(&MF.getTarget());
106 if (TM->getRelocationModel() != Reloc::PIC_)
109 LLVMContext* Context = &MF.getFunction()->getContext();
110 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
111 GlobalValue::ExternalLinkage, 0,
112 "_GLOBAL_OFFSET_TABLE_");
113 unsigned Id = AFI->createPICLabelUId();
114 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id);
115 unsigned Align = TM->getDataLayout()->getPrefTypeAlignment(GV->getType());
116 unsigned Idx = MF.getConstantPool()->getConstantPoolIndex(CPV, Align);
118 MachineBasicBlock &FirstMBB = MF.front();
119 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
120 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
121 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
122 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
123 ARM::t2LDRpci : ARM::LDRcp;
124 const TargetInstrInfo &TII = *TM->getInstrInfo();
125 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
126 TII.get(Opc), GlobalBaseReg)
127 .addConstantPoolIndex(Idx);
128 if (Opc == ARM::LDRcp)
135 virtual const char *getPassName() const {
136 return "ARM PIC Global Base Reg Initialization";
139 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
140 AU.setPreservesCFG();
141 MachineFunctionPass::getAnalysisUsage(AU);
146 char ARMCGBR::ID = 0;
148 llvm::createARMGlobalBaseRegPass() { return new ARMCGBR(); }