1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
28 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
41 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
46 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
47 return &ARM::GPRRegClass;
50 /// Return true if the instruction is a register to register move and
51 /// leave the source and dest operands in the passed parameters.
53 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
54 unsigned &SrcReg, unsigned &DstReg) const {
55 unsigned oc = MI.getOpcode();
61 SrcReg = MI.getOperand(1).getReg();
62 DstReg = MI.getOperand(0).getReg();
66 assert(MI.getDesc().getNumOperands() >= 2 &&
67 MI.getOperand(0).isRegister() &&
68 MI.getOperand(1).isRegister() &&
69 "Invalid ARM MOV instruction");
70 SrcReg = MI.getOperand(1).getReg();
71 DstReg = MI.getOperand(0).getReg();
76 unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
77 switch (MI->getOpcode()) {
80 if (MI->getOperand(1).isFrameIndex() &&
81 MI->getOperand(2).isRegister() &&
82 MI->getOperand(3).isImmediate() &&
83 MI->getOperand(2).getReg() == 0 &&
84 MI->getOperand(3).getImm() == 0) {
85 FrameIndex = MI->getOperand(1).getIndex();
86 return MI->getOperand(0).getReg();
91 if (MI->getOperand(1).isFrameIndex() &&
92 MI->getOperand(2).isImmediate() &&
93 MI->getOperand(2).getImm() == 0) {
94 FrameIndex = MI->getOperand(1).getIndex();
95 return MI->getOperand(0).getReg();
99 if (MI->getOperand(1).isFrameIndex() &&
100 MI->getOperand(2).isImmediate() &&
101 MI->getOperand(2).getImm() == 0) {
102 FrameIndex = MI->getOperand(1).getIndex();
103 return MI->getOperand(0).getReg();
110 unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
111 switch (MI->getOpcode()) {
114 if (MI->getOperand(1).isFrameIndex() &&
115 MI->getOperand(2).isRegister() &&
116 MI->getOperand(3).isImmediate() &&
117 MI->getOperand(2).getReg() == 0 &&
118 MI->getOperand(3).getImm() == 0) {
119 FrameIndex = MI->getOperand(1).getIndex();
120 return MI->getOperand(0).getReg();
125 if (MI->getOperand(1).isFrameIndex() &&
126 MI->getOperand(2).isImmediate() &&
127 MI->getOperand(2).getImm() == 0) {
128 FrameIndex = MI->getOperand(1).getIndex();
129 return MI->getOperand(0).getReg();
133 if (MI->getOperand(1).isFrameIndex() &&
134 MI->getOperand(2).isImmediate() &&
135 MI->getOperand(2).getImm() == 0) {
136 FrameIndex = MI->getOperand(1).getIndex();
137 return MI->getOperand(0).getReg();
144 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
145 MachineBasicBlock::iterator I,
147 const MachineInstr *Orig) const {
148 if (Orig->getOpcode() == ARM::MOVi2pieces) {
149 RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
150 Orig->getOperand(2).getImm(),
151 Orig->getOperand(3).getReg(), this, false);
155 MachineInstr *MI = Orig->clone();
156 MI->getOperand(0).setReg(DestReg);
160 static unsigned getUnindexedOpcode(unsigned Opc) {
173 case ARM::LDRSH_POST:
176 case ARM::LDRSB_POST:
192 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
193 MachineBasicBlock::iterator &MBBI,
194 LiveVariables &LV) const {
198 MachineInstr *MI = MBBI;
199 unsigned TSFlags = MI->getDesc().TSFlags;
201 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
202 default: return NULL;
203 case ARMII::IndexModePre:
206 case ARMII::IndexModePost:
210 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
212 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
216 MachineInstr *UpdateMI = NULL;
217 MachineInstr *MemMI = NULL;
218 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
219 const TargetInstrDesc &TID = MI->getDesc();
220 unsigned NumOps = TID.getNumOperands();
221 bool isLoad = !TID.mayStore();
222 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
223 const MachineOperand &Base = MI->getOperand(2);
224 const MachineOperand &Offset = MI->getOperand(NumOps-3);
225 unsigned WBReg = WB.getReg();
226 unsigned BaseReg = Base.getReg();
227 unsigned OffReg = Offset.getReg();
228 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
229 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
232 assert(false && "Unknown indexed op!");
234 case ARMII::AddrMode2: {
235 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
236 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
238 int SOImmVal = ARM_AM::getSOImmVal(Amt);
240 // Can't encode it in a so_imm operand. This transformation will
241 // add more than 1 instruction. Abandon!
243 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
244 .addReg(BaseReg).addImm(SOImmVal)
245 .addImm(Pred).addReg(0).addReg(0);
246 } else if (Amt != 0) {
247 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
248 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
249 UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
250 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
251 .addImm(Pred).addReg(0).addReg(0);
253 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
254 .addReg(BaseReg).addReg(OffReg)
255 .addImm(Pred).addReg(0).addReg(0);
258 case ARMII::AddrMode3 : {
259 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
260 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
262 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
263 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
264 .addReg(BaseReg).addImm(Amt)
265 .addImm(Pred).addReg(0).addReg(0);
267 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
268 .addReg(BaseReg).addReg(OffReg)
269 .addImm(Pred).addReg(0).addReg(0);
274 std::vector<MachineInstr*> NewMIs;
277 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
278 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
280 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
281 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
282 NewMIs.push_back(MemMI);
283 NewMIs.push_back(UpdateMI);
286 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
287 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
289 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
290 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
292 UpdateMI->getOperand(0).setIsDead();
293 NewMIs.push_back(UpdateMI);
294 NewMIs.push_back(MemMI);
297 // Transfer LiveVariables states, kill / dead info.
298 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
299 MachineOperand &MO = MI->getOperand(i);
300 if (MO.isRegister() && MO.getReg() &&
301 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
302 unsigned Reg = MO.getReg();
303 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
305 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
307 LV.addVirtualRegisterDead(Reg, NewMI);
309 if (MO.isUse() && MO.isKill()) {
310 for (unsigned j = 0; j < 2; ++j) {
311 // Look at the two new MI's in reverse order.
312 MachineInstr *NewMI = NewMIs[j];
313 if (!NewMI->readsRegister(Reg))
315 LV.addVirtualRegisterKilled(Reg, NewMI);
316 if (VI.removeKill(MI))
317 VI.Kills.push_back(NewMI);
324 MFI->insert(MBBI, NewMIs[1]);
325 MFI->insert(MBBI, NewMIs[0]);
330 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
331 MachineBasicBlock *&FBB,
332 std::vector<MachineOperand> &Cond) const {
333 // If the block has no terminators, it just falls into the block after it.
334 MachineBasicBlock::iterator I = MBB.end();
335 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
338 // Get the last instruction in the block.
339 MachineInstr *LastInst = I;
341 // If there is only one terminator instruction, process it.
342 unsigned LastOpc = LastInst->getOpcode();
343 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
344 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
345 TBB = LastInst->getOperand(0).getMBB();
348 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
349 // Block ends with fall-through condbranch.
350 TBB = LastInst->getOperand(0).getMBB();
351 Cond.push_back(LastInst->getOperand(1));
352 Cond.push_back(LastInst->getOperand(2));
355 return true; // Can't handle indirect branch.
358 // Get the instruction before it if it is a terminator.
359 MachineInstr *SecondLastInst = I;
361 // If there are three terminators, we don't know what sort of block this is.
362 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
365 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
366 unsigned SecondLastOpc = SecondLastInst->getOpcode();
367 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
368 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
369 TBB = SecondLastInst->getOperand(0).getMBB();
370 Cond.push_back(SecondLastInst->getOperand(1));
371 Cond.push_back(SecondLastInst->getOperand(2));
372 FBB = LastInst->getOperand(0).getMBB();
376 // If the block ends with two unconditional branches, handle it. The second
377 // one is not executed, so remove it.
378 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
379 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
380 TBB = SecondLastInst->getOperand(0).getMBB();
382 I->eraseFromParent();
386 // Likewise if it ends with a branch table followed by an unconditional branch.
387 // The branch folder can create these, and we must get rid of them for
388 // correctness of Thumb constant islands.
389 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
390 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
391 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
393 I->eraseFromParent();
397 // Otherwise, can't handle this.
402 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
403 MachineFunction &MF = *MBB.getParent();
404 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
405 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
406 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
408 MachineBasicBlock::iterator I = MBB.end();
409 if (I == MBB.begin()) return 0;
411 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
414 // Remove the branch.
415 I->eraseFromParent();
419 if (I == MBB.begin()) return 1;
421 if (I->getOpcode() != BccOpc)
424 // Remove the branch.
425 I->eraseFromParent();
429 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
430 MachineBasicBlock *FBB,
431 const std::vector<MachineOperand> &Cond) const {
432 MachineFunction &MF = *MBB.getParent();
433 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
434 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
435 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
437 // Shouldn't be a fall through.
438 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
439 assert((Cond.size() == 2 || Cond.size() == 0) &&
440 "ARM branch conditions have two components!");
443 if (Cond.empty()) // Unconditional branch?
444 BuildMI(&MBB, get(BOpc)).addMBB(TBB);
446 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
447 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
451 // Two-way conditional branch.
452 BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
453 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
454 BuildMI(&MBB, get(BOpc)).addMBB(FBB);
458 void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
459 MachineBasicBlock::iterator I,
460 unsigned DestReg, unsigned SrcReg,
461 const TargetRegisterClass *DestRC,
462 const TargetRegisterClass *SrcRC) const {
463 if (DestRC != SrcRC) {
464 cerr << "Not yet supported!";
468 if (DestRC == ARM::GPRRegisterClass) {
469 MachineFunction &MF = *MBB.getParent();
470 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
471 if (AFI->isThumbFunction())
472 BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg);
474 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg)
476 } else if (DestRC == ARM::SPRRegisterClass)
477 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg)
479 else if (DestRC == ARM::DPRRegisterClass)
480 AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
486 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
487 MachineOperand &MO) {
489 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
490 else if (MO.isImmediate())
491 MIB = MIB.addImm(MO.getImm());
492 else if (MO.isFrameIndex())
493 MIB = MIB.addFrameIndex(MO.getIndex());
495 assert(0 && "Unknown operand for ARMInstrAddOperand!");
501 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
502 unsigned SrcReg, bool isKill, int FI,
503 const TargetRegisterClass *RC) const {
504 if (RC == ARM::GPRRegisterClass) {
505 MachineFunction &MF = *MBB.getParent();
506 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
507 if (AFI->isThumbFunction())
508 BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
509 .addFrameIndex(FI).addImm(0);
511 AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
512 .addReg(SrcReg, false, false, isKill)
513 .addFrameIndex(FI).addReg(0).addImm(0));
514 } else if (RC == ARM::DPRRegisterClass) {
515 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
516 .addReg(SrcReg, false, false, isKill)
517 .addFrameIndex(FI).addImm(0));
519 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
520 AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
521 .addReg(SrcReg, false, false, isKill)
522 .addFrameIndex(FI).addImm(0));
526 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
528 SmallVectorImpl<MachineOperand> &Addr,
529 const TargetRegisterClass *RC,
530 SmallVectorImpl<MachineInstr*> &NewMIs) const {
532 if (RC == ARM::GPRRegisterClass) {
533 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
534 if (AFI->isThumbFunction()) {
535 Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
536 MachineInstrBuilder MIB =
537 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
538 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
539 MIB = ARMInstrAddOperand(MIB, Addr[i]);
540 NewMIs.push_back(MIB);
544 } else if (RC == ARM::DPRRegisterClass) {
547 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
551 MachineInstrBuilder MIB =
552 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
553 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
554 MIB = ARMInstrAddOperand(MIB, Addr[i]);
556 NewMIs.push_back(MIB);
561 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
562 unsigned DestReg, int FI,
563 const TargetRegisterClass *RC) const {
564 if (RC == ARM::GPRRegisterClass) {
565 MachineFunction &MF = *MBB.getParent();
566 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
567 if (AFI->isThumbFunction())
568 BuildMI(MBB, I, get(ARM::tRestore), DestReg)
569 .addFrameIndex(FI).addImm(0);
571 AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
572 .addFrameIndex(FI).addReg(0).addImm(0));
573 } else if (RC == ARM::DPRRegisterClass) {
574 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
575 .addFrameIndex(FI).addImm(0));
577 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
578 AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
579 .addFrameIndex(FI).addImm(0));
583 void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
584 SmallVectorImpl<MachineOperand> &Addr,
585 const TargetRegisterClass *RC,
586 SmallVectorImpl<MachineInstr*> &NewMIs) const {
588 if (RC == ARM::GPRRegisterClass) {
589 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
590 if (AFI->isThumbFunction()) {
591 Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
592 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
593 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
594 MIB = ARMInstrAddOperand(MIB, Addr[i]);
595 NewMIs.push_back(MIB);
599 } else if (RC == ARM::DPRRegisterClass) {
602 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
606 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
607 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
608 MIB = ARMInstrAddOperand(MIB, Addr[i]);
610 NewMIs.push_back(MIB);
614 bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
615 MachineBasicBlock::iterator MI,
616 const std::vector<CalleeSavedInfo> &CSI) const {
617 MachineFunction &MF = *MBB.getParent();
618 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
619 if (!AFI->isThumbFunction() || CSI.empty())
622 MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH));
623 for (unsigned i = CSI.size(); i != 0; --i) {
624 unsigned Reg = CSI[i-1].getReg();
625 // Add the callee-saved register as live-in. It's killed at the spill.
627 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
632 bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
633 MachineBasicBlock::iterator MI,
634 const std::vector<CalleeSavedInfo> &CSI) const {
635 MachineFunction &MF = *MBB.getParent();
636 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
637 if (!AFI->isThumbFunction() || CSI.empty())
640 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
641 MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP));
642 MBB.insert(MI, PopMI);
643 for (unsigned i = CSI.size(); i != 0; --i) {
644 unsigned Reg = CSI[i-1].getReg();
645 if (Reg == ARM::LR) {
646 // Special epilogue for vararg functions. See emitEpilogue
650 PopMI->setDesc(get(ARM::tPOP_RET));
653 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
658 MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF,
660 SmallVectorImpl<unsigned> &Ops,
662 if (Ops.size() != 1) return NULL;
664 unsigned OpNum = Ops[0];
665 unsigned Opc = MI->getOpcode();
666 MachineInstr *NewMI = NULL;
670 if (MI->getOperand(4).getReg() == ARM::CPSR)
671 // If it is updating CPSR, then it cannot be foled.
673 unsigned Pred = MI->getOperand(2).getImm();
674 unsigned PredReg = MI->getOperand(3).getReg();
675 if (OpNum == 0) { // move -> store
676 unsigned SrcReg = MI->getOperand(1).getReg();
677 NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
678 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
679 } else { // move -> load
680 unsigned DstReg = MI->getOperand(0).getReg();
681 NewMI = BuildMI(get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
682 .addImm(0).addImm(Pred).addReg(PredReg);
687 if (OpNum == 0) { // move -> store
688 unsigned SrcReg = MI->getOperand(1).getReg();
689 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
690 // tSpill cannot take a high register operand.
692 NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
694 } else { // move -> load
695 unsigned DstReg = MI->getOperand(0).getReg();
696 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
697 // tRestore cannot target a high register operand.
699 NewMI = BuildMI(get(ARM::tRestore), DstReg).addFrameIndex(FI)
705 unsigned Pred = MI->getOperand(2).getImm();
706 unsigned PredReg = MI->getOperand(3).getReg();
707 if (OpNum == 0) { // move -> store
708 unsigned SrcReg = MI->getOperand(1).getReg();
709 NewMI = BuildMI(get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
710 .addImm(0).addImm(Pred).addReg(PredReg);
711 } else { // move -> load
712 unsigned DstReg = MI->getOperand(0).getReg();
713 NewMI = BuildMI(get(ARM::FLDS), DstReg).addFrameIndex(FI)
714 .addImm(0).addImm(Pred).addReg(PredReg);
719 unsigned Pred = MI->getOperand(2).getImm();
720 unsigned PredReg = MI->getOperand(3).getReg();
721 if (OpNum == 0) { // move -> store
722 unsigned SrcReg = MI->getOperand(1).getReg();
723 NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
724 .addImm(0).addImm(Pred).addReg(PredReg);
725 } else { // move -> load
726 unsigned DstReg = MI->getOperand(0).getReg();
727 NewMI = BuildMI(get(ARM::FLDD), DstReg).addFrameIndex(FI)
728 .addImm(0).addImm(Pred).addReg(PredReg);
735 NewMI->copyKillDeadInfo(MI);
739 bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
740 SmallVectorImpl<unsigned> &Ops) const {
741 if (Ops.size() != 1) return false;
743 unsigned OpNum = Ops[0];
744 unsigned Opc = MI->getOpcode();
748 // If it is updating CPSR, then it cannot be foled.
749 return MI->getOperand(4).getReg() != ARM::CPSR;
751 if (OpNum == 0) { // move -> store
752 unsigned SrcReg = MI->getOperand(1).getReg();
753 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
754 // tSpill cannot take a high register operand.
756 } else { // move -> load
757 unsigned DstReg = MI->getOperand(0).getReg();
758 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
759 // tRestore cannot target a high register operand.
772 bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
773 if (MBB.empty()) return false;
775 switch (MBB.back().getOpcode()) {
776 case ARM::BX_RET: // Return.
779 case ARM::tBX_RET_vararg:
782 case ARM::tB: // Uncond branch.
784 case ARM::BR_JTr: // Jumptable branch.
785 case ARM::BR_JTm: // Jumptable branch through mem.
786 case ARM::BR_JTadd: // Jumptable branch add to pc.
788 default: return false;
793 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
794 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
795 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
799 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
800 int PIdx = MI->findFirstPredOperandIdx();
801 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
804 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
805 const std::vector<MachineOperand> &Pred) const {
806 unsigned Opc = MI->getOpcode();
807 if (Opc == ARM::B || Opc == ARM::tB) {
808 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
809 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
810 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
814 int PIdx = MI->findFirstPredOperandIdx();
816 MachineOperand &PMO = MI->getOperand(PIdx);
817 PMO.setImm(Pred[0].getImm());
818 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
825 ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
826 const std::vector<MachineOperand> &Pred2) const{
827 if (Pred1.size() > 2 || Pred2.size() > 2)
830 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
831 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
841 return CC2 == ARMCC::HI;
843 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
845 return CC2 == ARMCC::GT;
847 return CC2 == ARMCC::LT;
851 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
852 std::vector<MachineOperand> &Pred) const {
853 const TargetInstrDesc &TID = MI->getDesc();
854 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
858 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
859 const MachineOperand &MO = MI->getOperand(i);
860 if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
870 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
871 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
872 unsigned JTI) DISABLE_INLINE;
873 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
875 return JT[JTI].MBBs.size();
878 /// GetInstSize - Return the size of the specified MachineInstr.
880 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
881 const MachineBasicBlock &MBB = *MI->getParent();
882 const MachineFunction *MF = MBB.getParent();
883 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
885 // Basic size info comes from the TSFlags field.
886 const TargetInstrDesc &TID = MI->getDesc();
887 unsigned TSFlags = TID.TSFlags;
889 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
891 // If this machine instr is an inline asm, measure it.
892 if (MI->getOpcode() == ARM::INLINEASM)
893 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
894 if (MI->getOpcode() == ARM::LABEL)
896 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
898 assert(0 && "Unknown or unset size field for instr!");
900 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
901 case ARMII::Size4Bytes: return 4; // Arm instruction.
902 case ARMII::Size2Bytes: return 2; // Thumb instruction.
903 case ARMII::SizeSpecial: {
904 switch (MI->getOpcode()) {
905 case ARM::CONSTPOOL_ENTRY:
906 // If this machine instr is a constant pool entry, its size is recorded as
908 return MI->getOperand(2).getImm();
913 // These are jumptable branches, i.e. a branch followed by an inlined
914 // jumptable. The size is 4 + 4 * number of entries.
915 unsigned NumOps = TID.getNumOperands();
916 MachineOperand JTOP =
917 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
918 unsigned JTI = JTOP.getIndex();
919 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
920 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
921 assert(JTI < JT.size());
922 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
923 // 4 aligned. The assembler / linker may add 2 byte padding just before
924 // the JT entries. The size does not include this padding; the
925 // constant islands pass does separate bookkeeping for it.
926 // FIXME: If we know the size of the function is less than (1 << 16) *2
927 // bytes, we can use 16-bit entries instead. Then there won't be an
929 return getNumJTEntries(JT, JTI) * 4 +
930 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
933 // Otherwise, pseudo-instruction sizes are zero.
938 return 0; // Not reached