1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
29 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
30 cl::desc("Enable ARM 2-addr to 3-addr conv"));
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
42 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 /// Return true if the instruction is a register to register move and
49 /// leave the source and dest operands in the passed parameters.
51 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
52 unsigned &SrcReg, unsigned &DstReg,
53 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
54 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
56 unsigned oc = MI.getOpcode();
64 SrcReg = MI.getOperand(1).getReg();
65 DstReg = MI.getOperand(0).getReg();
69 case ARM::tMOVhir2lor:
70 case ARM::tMOVlor2hir:
71 case ARM::tMOVhir2hir:
72 assert(MI.getDesc().getNumOperands() >= 2 &&
73 MI.getOperand(0).isReg() &&
74 MI.getOperand(1).isReg() &&
75 "Invalid ARM MOV instruction");
76 SrcReg = MI.getOperand(1).getReg();
77 DstReg = MI.getOperand(0).getReg();
82 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
83 int &FrameIndex) const {
84 switch (MI->getOpcode()) {
87 if (MI->getOperand(1).isFI() &&
88 MI->getOperand(2).isReg() &&
89 MI->getOperand(3).isImm() &&
90 MI->getOperand(2).getReg() == 0 &&
91 MI->getOperand(3).getImm() == 0) {
92 FrameIndex = MI->getOperand(1).getIndex();
93 return MI->getOperand(0).getReg();
98 if (MI->getOperand(1).isFI() &&
99 MI->getOperand(2).isImm() &&
100 MI->getOperand(2).getImm() == 0) {
101 FrameIndex = MI->getOperand(1).getIndex();
102 return MI->getOperand(0).getReg();
106 if (MI->getOperand(1).isFI() &&
107 MI->getOperand(2).isImm() &&
108 MI->getOperand(2).getImm() == 0) {
109 FrameIndex = MI->getOperand(1).getIndex();
110 return MI->getOperand(0).getReg();
117 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
118 int &FrameIndex) const {
119 switch (MI->getOpcode()) {
122 if (MI->getOperand(1).isFI() &&
123 MI->getOperand(2).isReg() &&
124 MI->getOperand(3).isImm() &&
125 MI->getOperand(2).getReg() == 0 &&
126 MI->getOperand(3).getImm() == 0) {
127 FrameIndex = MI->getOperand(1).getIndex();
128 return MI->getOperand(0).getReg();
133 if (MI->getOperand(1).isFI() &&
134 MI->getOperand(2).isImm() &&
135 MI->getOperand(2).getImm() == 0) {
136 FrameIndex = MI->getOperand(1).getIndex();
137 return MI->getOperand(0).getReg();
141 if (MI->getOperand(1).isFI() &&
142 MI->getOperand(2).isImm() &&
143 MI->getOperand(2).getImm() == 0) {
144 FrameIndex = MI->getOperand(1).getIndex();
145 return MI->getOperand(0).getReg();
152 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator I,
155 const MachineInstr *Orig) const {
156 DebugLoc dl = Orig->getDebugLoc();
157 if (Orig->getOpcode() == ARM::MOVi2pieces) {
158 RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
159 Orig->getOperand(2).getImm(),
160 Orig->getOperand(3).getReg(), this, false, dl);
164 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
165 MI->getOperand(0).setReg(DestReg);
169 static unsigned getUnindexedOpcode(unsigned Opc) {
182 case ARM::LDRSH_POST:
185 case ARM::LDRSB_POST:
201 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
202 MachineBasicBlock::iterator &MBBI,
203 LiveVariables *LV) const {
207 MachineInstr *MI = MBBI;
208 MachineFunction &MF = *MI->getParent()->getParent();
209 unsigned TSFlags = MI->getDesc().TSFlags;
211 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
212 default: return NULL;
213 case ARMII::IndexModePre:
216 case ARMII::IndexModePost:
220 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
222 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
226 MachineInstr *UpdateMI = NULL;
227 MachineInstr *MemMI = NULL;
228 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
229 const TargetInstrDesc &TID = MI->getDesc();
230 unsigned NumOps = TID.getNumOperands();
231 bool isLoad = !TID.mayStore();
232 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
233 const MachineOperand &Base = MI->getOperand(2);
234 const MachineOperand &Offset = MI->getOperand(NumOps-3);
235 unsigned WBReg = WB.getReg();
236 unsigned BaseReg = Base.getReg();
237 unsigned OffReg = Offset.getReg();
238 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
239 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
242 assert(false && "Unknown indexed op!");
244 case ARMII::AddrMode2: {
245 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
246 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
248 int SOImmVal = ARM_AM::getSOImmVal(Amt);
250 // Can't encode it in a so_imm operand. This transformation will
251 // add more than 1 instruction. Abandon!
253 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
254 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
255 .addReg(BaseReg).addImm(SOImmVal)
256 .addImm(Pred).addReg(0).addReg(0);
257 } else if (Amt != 0) {
258 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
259 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
260 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
261 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
262 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
263 .addImm(Pred).addReg(0).addReg(0);
265 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
266 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
267 .addReg(BaseReg).addReg(OffReg)
268 .addImm(Pred).addReg(0).addReg(0);
271 case ARMII::AddrMode3 : {
272 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
273 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
275 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
276 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
277 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
278 .addReg(BaseReg).addImm(Amt)
279 .addImm(Pred).addReg(0).addReg(0);
281 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
282 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
283 .addReg(BaseReg).addReg(OffReg)
284 .addImm(Pred).addReg(0).addReg(0);
289 std::vector<MachineInstr*> NewMIs;
292 MemMI = BuildMI(MF, MI->getDebugLoc(),
293 get(MemOpc), MI->getOperand(0).getReg())
294 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
296 MemMI = BuildMI(MF, MI->getDebugLoc(),
297 get(MemOpc)).addReg(MI->getOperand(1).getReg())
298 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
299 NewMIs.push_back(MemMI);
300 NewMIs.push_back(UpdateMI);
303 MemMI = BuildMI(MF, MI->getDebugLoc(),
304 get(MemOpc), MI->getOperand(0).getReg())
305 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
307 MemMI = BuildMI(MF, MI->getDebugLoc(),
308 get(MemOpc)).addReg(MI->getOperand(1).getReg())
309 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
311 UpdateMI->getOperand(0).setIsDead();
312 NewMIs.push_back(UpdateMI);
313 NewMIs.push_back(MemMI);
316 // Transfer LiveVariables states, kill / dead info.
318 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
319 MachineOperand &MO = MI->getOperand(i);
320 if (MO.isReg() && MO.getReg() &&
321 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
322 unsigned Reg = MO.getReg();
324 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
326 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
328 LV->addVirtualRegisterDead(Reg, NewMI);
330 if (MO.isUse() && MO.isKill()) {
331 for (unsigned j = 0; j < 2; ++j) {
332 // Look at the two new MI's in reverse order.
333 MachineInstr *NewMI = NewMIs[j];
334 if (!NewMI->readsRegister(Reg))
336 LV->addVirtualRegisterKilled(Reg, NewMI);
337 if (VI.removeKill(MI))
338 VI.Kills.push_back(NewMI);
346 MFI->insert(MBBI, NewMIs[1]);
347 MFI->insert(MBBI, NewMIs[0]);
352 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
353 MachineBasicBlock *&FBB,
354 SmallVectorImpl<MachineOperand> &Cond,
355 bool AllowModify) const {
356 // If the block has no terminators, it just falls into the block after it.
357 MachineBasicBlock::iterator I = MBB.end();
358 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
361 // Get the last instruction in the block.
362 MachineInstr *LastInst = I;
364 // If there is only one terminator instruction, process it.
365 unsigned LastOpc = LastInst->getOpcode();
366 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
367 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
368 TBB = LastInst->getOperand(0).getMBB();
371 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
372 // Block ends with fall-through condbranch.
373 TBB = LastInst->getOperand(0).getMBB();
374 Cond.push_back(LastInst->getOperand(1));
375 Cond.push_back(LastInst->getOperand(2));
378 return true; // Can't handle indirect branch.
381 // Get the instruction before it if it is a terminator.
382 MachineInstr *SecondLastInst = I;
384 // If there are three terminators, we don't know what sort of block this is.
385 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
388 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
389 unsigned SecondLastOpc = SecondLastInst->getOpcode();
390 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
391 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
392 TBB = SecondLastInst->getOperand(0).getMBB();
393 Cond.push_back(SecondLastInst->getOperand(1));
394 Cond.push_back(SecondLastInst->getOperand(2));
395 FBB = LastInst->getOperand(0).getMBB();
399 // If the block ends with two unconditional branches, handle it. The second
400 // one is not executed, so remove it.
401 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
402 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
403 TBB = SecondLastInst->getOperand(0).getMBB();
406 I->eraseFromParent();
410 // ...likewise if it ends with a branch table followed by an unconditional
411 // branch. The branch folder can create these, and we must get rid of them for
412 // correctness of Thumb constant islands.
413 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
414 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
415 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
418 I->eraseFromParent();
422 // Otherwise, can't handle this.
427 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
428 MachineFunction &MF = *MBB.getParent();
429 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
430 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
431 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
433 MachineBasicBlock::iterator I = MBB.end();
434 if (I == MBB.begin()) return 0;
436 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
439 // Remove the branch.
440 I->eraseFromParent();
444 if (I == MBB.begin()) return 1;
446 if (I->getOpcode() != BccOpc)
449 // Remove the branch.
450 I->eraseFromParent();
455 ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
456 MachineBasicBlock *FBB,
457 const SmallVectorImpl<MachineOperand> &Cond) const {
458 // FIXME this should probably have a DebugLoc argument
459 DebugLoc dl = DebugLoc::getUnknownLoc();
460 MachineFunction &MF = *MBB.getParent();
461 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
462 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
463 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
465 // Shouldn't be a fall through.
466 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
467 assert((Cond.size() == 2 || Cond.size() == 0) &&
468 "ARM branch conditions have two components!");
471 if (Cond.empty()) // Unconditional branch?
472 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
474 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
475 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
479 // Two-way conditional branch.
480 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
481 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
482 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
486 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
487 MachineBasicBlock::iterator I,
488 unsigned DestReg, unsigned SrcReg,
489 const TargetRegisterClass *DestRC,
490 const TargetRegisterClass *SrcRC) const {
491 MachineFunction &MF = *MBB.getParent();
492 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
493 DebugLoc DL = DebugLoc::getUnknownLoc();
494 if (I != MBB.end()) DL = I->getDebugLoc();
496 if (!AFI->isThumbFunction()) {
497 if (DestRC == ARM::GPRRegisterClass) {
498 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
503 if (DestRC == ARM::GPRRegisterClass) {
504 if (SrcRC == ARM::GPRRegisterClass) {
505 BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg);
507 } else if (SrcRC == ARM::tGPRRegisterClass) {
508 BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg);
511 } else if (DestRC == ARM::tGPRRegisterClass) {
512 if (SrcRC == ARM::GPRRegisterClass) {
513 BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg);
515 } else if (SrcRC == ARM::tGPRRegisterClass) {
516 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
521 if (DestRC != SrcRC) {
522 // Not yet supported!
527 if (DestRC == ARM::SPRRegisterClass)
528 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
530 else if (DestRC == ARM::DPRRegisterClass)
531 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
533 else if (DestRC == ARM::QPRRegisterClass)
534 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
542 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
543 unsigned SrcReg, bool isKill, int FI,
544 const TargetRegisterClass *RC) const {
545 DebugLoc DL = DebugLoc::getUnknownLoc();
546 if (I != MBB.end()) DL = I->getDebugLoc();
548 if (RC == ARM::GPRRegisterClass) {
549 MachineFunction &MF = *MBB.getParent();
550 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
551 assert (!AFI->isThumbFunction());
552 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
553 .addReg(SrcReg, getKillRegState(isKill))
554 .addFrameIndex(FI).addReg(0).addImm(0));
555 } else if (RC == ARM::tGPRRegisterClass) {
556 MachineFunction &MF = *MBB.getParent();
557 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
558 assert (AFI->isThumbFunction());
559 BuildMI(MBB, I, DL, get(ARM::tSpill))
560 .addReg(SrcReg, getKillRegState(isKill))
561 .addFrameIndex(FI).addImm(0);
562 } else if (RC == ARM::DPRRegisterClass) {
563 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
564 .addReg(SrcReg, getKillRegState(isKill))
565 .addFrameIndex(FI).addImm(0));
567 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
568 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
569 .addReg(SrcReg, getKillRegState(isKill))
570 .addFrameIndex(FI).addImm(0));
574 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
576 SmallVectorImpl<MachineOperand> &Addr,
577 const TargetRegisterClass *RC,
578 SmallVectorImpl<MachineInstr*> &NewMIs) const{
579 DebugLoc DL = DebugLoc::getUnknownLoc();
581 if (RC == ARM::GPRRegisterClass) {
582 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
583 if (AFI->isThumbFunction()) {
584 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
585 MachineInstrBuilder MIB =
586 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
587 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
588 MIB.addOperand(Addr[i]);
589 NewMIs.push_back(MIB);
593 } else if (RC == ARM::DPRRegisterClass) {
596 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
600 MachineInstrBuilder MIB =
601 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
602 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
603 MIB.addOperand(Addr[i]);
605 NewMIs.push_back(MIB);
610 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
611 unsigned DestReg, int FI,
612 const TargetRegisterClass *RC) const {
613 DebugLoc DL = DebugLoc::getUnknownLoc();
614 if (I != MBB.end()) DL = I->getDebugLoc();
616 if (RC == ARM::GPRRegisterClass) {
617 MachineFunction &MF = *MBB.getParent();
618 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
619 assert (!AFI->isThumbFunction());
620 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
621 .addFrameIndex(FI).addReg(0).addImm(0));
622 } else if (RC == ARM::tGPRRegisterClass) {
623 MachineFunction &MF = *MBB.getParent();
624 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
625 assert (AFI->isThumbFunction());
626 BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
627 .addFrameIndex(FI).addImm(0);
628 } else if (RC == ARM::DPRRegisterClass) {
629 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
630 .addFrameIndex(FI).addImm(0));
632 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
633 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
634 .addFrameIndex(FI).addImm(0));
639 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
640 SmallVectorImpl<MachineOperand> &Addr,
641 const TargetRegisterClass *RC,
642 SmallVectorImpl<MachineInstr*> &NewMIs) const {
643 DebugLoc DL = DebugLoc::getUnknownLoc();
645 if (RC == ARM::GPRRegisterClass) {
646 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
647 if (AFI->isThumbFunction()) {
648 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
649 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
650 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
651 MIB.addOperand(Addr[i]);
652 NewMIs.push_back(MIB);
656 } else if (RC == ARM::DPRRegisterClass) {
659 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
663 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
664 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
665 MIB.addOperand(Addr[i]);
667 NewMIs.push_back(MIB);
672 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
673 MachineBasicBlock::iterator MI,
674 const std::vector<CalleeSavedInfo> &CSI) const {
675 MachineFunction &MF = *MBB.getParent();
676 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
677 if (!AFI->isThumbFunction() || CSI.empty())
680 DebugLoc DL = DebugLoc::getUnknownLoc();
681 if (MI != MBB.end()) DL = MI->getDebugLoc();
683 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
684 for (unsigned i = CSI.size(); i != 0; --i) {
685 unsigned Reg = CSI[i-1].getReg();
686 // Add the callee-saved register as live-in. It's killed at the spill.
688 MIB.addReg(Reg, RegState::Kill);
694 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
695 MachineBasicBlock::iterator MI,
696 const std::vector<CalleeSavedInfo> &CSI) const {
697 MachineFunction &MF = *MBB.getParent();
698 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
699 if (!AFI->isThumbFunction() || CSI.empty())
702 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
703 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
704 for (unsigned i = CSI.size(); i != 0; --i) {
705 unsigned Reg = CSI[i-1].getReg();
706 if (Reg == ARM::LR) {
707 // Special epilogue for vararg functions. See emitEpilogue
711 PopMI->setDesc(get(ARM::tPOP_RET));
714 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
717 // It's illegal to emit pop instruction without operands.
718 if (PopMI->getNumOperands() > 0)
719 MBB.insert(MI, PopMI);
724 MachineInstr *ARMInstrInfo::
725 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
726 const SmallVectorImpl<unsigned> &Ops, int FI) const {
727 if (Ops.size() != 1) return NULL;
729 unsigned OpNum = Ops[0];
730 unsigned Opc = MI->getOpcode();
731 MachineInstr *NewMI = NULL;
735 if (MI->getOperand(4).getReg() == ARM::CPSR)
736 // If it is updating CPSR, then it cannot be folded.
738 unsigned Pred = MI->getOperand(2).getImm();
739 unsigned PredReg = MI->getOperand(3).getReg();
740 if (OpNum == 0) { // move -> store
741 unsigned SrcReg = MI->getOperand(1).getReg();
742 bool isKill = MI->getOperand(1).isKill();
743 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
744 .addReg(SrcReg, getKillRegState(isKill))
745 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
746 } else { // move -> load
747 unsigned DstReg = MI->getOperand(0).getReg();
748 bool isDead = MI->getOperand(0).isDead();
749 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
750 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
751 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
756 case ARM::tMOVlor2hir:
757 case ARM::tMOVhir2lor:
758 case ARM::tMOVhir2hir: {
759 if (OpNum == 0) { // move -> store
760 unsigned SrcReg = MI->getOperand(1).getReg();
761 bool isKill = MI->getOperand(1).isKill();
762 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
763 // tSpill cannot take a high register operand.
765 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
766 .addReg(SrcReg, getKillRegState(isKill))
767 .addFrameIndex(FI).addImm(0);
768 } else { // move -> load
769 unsigned DstReg = MI->getOperand(0).getReg();
770 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
771 // tRestore cannot target a high register operand.
773 bool isDead = MI->getOperand(0).isDead();
774 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
775 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
776 .addFrameIndex(FI).addImm(0);
781 unsigned Pred = MI->getOperand(2).getImm();
782 unsigned PredReg = MI->getOperand(3).getReg();
783 if (OpNum == 0) { // move -> store
784 unsigned SrcReg = MI->getOperand(1).getReg();
785 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
786 .addReg(SrcReg).addFrameIndex(FI)
787 .addImm(0).addImm(Pred).addReg(PredReg);
788 } else { // move -> load
789 unsigned DstReg = MI->getOperand(0).getReg();
790 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
792 .addImm(0).addImm(Pred).addReg(PredReg);
797 unsigned Pred = MI->getOperand(2).getImm();
798 unsigned PredReg = MI->getOperand(3).getReg();
799 if (OpNum == 0) { // move -> store
800 unsigned SrcReg = MI->getOperand(1).getReg();
801 bool isKill = MI->getOperand(1).isKill();
802 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
803 .addReg(SrcReg, getKillRegState(isKill))
804 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
805 } else { // move -> load
806 unsigned DstReg = MI->getOperand(0).getReg();
807 bool isDead = MI->getOperand(0).isDead();
808 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
809 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
810 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
820 canFoldMemoryOperand(const MachineInstr *MI,
821 const SmallVectorImpl<unsigned> &Ops) const {
822 if (Ops.size() != 1) return false;
824 unsigned OpNum = Ops[0];
825 unsigned Opc = MI->getOpcode();
829 // If it is updating CPSR, then it cannot be folded.
830 return MI->getOperand(4).getReg() != ARM::CPSR;
832 case ARM::tMOVlor2hir:
833 case ARM::tMOVhir2lor:
834 case ARM::tMOVhir2hir: {
835 if (OpNum == 0) { // move -> store
836 unsigned SrcReg = MI->getOperand(1).getReg();
837 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
838 // tSpill cannot take a high register operand.
840 } else { // move -> load
841 unsigned DstReg = MI->getOperand(0).getReg();
842 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
843 // tRestore cannot target a high register operand.
854 return false; // FIXME
860 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
861 if (MBB.empty()) return false;
863 switch (MBB.back().getOpcode()) {
864 case ARM::BX_RET: // Return.
867 case ARM::tBX_RET_vararg:
870 case ARM::tB: // Uncond branch.
872 case ARM::BR_JTr: // Jumptable branch.
873 case ARM::BR_JTm: // Jumptable branch through mem.
874 case ARM::BR_JTadd: // Jumptable branch add to pc.
876 default: return false;
881 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
882 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
883 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
887 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
888 int PIdx = MI->findFirstPredOperandIdx();
889 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
893 PredicateInstruction(MachineInstr *MI,
894 const SmallVectorImpl<MachineOperand> &Pred) const {
895 unsigned Opc = MI->getOpcode();
896 if (Opc == ARM::B || Opc == ARM::tB) {
897 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
898 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
899 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
903 int PIdx = MI->findFirstPredOperandIdx();
905 MachineOperand &PMO = MI->getOperand(PIdx);
906 PMO.setImm(Pred[0].getImm());
907 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
914 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
915 const SmallVectorImpl<MachineOperand> &Pred2) const {
916 if (Pred1.size() > 2 || Pred2.size() > 2)
919 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
920 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
930 return CC2 == ARMCC::HI;
932 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
934 return CC2 == ARMCC::GT;
936 return CC2 == ARMCC::LT;
940 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
941 std::vector<MachineOperand> &Pred) const {
942 const TargetInstrDesc &TID = MI->getDesc();
943 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
947 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
948 const MachineOperand &MO = MI->getOperand(i);
949 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
959 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
960 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
961 unsigned JTI) DISABLE_INLINE;
962 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
964 return JT[JTI].MBBs.size();
967 /// GetInstSize - Return the size of the specified MachineInstr.
969 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
970 const MachineBasicBlock &MBB = *MI->getParent();
971 const MachineFunction *MF = MBB.getParent();
972 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
974 // Basic size info comes from the TSFlags field.
975 const TargetInstrDesc &TID = MI->getDesc();
976 unsigned TSFlags = TID.TSFlags;
978 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
980 // If this machine instr is an inline asm, measure it.
981 if (MI->getOpcode() == ARM::INLINEASM)
982 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
985 switch (MI->getOpcode()) {
987 assert(0 && "Unknown or unset size field for instr!");
989 case TargetInstrInfo::IMPLICIT_DEF:
990 case TargetInstrInfo::DECLARE:
991 case TargetInstrInfo::DBG_LABEL:
992 case TargetInstrInfo::EH_LABEL:
997 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
998 case ARMII::Size4Bytes: return 4; // Arm instruction.
999 case ARMII::Size2Bytes: return 2; // Thumb instruction.
1000 case ARMII::SizeSpecial: {
1001 switch (MI->getOpcode()) {
1002 case ARM::CONSTPOOL_ENTRY:
1003 // If this machine instr is a constant pool entry, its size is recorded as
1005 return MI->getOperand(2).getImm();
1006 case ARM::Int_eh_sjlj_setjmp: return 12;
1010 case ARM::tBR_JTr: {
1011 // These are jumptable branches, i.e. a branch followed by an inlined
1012 // jumptable. The size is 4 + 4 * number of entries.
1013 unsigned NumOps = TID.getNumOperands();
1014 MachineOperand JTOP =
1015 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
1016 unsigned JTI = JTOP.getIndex();
1017 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1018 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1019 assert(JTI < JT.size());
1020 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
1021 // 4 aligned. The assembler / linker may add 2 byte padding just before
1022 // the JT entries. The size does not include this padding; the
1023 // constant islands pass does separate bookkeeping for it.
1024 // FIXME: If we know the size of the function is less than (1 << 16) *2
1025 // bytes, we can use 16-bit entries instead. Then there won't be an
1027 return getNumJTEntries(JT, JTI) * 4 +
1028 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
1031 // Otherwise, pseudo-instruction sizes are zero.
1036 return 0; // Not reached