1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
28 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
29 : ARMBaseInstrInfo(STI), RI(*this, STI) {
32 unsigned ARMInstrInfo::
33 getUnindexedOpcode(unsigned Opc) const {
65 unsigned ARMInstrInfo::
66 getOpcode(ARMII::Op Op) const {
68 case ARMII::ADDri: return ARM::ADDri;
69 case ARMII::ADDrs: return ARM::ADDrs;
70 case ARMII::ADDrr: return ARM::ADDrr;
71 case ARMII::B: return ARM::B;
72 case ARMII::Bcc: return ARM::Bcc;
73 case ARMII::BR_JTr: return ARM::BR_JTr;
74 case ARMII::BR_JTm: return ARM::BR_JTm;
75 case ARMII::BR_JTadd: return ARM::BR_JTadd;
76 case ARMII::FCPYS: return ARM::FCPYS;
77 case ARMII::FCPYD: return ARM::FCPYD;
78 case ARMII::FLDD: return ARM::FLDD;
79 case ARMII::FLDS: return ARM::FLDS;
80 case ARMII::FSTD: return ARM::FSTD;
81 case ARMII::FSTS: return ARM::FSTS;
82 case ARMII::LDR: return ARM::LDR;
83 case ARMII::MOVr: return ARM::MOVr;
84 case ARMII::STR: return ARM::STR;
85 case ARMII::SUBri: return ARM::SUBri;
86 case ARMII::SUBrs: return ARM::SUBrs;
87 case ARMII::SUBrr: return ARM::SUBrr;
88 case ARMII::VMOVD: return ARM::VMOVD;
89 case ARMII::VMOVQ: return ARM::VMOVQ;
98 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
99 if (MBB.empty()) return false;
101 switch (MBB.back().getOpcode()) {
102 case ARM::BX_RET: // Return.
105 case ARM::BR_JTr: // Jumptable branch.
106 case ARM::BR_JTm: // Jumptable branch through mem.
107 case ARM::BR_JTadd: // Jumptable branch add to pc.
117 reMaterialize(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator I,
120 const MachineInstr *Orig) const {
121 DebugLoc dl = Orig->getDebugLoc();
122 if (Orig->getOpcode() == ARM::MOVi2pieces) {
123 RI.emitLoadConstPool(MBB, I, this, dl,
125 Orig->getOperand(1).getImm(),
126 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
127 Orig->getOperand(3).getReg());
131 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
132 MI->getOperand(0).setReg(DestReg);