1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
28 static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29 cl::desc("Enable ARM 2-addr to 3-addr conv"));
32 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
37 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
41 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
42 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
47 /// Return true if the instruction is a register to register move and
48 /// leave the source and dest operands in the passed parameters.
50 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
51 unsigned &SrcReg, unsigned &DstReg,
52 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
53 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
55 unsigned oc = MI.getOpcode();
61 SrcReg = MI.getOperand(1).getReg();
62 DstReg = MI.getOperand(0).getReg();
66 assert(MI.getDesc().getNumOperands() >= 2 &&
67 MI.getOperand(0).isReg() &&
68 MI.getOperand(1).isReg() &&
69 "Invalid ARM MOV instruction");
70 SrcReg = MI.getOperand(1).getReg();
71 DstReg = MI.getOperand(0).getReg();
76 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
77 int &FrameIndex) const {
78 switch (MI->getOpcode()) {
81 if (MI->getOperand(1).isFI() &&
82 MI->getOperand(2).isReg() &&
83 MI->getOperand(3).isImm() &&
84 MI->getOperand(2).getReg() == 0 &&
85 MI->getOperand(3).getImm() == 0) {
86 FrameIndex = MI->getOperand(1).getIndex();
87 return MI->getOperand(0).getReg();
92 if (MI->getOperand(1).isFI() &&
93 MI->getOperand(2).isImm() &&
94 MI->getOperand(2).getImm() == 0) {
95 FrameIndex = MI->getOperand(1).getIndex();
96 return MI->getOperand(0).getReg();
100 if (MI->getOperand(1).isFI() &&
101 MI->getOperand(2).isImm() &&
102 MI->getOperand(2).getImm() == 0) {
103 FrameIndex = MI->getOperand(1).getIndex();
104 return MI->getOperand(0).getReg();
111 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
112 int &FrameIndex) const {
113 switch (MI->getOpcode()) {
116 if (MI->getOperand(1).isFI() &&
117 MI->getOperand(2).isReg() &&
118 MI->getOperand(3).isImm() &&
119 MI->getOperand(2).getReg() == 0 &&
120 MI->getOperand(3).getImm() == 0) {
121 FrameIndex = MI->getOperand(1).getIndex();
122 return MI->getOperand(0).getReg();
127 if (MI->getOperand(1).isFI() &&
128 MI->getOperand(2).isImm() &&
129 MI->getOperand(2).getImm() == 0) {
130 FrameIndex = MI->getOperand(1).getIndex();
131 return MI->getOperand(0).getReg();
135 if (MI->getOperand(1).isFI() &&
136 MI->getOperand(2).isImm() &&
137 MI->getOperand(2).getImm() == 0) {
138 FrameIndex = MI->getOperand(1).getIndex();
139 return MI->getOperand(0).getReg();
146 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator I,
149 const MachineInstr *Orig) const {
150 DebugLoc dl = Orig->getDebugLoc();
151 if (Orig->getOpcode() == ARM::MOVi2pieces) {
152 RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
153 Orig->getOperand(2).getImm(),
154 Orig->getOperand(3).getReg(), this, false, dl);
158 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
159 MI->getOperand(0).setReg(DestReg);
163 static unsigned getUnindexedOpcode(unsigned Opc) {
176 case ARM::LDRSH_POST:
179 case ARM::LDRSB_POST:
195 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
196 MachineBasicBlock::iterator &MBBI,
197 LiveVariables *LV) const {
201 MachineInstr *MI = MBBI;
202 MachineFunction &MF = *MI->getParent()->getParent();
203 unsigned TSFlags = MI->getDesc().TSFlags;
205 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
206 default: return NULL;
207 case ARMII::IndexModePre:
210 case ARMII::IndexModePost:
214 // Try spliting an indexed load / store to a un-indexed one plus an add/sub
216 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
220 MachineInstr *UpdateMI = NULL;
221 MachineInstr *MemMI = NULL;
222 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
223 const TargetInstrDesc &TID = MI->getDesc();
224 unsigned NumOps = TID.getNumOperands();
225 bool isLoad = !TID.mayStore();
226 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
227 const MachineOperand &Base = MI->getOperand(2);
228 const MachineOperand &Offset = MI->getOperand(NumOps-3);
229 unsigned WBReg = WB.getReg();
230 unsigned BaseReg = Base.getReg();
231 unsigned OffReg = Offset.getReg();
232 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
233 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
236 assert(false && "Unknown indexed op!");
238 case ARMII::AddrMode2: {
239 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
240 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
242 int SOImmVal = ARM_AM::getSOImmVal(Amt);
244 // Can't encode it in a so_imm operand. This transformation will
245 // add more than 1 instruction. Abandon!
247 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
248 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
249 .addReg(BaseReg).addImm(SOImmVal)
250 .addImm(Pred).addReg(0).addReg(0);
251 } else if (Amt != 0) {
252 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
253 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
254 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
255 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
256 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
257 .addImm(Pred).addReg(0).addReg(0);
259 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
260 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
261 .addReg(BaseReg).addReg(OffReg)
262 .addImm(Pred).addReg(0).addReg(0);
265 case ARMII::AddrMode3 : {
266 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
267 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
269 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
270 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
271 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
272 .addReg(BaseReg).addImm(Amt)
273 .addImm(Pred).addReg(0).addReg(0);
275 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
276 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
277 .addReg(BaseReg).addReg(OffReg)
278 .addImm(Pred).addReg(0).addReg(0);
283 std::vector<MachineInstr*> NewMIs;
286 MemMI = BuildMI(MF, MI->getDebugLoc(),
287 get(MemOpc), MI->getOperand(0).getReg())
288 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
290 MemMI = BuildMI(MF, MI->getDebugLoc(),
291 get(MemOpc)).addReg(MI->getOperand(1).getReg())
292 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
293 NewMIs.push_back(MemMI);
294 NewMIs.push_back(UpdateMI);
297 MemMI = BuildMI(MF, MI->getDebugLoc(),
298 get(MemOpc), MI->getOperand(0).getReg())
299 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
301 MemMI = BuildMI(MF, MI->getDebugLoc(),
302 get(MemOpc)).addReg(MI->getOperand(1).getReg())
303 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
305 UpdateMI->getOperand(0).setIsDead();
306 NewMIs.push_back(UpdateMI);
307 NewMIs.push_back(MemMI);
310 // Transfer LiveVariables states, kill / dead info.
312 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
313 MachineOperand &MO = MI->getOperand(i);
314 if (MO.isReg() && MO.getReg() &&
315 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
316 unsigned Reg = MO.getReg();
318 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
320 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
322 LV->addVirtualRegisterDead(Reg, NewMI);
324 if (MO.isUse() && MO.isKill()) {
325 for (unsigned j = 0; j < 2; ++j) {
326 // Look at the two new MI's in reverse order.
327 MachineInstr *NewMI = NewMIs[j];
328 if (!NewMI->readsRegister(Reg))
330 LV->addVirtualRegisterKilled(Reg, NewMI);
331 if (VI.removeKill(MI))
332 VI.Kills.push_back(NewMI);
340 MFI->insert(MBBI, NewMIs[1]);
341 MFI->insert(MBBI, NewMIs[0]);
346 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
347 MachineBasicBlock *&FBB,
348 SmallVectorImpl<MachineOperand> &Cond,
349 bool AllowModify) const {
350 // If the block has no terminators, it just falls into the block after it.
351 MachineBasicBlock::iterator I = MBB.end();
352 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
355 // Get the last instruction in the block.
356 MachineInstr *LastInst = I;
358 // If there is only one terminator instruction, process it.
359 unsigned LastOpc = LastInst->getOpcode();
360 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
361 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
362 TBB = LastInst->getOperand(0).getMBB();
365 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
366 // Block ends with fall-through condbranch.
367 TBB = LastInst->getOperand(0).getMBB();
368 Cond.push_back(LastInst->getOperand(1));
369 Cond.push_back(LastInst->getOperand(2));
372 return true; // Can't handle indirect branch.
375 // Get the instruction before it if it is a terminator.
376 MachineInstr *SecondLastInst = I;
378 // If there are three terminators, we don't know what sort of block this is.
379 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
382 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
383 unsigned SecondLastOpc = SecondLastInst->getOpcode();
384 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
385 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
386 TBB = SecondLastInst->getOperand(0).getMBB();
387 Cond.push_back(SecondLastInst->getOperand(1));
388 Cond.push_back(SecondLastInst->getOperand(2));
389 FBB = LastInst->getOperand(0).getMBB();
393 // If the block ends with two unconditional branches, handle it. The second
394 // one is not executed, so remove it.
395 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
396 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
397 TBB = SecondLastInst->getOperand(0).getMBB();
400 I->eraseFromParent();
404 // Likewise if it ends with a branch table followed by an unconditional branch.
405 // The branch folder can create these, and we must get rid of them for
406 // correctness of Thumb constant islands.
407 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
408 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
409 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
412 I->eraseFromParent();
416 // Otherwise, can't handle this.
421 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
422 MachineFunction &MF = *MBB.getParent();
423 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
424 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
425 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
427 MachineBasicBlock::iterator I = MBB.end();
428 if (I == MBB.begin()) return 0;
430 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
433 // Remove the branch.
434 I->eraseFromParent();
438 if (I == MBB.begin()) return 1;
440 if (I->getOpcode() != BccOpc)
443 // Remove the branch.
444 I->eraseFromParent();
448 unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
449 MachineBasicBlock *FBB,
450 const SmallVectorImpl<MachineOperand> &Cond) const {
451 // FIXME this should probably have a DebugLoc argument
452 DebugLoc dl = DebugLoc::getUnknownLoc();
453 MachineFunction &MF = *MBB.getParent();
454 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
455 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
456 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
458 // Shouldn't be a fall through.
459 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
460 assert((Cond.size() == 2 || Cond.size() == 0) &&
461 "ARM branch conditions have two components!");
464 if (Cond.empty()) // Unconditional branch?
465 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
467 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
468 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
472 // Two-way conditional branch.
473 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
474 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
475 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
479 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
480 MachineBasicBlock::iterator I,
481 unsigned DestReg, unsigned SrcReg,
482 const TargetRegisterClass *DestRC,
483 const TargetRegisterClass *SrcRC) const {
484 if (DestRC != SrcRC) {
485 // Not yet supported!
489 DebugLoc DL = DebugLoc::getUnknownLoc();
490 if (I != MBB.end()) DL = I->getDebugLoc();
492 if (DestRC == ARM::GPRRegisterClass) {
493 MachineFunction &MF = *MBB.getParent();
494 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
495 if (AFI->isThumbFunction())
496 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
498 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
500 } else if (DestRC == ARM::SPRRegisterClass)
501 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
503 else if (DestRC == ARM::DPRRegisterClass)
504 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
512 static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
513 MachineOperand &MO) {
515 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
517 MIB = MIB.addImm(MO.getImm());
519 MIB = MIB.addFrameIndex(MO.getIndex());
521 assert(0 && "Unknown operand for ARMInstrAddOperand!");
527 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
528 unsigned SrcReg, bool isKill, int FI,
529 const TargetRegisterClass *RC) const {
530 DebugLoc DL = DebugLoc::getUnknownLoc();
531 if (I != MBB.end()) DL = I->getDebugLoc();
533 if (RC == ARM::GPRRegisterClass) {
534 MachineFunction &MF = *MBB.getParent();
535 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
536 if (AFI->isThumbFunction())
537 BuildMI(MBB, I, DL, get(ARM::tSpill))
538 .addReg(SrcReg, false, false, isKill)
539 .addFrameIndex(FI).addImm(0);
541 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
542 .addReg(SrcReg, false, false, isKill)
543 .addFrameIndex(FI).addReg(0).addImm(0));
544 } else if (RC == ARM::DPRRegisterClass) {
545 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
546 .addReg(SrcReg, false, false, isKill)
547 .addFrameIndex(FI).addImm(0));
549 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
550 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
551 .addReg(SrcReg, false, false, isKill)
552 .addFrameIndex(FI).addImm(0));
556 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
558 SmallVectorImpl<MachineOperand> &Addr,
559 const TargetRegisterClass *RC,
560 SmallVectorImpl<MachineInstr*> &NewMIs) const{
561 DebugLoc DL = DebugLoc::getUnknownLoc();
563 if (RC == ARM::GPRRegisterClass) {
564 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
565 if (AFI->isThumbFunction()) {
566 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
567 MachineInstrBuilder MIB =
568 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
569 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
570 MIB = ARMInstrAddOperand(MIB, Addr[i]);
571 NewMIs.push_back(MIB);
575 } else if (RC == ARM::DPRRegisterClass) {
578 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
582 MachineInstrBuilder MIB =
583 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
584 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
585 MIB = ARMInstrAddOperand(MIB, Addr[i]);
587 NewMIs.push_back(MIB);
592 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
593 unsigned DestReg, int FI,
594 const TargetRegisterClass *RC) const {
595 DebugLoc DL = DebugLoc::getUnknownLoc();
596 if (I != MBB.end()) DL = I->getDebugLoc();
598 if (RC == ARM::GPRRegisterClass) {
599 MachineFunction &MF = *MBB.getParent();
600 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
601 if (AFI->isThumbFunction())
602 BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
603 .addFrameIndex(FI).addImm(0);
605 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
606 .addFrameIndex(FI).addReg(0).addImm(0));
607 } else if (RC == ARM::DPRRegisterClass) {
608 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
609 .addFrameIndex(FI).addImm(0));
611 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
612 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
613 .addFrameIndex(FI).addImm(0));
617 void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
618 SmallVectorImpl<MachineOperand> &Addr,
619 const TargetRegisterClass *RC,
620 SmallVectorImpl<MachineInstr*> &NewMIs) const {
621 DebugLoc DL = DebugLoc::getUnknownLoc();
623 if (RC == ARM::GPRRegisterClass) {
624 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
625 if (AFI->isThumbFunction()) {
626 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
627 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
628 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
629 MIB = ARMInstrAddOperand(MIB, Addr[i]);
630 NewMIs.push_back(MIB);
634 } else if (RC == ARM::DPRRegisterClass) {
637 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
641 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
642 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
643 MIB = ARMInstrAddOperand(MIB, Addr[i]);
645 NewMIs.push_back(MIB);
649 bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
650 MachineBasicBlock::iterator MI,
651 const std::vector<CalleeSavedInfo> &CSI) const {
652 MachineFunction &MF = *MBB.getParent();
653 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
654 if (!AFI->isThumbFunction() || CSI.empty())
657 DebugLoc DL = DebugLoc::getUnknownLoc();
658 if (MI != MBB.end()) DL = MI->getDebugLoc();
660 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
661 for (unsigned i = CSI.size(); i != 0; --i) {
662 unsigned Reg = CSI[i-1].getReg();
663 // Add the callee-saved register as live-in. It's killed at the spill.
665 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
670 bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
671 MachineBasicBlock::iterator MI,
672 const std::vector<CalleeSavedInfo> &CSI) const {
673 MachineFunction &MF = *MBB.getParent();
674 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
675 if (!AFI->isThumbFunction() || CSI.empty())
678 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
679 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
680 MBB.insert(MI, PopMI);
681 for (unsigned i = CSI.size(); i != 0; --i) {
682 unsigned Reg = CSI[i-1].getReg();
683 if (Reg == ARM::LR) {
684 // Special epilogue for vararg functions. See emitEpilogue
688 PopMI->setDesc(get(ARM::tPOP_RET));
691 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
696 MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
698 const SmallVectorImpl<unsigned> &Ops,
700 if (Ops.size() != 1) return NULL;
702 unsigned OpNum = Ops[0];
703 unsigned Opc = MI->getOpcode();
704 MachineInstr *NewMI = NULL;
708 if (MI->getOperand(4).getReg() == ARM::CPSR)
709 // If it is updating CPSR, then it cannot be foled.
711 unsigned Pred = MI->getOperand(2).getImm();
712 unsigned PredReg = MI->getOperand(3).getReg();
713 if (OpNum == 0) { // move -> store
714 unsigned SrcReg = MI->getOperand(1).getReg();
715 bool isKill = MI->getOperand(1).isKill();
716 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
717 .addReg(SrcReg, false, false, isKill)
718 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
719 } else { // move -> load
720 unsigned DstReg = MI->getOperand(0).getReg();
721 bool isDead = MI->getOperand(0).isDead();
722 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
723 .addReg(DstReg, true, false, false, isDead)
724 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
729 if (OpNum == 0) { // move -> store
730 unsigned SrcReg = MI->getOperand(1).getReg();
731 bool isKill = MI->getOperand(1).isKill();
732 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
733 // tSpill cannot take a high register operand.
735 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
736 .addReg(SrcReg, false, false, isKill)
737 .addFrameIndex(FI).addImm(0);
738 } else { // move -> load
739 unsigned DstReg = MI->getOperand(0).getReg();
740 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
741 // tRestore cannot target a high register operand.
743 bool isDead = MI->getOperand(0).isDead();
744 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
745 .addReg(DstReg, true, false, false, isDead)
746 .addFrameIndex(FI).addImm(0);
751 unsigned Pred = MI->getOperand(2).getImm();
752 unsigned PredReg = MI->getOperand(3).getReg();
753 if (OpNum == 0) { // move -> store
754 unsigned SrcReg = MI->getOperand(1).getReg();
755 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
756 .addReg(SrcReg).addFrameIndex(FI)
757 .addImm(0).addImm(Pred).addReg(PredReg);
758 } else { // move -> load
759 unsigned DstReg = MI->getOperand(0).getReg();
760 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
762 .addImm(0).addImm(Pred).addReg(PredReg);
767 unsigned Pred = MI->getOperand(2).getImm();
768 unsigned PredReg = MI->getOperand(3).getReg();
769 if (OpNum == 0) { // move -> store
770 unsigned SrcReg = MI->getOperand(1).getReg();
771 bool isKill = MI->getOperand(1).isKill();
772 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
773 .addReg(SrcReg, false, false, isKill)
774 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
775 } else { // move -> load
776 unsigned DstReg = MI->getOperand(0).getReg();
777 bool isDead = MI->getOperand(0).isDead();
778 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
779 .addReg(DstReg, true, false, false, isDead)
780 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
789 bool ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
790 const SmallVectorImpl<unsigned> &Ops) const {
791 if (Ops.size() != 1) return false;
793 unsigned OpNum = Ops[0];
794 unsigned Opc = MI->getOpcode();
798 // If it is updating CPSR, then it cannot be foled.
799 return MI->getOperand(4).getReg() != ARM::CPSR;
801 if (OpNum == 0) { // move -> store
802 unsigned SrcReg = MI->getOperand(1).getReg();
803 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
804 // tSpill cannot take a high register operand.
806 } else { // move -> load
807 unsigned DstReg = MI->getOperand(0).getReg();
808 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
809 // tRestore cannot target a high register operand.
822 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
823 if (MBB.empty()) return false;
825 switch (MBB.back().getOpcode()) {
826 case ARM::BX_RET: // Return.
829 case ARM::tBX_RET_vararg:
832 case ARM::tB: // Uncond branch.
834 case ARM::BR_JTr: // Jumptable branch.
835 case ARM::BR_JTm: // Jumptable branch through mem.
836 case ARM::BR_JTadd: // Jumptable branch add to pc.
838 default: return false;
843 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
844 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
845 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
849 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
850 int PIdx = MI->findFirstPredOperandIdx();
851 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
854 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
855 const SmallVectorImpl<MachineOperand> &Pred) const {
856 unsigned Opc = MI->getOpcode();
857 if (Opc == ARM::B || Opc == ARM::tB) {
858 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
859 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
860 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
864 int PIdx = MI->findFirstPredOperandIdx();
866 MachineOperand &PMO = MI->getOperand(PIdx);
867 PMO.setImm(Pred[0].getImm());
868 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
875 ARMInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
876 const SmallVectorImpl<MachineOperand> &Pred2) const{
877 if (Pred1.size() > 2 || Pred2.size() > 2)
880 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
881 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
891 return CC2 == ARMCC::HI;
893 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
895 return CC2 == ARMCC::GT;
897 return CC2 == ARMCC::LT;
901 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
902 std::vector<MachineOperand> &Pred) const {
903 const TargetInstrDesc &TID = MI->getDesc();
904 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
908 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
909 const MachineOperand &MO = MI->getOperand(i);
910 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
920 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
921 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
922 unsigned JTI) DISABLE_INLINE;
923 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
925 return JT[JTI].MBBs.size();
928 /// GetInstSize - Return the size of the specified MachineInstr.
930 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
931 const MachineBasicBlock &MBB = *MI->getParent();
932 const MachineFunction *MF = MBB.getParent();
933 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
935 // Basic size info comes from the TSFlags field.
936 const TargetInstrDesc &TID = MI->getDesc();
937 unsigned TSFlags = TID.TSFlags;
939 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
941 // If this machine instr is an inline asm, measure it.
942 if (MI->getOpcode() == ARM::INLINEASM)
943 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
946 switch (MI->getOpcode()) {
948 assert(0 && "Unknown or unset size field for instr!");
950 case TargetInstrInfo::IMPLICIT_DEF:
951 case TargetInstrInfo::DECLARE:
952 case TargetInstrInfo::DBG_LABEL:
953 case TargetInstrInfo::EH_LABEL:
958 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
959 case ARMII::Size4Bytes: return 4; // Arm instruction.
960 case ARMII::Size2Bytes: return 2; // Thumb instruction.
961 case ARMII::SizeSpecial: {
962 switch (MI->getOpcode()) {
963 case ARM::CONSTPOOL_ENTRY:
964 // If this machine instr is a constant pool entry, its size is recorded as
966 return MI->getOperand(2).getImm();
971 // These are jumptable branches, i.e. a branch followed by an inlined
972 // jumptable. The size is 4 + 4 * number of entries.
973 unsigned NumOps = TID.getNumOperands();
974 MachineOperand JTOP =
975 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
976 unsigned JTI = JTOP.getIndex();
977 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
978 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
979 assert(JTI < JT.size());
980 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
981 // 4 aligned. The assembler / linker may add 2 byte padding just before
982 // the JT entries. The size does not include this padding; the
983 // constant islands pass does separate bookkeeping for it.
984 // FIXME: If we know the size of the function is less than (1 << 16) *2
985 // bytes, we can use 16-bit entries instead. Then there won't be an
987 return getNumJTEntries(JT, JTI) * 4 +
988 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
991 // Otherwise, pseudo-instruction sizes are zero.
996 return 0; // Not reached