1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/MC/MCAsmInfo.h"
27 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
28 : ARMBaseInstrInfo(STI), RI(*this, STI) {
31 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
63 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
64 if (MBB.empty()) return false;
66 switch (MBB.back().getOpcode()) {
67 case ARM::BX_RET: // Return.
71 case ARM::BR_JTr: // Jumptable branch.
72 case ARM::BR_JTm: // Jumptable branch through mem.
73 case ARM::BR_JTadd: // Jumptable branch add to pc.
83 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
84 unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
85 const TargetRegisterInfo *TRI) const {
86 DebugLoc dl = Orig->getDebugLoc();
87 unsigned Opcode = Orig->getOpcode();
91 case ARM::MOVi2pieces: {
92 RI.emitLoadConstPool(MBB, I, dl,
94 Orig->getOperand(1).getImm(),
95 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
96 Orig->getOperand(3).getReg());
97 MachineInstr *NewMI = prior(I);
98 NewMI->getOperand(0).setSubReg(SubIdx);
103 return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);