1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
62 //===------------------------------------------------------------------===//
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0x1f << FormShift,
75 // Pseudo instructions
76 Pseudo = 1 << FormShift,
78 // Multiply instructions
79 MulFrm = 2 << FormShift,
81 // Branch instructions
82 BrFrm = 3 << FormShift,
83 BrMiscFrm = 4 << FormShift,
85 // Data Processing instructions
86 DPFrm = 5 << FormShift,
87 DPSoRegFrm = 6 << FormShift,
90 LdFrm = 7 << FormShift,
91 StFrm = 8 << FormShift,
92 LdMiscFrm = 9 << FormShift,
93 StMiscFrm = 10 << FormShift,
94 LdMulFrm = 11 << FormShift,
95 StMulFrm = 12 << FormShift,
97 // Miscellaneous arithmetic instructions
98 ArithMiscFrm = 13 << FormShift,
100 // Extend instructions
101 ExtFrm = 14 << FormShift,
104 VFPUnaryFrm = 15 << FormShift,
105 VFPBinaryFrm = 16 << FormShift,
106 VFPConv1Frm = 17 << FormShift,
107 VFPConv2Frm = 18 << FormShift,
108 VFPConv3Frm = 19 << FormShift,
109 VFPLdStFrm = 20 << FormShift,
110 VFPLdStMulFrm = 21 << FormShift,
111 VFPMiscFrm = 22 << FormShift,
114 ThumbFrm = 23 << FormShift,
116 //===------------------------------------------------------------------===//
117 // Field shifts - such shifts are used to set field while generating
118 // machine instructions.
140 class ARMInstrInfo : public TargetInstrInfoImpl {
141 const ARMRegisterInfo RI;
143 explicit ARMInstrInfo(const ARMSubtarget &STI);
145 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
146 /// such, whenever a client has an instance of instruction info, it should
147 /// always be able to get register info as well (through this method).
149 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
151 /// getPointerRegClass - Return the register class to use to hold pointers.
152 /// This is used for addressing modes.
153 virtual const TargetRegisterClass *getPointerRegClass() const;
155 /// Return true if the instruction is a register to register move and
156 /// leave the source and dest operands in the passed parameters.
158 virtual bool isMoveInstr(const MachineInstr &MI,
159 unsigned &SrcReg, unsigned &DstReg) const;
160 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
161 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
163 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
164 unsigned DestReg, const MachineInstr *Orig) const;
166 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
167 MachineBasicBlock::iterator &MBBI,
168 LiveVariables *LV) const;
171 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
172 MachineBasicBlock *&FBB,
173 SmallVectorImpl<MachineOperand> &Cond) const;
174 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
175 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
176 MachineBasicBlock *FBB,
177 const SmallVectorImpl<MachineOperand> &Cond) const;
178 virtual bool copyRegToReg(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator I,
180 unsigned DestReg, unsigned SrcReg,
181 const TargetRegisterClass *DestRC,
182 const TargetRegisterClass *SrcRC) const;
183 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MBBI,
185 unsigned SrcReg, bool isKill, int FrameIndex,
186 const TargetRegisterClass *RC) const;
188 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
189 SmallVectorImpl<MachineOperand> &Addr,
190 const TargetRegisterClass *RC,
191 SmallVectorImpl<MachineInstr*> &NewMIs) const;
193 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator MBBI,
195 unsigned DestReg, int FrameIndex,
196 const TargetRegisterClass *RC) const;
198 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
199 SmallVectorImpl<MachineOperand> &Addr,
200 const TargetRegisterClass *RC,
201 SmallVectorImpl<MachineInstr*> &NewMIs) const;
202 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
203 MachineBasicBlock::iterator MI,
204 const std::vector<CalleeSavedInfo> &CSI) const;
205 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
206 MachineBasicBlock::iterator MI,
207 const std::vector<CalleeSavedInfo> &CSI) const;
209 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
211 const SmallVectorImpl<unsigned> &Ops,
212 int FrameIndex) const;
214 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
216 const SmallVectorImpl<unsigned> &Ops,
217 MachineInstr* LoadMI) const {
221 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
222 const SmallVectorImpl<unsigned> &Ops) const;
224 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
226 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
228 // Predication support.
229 virtual bool isPredicated(const MachineInstr *MI) const;
231 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
232 int PIdx = MI->findFirstPredOperandIdx();
233 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
238 bool PredicateInstruction(MachineInstr *MI,
239 const SmallVectorImpl<MachineOperand> &Pred) const;
242 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
243 const SmallVectorImpl<MachineOperand> &Pred2) const;
245 virtual bool DefinesPredicate(MachineInstr *MI,
246 std::vector<MachineOperand> &Pred) const;
248 /// GetInstSize - Returns the size of the specified MachineInstr.
250 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;