1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the TargetInstrInfo class.
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMINSTRUCTIONINFO_H
16 #define ARMINSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This three-bit field describes the addressing mode used. Zero is unused
34 // so that we can tell if we forgot to set a value.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
64 OpcodeMask = 0xf << OpcodeShift
68 class ARMInstrInfo : public TargetInstrInfo {
69 const ARMRegisterInfo RI;
71 ARMInstrInfo(const ARMSubtarget &STI);
73 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
74 /// such, whenever a client has an instance of instruction info, it should
75 /// always be able to get register info as well (through this method).
77 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
79 /// getPointerRegClass - Return the register class to use to hold pointers.
80 /// This is used for addressing modes.
81 virtual const TargetRegisterClass *getPointerRegClass() const;
83 /// Return true if the instruction is a register to register move and
84 /// leave the source and dest operands in the passed parameters.
86 virtual bool isMoveInstr(const MachineInstr &MI,
87 unsigned &SrcReg, unsigned &DstReg) const;
88 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
89 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
91 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
92 MachineBasicBlock::iterator &MBBI,
93 LiveVariables &LV) const;
96 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
97 MachineBasicBlock *&FBB,
98 std::vector<MachineOperand> &Cond) const;
99 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
100 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
101 MachineBasicBlock *FBB,
102 const std::vector<MachineOperand> &Cond) const;
103 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
104 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
106 // Predication support.
107 virtual bool isPredicated(const MachineInstr *MI) const;
110 bool PredicateInstruction(MachineInstr *MI,
111 const std::vector<MachineOperand> &Pred) const;
114 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
115 const std::vector<MachineOperand> &Pred1) const;
117 virtual bool DefinesPredicate(MachineInstr *MI,
118 std::vector<MachineOperand> &Pred) const;
123 /// GetInstSize - Returns the size of the specified MachineInstr.
125 unsigned GetInstSize(MachineInstr *MI);
127 /// GetFunctionSize - Returns the size of the specified MachineFunction.
129 unsigned GetFunctionSize(MachineFunction &MF);