1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
62 //===------------------------------------------------------------------===//
65 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66 // it doesn't have a Rn operand.
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0xf << FormShift,
75 // Pseudo instructions
76 Pseudo = 1 << FormShift,
78 // Multiply instructions
79 MulFrm = 2 << FormShift,
81 // Branch instructions
82 BrFrm = 3 << FormShift,
83 BrMiscFrm = 4 << FormShift,
85 // Data Processing instructions
86 DPFrm = 5 << FormShift,
87 DPSoRegFrm = 6 << FormShift,
90 LdFrm = 7 << FormShift,
91 StFrm = 8 << FormShift,
92 LdMiscFrm = 9 << FormShift,
93 StMiscFrm = 10 << FormShift,
94 LdMulFrm = 11 << FormShift,
95 StMulFrm = 12 << FormShift,
97 // Miscellaneous arithmetic instructions
98 ArithMiscFrm= 13 << FormShift,
100 // Extend instructions
101 ExtFrm = 14 << FormShift,
104 VPFFrm = 15 << FormShift,
105 VFPUnaryFrm = 16 << FormShift,
106 VFPBinaryFrm = 17 << FormShift,
109 ThumbFrm = 18 << FormShift,
111 //===------------------------------------------------------------------===//
112 // Field shifts - such shifts are used to set field while generating
113 // machine instructions.
137 class ARMInstrInfo : public TargetInstrInfoImpl {
138 const ARMRegisterInfo RI;
140 explicit ARMInstrInfo(const ARMSubtarget &STI);
142 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
143 /// such, whenever a client has an instance of instruction info, it should
144 /// always be able to get register info as well (through this method).
146 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
148 /// getPointerRegClass - Return the register class to use to hold pointers.
149 /// This is used for addressing modes.
150 virtual const TargetRegisterClass *getPointerRegClass() const;
152 /// Return true if the instruction is a register to register move and
153 /// leave the source and dest operands in the passed parameters.
155 virtual bool isMoveInstr(const MachineInstr &MI,
156 unsigned &SrcReg, unsigned &DstReg) const;
157 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
158 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
160 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
161 unsigned DestReg, const MachineInstr *Orig) const;
163 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
164 MachineBasicBlock::iterator &MBBI,
165 LiveVariables *LV) const;
168 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
169 MachineBasicBlock *&FBB,
170 SmallVectorImpl<MachineOperand> &Cond) const;
171 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
172 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
173 MachineBasicBlock *FBB,
174 const SmallVectorImpl<MachineOperand> &Cond) const;
175 virtual bool copyRegToReg(MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator I,
177 unsigned DestReg, unsigned SrcReg,
178 const TargetRegisterClass *DestRC,
179 const TargetRegisterClass *SrcRC) const;
180 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator MBBI,
182 unsigned SrcReg, bool isKill, int FrameIndex,
183 const TargetRegisterClass *RC) const;
185 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
186 SmallVectorImpl<MachineOperand> &Addr,
187 const TargetRegisterClass *RC,
188 SmallVectorImpl<MachineInstr*> &NewMIs) const;
190 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator MBBI,
192 unsigned DestReg, int FrameIndex,
193 const TargetRegisterClass *RC) const;
195 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
196 SmallVectorImpl<MachineOperand> &Addr,
197 const TargetRegisterClass *RC,
198 SmallVectorImpl<MachineInstr*> &NewMIs) const;
199 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
200 MachineBasicBlock::iterator MI,
201 const std::vector<CalleeSavedInfo> &CSI) const;
202 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
203 MachineBasicBlock::iterator MI,
204 const std::vector<CalleeSavedInfo> &CSI) const;
206 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
208 const SmallVectorImpl<unsigned> &Ops,
209 int FrameIndex) const;
211 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
213 const SmallVectorImpl<unsigned> &Ops,
214 MachineInstr* LoadMI) const {
218 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
219 const SmallVectorImpl<unsigned> &Ops) const;
221 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
223 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
225 // Predication support.
226 virtual bool isPredicated(const MachineInstr *MI) const;
228 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
229 int PIdx = MI->findFirstPredOperandIdx();
230 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
235 bool PredicateInstruction(MachineInstr *MI,
236 const SmallVectorImpl<MachineOperand> &Pred) const;
239 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
240 const SmallVectorImpl<MachineOperand> &Pred2) const;
242 virtual bool DefinesPredicate(MachineInstr *MI,
243 std::vector<MachineOperand> &Pred) const;
245 /// GetInstSize - Returns the size of the specified MachineInstr.
247 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;