1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
26 class ARMInstrInfo : public ARMBaseInstrInfo {
29 explicit ARMInstrInfo(const ARMSubtarget &STI);
31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
32 // if there is not such an opcode.
33 unsigned getUnindexedOpcode(unsigned Opc) const;
35 // Return true if the block does not fall through.
36 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
38 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
39 unsigned DestReg, unsigned SubIdx,
40 const MachineInstr *Orig,
41 const TargetRegisterInfo *TRI) const;
43 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
44 /// such, whenever a client has an instance of instruction info, it should
45 /// always be able to get register info as well (through this method).
47 const ARMRegisterInfo &getRegisterInfo() const { return RI; }