1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
23 /// ARMII - This namespace holds all of the target specific flags that
24 /// instruction info tracks.
28 //===------------------------------------------------------------------===//
31 //===------------------------------------------------------------------===//
32 // This three-bit field describes the addressing mode used. Zero is unused
33 // so that we can tell if we forgot to set a value.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
64 OpcodeMask = 0xf << OpcodeShift,
68 FormMask = 31 << FormShift,
70 // Pseudo instructions
71 Pseudo = 1 << FormShift,
73 // Multiply instructions
74 MulFrm = 2 << FormShift,
75 MulSMLAW = 3 << FormShift,
76 MulSMULW = 4 << FormShift,
77 MulSMLA = 5 << FormShift,
78 MulSMUL = 6 << FormShift,
80 // Branch instructions
81 Branch = 7 << FormShift,
82 BranchMisc = 8 << FormShift,
84 // Data Processing instructions
85 DPRdIm = 9 << FormShift,
86 DPRdReg = 10 << FormShift,
87 DPRdSoReg = 11 << FormShift,
88 DPRdMisc = 12 << FormShift,
90 DPRnIm = 13 << FormShift,
91 DPRnReg = 14 << FormShift,
92 DPRnSoReg = 15 << FormShift,
94 DPRIm = 16 << FormShift,
95 DPRReg = 17 << FormShift,
96 DPRSoReg = 18 << FormShift,
98 DPRImS = 19 << FormShift,
99 DPRRegS = 20 << FormShift,
100 DPRSoRegS = 21 << FormShift,
103 LdFrm = 22 << FormShift,
104 StFrm = 23 << FormShift,
106 // Miscellaneous arithmetic instructions
107 ArithMisc = 24 << FormShift,
110 ThumbFrm = 25 << FormShift,
113 VPFFrm = 26 << FormShift,
115 // Field shifts - such shifts are used to set field while generating
116 // machine instructions.
128 class ARMInstrInfo : public TargetInstrInfoImpl {
129 const ARMRegisterInfo RI;
131 explicit ARMInstrInfo(const ARMSubtarget &STI);
133 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
134 /// such, whenever a client has an instance of instruction info, it should
135 /// always be able to get register info as well (through this method).
137 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
139 /// getPointerRegClass - Return the register class to use to hold pointers.
140 /// This is used for addressing modes.
141 virtual const TargetRegisterClass *getPointerRegClass() const;
143 /// Return true if the instruction is a register to register move and
144 /// leave the source and dest operands in the passed parameters.
146 virtual bool isMoveInstr(const MachineInstr &MI,
147 unsigned &SrcReg, unsigned &DstReg) const;
148 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
149 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
151 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
152 unsigned DestReg, const MachineInstr *Orig) const;
154 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
155 MachineBasicBlock::iterator &MBBI,
156 LiveVariables &LV) const;
159 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
160 MachineBasicBlock *&FBB,
161 std::vector<MachineOperand> &Cond) const;
162 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
163 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
164 MachineBasicBlock *FBB,
165 const std::vector<MachineOperand> &Cond) const;
166 virtual void copyRegToReg(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator I,
168 unsigned DestReg, unsigned SrcReg,
169 const TargetRegisterClass *DestRC,
170 const TargetRegisterClass *SrcRC) const;
171 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
172 MachineBasicBlock::iterator MBBI,
173 unsigned SrcReg, bool isKill, int FrameIndex,
174 const TargetRegisterClass *RC) const;
176 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
177 SmallVectorImpl<MachineOperand> &Addr,
178 const TargetRegisterClass *RC,
179 SmallVectorImpl<MachineInstr*> &NewMIs) const;
181 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator MBBI,
183 unsigned DestReg, int FrameIndex,
184 const TargetRegisterClass *RC) const;
186 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
187 SmallVectorImpl<MachineOperand> &Addr,
188 const TargetRegisterClass *RC,
189 SmallVectorImpl<MachineInstr*> &NewMIs) const;
190 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator MI,
192 const std::vector<CalleeSavedInfo> &CSI) const;
193 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator MI,
195 const std::vector<CalleeSavedInfo> &CSI) const;
197 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
199 SmallVectorImpl<unsigned> &Ops,
200 int FrameIndex) const;
202 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
204 SmallVectorImpl<unsigned> &Ops,
205 MachineInstr* LoadMI) const {
209 virtual bool canFoldMemoryOperand(MachineInstr *MI,
210 SmallVectorImpl<unsigned> &Ops) const;
212 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
213 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
215 // Predication support.
216 virtual bool isPredicated(const MachineInstr *MI) const;
219 bool PredicateInstruction(MachineInstr *MI,
220 const std::vector<MachineOperand> &Pred) const;
223 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
224 const std::vector<MachineOperand> &Pred2) const;
226 virtual bool DefinesPredicate(MachineInstr *MI,
227 std::vector<MachineOperand> &Pred) const;
229 /// GetInstSize - Returns the size of the specified MachineInstr.
231 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;