1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the TargetInstrInfo class.
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMINSTRUCTIONINFO_H
16 #define ARMINSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This three-bit field describes the addressing mode used. Zero is unused
34 // so that we can tell if we forgot to set a value.
46 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
48 // Size* - Flags to keep track of the size of an instruction.
50 SizeMask = 7 << SizeShift,
51 SizeSpecial = 1, // 0 byte pseudo or special case.
56 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
59 IndexModeMask = 3 << IndexModeShift,
65 OpcodeMask = 0xf << OpcodeShift,
69 FormMask = 31 << FormShift,
71 // Pseudo instructions
72 Pseudo = 1 << FormShift,
74 // Multiply instructions
75 MulFrm = 2 << FormShift,
76 MulSMLAW = 3 << FormShift,
77 MulSMULW = 4 << FormShift,
78 MulSMLA = 5 << FormShift,
79 MulSMUL = 6 << FormShift,
81 // Branch instructions
82 Branch = 7 << FormShift,
83 BranchMisc = 8 << FormShift,
85 // Data Processing instructions
86 DPRdIm = 9 << FormShift,
87 DPRdReg = 10 << FormShift,
88 DPRdSoReg = 11 << FormShift,
89 DPRdMisc = 12 << FormShift,
91 DPRnIm = 13 << FormShift,
92 DPRnReg = 14 << FormShift,
93 DPRnSoReg = 15 << FormShift,
95 DPRIm = 16 << FormShift,
96 DPRReg = 17 << FormShift,
97 DPRSoReg = 18 << FormShift,
99 DPRImS = 19 << FormShift,
100 DPRRegS = 20 << FormShift,
101 DPRSoRegS = 21 << FormShift,
104 LdFrm = 22 << FormShift,
105 StFrm = 23 << FormShift,
107 // Miscellaneous arithmetic instructions
108 ArithMisc = 24 << FormShift,
111 ThumbFrm = 25 << FormShift,
114 VPFFrm = 26 << FormShift,
116 // Field shifts - such shifts are used to set field while generating
117 // machine instructions.
129 class ARMInstrInfo : public TargetInstrInfo {
130 const ARMRegisterInfo RI;
132 ARMInstrInfo(const ARMSubtarget &STI);
134 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
135 /// such, whenever a client has an instance of instruction info, it should
136 /// always be able to get register info as well (through this method).
138 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
140 /// getPointerRegClass - Return the register class to use to hold pointers.
141 /// This is used for addressing modes.
142 virtual const TargetRegisterClass *getPointerRegClass() const;
144 /// Return true if the instruction is a register to register move and
145 /// leave the source and dest operands in the passed parameters.
147 virtual bool isMoveInstr(const MachineInstr &MI,
148 unsigned &SrcReg, unsigned &DstReg) const;
149 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
150 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
152 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
153 MachineBasicBlock::iterator &MBBI,
154 LiveVariables &LV) const;
157 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
158 MachineBasicBlock *&FBB,
159 std::vector<MachineOperand> &Cond) const;
160 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
161 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
162 MachineBasicBlock *FBB,
163 const std::vector<MachineOperand> &Cond) const;
164 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
165 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
167 // Predication support.
168 virtual bool isPredicated(const MachineInstr *MI) const;
171 bool PredicateInstruction(MachineInstr *MI,
172 const std::vector<MachineOperand> &Pred) const;
175 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
176 const std::vector<MachineOperand> &Pred2) const;
178 virtual bool DefinesPredicate(MachineInstr *MI,
179 std::vector<MachineOperand> &Pred) const;
184 /// GetInstSize - Returns the size of the specified MachineInstr.
186 unsigned GetInstSize(MachineInstr *MI);
188 /// GetFunctionSize - Returns the size of the specified MachineFunction.
190 unsigned GetFunctionSize(MachineFunction &MF);