1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
23 /// ARMII - This namespace holds all of the target specific flags that
24 /// instruction info tracks.
28 //===------------------------------------------------------------------===//
31 //===------------------------------------------------------------------===//
32 // This three-bit field describes the addressing mode used. Zero is unused
33 // so that we can tell if we forgot to set a value.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
64 OpcodeMask = 0xf << OpcodeShift,
68 FormMask = 31 << FormShift,
70 // Pseudo instructions
71 Pseudo = 1 << FormShift,
73 // Multiply instructions
74 MulFrm = 2 << FormShift,
75 MulSMLAW = 3 << FormShift,
76 MulSMULW = 4 << FormShift,
77 MulSMLA = 5 << FormShift,
78 MulSMUL = 6 << FormShift,
80 // Branch instructions
81 Branch = 7 << FormShift,
82 BranchMisc = 8 << FormShift,
84 // Data Processing instructions
85 DPRdIm = 9 << FormShift,
86 DPRdReg = 10 << FormShift,
87 DPRdSoReg = 11 << FormShift,
88 DPRdMisc = 12 << FormShift,
90 DPRnIm = 13 << FormShift,
91 DPRnReg = 14 << FormShift,
92 DPRnSoReg = 15 << FormShift,
94 DPRIm = 16 << FormShift,
95 DPRReg = 17 << FormShift,
96 DPRSoReg = 18 << FormShift,
98 DPRImS = 19 << FormShift,
99 DPRRegS = 20 << FormShift,
100 DPRSoRegS = 21 << FormShift,
103 LdFrm = 22 << FormShift,
104 StFrm = 23 << FormShift,
106 // Miscellaneous arithmetic instructions
107 ArithMisc = 24 << FormShift,
110 ThumbFrm = 25 << FormShift,
113 VPFFrm = 26 << FormShift,
115 // Field shifts - such shifts are used to set field while generating
116 // machine instructions.
129 class ARMInstrInfo : public TargetInstrInfoImpl {
130 const ARMRegisterInfo RI;
132 explicit ARMInstrInfo(const ARMSubtarget &STI);
134 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
135 /// such, whenever a client has an instance of instruction info, it should
136 /// always be able to get register info as well (through this method).
138 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
140 /// getPointerRegClass - Return the register class to use to hold pointers.
141 /// This is used for addressing modes.
142 virtual const TargetRegisterClass *getPointerRegClass() const;
144 /// Return true if the instruction is a register to register move and
145 /// leave the source and dest operands in the passed parameters.
147 virtual bool isMoveInstr(const MachineInstr &MI,
148 unsigned &SrcReg, unsigned &DstReg) const;
149 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
150 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
152 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
153 unsigned DestReg, const MachineInstr *Orig) const;
155 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
156 MachineBasicBlock::iterator &MBBI,
157 LiveVariables *LV) const;
160 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
161 MachineBasicBlock *&FBB,
162 SmallVectorImpl<MachineOperand> &Cond) const;
163 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
164 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
165 MachineBasicBlock *FBB,
166 const SmallVectorImpl<MachineOperand> &Cond) const;
167 virtual bool copyRegToReg(MachineBasicBlock &MBB,
168 MachineBasicBlock::iterator I,
169 unsigned DestReg, unsigned SrcReg,
170 const TargetRegisterClass *DestRC,
171 const TargetRegisterClass *SrcRC) const;
172 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
173 MachineBasicBlock::iterator MBBI,
174 unsigned SrcReg, bool isKill, int FrameIndex,
175 const TargetRegisterClass *RC) const;
177 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
178 SmallVectorImpl<MachineOperand> &Addr,
179 const TargetRegisterClass *RC,
180 SmallVectorImpl<MachineInstr*> &NewMIs) const;
182 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
183 MachineBasicBlock::iterator MBBI,
184 unsigned DestReg, int FrameIndex,
185 const TargetRegisterClass *RC) const;
187 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
188 SmallVectorImpl<MachineOperand> &Addr,
189 const TargetRegisterClass *RC,
190 SmallVectorImpl<MachineInstr*> &NewMIs) const;
191 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
192 MachineBasicBlock::iterator MI,
193 const std::vector<CalleeSavedInfo> &CSI) const;
194 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
195 MachineBasicBlock::iterator MI,
196 const std::vector<CalleeSavedInfo> &CSI) const;
198 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
200 SmallVectorImpl<unsigned> &Ops,
201 int FrameIndex) const;
203 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
205 SmallVectorImpl<unsigned> &Ops,
206 MachineInstr* LoadMI) const {
210 virtual bool canFoldMemoryOperand(MachineInstr *MI,
211 SmallVectorImpl<unsigned> &Ops) const;
213 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
215 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
217 // Predication support.
218 virtual bool isPredicated(const MachineInstr *MI) const;
221 bool PredicateInstruction(MachineInstr *MI,
222 const SmallVectorImpl<MachineOperand> &Pred) const;
225 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
226 const SmallVectorImpl<MachineOperand> &Pred2) const;
228 virtual bool DefinesPredicate(MachineInstr *MI,
229 std::vector<MachineOperand> &Pred) const;
231 /// GetInstSize - Returns the size of the specified MachineInstr.
233 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;