1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
53 // Size* - Flags to keep track of the size of an instruction.
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
61 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
64 IndexModeMask = 3 << IndexModeShift,
68 //===------------------------------------------------------------------===//
71 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
72 // it doesn't have a Rn operand.
75 //===------------------------------------------------------------------===//
76 // Instruction encoding formats.
79 FormMask = 0x1f << FormShift,
81 // Pseudo instructions
82 Pseudo = 0 << FormShift,
84 // Multiply instructions
85 MulFrm = 1 << FormShift,
87 // Branch instructions
88 BrFrm = 2 << FormShift,
89 BrMiscFrm = 3 << FormShift,
91 // Data Processing instructions
92 DPFrm = 4 << FormShift,
93 DPSoRegFrm = 5 << FormShift,
96 LdFrm = 6 << FormShift,
97 StFrm = 7 << FormShift,
98 LdMiscFrm = 8 << FormShift,
99 StMiscFrm = 9 << FormShift,
100 LdStMulFrm = 10 << FormShift,
102 // Miscellaneous arithmetic instructions
103 ArithMiscFrm = 11 << FormShift,
105 // Extend instructions
106 ExtFrm = 12 << FormShift,
109 VFPUnaryFrm = 13 << FormShift,
110 VFPBinaryFrm = 14 << FormShift,
111 VFPConv1Frm = 15 << FormShift,
112 VFPConv2Frm = 16 << FormShift,
113 VFPConv3Frm = 17 << FormShift,
114 VFPConv4Frm = 18 << FormShift,
115 VFPConv5Frm = 19 << FormShift,
116 VFPLdStFrm = 20 << FormShift,
117 VFPLdStMulFrm = 21 << FormShift,
118 VFPMiscFrm = 22 << FormShift,
121 ThumbFrm = 23 << FormShift,
124 NEONFrm = 24 << FormShift,
125 NEONGetLnFrm = 25 << FormShift,
126 NEONSetLnFrm = 26 << FormShift,
127 NEONDupFrm = 27 << FormShift,
129 //===------------------------------------------------------------------===//
130 // Field shifts - such shifts are used to set field while generating
131 // machine instructions.
155 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
157 // Can be only subclassed.
158 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
160 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
161 MachineBasicBlock::iterator &MBBI,
162 LiveVariables *LV) const;
164 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
167 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
168 MachineBasicBlock *&FBB,
169 SmallVectorImpl<MachineOperand> &Cond,
170 bool AllowModify) const;
171 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
172 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
173 MachineBasicBlock *FBB,
174 const SmallVectorImpl<MachineOperand> &Cond) const;
176 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
178 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
180 // Predication support.
181 virtual bool isPredicated(const MachineInstr *MI) const;
183 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
184 int PIdx = MI->findFirstPredOperandIdx();
185 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
190 bool PredicateInstruction(MachineInstr *MI,
191 const SmallVectorImpl<MachineOperand> &Pred) const;
194 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
195 const SmallVectorImpl<MachineOperand> &Pred2) const;
197 virtual bool DefinesPredicate(MachineInstr *MI,
198 std::vector<MachineOperand> &Pred) const;
200 /// GetInstSize - Returns the size of the specified MachineInstr.
202 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
204 /// Return true if the instruction is a register to register move and return
205 /// the source and dest operands and their sub-register indices by reference.
206 virtual bool isMoveInstr(const MachineInstr &MI,
207 unsigned &SrcReg, unsigned &DstReg,
208 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
210 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
211 int &FrameIndex) const;
212 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
213 int &FrameIndex) const;
215 virtual bool copyRegToReg(MachineBasicBlock &MBB,
216 MachineBasicBlock::iterator I,
217 unsigned DestReg, unsigned SrcReg,
218 const TargetRegisterClass *DestRC,
219 const TargetRegisterClass *SrcRC) const;
220 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
221 MachineBasicBlock::iterator MBBI,
222 unsigned SrcReg, bool isKill, int FrameIndex,
223 const TargetRegisterClass *RC) const;
225 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
226 SmallVectorImpl<MachineOperand> &Addr,
227 const TargetRegisterClass *RC,
228 SmallVectorImpl<MachineInstr*> &NewMIs) const;
230 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
231 MachineBasicBlock::iterator MBBI,
232 unsigned DestReg, int FrameIndex,
233 const TargetRegisterClass *RC) const;
235 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
236 SmallVectorImpl<MachineOperand> &Addr,
237 const TargetRegisterClass *RC,
238 SmallVectorImpl<MachineInstr*> &NewMIs) const;
240 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
241 const SmallVectorImpl<unsigned> &Ops) const;
243 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
245 const SmallVectorImpl<unsigned> &Ops,
246 int FrameIndex) const;
248 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
250 const SmallVectorImpl<unsigned> &Ops,
251 MachineInstr* LoadMI) const;
254 class ARMInstrInfo : public ARMBaseInstrInfo {
257 explicit ARMInstrInfo(const ARMSubtarget &STI);
259 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
260 /// such, whenever a client has an instance of instruction info, it should
261 /// always be able to get register info as well (through this method).
263 const ARMRegisterInfo &getRegisterInfo() const { return RI; }
265 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
266 unsigned DestReg, const MachineInstr *Orig) const;