1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
99 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
101 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
103 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
104 [SDNPHasChain, SDNPSideEffect,
105 SDNPOptInGlue, SDNPOutGlue]>;
106 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
109 SDNPMayStore, SDNPMayLoad]>;
111 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
121 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
173 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
175 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
181 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
183 //===----------------------------------------------------------------------===//
184 // ARM Instruction Predicate Definitions.
186 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
187 AssemblerPredicate<"HasV4TOps", "armv4t">;
188 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
189 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
190 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
191 AssemblerPredicate<"HasV5TEOps", "armv5te">;
192 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
193 AssemblerPredicate<"HasV6Ops", "armv6">;
194 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
195 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
196 AssemblerPredicate<"HasV6MOps",
197 "armv6m or armv6t2">;
198 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
199 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
200 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
201 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
202 AssemblerPredicate<"HasV7Ops", "armv7">;
203 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
204 AssemblerPredicate<"HasV8Ops", "armv8">;
205 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
206 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
207 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
208 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
209 AssemblerPredicate<"FeatureVFP2", "VFP2">;
210 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
211 AssemblerPredicate<"FeatureVFP3", "VFP3">;
212 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
213 AssemblerPredicate<"FeatureVFP4", "VFP4">;
214 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
215 AssemblerPredicate<"!FeatureVFPOnlySP",
216 "double precision VFP">;
217 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
218 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
219 def HasNEON : Predicate<"Subtarget->hasNEON()">,
220 AssemblerPredicate<"FeatureNEON", "NEON">;
221 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
222 AssemblerPredicate<"FeatureCrypto", "crypto">;
223 def HasCRC : Predicate<"Subtarget->hasCRC()">,
224 AssemblerPredicate<"FeatureCRC", "crc">;
225 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
226 AssemblerPredicate<"FeatureFP16","half-float">;
227 def HasDivide : Predicate<"Subtarget->hasDivide()">,
228 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
229 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
230 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
231 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
232 AssemblerPredicate<"FeatureT2XtPk",
234 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
235 AssemblerPredicate<"FeatureDSPThumb2",
237 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
238 AssemblerPredicate<"FeatureDB",
240 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
241 AssemblerPredicate<"FeatureMP",
243 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
244 AssemblerPredicate<"FeatureTrustZone",
246 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
247 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
248 def IsThumb : Predicate<"Subtarget->isThumb()">,
249 AssemblerPredicate<"ModeThumb", "thumb">;
250 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
251 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
252 AssemblerPredicate<"ModeThumb,FeatureThumb2",
254 def IsMClass : Predicate<"Subtarget->isMClass()">,
255 AssemblerPredicate<"FeatureMClass", "armv*m">;
256 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
257 AssemblerPredicate<"!FeatureMClass",
259 def IsARM : Predicate<"!Subtarget->isThumb()">,
260 AssemblerPredicate<"!ModeThumb", "arm-mode">;
261 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
262 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
263 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
264 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
265 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
266 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
267 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
268 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
270 // FIXME: Eventually this will be just "hasV6T2Ops".
271 def UseMovt : Predicate<"Subtarget->useMovt()">;
272 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
273 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
274 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
276 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
277 // But only select them if more precision in FP computation is allowed.
278 // Do not use them for Darwin platforms.
279 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
280 " FPOpFusion::Fast && "
281 " Subtarget->hasVFP4()) && "
282 "!Subtarget->isTargetDarwin()">;
283 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
284 " FPOpFusion::Fast &&"
285 " Subtarget->hasVFP4()) || "
286 "Subtarget->isTargetDarwin()">;
288 // VGETLNi32 is microcoded on Swift - prefer VMOV.
289 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
290 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
292 // VDUP.32 is microcoded on Swift - prefer VMOV.
293 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
294 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
296 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
297 // this allows more effective execution domain optimization. See
298 // setExecutionDomain().
299 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
300 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
302 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
303 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
305 //===----------------------------------------------------------------------===//
306 // ARM Flag Definitions.
308 class RegConstraint<string C> {
309 string Constraints = C;
312 //===----------------------------------------------------------------------===//
313 // ARM specific transformation functions and pattern fragments.
316 // imm_neg_XFORM - Return the negation of an i32 immediate value.
317 def imm_neg_XFORM : SDNodeXForm<imm, [{
318 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
321 // imm_not_XFORM - Return the complement of a i32 immediate value.
322 def imm_not_XFORM : SDNodeXForm<imm, [{
323 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
326 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
327 def imm16_31 : ImmLeaf<i32, [{
328 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
331 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
332 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
333 unsigned Value = -(unsigned)N->getZExtValue();
334 return Value && ARM_AM::getSOImmVal(Value) != -1;
336 let ParserMatchClass = so_imm_neg_asmoperand;
339 // Note: this pattern doesn't require an encoder method and such, as it's
340 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
341 // is handled by the destination instructions, which use so_imm.
342 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
343 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
344 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
346 let ParserMatchClass = so_imm_not_asmoperand;
349 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
350 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
351 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
354 /// Split a 32-bit immediate into two 16 bit parts.
355 def hi16 : SDNodeXForm<imm, [{
356 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
359 def lo16AllZero : PatLeaf<(i32 imm), [{
360 // Returns true if all low 16-bits are 0.
361 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
364 class BinOpWithFlagFrag<dag res> :
365 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
366 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
367 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
369 // An 'and' node with a single use.
370 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
371 return N->hasOneUse();
374 // An 'xor' node with a single use.
375 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
376 return N->hasOneUse();
379 // An 'fmul' node with a single use.
380 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
381 return N->hasOneUse();
384 // An 'fadd' node which checks for single non-hazardous use.
385 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
386 return hasNoVMLxHazardUse(N);
389 // An 'fsub' node which checks for single non-hazardous use.
390 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
391 return hasNoVMLxHazardUse(N);
394 //===----------------------------------------------------------------------===//
395 // Operand Definitions.
398 // Immediate operands with a shared generic asm render method.
399 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
402 // FIXME: rename brtarget to t2_brtarget
403 def brtarget : Operand<OtherVT> {
404 let EncoderMethod = "getBranchTargetOpValue";
405 let OperandType = "OPERAND_PCREL";
406 let DecoderMethod = "DecodeT2BROperand";
409 // FIXME: get rid of this one?
410 def uncondbrtarget : Operand<OtherVT> {
411 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
412 let OperandType = "OPERAND_PCREL";
415 // Branch target for ARM. Handles conditional/unconditional
416 def br_target : Operand<OtherVT> {
417 let EncoderMethod = "getARMBranchTargetOpValue";
418 let OperandType = "OPERAND_PCREL";
422 // FIXME: rename bltarget to t2_bl_target?
423 def bltarget : Operand<i32> {
424 // Encoded the same as branch targets.
425 let EncoderMethod = "getBranchTargetOpValue";
426 let OperandType = "OPERAND_PCREL";
429 // Call target for ARM. Handles conditional/unconditional
430 // FIXME: rename bl_target to t2_bltarget?
431 def bl_target : Operand<i32> {
432 let EncoderMethod = "getARMBLTargetOpValue";
433 let OperandType = "OPERAND_PCREL";
436 def blx_target : Operand<i32> {
437 let EncoderMethod = "getARMBLXTargetOpValue";
438 let OperandType = "OPERAND_PCREL";
441 // A list of registers separated by comma. Used by load/store multiple.
442 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
443 def reglist : Operand<i32> {
444 let EncoderMethod = "getRegisterListOpValue";
445 let ParserMatchClass = RegListAsmOperand;
446 let PrintMethod = "printRegisterList";
447 let DecoderMethod = "DecodeRegListOperand";
450 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
452 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
453 def dpr_reglist : Operand<i32> {
454 let EncoderMethod = "getRegisterListOpValue";
455 let ParserMatchClass = DPRRegListAsmOperand;
456 let PrintMethod = "printRegisterList";
457 let DecoderMethod = "DecodeDPRRegListOperand";
460 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
461 def spr_reglist : Operand<i32> {
462 let EncoderMethod = "getRegisterListOpValue";
463 let ParserMatchClass = SPRRegListAsmOperand;
464 let PrintMethod = "printRegisterList";
465 let DecoderMethod = "DecodeSPRRegListOperand";
468 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
469 def cpinst_operand : Operand<i32> {
470 let PrintMethod = "printCPInstOperand";
474 def pclabel : Operand<i32> {
475 let PrintMethod = "printPCLabel";
478 // ADR instruction labels.
479 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
480 def adrlabel : Operand<i32> {
481 let EncoderMethod = "getAdrLabelOpValue";
482 let ParserMatchClass = AdrLabelAsmOperand;
483 let PrintMethod = "printAdrLabelOperand<0>";
486 def neon_vcvt_imm32 : Operand<i32> {
487 let EncoderMethod = "getNEONVcvtImm32OpValue";
488 let DecoderMethod = "DecodeVCVTImmOperand";
491 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
492 def rot_imm_XFORM: SDNodeXForm<imm, [{
493 switch (N->getZExtValue()){
495 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
496 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
497 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
498 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
501 def RotImmAsmOperand : AsmOperandClass {
503 let ParserMethod = "parseRotImm";
505 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
506 int32_t v = N->getZExtValue();
507 return v == 8 || v == 16 || v == 24; }],
509 let PrintMethod = "printRotImmOperand";
510 let ParserMatchClass = RotImmAsmOperand;
513 // shift_imm: An integer that encodes a shift amount and the type of shift
514 // (asr or lsl). The 6-bit immediate encodes as:
517 // {4-0} imm5 shift amount.
518 // asr #32 encoded as imm5 == 0.
519 def ShifterImmAsmOperand : AsmOperandClass {
520 let Name = "ShifterImm";
521 let ParserMethod = "parseShifterImm";
523 def shift_imm : Operand<i32> {
524 let PrintMethod = "printShiftImmOperand";
525 let ParserMatchClass = ShifterImmAsmOperand;
528 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
529 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
530 def so_reg_reg : Operand<i32>, // reg reg imm
531 ComplexPattern<i32, 3, "SelectRegShifterOperand",
532 [shl, srl, sra, rotr]> {
533 let EncoderMethod = "getSORegRegOpValue";
534 let PrintMethod = "printSORegRegOperand";
535 let DecoderMethod = "DecodeSORegRegOperand";
536 let ParserMatchClass = ShiftedRegAsmOperand;
537 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
540 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
541 def so_reg_imm : Operand<i32>, // reg imm
542 ComplexPattern<i32, 2, "SelectImmShifterOperand",
543 [shl, srl, sra, rotr]> {
544 let EncoderMethod = "getSORegImmOpValue";
545 let PrintMethod = "printSORegImmOperand";
546 let DecoderMethod = "DecodeSORegImmOperand";
547 let ParserMatchClass = ShiftedImmAsmOperand;
548 let MIOperandInfo = (ops GPR, i32imm);
551 // FIXME: Does this need to be distinct from so_reg?
552 def shift_so_reg_reg : Operand<i32>, // reg reg imm
553 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
554 [shl,srl,sra,rotr]> {
555 let EncoderMethod = "getSORegRegOpValue";
556 let PrintMethod = "printSORegRegOperand";
557 let DecoderMethod = "DecodeSORegRegOperand";
558 let ParserMatchClass = ShiftedRegAsmOperand;
559 let MIOperandInfo = (ops GPR, GPR, i32imm);
562 // FIXME: Does this need to be distinct from so_reg?
563 def shift_so_reg_imm : Operand<i32>, // reg reg imm
564 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
565 [shl,srl,sra,rotr]> {
566 let EncoderMethod = "getSORegImmOpValue";
567 let PrintMethod = "printSORegImmOperand";
568 let DecoderMethod = "DecodeSORegImmOperand";
569 let ParserMatchClass = ShiftedImmAsmOperand;
570 let MIOperandInfo = (ops GPR, i32imm);
574 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
575 // 8-bit immediate rotated by an arbitrary number of bits.
576 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
577 def so_imm : Operand<i32>, ImmLeaf<i32, [{
578 return ARM_AM::getSOImmVal(Imm) != -1;
580 let EncoderMethod = "getSOImmOpValue";
581 let ParserMatchClass = SOImmAsmOperand;
582 let DecoderMethod = "DecodeSOImmOperand";
585 // Break so_imm's up into two pieces. This handles immediates with up to 16
586 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
587 // get the first/second pieces.
588 def so_imm2part : PatLeaf<(imm), [{
589 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
592 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
594 def arm_i32imm : PatLeaf<(imm), [{
595 if (Subtarget->hasV6T2Ops())
597 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
600 /// imm0_1 predicate - Immediate in the range [0,1].
601 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
602 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
604 /// imm0_3 predicate - Immediate in the range [0,3].
605 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
606 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
608 /// imm0_7 predicate - Immediate in the range [0,7].
609 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
610 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
611 return Imm >= 0 && Imm < 8;
613 let ParserMatchClass = Imm0_7AsmOperand;
616 /// imm8 predicate - Immediate is exactly 8.
617 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
618 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
619 let ParserMatchClass = Imm8AsmOperand;
622 /// imm16 predicate - Immediate is exactly 16.
623 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
624 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
625 let ParserMatchClass = Imm16AsmOperand;
628 /// imm32 predicate - Immediate is exactly 32.
629 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
630 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
631 let ParserMatchClass = Imm32AsmOperand;
634 /// imm1_7 predicate - Immediate in the range [1,7].
635 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
636 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
637 let ParserMatchClass = Imm1_7AsmOperand;
640 /// imm1_15 predicate - Immediate in the range [1,15].
641 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
642 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
643 let ParserMatchClass = Imm1_15AsmOperand;
646 /// imm1_31 predicate - Immediate in the range [1,31].
647 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
648 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
649 let ParserMatchClass = Imm1_31AsmOperand;
652 /// imm0_15 predicate - Immediate in the range [0,15].
653 def Imm0_15AsmOperand: ImmAsmOperand {
654 let Name = "Imm0_15";
655 let DiagnosticType = "ImmRange0_15";
657 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
658 return Imm >= 0 && Imm < 16;
660 let ParserMatchClass = Imm0_15AsmOperand;
663 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
664 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
665 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
666 return Imm >= 0 && Imm < 32;
668 let ParserMatchClass = Imm0_31AsmOperand;
671 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
672 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
673 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
674 return Imm >= 0 && Imm < 32;
676 let ParserMatchClass = Imm0_32AsmOperand;
679 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
680 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
681 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
682 return Imm >= 0 && Imm < 64;
684 let ParserMatchClass = Imm0_63AsmOperand;
687 /// imm0_239 predicate - Immediate in the range [0,239].
688 def Imm0_239AsmOperand : ImmAsmOperand {
689 let Name = "Imm0_239";
690 let DiagnosticType = "ImmRange0_239";
692 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
693 let ParserMatchClass = Imm0_239AsmOperand;
696 /// imm0_255 predicate - Immediate in the range [0,255].
697 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
698 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
699 let ParserMatchClass = Imm0_255AsmOperand;
702 /// imm0_65535 - An immediate is in the range [0.65535].
703 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
704 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
705 return Imm >= 0 && Imm < 65536;
707 let ParserMatchClass = Imm0_65535AsmOperand;
710 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
711 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
712 return -Imm >= 0 && -Imm < 65536;
715 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
716 // a relocatable expression.
718 // FIXME: This really needs a Thumb version separate from the ARM version.
719 // While the range is the same, and can thus use the same match class,
720 // the encoding is different so it should have a different encoder method.
721 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
722 def imm0_65535_expr : Operand<i32> {
723 let EncoderMethod = "getHiLo16ImmOpValue";
724 let ParserMatchClass = Imm0_65535ExprAsmOperand;
727 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
728 def imm256_65535_expr : Operand<i32> {
729 let ParserMatchClass = Imm256_65535ExprAsmOperand;
732 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
733 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
734 def imm24b : Operand<i32>, ImmLeaf<i32, [{
735 return Imm >= 0 && Imm <= 0xffffff;
737 let ParserMatchClass = Imm24bitAsmOperand;
741 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
743 def BitfieldAsmOperand : AsmOperandClass {
744 let Name = "Bitfield";
745 let ParserMethod = "parseBitfield";
748 def bf_inv_mask_imm : Operand<i32>,
750 return ARM::isBitFieldInvertedMask(N->getZExtValue());
752 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
753 let PrintMethod = "printBitfieldInvMaskImmOperand";
754 let DecoderMethod = "DecodeBitfieldMaskOperand";
755 let ParserMatchClass = BitfieldAsmOperand;
758 def imm1_32_XFORM: SDNodeXForm<imm, [{
759 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
761 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
762 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
763 uint64_t Imm = N->getZExtValue();
764 return Imm > 0 && Imm <= 32;
767 let PrintMethod = "printImmPlusOneOperand";
768 let ParserMatchClass = Imm1_32AsmOperand;
771 def imm1_16_XFORM: SDNodeXForm<imm, [{
772 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
774 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
775 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
777 let PrintMethod = "printImmPlusOneOperand";
778 let ParserMatchClass = Imm1_16AsmOperand;
781 // Define ARM specific addressing modes.
782 // addrmode_imm12 := reg +/- imm12
784 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
785 class AddrMode_Imm12 : Operand<i32>,
786 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
787 // 12-bit immediate operand. Note that instructions using this encode
788 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
789 // immediate values are as normal.
791 let EncoderMethod = "getAddrModeImm12OpValue";
792 let DecoderMethod = "DecodeAddrModeImm12Operand";
793 let ParserMatchClass = MemImm12OffsetAsmOperand;
794 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
797 def addrmode_imm12 : AddrMode_Imm12 {
798 let PrintMethod = "printAddrModeImm12Operand<false>";
801 def addrmode_imm12_pre : AddrMode_Imm12 {
802 let PrintMethod = "printAddrModeImm12Operand<true>";
805 // ldst_so_reg := reg +/- reg shop imm
807 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
808 def ldst_so_reg : Operand<i32>,
809 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
810 let EncoderMethod = "getLdStSORegOpValue";
811 // FIXME: Simplify the printer
812 let PrintMethod = "printAddrMode2Operand";
813 let DecoderMethod = "DecodeSORegMemOperand";
814 let ParserMatchClass = MemRegOffsetAsmOperand;
815 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
818 // postidx_imm8 := +/- [0,255]
821 // {8} 1 is imm8 is non-negative. 0 otherwise.
822 // {7-0} [0,255] imm8 value.
823 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
824 def postidx_imm8 : Operand<i32> {
825 let PrintMethod = "printPostIdxImm8Operand";
826 let ParserMatchClass = PostIdxImm8AsmOperand;
827 let MIOperandInfo = (ops i32imm);
830 // postidx_imm8s4 := +/- [0,1020]
833 // {8} 1 is imm8 is non-negative. 0 otherwise.
834 // {7-0} [0,255] imm8 value, scaled by 4.
835 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
836 def postidx_imm8s4 : Operand<i32> {
837 let PrintMethod = "printPostIdxImm8s4Operand";
838 let ParserMatchClass = PostIdxImm8s4AsmOperand;
839 let MIOperandInfo = (ops i32imm);
843 // postidx_reg := +/- reg
845 def PostIdxRegAsmOperand : AsmOperandClass {
846 let Name = "PostIdxReg";
847 let ParserMethod = "parsePostIdxReg";
849 def postidx_reg : Operand<i32> {
850 let EncoderMethod = "getPostIdxRegOpValue";
851 let DecoderMethod = "DecodePostIdxReg";
852 let PrintMethod = "printPostIdxRegOperand";
853 let ParserMatchClass = PostIdxRegAsmOperand;
854 let MIOperandInfo = (ops GPRnopc, i32imm);
858 // addrmode2 := reg +/- imm12
859 // := reg +/- reg shop imm
861 // FIXME: addrmode2 should be refactored the rest of the way to always
862 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
863 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
864 def addrmode2 : Operand<i32>,
865 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
866 let EncoderMethod = "getAddrMode2OpValue";
867 let PrintMethod = "printAddrMode2Operand";
868 let ParserMatchClass = AddrMode2AsmOperand;
869 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
872 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
873 let Name = "PostIdxRegShifted";
874 let ParserMethod = "parsePostIdxReg";
876 def am2offset_reg : Operand<i32>,
877 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
878 [], [SDNPWantRoot]> {
879 let EncoderMethod = "getAddrMode2OffsetOpValue";
880 let PrintMethod = "printAddrMode2OffsetOperand";
881 // When using this for assembly, it's always as a post-index offset.
882 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
883 let MIOperandInfo = (ops GPRnopc, i32imm);
886 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
887 // the GPR is purely vestigal at this point.
888 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
889 def am2offset_imm : Operand<i32>,
890 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
891 [], [SDNPWantRoot]> {
892 let EncoderMethod = "getAddrMode2OffsetOpValue";
893 let PrintMethod = "printAddrMode2OffsetOperand";
894 let ParserMatchClass = AM2OffsetImmAsmOperand;
895 let MIOperandInfo = (ops GPRnopc, i32imm);
899 // addrmode3 := reg +/- reg
900 // addrmode3 := reg +/- imm8
902 // FIXME: split into imm vs. reg versions.
903 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
904 class AddrMode3 : Operand<i32>,
905 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
906 let EncoderMethod = "getAddrMode3OpValue";
907 let ParserMatchClass = AddrMode3AsmOperand;
908 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
911 def addrmode3 : AddrMode3
913 let PrintMethod = "printAddrMode3Operand<false>";
916 def addrmode3_pre : AddrMode3
918 let PrintMethod = "printAddrMode3Operand<true>";
921 // FIXME: split into imm vs. reg versions.
922 // FIXME: parser method to handle +/- register.
923 def AM3OffsetAsmOperand : AsmOperandClass {
924 let Name = "AM3Offset";
925 let ParserMethod = "parseAM3Offset";
927 def am3offset : Operand<i32>,
928 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
929 [], [SDNPWantRoot]> {
930 let EncoderMethod = "getAddrMode3OffsetOpValue";
931 let PrintMethod = "printAddrMode3OffsetOperand";
932 let ParserMatchClass = AM3OffsetAsmOperand;
933 let MIOperandInfo = (ops GPR, i32imm);
936 // ldstm_mode := {ia, ib, da, db}
938 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
939 let EncoderMethod = "getLdStmModeOpValue";
940 let PrintMethod = "printLdStmModeOperand";
943 // addrmode5 := reg +/- imm8*4
945 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
946 class AddrMode5 : Operand<i32>,
947 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
948 let EncoderMethod = "getAddrMode5OpValue";
949 let DecoderMethod = "DecodeAddrMode5Operand";
950 let ParserMatchClass = AddrMode5AsmOperand;
951 let MIOperandInfo = (ops GPR:$base, i32imm);
954 def addrmode5 : AddrMode5 {
955 let PrintMethod = "printAddrMode5Operand<false>";
958 def addrmode5_pre : AddrMode5 {
959 let PrintMethod = "printAddrMode5Operand<true>";
962 // addrmode6 := reg with optional alignment
964 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
965 def addrmode6 : Operand<i32>,
966 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
967 let PrintMethod = "printAddrMode6Operand";
968 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
969 let EncoderMethod = "getAddrMode6AddressOpValue";
970 let DecoderMethod = "DecodeAddrMode6Operand";
971 let ParserMatchClass = AddrMode6AsmOperand;
974 def am6offset : Operand<i32>,
975 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
976 [], [SDNPWantRoot]> {
977 let PrintMethod = "printAddrMode6OffsetOperand";
978 let MIOperandInfo = (ops GPR);
979 let EncoderMethod = "getAddrMode6OffsetOpValue";
980 let DecoderMethod = "DecodeGPRRegisterClass";
983 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
984 // (single element from one lane) for size 32.
985 def addrmode6oneL32 : Operand<i32>,
986 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
987 let PrintMethod = "printAddrMode6Operand";
988 let MIOperandInfo = (ops GPR:$addr, i32imm);
989 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
992 // Special version of addrmode6 to handle alignment encoding for VLD-dup
993 // instructions, specifically VLD4-dup.
994 def addrmode6dup : Operand<i32>,
995 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
996 let PrintMethod = "printAddrMode6Operand";
997 let MIOperandInfo = (ops GPR:$addr, i32imm);
998 let EncoderMethod = "getAddrMode6DupAddressOpValue";
999 // FIXME: This is close, but not quite right. The alignment specifier is
1001 let ParserMatchClass = AddrMode6AsmOperand;
1004 // addrmodepc := pc + reg
1006 def addrmodepc : Operand<i32>,
1007 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1008 let PrintMethod = "printAddrModePCOperand";
1009 let MIOperandInfo = (ops GPR, i32imm);
1012 // addr_offset_none := reg
1014 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1015 def addr_offset_none : Operand<i32>,
1016 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1017 let PrintMethod = "printAddrMode7Operand";
1018 let DecoderMethod = "DecodeAddrMode7Operand";
1019 let ParserMatchClass = MemNoOffsetAsmOperand;
1020 let MIOperandInfo = (ops GPR:$base);
1023 def nohash_imm : Operand<i32> {
1024 let PrintMethod = "printNoHashImmediate";
1027 def CoprocNumAsmOperand : AsmOperandClass {
1028 let Name = "CoprocNum";
1029 let ParserMethod = "parseCoprocNumOperand";
1031 def p_imm : Operand<i32> {
1032 let PrintMethod = "printPImmediate";
1033 let ParserMatchClass = CoprocNumAsmOperand;
1034 let DecoderMethod = "DecodeCoprocessor";
1037 def CoprocRegAsmOperand : AsmOperandClass {
1038 let Name = "CoprocReg";
1039 let ParserMethod = "parseCoprocRegOperand";
1041 def c_imm : Operand<i32> {
1042 let PrintMethod = "printCImmediate";
1043 let ParserMatchClass = CoprocRegAsmOperand;
1045 def CoprocOptionAsmOperand : AsmOperandClass {
1046 let Name = "CoprocOption";
1047 let ParserMethod = "parseCoprocOptionOperand";
1049 def coproc_option_imm : Operand<i32> {
1050 let PrintMethod = "printCoprocOptionImm";
1051 let ParserMatchClass = CoprocOptionAsmOperand;
1054 //===----------------------------------------------------------------------===//
1056 include "ARMInstrFormats.td"
1058 //===----------------------------------------------------------------------===//
1059 // Multiclass helpers...
1062 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1063 /// binop that produces a value.
1064 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1065 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1066 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1067 PatFrag opnode, bit Commutable = 0> {
1068 // The register-immediate version is re-materializable. This is useful
1069 // in particular for taking the address of a local.
1070 let isReMaterializable = 1 in {
1071 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1072 iii, opc, "\t$Rd, $Rn, $imm",
1073 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1074 Sched<[WriteALU, ReadALU]> {
1079 let Inst{19-16} = Rn;
1080 let Inst{15-12} = Rd;
1081 let Inst{11-0} = imm;
1084 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1085 iir, opc, "\t$Rd, $Rn, $Rm",
1086 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1087 Sched<[WriteALU, ReadALU, ReadALU]> {
1092 let isCommutable = Commutable;
1093 let Inst{19-16} = Rn;
1094 let Inst{15-12} = Rd;
1095 let Inst{11-4} = 0b00000000;
1099 def rsi : AsI1<opcod, (outs GPR:$Rd),
1100 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1101 iis, opc, "\t$Rd, $Rn, $shift",
1102 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1103 Sched<[WriteALUsi, ReadALU]> {
1108 let Inst{19-16} = Rn;
1109 let Inst{15-12} = Rd;
1110 let Inst{11-5} = shift{11-5};
1112 let Inst{3-0} = shift{3-0};
1115 def rsr : AsI1<opcod, (outs GPR:$Rd),
1116 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1117 iis, opc, "\t$Rd, $Rn, $shift",
1118 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1119 Sched<[WriteALUsr, ReadALUsr]> {
1124 let Inst{19-16} = Rn;
1125 let Inst{15-12} = Rd;
1126 let Inst{11-8} = shift{11-8};
1128 let Inst{6-5} = shift{6-5};
1130 let Inst{3-0} = shift{3-0};
1134 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1135 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1136 /// it is equivalent to the AsI1_bin_irs counterpart.
1137 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1138 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1139 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1140 PatFrag opnode, bit Commutable = 0> {
1141 // The register-immediate version is re-materializable. This is useful
1142 // in particular for taking the address of a local.
1143 let isReMaterializable = 1 in {
1144 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1145 iii, opc, "\t$Rd, $Rn, $imm",
1146 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1147 Sched<[WriteALU, ReadALU]> {
1152 let Inst{19-16} = Rn;
1153 let Inst{15-12} = Rd;
1154 let Inst{11-0} = imm;
1157 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1158 iir, opc, "\t$Rd, $Rn, $Rm",
1159 [/* pattern left blank */]>,
1160 Sched<[WriteALU, ReadALU, ReadALU]> {
1164 let Inst{11-4} = 0b00000000;
1167 let Inst{15-12} = Rd;
1168 let Inst{19-16} = Rn;
1171 def rsi : AsI1<opcod, (outs GPR:$Rd),
1172 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1173 iis, opc, "\t$Rd, $Rn, $shift",
1174 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1175 Sched<[WriteALUsi, ReadALU]> {
1180 let Inst{19-16} = Rn;
1181 let Inst{15-12} = Rd;
1182 let Inst{11-5} = shift{11-5};
1184 let Inst{3-0} = shift{3-0};
1187 def rsr : AsI1<opcod, (outs GPR:$Rd),
1188 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1189 iis, opc, "\t$Rd, $Rn, $shift",
1190 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1191 Sched<[WriteALUsr, ReadALUsr]> {
1196 let Inst{19-16} = Rn;
1197 let Inst{15-12} = Rd;
1198 let Inst{11-8} = shift{11-8};
1200 let Inst{6-5} = shift{6-5};
1202 let Inst{3-0} = shift{3-0};
1206 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1208 /// These opcodes will be converted to the real non-S opcodes by
1209 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1210 let hasPostISelHook = 1, Defs = [CPSR] in {
1211 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1212 InstrItinClass iis, PatFrag opnode,
1213 bit Commutable = 0> {
1214 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1216 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1217 Sched<[WriteALU, ReadALU]>;
1219 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1221 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1222 Sched<[WriteALU, ReadALU, ReadALU]> {
1223 let isCommutable = Commutable;
1225 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1226 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1228 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1229 so_reg_imm:$shift))]>,
1230 Sched<[WriteALUsi, ReadALU]>;
1232 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1233 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1235 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1236 so_reg_reg:$shift))]>,
1237 Sched<[WriteALUSsr, ReadALUsr]>;
1241 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1242 /// operands are reversed.
1243 let hasPostISelHook = 1, Defs = [CPSR] in {
1244 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1245 InstrItinClass iis, PatFrag opnode,
1246 bit Commutable = 0> {
1247 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1249 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1250 Sched<[WriteALU, ReadALU]>;
1252 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1253 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1255 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1257 Sched<[WriteALUsi, ReadALU]>;
1259 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1260 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1262 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1264 Sched<[WriteALUSsr, ReadALUsr]>;
1268 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1269 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1270 /// a explicit result, only implicitly set CPSR.
1271 let isCompare = 1, Defs = [CPSR] in {
1272 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1273 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1274 PatFrag opnode, bit Commutable = 0> {
1275 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1277 [(opnode GPR:$Rn, so_imm:$imm)]>,
1278 Sched<[WriteCMP, ReadALU]> {
1283 let Inst{19-16} = Rn;
1284 let Inst{15-12} = 0b0000;
1285 let Inst{11-0} = imm;
1287 let Unpredictable{15-12} = 0b1111;
1289 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1291 [(opnode GPR:$Rn, GPR:$Rm)]>,
1292 Sched<[WriteCMP, ReadALU, ReadALU]> {
1295 let isCommutable = Commutable;
1298 let Inst{19-16} = Rn;
1299 let Inst{15-12} = 0b0000;
1300 let Inst{11-4} = 0b00000000;
1303 let Unpredictable{15-12} = 0b1111;
1305 def rsi : AI1<opcod, (outs),
1306 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1307 opc, "\t$Rn, $shift",
1308 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1309 Sched<[WriteCMPsi, ReadALU]> {
1314 let Inst{19-16} = Rn;
1315 let Inst{15-12} = 0b0000;
1316 let Inst{11-5} = shift{11-5};
1318 let Inst{3-0} = shift{3-0};
1320 let Unpredictable{15-12} = 0b1111;
1322 def rsr : AI1<opcod, (outs),
1323 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1324 opc, "\t$Rn, $shift",
1325 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1326 Sched<[WriteCMPsr, ReadALU]> {
1331 let Inst{19-16} = Rn;
1332 let Inst{15-12} = 0b0000;
1333 let Inst{11-8} = shift{11-8};
1335 let Inst{6-5} = shift{6-5};
1337 let Inst{3-0} = shift{3-0};
1339 let Unpredictable{15-12} = 0b1111;
1345 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1346 /// register and one whose operand is a register rotated by 8/16/24.
1347 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1348 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1349 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1350 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1351 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1352 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1356 let Inst{19-16} = 0b1111;
1357 let Inst{15-12} = Rd;
1358 let Inst{11-10} = rot;
1362 class AI_ext_rrot_np<bits<8> opcod, string opc>
1363 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1364 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1365 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1367 let Inst{19-16} = 0b1111;
1368 let Inst{11-10} = rot;
1371 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1372 /// register and one whose operand is a register rotated by 8/16/24.
1373 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1374 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1375 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1376 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1377 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1378 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1383 let Inst{19-16} = Rn;
1384 let Inst{15-12} = Rd;
1385 let Inst{11-10} = rot;
1386 let Inst{9-4} = 0b000111;
1390 class AI_exta_rrot_np<bits<8> opcod, string opc>
1391 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1392 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1393 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1396 let Inst{19-16} = Rn;
1397 let Inst{11-10} = rot;
1400 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1401 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1402 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1403 bit Commutable = 0> {
1404 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1405 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1406 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1407 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1409 Sched<[WriteALU, ReadALU]> {
1414 let Inst{15-12} = Rd;
1415 let Inst{19-16} = Rn;
1416 let Inst{11-0} = imm;
1418 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1419 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1420 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1422 Sched<[WriteALU, ReadALU, ReadALU]> {
1426 let Inst{11-4} = 0b00000000;
1428 let isCommutable = Commutable;
1430 let Inst{15-12} = Rd;
1431 let Inst{19-16} = Rn;
1433 def rsi : AsI1<opcod, (outs GPR:$Rd),
1434 (ins GPR:$Rn, so_reg_imm:$shift),
1435 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1436 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1438 Sched<[WriteALUsi, ReadALU]> {
1443 let Inst{19-16} = Rn;
1444 let Inst{15-12} = Rd;
1445 let Inst{11-5} = shift{11-5};
1447 let Inst{3-0} = shift{3-0};
1449 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1450 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1451 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1452 [(set GPRnopc:$Rd, CPSR,
1453 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1455 Sched<[WriteALUsr, ReadALUsr]> {
1460 let Inst{19-16} = Rn;
1461 let Inst{15-12} = Rd;
1462 let Inst{11-8} = shift{11-8};
1464 let Inst{6-5} = shift{6-5};
1466 let Inst{3-0} = shift{3-0};
1471 /// AI1_rsc_irs - Define instructions and patterns for rsc
1472 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1473 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1474 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1475 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1476 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1477 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1479 Sched<[WriteALU, ReadALU]> {
1484 let Inst{15-12} = Rd;
1485 let Inst{19-16} = Rn;
1486 let Inst{11-0} = imm;
1488 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1489 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1490 [/* pattern left blank */]>,
1491 Sched<[WriteALU, ReadALU, ReadALU]> {
1495 let Inst{11-4} = 0b00000000;
1498 let Inst{15-12} = Rd;
1499 let Inst{19-16} = Rn;
1501 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1502 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1503 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1505 Sched<[WriteALUsi, ReadALU]> {
1510 let Inst{19-16} = Rn;
1511 let Inst{15-12} = Rd;
1512 let Inst{11-5} = shift{11-5};
1514 let Inst{3-0} = shift{3-0};
1516 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1517 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1518 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1520 Sched<[WriteALUsr, ReadALUsr]> {
1525 let Inst{19-16} = Rn;
1526 let Inst{15-12} = Rd;
1527 let Inst{11-8} = shift{11-8};
1529 let Inst{6-5} = shift{6-5};
1531 let Inst{3-0} = shift{3-0};
1536 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1537 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1538 InstrItinClass iir, PatFrag opnode> {
1539 // Note: We use the complex addrmode_imm12 rather than just an input
1540 // GPR and a constrained immediate so that we can use this to match
1541 // frame index references and avoid matching constant pool references.
1542 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1543 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1544 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1547 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1548 let Inst{19-16} = addr{16-13}; // Rn
1549 let Inst{15-12} = Rt;
1550 let Inst{11-0} = addr{11-0}; // imm12
1552 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1553 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1554 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1557 let shift{4} = 0; // Inst{4} = 0
1558 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1559 let Inst{19-16} = shift{16-13}; // Rn
1560 let Inst{15-12} = Rt;
1561 let Inst{11-0} = shift{11-0};
1566 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1567 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1568 InstrItinClass iir, PatFrag opnode> {
1569 // Note: We use the complex addrmode_imm12 rather than just an input
1570 // GPR and a constrained immediate so that we can use this to match
1571 // frame index references and avoid matching constant pool references.
1572 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1573 (ins addrmode_imm12:$addr),
1574 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1575 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1578 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1579 let Inst{19-16} = addr{16-13}; // Rn
1580 let Inst{15-12} = Rt;
1581 let Inst{11-0} = addr{11-0}; // imm12
1583 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1584 (ins ldst_so_reg:$shift),
1585 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1586 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1589 let shift{4} = 0; // Inst{4} = 0
1590 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1591 let Inst{19-16} = shift{16-13}; // Rn
1592 let Inst{15-12} = Rt;
1593 let Inst{11-0} = shift{11-0};
1599 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1600 InstrItinClass iir, PatFrag opnode> {
1601 // Note: We use the complex addrmode_imm12 rather than just an input
1602 // GPR and a constrained immediate so that we can use this to match
1603 // frame index references and avoid matching constant pool references.
1604 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1605 (ins GPR:$Rt, addrmode_imm12:$addr),
1606 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1607 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1610 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1611 let Inst{19-16} = addr{16-13}; // Rn
1612 let Inst{15-12} = Rt;
1613 let Inst{11-0} = addr{11-0}; // imm12
1615 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1616 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1617 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1620 let shift{4} = 0; // Inst{4} = 0
1621 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1622 let Inst{19-16} = shift{16-13}; // Rn
1623 let Inst{15-12} = Rt;
1624 let Inst{11-0} = shift{11-0};
1628 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1629 InstrItinClass iir, PatFrag opnode> {
1630 // Note: We use the complex addrmode_imm12 rather than just an input
1631 // GPR and a constrained immediate so that we can use this to match
1632 // frame index references and avoid matching constant pool references.
1633 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1634 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1635 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1636 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1639 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1640 let Inst{19-16} = addr{16-13}; // Rn
1641 let Inst{15-12} = Rt;
1642 let Inst{11-0} = addr{11-0}; // imm12
1644 def rs : AI2ldst<0b011, 0, isByte, (outs),
1645 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1646 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1647 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1650 let shift{4} = 0; // Inst{4} = 0
1651 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1652 let Inst{19-16} = shift{16-13}; // Rn
1653 let Inst{15-12} = Rt;
1654 let Inst{11-0} = shift{11-0};
1659 //===----------------------------------------------------------------------===//
1661 //===----------------------------------------------------------------------===//
1663 //===----------------------------------------------------------------------===//
1664 // Miscellaneous Instructions.
1667 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1668 /// the function. The first operand is the ID# for this instruction, the second
1669 /// is the index into the MachineConstantPool that this is, the third is the
1670 /// size in bytes of this constant pool entry.
1671 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1672 def CONSTPOOL_ENTRY :
1673 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1674 i32imm:$size), NoItinerary, []>;
1676 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1677 // from removing one half of the matched pairs. That breaks PEI, which assumes
1678 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1679 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1680 def ADJCALLSTACKUP :
1681 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1682 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1684 def ADJCALLSTACKDOWN :
1685 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1686 [(ARMcallseq_start timm:$amt)]>;
1689 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1690 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1692 let Inst{27-8} = 0b00110010000011110000;
1693 let Inst{7-0} = imm;
1696 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1697 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1698 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1699 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1700 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1701 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1703 def : Pat<(int_arm_sevl), (HINT 5)>;
1705 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1706 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1711 let Inst{15-12} = Rd;
1712 let Inst{19-16} = Rn;
1713 let Inst{27-20} = 0b01101000;
1714 let Inst{7-4} = 0b1011;
1715 let Inst{11-8} = 0b1111;
1716 let Unpredictable{11-8} = 0b1111;
1719 // The 16-bit operand $val can be used by a debugger to store more information
1720 // about the breakpoint.
1721 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1722 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1724 let Inst{3-0} = val{3-0};
1725 let Inst{19-8} = val{15-4};
1726 let Inst{27-20} = 0b00010010;
1727 let Inst{31-28} = 0xe; // AL
1728 let Inst{7-4} = 0b0111;
1730 // default immediate for breakpoint mnemonic
1731 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1733 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1734 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1736 let Inst{3-0} = val{3-0};
1737 let Inst{19-8} = val{15-4};
1738 let Inst{27-20} = 0b00010000;
1739 let Inst{31-28} = 0xe; // AL
1740 let Inst{7-4} = 0b0111;
1743 // Change Processor State
1744 // FIXME: We should use InstAlias to handle the optional operands.
1745 class CPS<dag iops, string asm_ops>
1746 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1747 []>, Requires<[IsARM]> {
1753 let Inst{31-28} = 0b1111;
1754 let Inst{27-20} = 0b00010000;
1755 let Inst{19-18} = imod;
1756 let Inst{17} = M; // Enabled if mode is set;
1757 let Inst{16-9} = 0b00000000;
1758 let Inst{8-6} = iflags;
1760 let Inst{4-0} = mode;
1763 let DecoderMethod = "DecodeCPSInstruction" in {
1765 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1766 "$imod\t$iflags, $mode">;
1767 let mode = 0, M = 0 in
1768 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1770 let imod = 0, iflags = 0, M = 1 in
1771 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1774 // Preload signals the memory system of possible future data/instruction access.
1775 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1777 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1778 !strconcat(opc, "\t$addr"),
1779 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1780 Sched<[WritePreLd]> {
1783 let Inst{31-26} = 0b111101;
1784 let Inst{25} = 0; // 0 for immediate form
1785 let Inst{24} = data;
1786 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1787 let Inst{22} = read;
1788 let Inst{21-20} = 0b01;
1789 let Inst{19-16} = addr{16-13}; // Rn
1790 let Inst{15-12} = 0b1111;
1791 let Inst{11-0} = addr{11-0}; // imm12
1794 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1795 !strconcat(opc, "\t$shift"),
1796 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1797 Sched<[WritePreLd]> {
1799 let Inst{31-26} = 0b111101;
1800 let Inst{25} = 1; // 1 for register form
1801 let Inst{24} = data;
1802 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1803 let Inst{22} = read;
1804 let Inst{21-20} = 0b01;
1805 let Inst{19-16} = shift{16-13}; // Rn
1806 let Inst{15-12} = 0b1111;
1807 let Inst{11-0} = shift{11-0};
1812 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1813 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1814 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1816 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1817 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1819 let Inst{31-10} = 0b1111000100000001000000;
1824 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1825 []>, Requires<[IsARM, HasV7]> {
1827 let Inst{27-4} = 0b001100100000111100001111;
1828 let Inst{3-0} = opt;
1832 * A5.4 Permanently UNDEFINED instructions.
1834 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1835 * Other UDF encodings generate SIGILL.
1837 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1839 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1841 * 1101 1110 iiii iiii
1842 * It uses the following encoding:
1843 * 1110 0111 1111 1110 1101 1110 1111 0000
1844 * - In ARM: UDF #60896;
1845 * - In Thumb: UDF #254 followed by a branch-to-self.
1847 let isBarrier = 1, isTerminator = 1 in
1848 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1850 Requires<[IsARM,UseNaClTrap]> {
1851 let Inst = 0xe7fedef0;
1853 let isBarrier = 1, isTerminator = 1 in
1854 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1856 Requires<[IsARM,DontUseNaClTrap]> {
1857 let Inst = 0xe7ffdefe;
1860 // Address computation and loads and stores in PIC mode.
1861 let isNotDuplicable = 1 in {
1862 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1864 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1865 Sched<[WriteALU, ReadALU]>;
1867 let AddedComplexity = 10 in {
1868 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1870 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1872 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1874 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1876 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1878 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1880 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1882 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1884 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1886 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1888 let AddedComplexity = 10 in {
1889 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1890 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1892 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1893 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1894 addrmodepc:$addr)]>;
1896 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1897 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1899 } // isNotDuplicable = 1
1902 // LEApcrel - Load a pc-relative address into a register without offending the
1904 let neverHasSideEffects = 1, isReMaterializable = 1 in
1905 // The 'adr' mnemonic encodes differently if the label is before or after
1906 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1907 // know until then which form of the instruction will be used.
1908 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1909 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1910 Sched<[WriteALU, ReadALU]> {
1913 let Inst{27-25} = 0b001;
1915 let Inst{23-22} = label{13-12};
1918 let Inst{19-16} = 0b1111;
1919 let Inst{15-12} = Rd;
1920 let Inst{11-0} = label{11-0};
1923 let hasSideEffects = 1 in {
1924 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1925 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1927 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1928 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1929 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1932 //===----------------------------------------------------------------------===//
1933 // Control Flow Instructions.
1936 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1938 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1939 "bx", "\tlr", [(ARMretflag)]>,
1940 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1941 let Inst{27-0} = 0b0001001011111111111100011110;
1945 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1946 "mov", "\tpc, lr", [(ARMretflag)]>,
1947 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1948 let Inst{27-0} = 0b0001101000001111000000001110;
1951 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
1952 // the user-space one).
1953 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
1955 [(ARMintretflag imm:$offset)]>;
1958 // Indirect branches
1959 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1961 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1962 [(brind GPR:$dst)]>,
1963 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1965 let Inst{31-4} = 0b1110000100101111111111110001;
1966 let Inst{3-0} = dst;
1969 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1970 "bx", "\t$dst", [/* pattern left blank */]>,
1971 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1973 let Inst{27-4} = 0b000100101111111111110001;
1974 let Inst{3-0} = dst;
1978 // SP is marked as a use to prevent stack-pointer assignments that appear
1979 // immediately before calls from potentially appearing dead.
1981 // FIXME: Do we really need a non-predicated version? If so, it should
1982 // at least be a pseudo instruction expanding to the predicated version
1983 // at MC lowering time.
1984 Defs = [LR], Uses = [SP] in {
1985 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1986 IIC_Br, "bl\t$func",
1987 [(ARMcall tglobaladdr:$func)]>,
1988 Requires<[IsARM]>, Sched<[WriteBrL]> {
1989 let Inst{31-28} = 0b1110;
1991 let Inst{23-0} = func;
1992 let DecoderMethod = "DecodeBranchImmInstruction";
1995 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1996 IIC_Br, "bl", "\t$func",
1997 [(ARMcall_pred tglobaladdr:$func)]>,
1998 Requires<[IsARM]>, Sched<[WriteBrL]> {
2000 let Inst{23-0} = func;
2001 let DecoderMethod = "DecodeBranchImmInstruction";
2005 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2006 IIC_Br, "blx\t$func",
2007 [(ARMcall GPR:$func)]>,
2008 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2010 let Inst{31-4} = 0b1110000100101111111111110011;
2011 let Inst{3-0} = func;
2014 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2015 IIC_Br, "blx", "\t$func",
2016 [(ARMcall_pred GPR:$func)]>,
2017 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2019 let Inst{27-4} = 0b000100101111111111110011;
2020 let Inst{3-0} = func;
2024 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2025 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2026 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2027 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2030 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2031 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2032 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2034 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2035 // return stack predictor.
2036 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2037 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2038 Requires<[IsARM]>, Sched<[WriteBr]>;
2041 let isBranch = 1, isTerminator = 1 in {
2042 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2043 // a two-value operand where a dag node expects two operands. :(
2044 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2045 IIC_Br, "b", "\t$target",
2046 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2049 let Inst{23-0} = target;
2050 let DecoderMethod = "DecodeBranchImmInstruction";
2053 let isBarrier = 1 in {
2054 // B is "predicable" since it's just a Bcc with an 'always' condition.
2055 let isPredicable = 1 in
2056 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2057 // should be sufficient.
2058 // FIXME: Is B really a Barrier? That doesn't seem right.
2059 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2060 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2063 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2064 def BR_JTr : ARMPseudoInst<(outs),
2065 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2067 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2069 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2070 // into i12 and rs suffixed versions.
2071 def BR_JTm : ARMPseudoInst<(outs),
2072 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2074 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2075 imm:$id)]>, Sched<[WriteBrTbl]>;
2076 def BR_JTadd : ARMPseudoInst<(outs),
2077 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2079 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2080 imm:$id)]>, Sched<[WriteBrTbl]>;
2081 } // isNotDuplicable = 1, isIndirectBranch = 1
2087 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2088 "blx\t$target", []>,
2089 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2090 let Inst{31-25} = 0b1111101;
2092 let Inst{23-0} = target{24-1};
2093 let Inst{24} = target{0};
2096 // Branch and Exchange Jazelle
2097 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2098 [/* pattern left blank */]>, Sched<[WriteBr]> {
2100 let Inst{23-20} = 0b0010;
2101 let Inst{19-8} = 0xfff;
2102 let Inst{7-4} = 0b0010;
2103 let Inst{3-0} = func;
2108 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2109 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2112 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2115 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2117 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2118 Requires<[IsARM]>, Sched<[WriteBr]>;
2120 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2122 (BX GPR:$dst)>, Sched<[WriteBr]>,
2126 // Secure Monitor Call is a system instruction.
2127 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2128 []>, Requires<[IsARM, HasTrustZone]> {
2130 let Inst{23-4} = 0b01100000000000000111;
2131 let Inst{3-0} = opt;
2134 // Supervisor Call (Software Interrupt)
2135 let isCall = 1, Uses = [SP] in {
2136 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2139 let Inst{23-0} = svc;
2143 // Store Return State
2144 class SRSI<bit wb, string asm>
2145 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2146 NoItinerary, asm, "", []> {
2148 let Inst{31-28} = 0b1111;
2149 let Inst{27-25} = 0b100;
2153 let Inst{19-16} = 0b1101; // SP
2154 let Inst{15-5} = 0b00000101000;
2155 let Inst{4-0} = mode;
2158 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2159 let Inst{24-23} = 0;
2161 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2162 let Inst{24-23} = 0;
2164 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2165 let Inst{24-23} = 0b10;
2167 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2168 let Inst{24-23} = 0b10;
2170 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2171 let Inst{24-23} = 0b01;
2173 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2174 let Inst{24-23} = 0b01;
2176 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2177 let Inst{24-23} = 0b11;
2179 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2180 let Inst{24-23} = 0b11;
2183 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2184 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2186 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2187 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2189 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2190 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2192 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2193 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2195 // Return From Exception
2196 class RFEI<bit wb, string asm>
2197 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2198 NoItinerary, asm, "", []> {
2200 let Inst{31-28} = 0b1111;
2201 let Inst{27-25} = 0b100;
2205 let Inst{19-16} = Rn;
2206 let Inst{15-0} = 0xa00;
2209 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2210 let Inst{24-23} = 0;
2212 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2213 let Inst{24-23} = 0;
2215 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2216 let Inst{24-23} = 0b10;
2218 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2219 let Inst{24-23} = 0b10;
2221 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2222 let Inst{24-23} = 0b01;
2224 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2225 let Inst{24-23} = 0b01;
2227 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2228 let Inst{24-23} = 0b11;
2230 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2231 let Inst{24-23} = 0b11;
2234 //===----------------------------------------------------------------------===//
2235 // Load / Store Instructions.
2241 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2242 UnOpFrag<(load node:$Src)>>;
2243 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2244 UnOpFrag<(zextloadi8 node:$Src)>>;
2245 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2246 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2247 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2248 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2250 // Special LDR for loads from non-pc-relative constpools.
2251 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2252 isReMaterializable = 1, isCodeGenOnly = 1 in
2253 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2254 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2258 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2259 let Inst{19-16} = 0b1111;
2260 let Inst{15-12} = Rt;
2261 let Inst{11-0} = addr{11-0}; // imm12
2264 // Loads with zero extension
2265 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2266 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2267 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2269 // Loads with sign extension
2270 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2271 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2272 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2274 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2275 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2276 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2278 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2280 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2281 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2282 Requires<[IsARM, HasV5TE]>;
2284 // GNU Assembler extension (compatibility)
2285 let isAsmParserOnly = 1 in
2286 def LDRD_PAIR : AI3ld<0b1101, 0, (outs GPRPairOp:$Rt), (ins addrmode3:$addr),
2287 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $addr", []>,
2288 Requires<[IsARM, HasV5TE]>;
2291 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2292 NoItinerary, "lda", "\t$Rt, $addr", []>;
2293 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2294 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2295 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2296 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2299 multiclass AI2_ldridx<bit isByte, string opc,
2300 InstrItinClass iii, InstrItinClass iir> {
2301 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2302 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2303 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2306 let Inst{23} = addr{12};
2307 let Inst{19-16} = addr{16-13};
2308 let Inst{11-0} = addr{11-0};
2309 let DecoderMethod = "DecodeLDRPreImm";
2312 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2313 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2314 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2317 let Inst{23} = addr{12};
2318 let Inst{19-16} = addr{16-13};
2319 let Inst{11-0} = addr{11-0};
2321 let DecoderMethod = "DecodeLDRPreReg";
2324 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2325 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2326 IndexModePost, LdFrm, iir,
2327 opc, "\t$Rt, $addr, $offset",
2328 "$addr.base = $Rn_wb", []> {
2334 let Inst{23} = offset{12};
2335 let Inst{19-16} = addr;
2336 let Inst{11-0} = offset{11-0};
2339 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2342 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2343 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2344 IndexModePost, LdFrm, iii,
2345 opc, "\t$Rt, $addr, $offset",
2346 "$addr.base = $Rn_wb", []> {
2352 let Inst{23} = offset{12};
2353 let Inst{19-16} = addr;
2354 let Inst{11-0} = offset{11-0};
2356 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2361 let mayLoad = 1, neverHasSideEffects = 1 in {
2362 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2363 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2364 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2365 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2368 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2369 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2370 (ins addrmode3_pre:$addr), IndexModePre,
2372 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2374 let Inst{23} = addr{8}; // U bit
2375 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2376 let Inst{19-16} = addr{12-9}; // Rn
2377 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2378 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2379 let DecoderMethod = "DecodeAddrMode3Instruction";
2381 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2382 (ins addr_offset_none:$addr, am3offset:$offset),
2383 IndexModePost, LdMiscFrm, itin,
2384 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2388 let Inst{23} = offset{8}; // U bit
2389 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2390 let Inst{19-16} = addr;
2391 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2392 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2393 let DecoderMethod = "DecodeAddrMode3Instruction";
2397 let mayLoad = 1, neverHasSideEffects = 1 in {
2398 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2399 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2400 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2401 let hasExtraDefRegAllocReq = 1 in {
2402 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2403 (ins addrmode3_pre:$addr), IndexModePre,
2404 LdMiscFrm, IIC_iLoad_d_ru,
2405 "ldrd", "\t$Rt, $Rt2, $addr!",
2406 "$addr.base = $Rn_wb", []> {
2408 let Inst{23} = addr{8}; // U bit
2409 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2410 let Inst{19-16} = addr{12-9}; // Rn
2411 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2412 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2413 let DecoderMethod = "DecodeAddrMode3Instruction";
2415 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2416 (ins addr_offset_none:$addr, am3offset:$offset),
2417 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2418 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2419 "$addr.base = $Rn_wb", []> {
2422 let Inst{23} = offset{8}; // U bit
2423 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2424 let Inst{19-16} = addr;
2425 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2426 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2427 let DecoderMethod = "DecodeAddrMode3Instruction";
2429 } // hasExtraDefRegAllocReq = 1
2430 } // mayLoad = 1, neverHasSideEffects = 1
2432 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2433 let mayLoad = 1, neverHasSideEffects = 1 in {
2434 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2435 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2436 IndexModePost, LdFrm, IIC_iLoad_ru,
2437 "ldrt", "\t$Rt, $addr, $offset",
2438 "$addr.base = $Rn_wb", []> {
2444 let Inst{23} = offset{12};
2445 let Inst{21} = 1; // overwrite
2446 let Inst{19-16} = addr;
2447 let Inst{11-5} = offset{11-5};
2449 let Inst{3-0} = offset{3-0};
2450 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2454 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2455 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2456 IndexModePost, LdFrm, IIC_iLoad_ru,
2457 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2463 let Inst{23} = offset{12};
2464 let Inst{21} = 1; // overwrite
2465 let Inst{19-16} = addr;
2466 let Inst{11-0} = offset{11-0};
2467 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2470 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2471 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2472 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2473 "ldrbt", "\t$Rt, $addr, $offset",
2474 "$addr.base = $Rn_wb", []> {
2480 let Inst{23} = offset{12};
2481 let Inst{21} = 1; // overwrite
2482 let Inst{19-16} = addr;
2483 let Inst{11-5} = offset{11-5};
2485 let Inst{3-0} = offset{3-0};
2486 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2490 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2491 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2492 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2493 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2499 let Inst{23} = offset{12};
2500 let Inst{21} = 1; // overwrite
2501 let Inst{19-16} = addr;
2502 let Inst{11-0} = offset{11-0};
2503 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2506 multiclass AI3ldrT<bits<4> op, string opc> {
2507 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2508 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2509 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2510 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2512 let Inst{23} = offset{8};
2514 let Inst{11-8} = offset{7-4};
2515 let Inst{3-0} = offset{3-0};
2517 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2518 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2519 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2520 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2522 let Inst{23} = Rm{4};
2525 let Unpredictable{11-8} = 0b1111;
2526 let Inst{3-0} = Rm{3-0};
2527 let DecoderMethod = "DecodeLDR";
2531 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2532 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2533 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2537 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2541 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2546 // Stores with truncate
2547 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2548 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2549 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2552 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2553 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2554 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2555 Requires<[IsARM, HasV5TE]> {
2559 // GNU Assembler extension (compatibility)
2560 let isAsmParserOnly = 1 in
2561 def STRD_PAIR : AI3str<0b1111, (outs), (ins GPRPairOp:$Rt, addrmode3:$addr),
2562 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $addr", []>,
2563 Requires<[IsARM, HasV5TE]> {
2569 multiclass AI2_stridx<bit isByte, string opc,
2570 InstrItinClass iii, InstrItinClass iir> {
2571 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2572 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2574 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2577 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2578 let Inst{19-16} = addr{16-13}; // Rn
2579 let Inst{11-0} = addr{11-0}; // imm12
2580 let DecoderMethod = "DecodeSTRPreImm";
2583 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2584 (ins GPR:$Rt, ldst_so_reg:$addr),
2585 IndexModePre, StFrm, iir,
2586 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2589 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2590 let Inst{19-16} = addr{16-13}; // Rn
2591 let Inst{11-0} = addr{11-0};
2592 let Inst{4} = 0; // Inst{4} = 0
2593 let DecoderMethod = "DecodeSTRPreReg";
2595 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2596 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2597 IndexModePost, StFrm, iir,
2598 opc, "\t$Rt, $addr, $offset",
2599 "$addr.base = $Rn_wb", []> {
2605 let Inst{23} = offset{12};
2606 let Inst{19-16} = addr;
2607 let Inst{11-0} = offset{11-0};
2610 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2613 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2614 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2615 IndexModePost, StFrm, iii,
2616 opc, "\t$Rt, $addr, $offset",
2617 "$addr.base = $Rn_wb", []> {
2623 let Inst{23} = offset{12};
2624 let Inst{19-16} = addr;
2625 let Inst{11-0} = offset{11-0};
2627 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2631 let mayStore = 1, neverHasSideEffects = 1 in {
2632 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2633 // IIC_iStore_siu depending on whether it the offset register is shifted.
2634 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2635 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2638 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2639 am2offset_reg:$offset),
2640 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2641 am2offset_reg:$offset)>;
2642 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2643 am2offset_imm:$offset),
2644 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2645 am2offset_imm:$offset)>;
2646 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2647 am2offset_reg:$offset),
2648 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2649 am2offset_reg:$offset)>;
2650 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2651 am2offset_imm:$offset),
2652 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2653 am2offset_imm:$offset)>;
2655 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2656 // put the patterns on the instruction definitions directly as ISel wants
2657 // the address base and offset to be separate operands, not a single
2658 // complex operand like we represent the instructions themselves. The
2659 // pseudos map between the two.
2660 let usesCustomInserter = 1,
2661 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2662 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2663 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2666 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2667 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2668 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2671 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2672 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2673 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2676 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2677 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2678 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2681 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2682 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2683 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2686 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2691 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2692 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2693 StMiscFrm, IIC_iStore_bh_ru,
2694 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2696 let Inst{23} = addr{8}; // U bit
2697 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2698 let Inst{19-16} = addr{12-9}; // Rn
2699 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2700 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2701 let DecoderMethod = "DecodeAddrMode3Instruction";
2704 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2705 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2706 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2707 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2708 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2709 addr_offset_none:$addr,
2710 am3offset:$offset))]> {
2713 let Inst{23} = offset{8}; // U bit
2714 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2715 let Inst{19-16} = addr;
2716 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2717 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2718 let DecoderMethod = "DecodeAddrMode3Instruction";
2721 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2722 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2723 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2724 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2725 "strd", "\t$Rt, $Rt2, $addr!",
2726 "$addr.base = $Rn_wb", []> {
2728 let Inst{23} = addr{8}; // U bit
2729 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2730 let Inst{19-16} = addr{12-9}; // Rn
2731 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2732 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2733 let DecoderMethod = "DecodeAddrMode3Instruction";
2736 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2737 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2739 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2740 "strd", "\t$Rt, $Rt2, $addr, $offset",
2741 "$addr.base = $Rn_wb", []> {
2744 let Inst{23} = offset{8}; // U bit
2745 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2746 let Inst{19-16} = addr;
2747 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2748 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2749 let DecoderMethod = "DecodeAddrMode3Instruction";
2751 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2753 // STRT, STRBT, and STRHT
2755 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2756 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2757 IndexModePost, StFrm, IIC_iStore_bh_ru,
2758 "strbt", "\t$Rt, $addr, $offset",
2759 "$addr.base = $Rn_wb", []> {
2765 let Inst{23} = offset{12};
2766 let Inst{21} = 1; // overwrite
2767 let Inst{19-16} = addr;
2768 let Inst{11-5} = offset{11-5};
2770 let Inst{3-0} = offset{3-0};
2771 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2775 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2776 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2777 IndexModePost, StFrm, IIC_iStore_bh_ru,
2778 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2784 let Inst{23} = offset{12};
2785 let Inst{21} = 1; // overwrite
2786 let Inst{19-16} = addr;
2787 let Inst{11-0} = offset{11-0};
2788 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2792 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
2793 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2795 let mayStore = 1, neverHasSideEffects = 1 in {
2796 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2797 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2798 IndexModePost, StFrm, IIC_iStore_ru,
2799 "strt", "\t$Rt, $addr, $offset",
2800 "$addr.base = $Rn_wb", []> {
2806 let Inst{23} = offset{12};
2807 let Inst{21} = 1; // overwrite
2808 let Inst{19-16} = addr;
2809 let Inst{11-5} = offset{11-5};
2811 let Inst{3-0} = offset{3-0};
2812 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2816 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2817 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2818 IndexModePost, StFrm, IIC_iStore_ru,
2819 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2825 let Inst{23} = offset{12};
2826 let Inst{21} = 1; // overwrite
2827 let Inst{19-16} = addr;
2828 let Inst{11-0} = offset{11-0};
2829 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2834 : ARMAsmPseudo<"strt${q} $Rt, $addr",
2835 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
2837 multiclass AI3strT<bits<4> op, string opc> {
2838 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2839 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2840 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2841 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2843 let Inst{23} = offset{8};
2845 let Inst{11-8} = offset{7-4};
2846 let Inst{3-0} = offset{3-0};
2848 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2849 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2850 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2851 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2853 let Inst{23} = Rm{4};
2856 let Inst{3-0} = Rm{3-0};
2861 defm STRHT : AI3strT<0b1011, "strht">;
2863 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2864 NoItinerary, "stl", "\t$Rt, $addr", []>;
2865 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2866 NoItinerary, "stlb", "\t$Rt, $addr", []>;
2867 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2868 NoItinerary, "stlh", "\t$Rt, $addr", []>;
2870 //===----------------------------------------------------------------------===//
2871 // Load / store multiple Instructions.
2874 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2875 InstrItinClass itin, InstrItinClass itin_upd> {
2876 // IA is the default, so no need for an explicit suffix on the
2877 // mnemonic here. Without it is the canonical spelling.
2879 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2880 IndexModeNone, f, itin,
2881 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2882 let Inst{24-23} = 0b01; // Increment After
2883 let Inst{22} = P_bit;
2884 let Inst{21} = 0; // No writeback
2885 let Inst{20} = L_bit;
2888 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2889 IndexModeUpd, f, itin_upd,
2890 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2891 let Inst{24-23} = 0b01; // Increment After
2892 let Inst{22} = P_bit;
2893 let Inst{21} = 1; // Writeback
2894 let Inst{20} = L_bit;
2896 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2899 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2900 IndexModeNone, f, itin,
2901 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2902 let Inst{24-23} = 0b00; // Decrement After
2903 let Inst{22} = P_bit;
2904 let Inst{21} = 0; // No writeback
2905 let Inst{20} = L_bit;
2908 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2909 IndexModeUpd, f, itin_upd,
2910 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2911 let Inst{24-23} = 0b00; // Decrement After
2912 let Inst{22} = P_bit;
2913 let Inst{21} = 1; // Writeback
2914 let Inst{20} = L_bit;
2916 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2919 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2920 IndexModeNone, f, itin,
2921 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2922 let Inst{24-23} = 0b10; // Decrement Before
2923 let Inst{22} = P_bit;
2924 let Inst{21} = 0; // No writeback
2925 let Inst{20} = L_bit;
2928 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2929 IndexModeUpd, f, itin_upd,
2930 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2931 let Inst{24-23} = 0b10; // Decrement Before
2932 let Inst{22} = P_bit;
2933 let Inst{21} = 1; // Writeback
2934 let Inst{20} = L_bit;
2936 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2939 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2940 IndexModeNone, f, itin,
2941 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2942 let Inst{24-23} = 0b11; // Increment Before
2943 let Inst{22} = P_bit;
2944 let Inst{21} = 0; // No writeback
2945 let Inst{20} = L_bit;
2948 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2949 IndexModeUpd, f, itin_upd,
2950 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2951 let Inst{24-23} = 0b11; // Increment Before
2952 let Inst{22} = P_bit;
2953 let Inst{21} = 1; // Writeback
2954 let Inst{20} = L_bit;
2956 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2960 let neverHasSideEffects = 1 in {
2962 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2963 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2966 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2967 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2970 } // neverHasSideEffects
2972 // FIXME: remove when we have a way to marking a MI with these properties.
2973 // FIXME: Should pc be an implicit operand like PICADD, etc?
2974 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2975 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2976 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2977 reglist:$regs, variable_ops),
2978 4, IIC_iLoad_mBr, [],
2979 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2980 RegConstraint<"$Rn = $wb">;
2982 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2983 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2986 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2987 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2992 //===----------------------------------------------------------------------===//
2993 // Move Instructions.
2996 let neverHasSideEffects = 1 in
2997 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2998 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3002 let Inst{19-16} = 0b0000;
3003 let Inst{11-4} = 0b00000000;
3006 let Inst{15-12} = Rd;
3009 // A version for the smaller set of tail call registers.
3010 let neverHasSideEffects = 1 in
3011 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3012 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3016 let Inst{11-4} = 0b00000000;
3019 let Inst{15-12} = Rd;
3022 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3023 DPSoRegRegFrm, IIC_iMOVsr,
3024 "mov", "\t$Rd, $src",
3025 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3029 let Inst{15-12} = Rd;
3030 let Inst{19-16} = 0b0000;
3031 let Inst{11-8} = src{11-8};
3033 let Inst{6-5} = src{6-5};
3035 let Inst{3-0} = src{3-0};
3039 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3040 DPSoRegImmFrm, IIC_iMOVsr,
3041 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3042 UnaryDP, Sched<[WriteALU]> {
3045 let Inst{15-12} = Rd;
3046 let Inst{19-16} = 0b0000;
3047 let Inst{11-5} = src{11-5};
3049 let Inst{3-0} = src{3-0};
3053 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3054 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3055 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3060 let Inst{15-12} = Rd;
3061 let Inst{19-16} = 0b0000;
3062 let Inst{11-0} = imm;
3065 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3066 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3068 "movw", "\t$Rd, $imm",
3069 [(set GPR:$Rd, imm0_65535:$imm)]>,
3070 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3073 let Inst{15-12} = Rd;
3074 let Inst{11-0} = imm{11-0};
3075 let Inst{19-16} = imm{15-12};
3078 let DecoderMethod = "DecodeArmMOVTWInstruction";
3081 def : InstAlias<"mov${p} $Rd, $imm",
3082 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3085 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3086 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3089 let Constraints = "$src = $Rd" in {
3090 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3091 (ins GPR:$src, imm0_65535_expr:$imm),
3093 "movt", "\t$Rd, $imm",
3095 (or (and GPR:$src, 0xffff),
3096 lo16AllZero:$imm))]>, UnaryDP,
3097 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3100 let Inst{15-12} = Rd;
3101 let Inst{11-0} = imm{11-0};
3102 let Inst{19-16} = imm{15-12};
3105 let DecoderMethod = "DecodeArmMOVTWInstruction";
3108 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3109 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3114 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3115 Requires<[IsARM, HasV6T2]>;
3117 let Uses = [CPSR] in
3118 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3119 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3120 Requires<[IsARM]>, Sched<[WriteALU]>;
3122 // These aren't really mov instructions, but we have to define them this way
3123 // due to flag operands.
3125 let Defs = [CPSR] in {
3126 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3127 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3128 Sched<[WriteALU]>, Requires<[IsARM]>;
3129 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3130 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3131 Sched<[WriteALU]>, Requires<[IsARM]>;
3134 //===----------------------------------------------------------------------===//
3135 // Extend Instructions.
3140 def SXTB : AI_ext_rrot<0b01101010,
3141 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3142 def SXTH : AI_ext_rrot<0b01101011,
3143 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3145 def SXTAB : AI_exta_rrot<0b01101010,
3146 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3147 def SXTAH : AI_exta_rrot<0b01101011,
3148 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3150 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3152 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3156 let AddedComplexity = 16 in {
3157 def UXTB : AI_ext_rrot<0b01101110,
3158 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3159 def UXTH : AI_ext_rrot<0b01101111,
3160 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3161 def UXTB16 : AI_ext_rrot<0b01101100,
3162 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3164 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3165 // The transformation should probably be done as a combiner action
3166 // instead so we can include a check for masking back in the upper
3167 // eight bits of the source into the lower eight bits of the result.
3168 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3169 // (UXTB16r_rot GPR:$Src, 3)>;
3170 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3171 (UXTB16 GPR:$Src, 1)>;
3173 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3174 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3175 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3176 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3179 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3180 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3183 def SBFX : I<(outs GPRnopc:$Rd),
3184 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3185 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3186 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3187 Requires<[IsARM, HasV6T2]> {
3192 let Inst{27-21} = 0b0111101;
3193 let Inst{6-4} = 0b101;
3194 let Inst{20-16} = width;
3195 let Inst{15-12} = Rd;
3196 let Inst{11-7} = lsb;
3200 def UBFX : I<(outs GPR:$Rd),
3201 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3202 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3203 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3204 Requires<[IsARM, HasV6T2]> {
3209 let Inst{27-21} = 0b0111111;
3210 let Inst{6-4} = 0b101;
3211 let Inst{20-16} = width;
3212 let Inst{15-12} = Rd;
3213 let Inst{11-7} = lsb;
3217 //===----------------------------------------------------------------------===//
3218 // Arithmetic Instructions.
3221 defm ADD : AsI1_bin_irs<0b0100, "add",
3222 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3223 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3224 defm SUB : AsI1_bin_irs<0b0010, "sub",
3225 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3226 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3228 // ADD and SUB with 's' bit set.
3230 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3231 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3232 // AdjustInstrPostInstrSelection where we determine whether or not to
3233 // set the "s" bit based on CPSR liveness.
3235 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3236 // support for an optional CPSR definition that corresponds to the DAG
3237 // node's second value. We can then eliminate the implicit def of CPSR.
3238 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3239 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3240 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3241 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3243 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3244 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3245 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3246 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3248 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3249 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3250 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3252 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3253 // CPSR and the implicit def of CPSR is not needed.
3254 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3255 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3257 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3258 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3260 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3261 // The assume-no-carry-in form uses the negation of the input since add/sub
3262 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3263 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3265 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3266 (SUBri GPR:$src, so_imm_neg:$imm)>;
3267 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3268 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3270 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3271 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3272 Requires<[IsARM, HasV6T2]>;
3273 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3274 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3275 Requires<[IsARM, HasV6T2]>;
3277 // The with-carry-in form matches bitwise not instead of the negation.
3278 // Effectively, the inverse interpretation of the carry flag already accounts
3279 // for part of the negation.
3280 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3281 (SBCri GPR:$src, so_imm_not:$imm)>;
3282 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3283 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3285 // Note: These are implemented in C++ code, because they have to generate
3286 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3288 // (mul X, 2^n+1) -> (add (X << n), X)
3289 // (mul X, 2^n-1) -> (rsb X, (X << n))
3291 // ARM Arithmetic Instruction
3292 // GPR:$dst = GPR:$a op GPR:$b
3293 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3294 list<dag> pattern = [],
3295 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3296 string asm = "\t$Rd, $Rn, $Rm">
3297 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3298 Sched<[WriteALU, ReadALU, ReadALU]> {
3302 let Inst{27-20} = op27_20;
3303 let Inst{11-4} = op11_4;
3304 let Inst{19-16} = Rn;
3305 let Inst{15-12} = Rd;
3308 let Unpredictable{11-8} = 0b1111;
3311 // Saturating add/subtract
3313 let DecoderMethod = "DecodeQADDInstruction" in
3314 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3315 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3316 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3318 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3319 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3320 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3321 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3322 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3324 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3325 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3328 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3329 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3330 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3331 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3332 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3333 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3334 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3335 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3336 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3337 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3338 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3339 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3341 // Signed/Unsigned add/subtract
3343 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3344 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3345 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3346 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3347 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3348 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3349 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3350 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3351 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3352 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3353 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3354 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3356 // Signed/Unsigned halving add/subtract
3358 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3359 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3360 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3361 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3362 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3363 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3364 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3365 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3366 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3367 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3368 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3369 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3371 // Unsigned Sum of Absolute Differences [and Accumulate].
3373 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3374 MulFrm /* for convenience */, NoItinerary, "usad8",
3375 "\t$Rd, $Rn, $Rm", []>,
3376 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3380 let Inst{27-20} = 0b01111000;
3381 let Inst{15-12} = 0b1111;
3382 let Inst{7-4} = 0b0001;
3383 let Inst{19-16} = Rd;
3384 let Inst{11-8} = Rm;
3387 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3388 MulFrm /* for convenience */, NoItinerary, "usada8",
3389 "\t$Rd, $Rn, $Rm, $Ra", []>,
3390 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3395 let Inst{27-20} = 0b01111000;
3396 let Inst{7-4} = 0b0001;
3397 let Inst{19-16} = Rd;
3398 let Inst{15-12} = Ra;
3399 let Inst{11-8} = Rm;
3403 // Signed/Unsigned saturate
3405 def SSAT : AI<(outs GPRnopc:$Rd),
3406 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3407 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3412 let Inst{27-21} = 0b0110101;
3413 let Inst{5-4} = 0b01;
3414 let Inst{20-16} = sat_imm;
3415 let Inst{15-12} = Rd;
3416 let Inst{11-7} = sh{4-0};
3417 let Inst{6} = sh{5};
3421 def SSAT16 : AI<(outs GPRnopc:$Rd),
3422 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3423 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3427 let Inst{27-20} = 0b01101010;
3428 let Inst{11-4} = 0b11110011;
3429 let Inst{15-12} = Rd;
3430 let Inst{19-16} = sat_imm;
3434 def USAT : AI<(outs GPRnopc:$Rd),
3435 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3436 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3441 let Inst{27-21} = 0b0110111;
3442 let Inst{5-4} = 0b01;
3443 let Inst{15-12} = Rd;
3444 let Inst{11-7} = sh{4-0};
3445 let Inst{6} = sh{5};
3446 let Inst{20-16} = sat_imm;
3450 def USAT16 : AI<(outs GPRnopc:$Rd),
3451 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3452 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3456 let Inst{27-20} = 0b01101110;
3457 let Inst{11-4} = 0b11110011;
3458 let Inst{15-12} = Rd;
3459 let Inst{19-16} = sat_imm;
3463 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3464 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3465 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3466 (USAT imm:$pos, GPRnopc:$a, 0)>;
3468 //===----------------------------------------------------------------------===//
3469 // Bitwise Instructions.
3472 defm AND : AsI1_bin_irs<0b0000, "and",
3473 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3474 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3475 defm ORR : AsI1_bin_irs<0b1100, "orr",
3476 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3477 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3478 defm EOR : AsI1_bin_irs<0b0001, "eor",
3479 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3480 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3481 defm BIC : AsI1_bin_irs<0b1110, "bic",
3482 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3483 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3485 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3486 // like in the actual instruction encoding. The complexity of mapping the mask
3487 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3488 // instruction description.
3489 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3490 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3491 "bfc", "\t$Rd, $imm", "$src = $Rd",
3492 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3493 Requires<[IsARM, HasV6T2]> {
3496 let Inst{27-21} = 0b0111110;
3497 let Inst{6-0} = 0b0011111;
3498 let Inst{15-12} = Rd;
3499 let Inst{11-7} = imm{4-0}; // lsb
3500 let Inst{20-16} = imm{9-5}; // msb
3503 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3504 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3505 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3506 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3507 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3508 bf_inv_mask_imm:$imm))]>,
3509 Requires<[IsARM, HasV6T2]> {
3513 let Inst{27-21} = 0b0111110;
3514 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3515 let Inst{15-12} = Rd;
3516 let Inst{11-7} = imm{4-0}; // lsb
3517 let Inst{20-16} = imm{9-5}; // width
3521 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3522 "mvn", "\t$Rd, $Rm",
3523 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3527 let Inst{19-16} = 0b0000;
3528 let Inst{11-4} = 0b00000000;
3529 let Inst{15-12} = Rd;
3532 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3533 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3534 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3539 let Inst{19-16} = 0b0000;
3540 let Inst{15-12} = Rd;
3541 let Inst{11-5} = shift{11-5};
3543 let Inst{3-0} = shift{3-0};
3545 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3546 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3547 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3552 let Inst{19-16} = 0b0000;
3553 let Inst{15-12} = Rd;
3554 let Inst{11-8} = shift{11-8};
3556 let Inst{6-5} = shift{6-5};
3558 let Inst{3-0} = shift{3-0};
3560 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3561 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3562 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3563 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3567 let Inst{19-16} = 0b0000;
3568 let Inst{15-12} = Rd;
3569 let Inst{11-0} = imm;
3572 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3573 (BICri GPR:$src, so_imm_not:$imm)>;
3575 //===----------------------------------------------------------------------===//
3576 // Multiply Instructions.
3578 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3579 string opc, string asm, list<dag> pattern>
3580 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3584 let Inst{19-16} = Rd;
3585 let Inst{11-8} = Rm;
3588 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3589 string opc, string asm, list<dag> pattern>
3590 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3595 let Inst{19-16} = RdHi;
3596 let Inst{15-12} = RdLo;
3597 let Inst{11-8} = Rm;
3600 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3601 string opc, string asm, list<dag> pattern>
3602 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3607 let Inst{19-16} = RdHi;
3608 let Inst{15-12} = RdLo;
3609 let Inst{11-8} = Rm;
3613 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3614 // property. Remove them when it's possible to add those properties
3615 // on an individual MachineInstr, not just an instruction description.
3616 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3617 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3618 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3619 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3620 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3621 Requires<[IsARM, HasV6]> {
3622 let Inst{15-12} = 0b0000;
3623 let Unpredictable{15-12} = 0b1111;
3626 let Constraints = "@earlyclobber $Rd" in
3627 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3628 pred:$p, cc_out:$s),
3630 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3631 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3632 Requires<[IsARM, NoV6, UseMulOps]>;
3635 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3636 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3637 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3638 Requires<[IsARM, HasV6, UseMulOps]> {
3640 let Inst{15-12} = Ra;
3643 let Constraints = "@earlyclobber $Rd" in
3644 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3645 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3647 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3648 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3649 Requires<[IsARM, NoV6]>;
3651 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3652 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3653 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3654 Requires<[IsARM, HasV6T2, UseMulOps]> {
3659 let Inst{19-16} = Rd;
3660 let Inst{15-12} = Ra;
3661 let Inst{11-8} = Rm;
3665 // Extra precision multiplies with low / high results
3666 let neverHasSideEffects = 1 in {
3667 let isCommutable = 1 in {
3668 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3669 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3670 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3671 Requires<[IsARM, HasV6]>;
3673 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3674 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3675 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3676 Requires<[IsARM, HasV6]>;
3678 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3679 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3680 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3682 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3683 Requires<[IsARM, NoV6]>;
3685 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3686 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3688 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3689 Requires<[IsARM, NoV6]>;
3693 // Multiply + accumulate
3694 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3695 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3696 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3697 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3698 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3699 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3700 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3701 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3703 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3704 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3705 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3706 Requires<[IsARM, HasV6]> {
3711 let Inst{19-16} = RdHi;
3712 let Inst{15-12} = RdLo;
3713 let Inst{11-8} = Rm;
3718 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3719 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3720 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3722 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3723 pred:$p, cc_out:$s)>,
3724 Requires<[IsARM, NoV6]>;
3725 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3726 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3728 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3729 pred:$p, cc_out:$s)>,
3730 Requires<[IsARM, NoV6]>;
3733 } // neverHasSideEffects
3735 // Most significant word multiply
3736 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3737 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3738 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3739 Requires<[IsARM, HasV6]> {
3740 let Inst{15-12} = 0b1111;
3743 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3744 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3745 Requires<[IsARM, HasV6]> {
3746 let Inst{15-12} = 0b1111;
3749 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3750 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3751 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3752 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3753 Requires<[IsARM, HasV6, UseMulOps]>;
3755 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3756 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3757 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3758 Requires<[IsARM, HasV6]>;
3760 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3761 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3762 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3763 Requires<[IsARM, HasV6, UseMulOps]>;
3765 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3766 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3767 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3768 Requires<[IsARM, HasV6]>;
3770 multiclass AI_smul<string opc, PatFrag opnode> {
3771 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3772 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3773 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3774 (sext_inreg GPR:$Rm, i16)))]>,
3775 Requires<[IsARM, HasV5TE]>;
3777 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3778 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3779 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3780 (sra GPR:$Rm, (i32 16))))]>,
3781 Requires<[IsARM, HasV5TE]>;
3783 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3784 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3785 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3786 (sext_inreg GPR:$Rm, i16)))]>,
3787 Requires<[IsARM, HasV5TE]>;
3789 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3790 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3791 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3792 (sra GPR:$Rm, (i32 16))))]>,
3793 Requires<[IsARM, HasV5TE]>;
3795 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3796 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3797 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3798 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3799 Requires<[IsARM, HasV5TE]>;
3801 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3802 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3803 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3804 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3805 Requires<[IsARM, HasV5TE]>;
3809 multiclass AI_smla<string opc, PatFrag opnode> {
3810 let DecoderMethod = "DecodeSMLAInstruction" in {
3811 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3812 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3813 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3814 [(set GPRnopc:$Rd, (add GPR:$Ra,
3815 (opnode (sext_inreg GPRnopc:$Rn, i16),
3816 (sext_inreg GPRnopc:$Rm, i16))))]>,
3817 Requires<[IsARM, HasV5TE, UseMulOps]>;
3819 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3820 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3821 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3823 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3824 (sra GPRnopc:$Rm, (i32 16)))))]>,
3825 Requires<[IsARM, HasV5TE, UseMulOps]>;
3827 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3828 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3829 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3831 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3832 (sext_inreg GPRnopc:$Rm, i16))))]>,
3833 Requires<[IsARM, HasV5TE, UseMulOps]>;
3835 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3836 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3837 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3839 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3840 (sra GPRnopc:$Rm, (i32 16)))))]>,
3841 Requires<[IsARM, HasV5TE, UseMulOps]>;
3843 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3844 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3845 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3847 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3848 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3849 Requires<[IsARM, HasV5TE, UseMulOps]>;
3851 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3852 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3853 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3855 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3856 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3857 Requires<[IsARM, HasV5TE, UseMulOps]>;
3861 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3862 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3864 // Halfword multiply accumulate long: SMLAL<x><y>.
3865 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3866 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3867 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3868 Requires<[IsARM, HasV5TE]>;
3870 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3871 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3872 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3873 Requires<[IsARM, HasV5TE]>;
3875 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3876 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3877 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3878 Requires<[IsARM, HasV5TE]>;
3880 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3881 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3882 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3883 Requires<[IsARM, HasV5TE]>;
3885 // Helper class for AI_smld.
3886 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3887 InstrItinClass itin, string opc, string asm>
3888 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3891 let Inst{27-23} = 0b01110;
3892 let Inst{22} = long;
3893 let Inst{21-20} = 0b00;
3894 let Inst{11-8} = Rm;
3901 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3902 InstrItinClass itin, string opc, string asm>
3903 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3905 let Inst{15-12} = 0b1111;
3906 let Inst{19-16} = Rd;
3908 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3909 InstrItinClass itin, string opc, string asm>
3910 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3913 let Inst{19-16} = Rd;
3914 let Inst{15-12} = Ra;
3916 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3917 InstrItinClass itin, string opc, string asm>
3918 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3921 let Inst{19-16} = RdHi;
3922 let Inst{15-12} = RdLo;
3925 multiclass AI_smld<bit sub, string opc> {
3927 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3928 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3929 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3931 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3932 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3933 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3935 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3936 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3937 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3939 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3940 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3941 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3945 defm SMLA : AI_smld<0, "smla">;
3946 defm SMLS : AI_smld<1, "smls">;
3948 multiclass AI_sdml<bit sub, string opc> {
3950 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3951 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3952 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3953 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3956 defm SMUA : AI_sdml<0, "smua">;
3957 defm SMUS : AI_sdml<1, "smus">;
3959 //===----------------------------------------------------------------------===//
3960 // Division Instructions (ARMv7-A with virtualization extension)
3962 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3963 "sdiv", "\t$Rd, $Rn, $Rm",
3964 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3965 Requires<[IsARM, HasDivideInARM]>;
3967 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3968 "udiv", "\t$Rd, $Rn, $Rm",
3969 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3970 Requires<[IsARM, HasDivideInARM]>;
3972 //===----------------------------------------------------------------------===//
3973 // Misc. Arithmetic Instructions.
3976 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3977 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3978 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3981 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3982 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3983 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3984 Requires<[IsARM, HasV6T2]>,
3987 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3988 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3989 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3992 let AddedComplexity = 5 in
3993 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3994 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3995 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3996 Requires<[IsARM, HasV6]>,
3999 let AddedComplexity = 5 in
4000 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4001 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4002 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4003 Requires<[IsARM, HasV6]>,
4006 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4007 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4010 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4011 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4012 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4013 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4014 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4016 Requires<[IsARM, HasV6]>,
4017 Sched<[WriteALUsi, ReadALU]>;
4019 // Alternate cases for PKHBT where identities eliminate some nodes.
4020 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4021 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4022 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4023 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4025 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4026 // will match the pattern below.
4027 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4028 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4029 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4030 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4031 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4033 Requires<[IsARM, HasV6]>,
4034 Sched<[WriteALUsi, ReadALU]>;
4036 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4037 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4038 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4039 // pkhtb src1, src2, asr (17..31).
4040 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4041 (srl GPRnopc:$src2, imm16:$sh)),
4042 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4043 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4044 (sra GPRnopc:$src2, imm16_31:$sh)),
4045 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4046 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4047 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4048 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4050 //===----------------------------------------------------------------------===//
4054 // + CRC32{B,H,W} 0x04C11DB7
4055 // + CRC32C{B,H,W} 0x1EDC6F41
4058 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4059 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4060 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4061 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4062 Requires<[IsARM, HasV8, HasCRC]> {
4067 let Inst{31-28} = 0b1110;
4068 let Inst{27-23} = 0b00010;
4069 let Inst{22-21} = sz;
4071 let Inst{19-16} = Rn;
4072 let Inst{15-12} = Rd;
4073 let Inst{11-10} = 0b00;
4076 let Inst{7-4} = 0b0100;
4079 let Unpredictable{11-8} = 0b1101;
4082 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4083 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4084 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4085 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4086 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4087 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4089 //===----------------------------------------------------------------------===//
4090 // Comparison Instructions...
4093 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4094 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4095 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4097 // ARMcmpZ can re-use the above instruction definitions.
4098 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4099 (CMPri GPR:$src, so_imm:$imm)>;
4100 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4101 (CMPrr GPR:$src, GPR:$rhs)>;
4102 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4103 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4104 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4105 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4107 // CMN register-integer
4108 let isCompare = 1, Defs = [CPSR] in {
4109 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4110 "cmn", "\t$Rn, $imm",
4111 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4112 Sched<[WriteCMP, ReadALU]> {
4117 let Inst{19-16} = Rn;
4118 let Inst{15-12} = 0b0000;
4119 let Inst{11-0} = imm;
4121 let Unpredictable{15-12} = 0b1111;
4124 // CMN register-register/shift
4125 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4126 "cmn", "\t$Rn, $Rm",
4127 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4128 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4131 let isCommutable = 1;
4134 let Inst{19-16} = Rn;
4135 let Inst{15-12} = 0b0000;
4136 let Inst{11-4} = 0b00000000;
4139 let Unpredictable{15-12} = 0b1111;
4142 def CMNzrsi : AI1<0b1011, (outs),
4143 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4144 "cmn", "\t$Rn, $shift",
4145 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4146 GPR:$Rn, so_reg_imm:$shift)]>,
4147 Sched<[WriteCMPsi, ReadALU]> {
4152 let Inst{19-16} = Rn;
4153 let Inst{15-12} = 0b0000;
4154 let Inst{11-5} = shift{11-5};
4156 let Inst{3-0} = shift{3-0};
4158 let Unpredictable{15-12} = 0b1111;
4161 def CMNzrsr : AI1<0b1011, (outs),
4162 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4163 "cmn", "\t$Rn, $shift",
4164 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4165 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4166 Sched<[WriteCMPsr, ReadALU]> {
4171 let Inst{19-16} = Rn;
4172 let Inst{15-12} = 0b0000;
4173 let Inst{11-8} = shift{11-8};
4175 let Inst{6-5} = shift{6-5};
4177 let Inst{3-0} = shift{3-0};
4179 let Unpredictable{15-12} = 0b1111;
4184 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4185 (CMNri GPR:$src, so_imm_neg:$imm)>;
4187 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4188 (CMNri GPR:$src, so_imm_neg:$imm)>;
4190 // Note that TST/TEQ don't set all the same flags that CMP does!
4191 defm TST : AI1_cmp_irs<0b1000, "tst",
4192 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4193 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4194 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4195 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4196 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4198 // Pseudo i64 compares for some floating point compares.
4199 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4201 def BCCi64 : PseudoInst<(outs),
4202 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4204 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4207 def BCCZi64 : PseudoInst<(outs),
4208 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4209 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4211 } // usesCustomInserter
4214 // Conditional moves
4215 let neverHasSideEffects = 1 in {
4217 let isCommutable = 1, isSelect = 1 in
4218 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4219 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4221 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4223 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4225 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4226 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4229 (ARMcmov GPR:$false, so_reg_imm:$shift,
4231 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4232 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4233 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4235 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4237 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4240 let isMoveImm = 1 in
4242 : ARMPseudoInst<(outs GPR:$Rd),
4243 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4245 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4247 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4250 let isMoveImm = 1 in
4251 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4252 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4254 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4256 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4258 // Two instruction predicate mov immediate.
4259 let isMoveImm = 1 in
4261 : ARMPseudoInst<(outs GPR:$Rd),
4262 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4264 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4266 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4268 let isMoveImm = 1 in
4269 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4270 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4272 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4274 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4276 } // neverHasSideEffects
4279 //===----------------------------------------------------------------------===//
4280 // Atomic operations intrinsics
4283 def MemBarrierOptOperand : AsmOperandClass {
4284 let Name = "MemBarrierOpt";
4285 let ParserMethod = "parseMemBarrierOptOperand";
4287 def memb_opt : Operand<i32> {
4288 let PrintMethod = "printMemBOption";
4289 let ParserMatchClass = MemBarrierOptOperand;
4290 let DecoderMethod = "DecodeMemBarrierOption";
4293 def InstSyncBarrierOptOperand : AsmOperandClass {
4294 let Name = "InstSyncBarrierOpt";
4295 let ParserMethod = "parseInstSyncBarrierOptOperand";
4297 def instsyncb_opt : Operand<i32> {
4298 let PrintMethod = "printInstSyncBOption";
4299 let ParserMatchClass = InstSyncBarrierOptOperand;
4300 let DecoderMethod = "DecodeInstSyncBarrierOption";
4303 // memory barriers protect the atomic sequences
4304 let hasSideEffects = 1 in {
4305 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4306 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4307 Requires<[IsARM, HasDB]> {
4309 let Inst{31-4} = 0xf57ff05;
4310 let Inst{3-0} = opt;
4314 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4315 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4316 Requires<[IsARM, HasDB]> {
4318 let Inst{31-4} = 0xf57ff04;
4319 let Inst{3-0} = opt;
4322 // ISB has only full system option
4323 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4324 "isb", "\t$opt", []>,
4325 Requires<[IsARM, HasDB]> {
4327 let Inst{31-4} = 0xf57ff06;
4328 let Inst{3-0} = opt;
4331 let usesCustomInserter = 1, Defs = [CPSR] in {
4333 // Pseudo instruction that combines movs + predicated rsbmi
4334 // to implement integer ABS
4335 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4337 // Atomic pseudo-insts which will be lowered to ldrex/strex loops.
4338 // (64-bit pseudos use a hand-written selection code).
4339 let mayLoad = 1, mayStore = 1 in {
4340 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4342 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4344 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4346 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4348 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4350 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4352 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4354 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4356 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4358 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4360 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4362 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4364 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4366 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4368 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4370 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4372 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4374 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4376 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4378 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4380 def ATOMIC_SWAP_I8 : PseudoInst<
4382 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4384 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4386 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4388 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4390 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4392 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4394 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4396 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4398 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4400 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4402 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4404 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4406 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4408 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4410 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4412 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4414 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4416 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4418 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4420 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4422 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4424 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4426 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4428 def ATOMIC_SWAP_I16 : PseudoInst<
4430 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4432 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4434 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4436 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4438 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4440 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4442 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4444 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4446 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4448 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4450 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4452 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4454 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4456 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4458 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4460 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4462 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4464 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4466 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4468 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4470 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4472 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4474 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4476 def ATOMIC_SWAP_I32 : PseudoInst<
4478 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4480 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4482 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4484 def ATOMIC_LOAD_ADD_I64 : PseudoInst<
4485 (outs GPR:$dst1, GPR:$dst2),
4486 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4488 def ATOMIC_LOAD_SUB_I64 : PseudoInst<
4489 (outs GPR:$dst1, GPR:$dst2),
4490 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4492 def ATOMIC_LOAD_AND_I64 : PseudoInst<
4493 (outs GPR:$dst1, GPR:$dst2),
4494 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4496 def ATOMIC_LOAD_OR_I64 : PseudoInst<
4497 (outs GPR:$dst1, GPR:$dst2),
4498 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4500 def ATOMIC_LOAD_XOR_I64 : PseudoInst<
4501 (outs GPR:$dst1, GPR:$dst2),
4502 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4504 def ATOMIC_LOAD_NAND_I64 : PseudoInst<
4505 (outs GPR:$dst1, GPR:$dst2),
4506 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4508 def ATOMIC_LOAD_MIN_I64 : PseudoInst<
4509 (outs GPR:$dst1, GPR:$dst2),
4510 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4512 def ATOMIC_LOAD_MAX_I64 : PseudoInst<
4513 (outs GPR:$dst1, GPR:$dst2),
4514 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4516 def ATOMIC_LOAD_UMIN_I64 : PseudoInst<
4517 (outs GPR:$dst1, GPR:$dst2),
4518 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4520 def ATOMIC_LOAD_UMAX_I64 : PseudoInst<
4521 (outs GPR:$dst1, GPR:$dst2),
4522 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4524 def ATOMIC_SWAP_I64 : PseudoInst<
4525 (outs GPR:$dst1, GPR:$dst2),
4526 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4528 def ATOMIC_CMP_SWAP_I64 : PseudoInst<
4529 (outs GPR:$dst1, GPR:$dst2),
4530 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
4531 GPR:$set1, GPR:$set2, i32imm:$ordering),
4535 def ATOMIC_LOAD_I64 : PseudoInst<
4536 (outs GPR:$dst1, GPR:$dst2),
4537 (ins GPR:$addr, i32imm:$ordering),
4540 def ATOMIC_STORE_I64 : PseudoInst<
4541 (outs GPR:$dst1, GPR:$dst2),
4542 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4546 let usesCustomInserter = 1 in {
4547 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4548 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4550 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4553 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4554 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4557 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4558 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4561 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4562 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4565 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4566 (int_arm_strex node:$val, node:$ptr), [{
4567 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4570 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4571 (int_arm_strex node:$val, node:$ptr), [{
4572 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4575 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4576 (int_arm_strex node:$val, node:$ptr), [{
4577 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4580 let mayLoad = 1 in {
4581 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4582 NoItinerary, "ldrexb", "\t$Rt, $addr",
4583 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4584 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4585 NoItinerary, "ldrexh", "\t$Rt, $addr",
4586 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4587 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4588 NoItinerary, "ldrex", "\t$Rt, $addr",
4589 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4590 let hasExtraDefRegAllocReq = 1 in
4591 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4592 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4593 let DecoderMethod = "DecodeDoubleRegLoad";
4596 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4597 NoItinerary, "ldaexb", "\t$Rt, $addr", []>;
4598 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4599 NoItinerary, "ldaexh", "\t$Rt, $addr", []>;
4600 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4601 NoItinerary, "ldaex", "\t$Rt, $addr", []>;
4602 let hasExtraDefRegAllocReq = 1 in
4603 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4604 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4605 let DecoderMethod = "DecodeDoubleRegLoad";
4609 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4610 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4611 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4612 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4613 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4614 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4615 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4616 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4617 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4618 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4619 let hasExtraSrcRegAllocReq = 1 in
4620 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4621 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4622 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4623 let DecoderMethod = "DecodeDoubleRegStore";
4625 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4626 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4628 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4629 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4631 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4632 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4634 let hasExtraSrcRegAllocReq = 1 in
4635 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4636 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4637 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4638 let DecoderMethod = "DecodeDoubleRegStore";
4642 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4644 Requires<[IsARM, HasV7]> {
4645 let Inst{31-0} = 0b11110101011111111111000000011111;
4648 def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
4649 (LDREXB addr_offset_none:$addr)>;
4650 def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
4651 (LDREXH addr_offset_none:$addr)>;
4652 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4653 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4654 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4655 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4657 class acquiring_load<PatFrag base>
4658 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4659 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4660 return Ordering == Acquire || Ordering == SequentiallyConsistent;
4663 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4664 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4665 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4667 class releasing_store<PatFrag base>
4668 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4669 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4670 return Ordering == Release || Ordering == SequentiallyConsistent;
4673 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4674 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4675 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4677 let AddedComplexity = 8 in {
4678 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4679 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4680 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4681 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4682 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4683 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4686 // SWP/SWPB are deprecated in V6/V7.
4687 let mayLoad = 1, mayStore = 1 in {
4688 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4689 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4691 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4692 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4696 //===----------------------------------------------------------------------===//
4697 // Coprocessor Instructions.
4700 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4701 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4702 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4703 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4704 imm:$CRm, imm:$opc2)]>,
4713 let Inst{3-0} = CRm;
4715 let Inst{7-5} = opc2;
4716 let Inst{11-8} = cop;
4717 let Inst{15-12} = CRd;
4718 let Inst{19-16} = CRn;
4719 let Inst{23-20} = opc1;
4722 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4723 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4724 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4725 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4726 imm:$CRm, imm:$opc2)]>,
4728 let Inst{31-28} = 0b1111;
4736 let Inst{3-0} = CRm;
4738 let Inst{7-5} = opc2;
4739 let Inst{11-8} = cop;
4740 let Inst{15-12} = CRd;
4741 let Inst{19-16} = CRn;
4742 let Inst{23-20} = opc1;
4745 class ACI<dag oops, dag iops, string opc, string asm,
4746 IndexMode im = IndexModeNone>
4747 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4749 let Inst{27-25} = 0b110;
4751 class ACInoP<dag oops, dag iops, string opc, string asm,
4752 IndexMode im = IndexModeNone>
4753 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4755 let Inst{31-28} = 0b1111;
4756 let Inst{27-25} = 0b110;
4758 multiclass LdStCop<bit load, bit Dbit, string asm> {
4759 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4760 asm, "\t$cop, $CRd, $addr"> {
4764 let Inst{24} = 1; // P = 1
4765 let Inst{23} = addr{8};
4766 let Inst{22} = Dbit;
4767 let Inst{21} = 0; // W = 0
4768 let Inst{20} = load;
4769 let Inst{19-16} = addr{12-9};
4770 let Inst{15-12} = CRd;
4771 let Inst{11-8} = cop;
4772 let Inst{7-0} = addr{7-0};
4773 let DecoderMethod = "DecodeCopMemInstruction";
4775 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4776 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4780 let Inst{24} = 1; // P = 1
4781 let Inst{23} = addr{8};
4782 let Inst{22} = Dbit;
4783 let Inst{21} = 1; // W = 1
4784 let Inst{20} = load;
4785 let Inst{19-16} = addr{12-9};
4786 let Inst{15-12} = CRd;
4787 let Inst{11-8} = cop;
4788 let Inst{7-0} = addr{7-0};
4789 let DecoderMethod = "DecodeCopMemInstruction";
4791 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4792 postidx_imm8s4:$offset),
4793 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4798 let Inst{24} = 0; // P = 0
4799 let Inst{23} = offset{8};
4800 let Inst{22} = Dbit;
4801 let Inst{21} = 1; // W = 1
4802 let Inst{20} = load;
4803 let Inst{19-16} = addr;
4804 let Inst{15-12} = CRd;
4805 let Inst{11-8} = cop;
4806 let Inst{7-0} = offset{7-0};
4807 let DecoderMethod = "DecodeCopMemInstruction";
4809 def _OPTION : ACI<(outs),
4810 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4811 coproc_option_imm:$option),
4812 asm, "\t$cop, $CRd, $addr, $option"> {
4817 let Inst{24} = 0; // P = 0
4818 let Inst{23} = 1; // U = 1
4819 let Inst{22} = Dbit;
4820 let Inst{21} = 0; // W = 0
4821 let Inst{20} = load;
4822 let Inst{19-16} = addr;
4823 let Inst{15-12} = CRd;
4824 let Inst{11-8} = cop;
4825 let Inst{7-0} = option;
4826 let DecoderMethod = "DecodeCopMemInstruction";
4829 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4830 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4831 asm, "\t$cop, $CRd, $addr"> {
4835 let Inst{24} = 1; // P = 1
4836 let Inst{23} = addr{8};
4837 let Inst{22} = Dbit;
4838 let Inst{21} = 0; // W = 0
4839 let Inst{20} = load;
4840 let Inst{19-16} = addr{12-9};
4841 let Inst{15-12} = CRd;
4842 let Inst{11-8} = cop;
4843 let Inst{7-0} = addr{7-0};
4844 let DecoderMethod = "DecodeCopMemInstruction";
4846 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4847 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4851 let Inst{24} = 1; // P = 1
4852 let Inst{23} = addr{8};
4853 let Inst{22} = Dbit;
4854 let Inst{21} = 1; // W = 1
4855 let Inst{20} = load;
4856 let Inst{19-16} = addr{12-9};
4857 let Inst{15-12} = CRd;
4858 let Inst{11-8} = cop;
4859 let Inst{7-0} = addr{7-0};
4860 let DecoderMethod = "DecodeCopMemInstruction";
4862 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4863 postidx_imm8s4:$offset),
4864 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4869 let Inst{24} = 0; // P = 0
4870 let Inst{23} = offset{8};
4871 let Inst{22} = Dbit;
4872 let Inst{21} = 1; // W = 1
4873 let Inst{20} = load;
4874 let Inst{19-16} = addr;
4875 let Inst{15-12} = CRd;
4876 let Inst{11-8} = cop;
4877 let Inst{7-0} = offset{7-0};
4878 let DecoderMethod = "DecodeCopMemInstruction";
4880 def _OPTION : ACInoP<(outs),
4881 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4882 coproc_option_imm:$option),
4883 asm, "\t$cop, $CRd, $addr, $option"> {
4888 let Inst{24} = 0; // P = 0
4889 let Inst{23} = 1; // U = 1
4890 let Inst{22} = Dbit;
4891 let Inst{21} = 0; // W = 0
4892 let Inst{20} = load;
4893 let Inst{19-16} = addr;
4894 let Inst{15-12} = CRd;
4895 let Inst{11-8} = cop;
4896 let Inst{7-0} = option;
4897 let DecoderMethod = "DecodeCopMemInstruction";
4901 defm LDC : LdStCop <1, 0, "ldc">;
4902 defm LDCL : LdStCop <1, 1, "ldcl">;
4903 defm STC : LdStCop <0, 0, "stc">;
4904 defm STCL : LdStCop <0, 1, "stcl">;
4905 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4906 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4907 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4908 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4910 //===----------------------------------------------------------------------===//
4911 // Move between coprocessor and ARM core register.
4914 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4916 : ABI<0b1110, oops, iops, NoItinerary, opc,
4917 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4918 let Inst{20} = direction;
4928 let Inst{15-12} = Rt;
4929 let Inst{11-8} = cop;
4930 let Inst{23-21} = opc1;
4931 let Inst{7-5} = opc2;
4932 let Inst{3-0} = CRm;
4933 let Inst{19-16} = CRn;
4936 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4938 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4939 c_imm:$CRm, imm0_7:$opc2),
4940 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4941 imm:$CRm, imm:$opc2)]>,
4942 ComplexDeprecationPredicate<"MCR">;
4943 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4944 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4945 c_imm:$CRm, 0, pred:$p)>;
4946 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4947 (outs GPRwithAPSR:$Rt),
4948 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4950 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4951 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4952 c_imm:$CRm, 0, pred:$p)>;
4954 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4955 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4957 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4959 : ABXI<0b1110, oops, iops, NoItinerary,
4960 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4961 let Inst{31-24} = 0b11111110;
4962 let Inst{20} = direction;
4972 let Inst{15-12} = Rt;
4973 let Inst{11-8} = cop;
4974 let Inst{23-21} = opc1;
4975 let Inst{7-5} = opc2;
4976 let Inst{3-0} = CRm;
4977 let Inst{19-16} = CRn;
4980 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4982 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4983 c_imm:$CRm, imm0_7:$opc2),
4984 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4985 imm:$CRm, imm:$opc2)]>,
4987 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4988 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4990 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4991 (outs GPRwithAPSR:$Rt),
4992 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4995 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4996 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4999 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5000 imm:$CRm, imm:$opc2),
5001 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5003 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
5004 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5005 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
5006 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
5007 let Inst{23-21} = 0b010;
5008 let Inst{20} = direction;
5016 let Inst{15-12} = Rt;
5017 let Inst{19-16} = Rt2;
5018 let Inst{11-8} = cop;
5019 let Inst{7-4} = opc1;
5020 let Inst{3-0} = CRm;
5023 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5024 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5025 GPRnopc:$Rt2, imm:$CRm)]>;
5026 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5028 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5029 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5030 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5031 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5033 let Inst{31-28} = 0b1111;
5034 let Inst{23-21} = 0b010;
5035 let Inst{20} = direction;
5043 let Inst{15-12} = Rt;
5044 let Inst{19-16} = Rt2;
5045 let Inst{11-8} = cop;
5046 let Inst{7-4} = opc1;
5047 let Inst{3-0} = CRm;
5049 let DecoderMethod = "DecodeMRRC2";
5052 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5053 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5054 GPRnopc:$Rt2, imm:$CRm)]>;
5055 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5057 //===----------------------------------------------------------------------===//
5058 // Move between special register and ARM core register
5061 // Move to ARM core register from Special Register
5062 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5063 "mrs", "\t$Rd, apsr", []> {
5065 let Inst{23-16} = 0b00001111;
5066 let Unpredictable{19-17} = 0b111;
5068 let Inst{15-12} = Rd;
5070 let Inst{11-0} = 0b000000000000;
5071 let Unpredictable{11-0} = 0b110100001111;
5074 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5077 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5078 // section B9.3.9, with the R bit set to 1.
5079 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5080 "mrs", "\t$Rd, spsr", []> {
5082 let Inst{23-16} = 0b01001111;
5083 let Unpredictable{19-16} = 0b1111;
5085 let Inst{15-12} = Rd;
5087 let Inst{11-0} = 0b000000000000;
5088 let Unpredictable{11-0} = 0b110100001111;
5091 // Move from ARM core register to Special Register
5093 // No need to have both system and application versions, the encodings are the
5094 // same and the assembly parser has no way to distinguish between them. The mask
5095 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
5096 // the mask with the fields to be accessed in the special register.
5097 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5098 "msr", "\t$mask, $Rn", []> {
5103 let Inst{22} = mask{4}; // R bit
5104 let Inst{21-20} = 0b10;
5105 let Inst{19-16} = mask{3-0};
5106 let Inst{15-12} = 0b1111;
5107 let Inst{11-4} = 0b00000000;
5111 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
5112 "msr", "\t$mask, $a", []> {
5117 let Inst{22} = mask{4}; // R bit
5118 let Inst{21-20} = 0b10;
5119 let Inst{19-16} = mask{3-0};
5120 let Inst{15-12} = 0b1111;
5124 //===----------------------------------------------------------------------===//
5128 // __aeabi_read_tp preserves the registers r1-r3.
5129 // This is a pseudo inst so that we can get the encoding right,
5130 // complete with fixup for the aeabi_read_tp function.
5132 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5133 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
5134 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5137 //===----------------------------------------------------------------------===//
5138 // SJLJ Exception handling intrinsics
5139 // eh_sjlj_setjmp() is an instruction sequence to store the return
5140 // address and save #0 in R0 for the non-longjmp case.
5141 // Since by its nature we may be coming from some other function to get
5142 // here, and we're using the stack frame for the containing function to
5143 // save/restore registers, we can't keep anything live in regs across
5144 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5145 // when we get here from a longjmp(). We force everything out of registers
5146 // except for our own input by listing the relevant registers in Defs. By
5147 // doing so, we also cause the prologue/epilogue code to actively preserve
5148 // all of the callee-saved resgisters, which is exactly what we want.
5149 // A constant value is passed in $val, and we use the location as a scratch.
5151 // These are pseudo-instructions and are lowered to individual MC-insts, so
5152 // no encoding information is necessary.
5154 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5155 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5156 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5157 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5159 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5160 Requires<[IsARM, HasVFP2]>;
5164 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5165 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5166 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5168 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5169 Requires<[IsARM, NoVFP]>;
5172 // FIXME: Non-IOS version(s)
5173 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5174 Defs = [ R7, LR, SP ] in {
5175 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5177 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5178 Requires<[IsARM, IsIOS]>;
5181 // eh.sjlj.dispatchsetup pseudo-instruction.
5182 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5183 // the pseudo is expanded (which happens before any passes that need the
5184 // instruction size).
5185 let isBarrier = 1 in
5186 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5189 //===----------------------------------------------------------------------===//
5190 // Non-Instruction Patterns
5193 // ARMv4 indirect branch using (MOVr PC, dst)
5194 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5195 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5196 4, IIC_Br, [(brind GPR:$dst)],
5197 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5198 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5200 // Large immediate handling.
5202 // 32-bit immediate using two piece so_imms or movw + movt.
5203 // This is a single pseudo instruction, the benefit is that it can be remat'd
5204 // as a single unit instead of having to handle reg inputs.
5205 // FIXME: Remove this when we can do generalized remat.
5206 let isReMaterializable = 1, isMoveImm = 1 in
5207 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5208 [(set GPR:$dst, (arm_i32imm:$src))]>,
5211 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5212 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5213 Requires<[IsARM, DontUseMovt]>;
5215 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5216 // It also makes it possible to rematerialize the instructions.
5217 // FIXME: Remove this when we can do generalized remat and when machine licm
5218 // can properly the instructions.
5219 let isReMaterializable = 1 in {
5220 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5222 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5223 Requires<[IsARM, UseMovt]>;
5225 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5228 (ARMWrapperPIC tglobaladdr:$addr))]>,
5229 Requires<[IsARM, DontUseMovt]>;
5231 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5234 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5235 Requires<[IsARM, DontUseMovt]>;
5237 let AddedComplexity = 10 in
5238 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5240 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5241 Requires<[IsARM, UseMovt]>;
5242 } // isReMaterializable
5244 // ConstantPool, GlobalAddress, and JumpTable
5245 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5246 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5247 Requires<[IsARM, UseMovt]>;
5248 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5249 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5251 // TODO: add,sub,and, 3-instr forms?
5253 // Tail calls. These patterns also apply to Thumb mode.
5254 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5255 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5256 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5259 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5260 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5261 (BMOVPCB_CALL texternalsym:$func)>;
5263 // zextload i1 -> zextload i8
5264 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5265 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5267 // extload -> zextload
5268 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5269 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5270 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5271 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5273 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5275 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5276 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5279 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5280 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5281 (SMULBB GPR:$a, GPR:$b)>;
5282 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5283 (SMULBB GPR:$a, GPR:$b)>;
5284 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5285 (sra GPR:$b, (i32 16))),
5286 (SMULBT GPR:$a, GPR:$b)>;
5287 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5288 (SMULBT GPR:$a, GPR:$b)>;
5289 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5290 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5291 (SMULTB GPR:$a, GPR:$b)>;
5292 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5293 (SMULTB GPR:$a, GPR:$b)>;
5294 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5296 (SMULWB GPR:$a, GPR:$b)>;
5297 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5298 (SMULWB GPR:$a, GPR:$b)>;
5300 def : ARMV5MOPat<(add GPR:$acc,
5301 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5302 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5303 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5304 def : ARMV5MOPat<(add GPR:$acc,
5305 (mul sext_16_node:$a, sext_16_node:$b)),
5306 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5307 def : ARMV5MOPat<(add GPR:$acc,
5308 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5309 (sra GPR:$b, (i32 16)))),
5310 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5311 def : ARMV5MOPat<(add GPR:$acc,
5312 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5313 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5314 def : ARMV5MOPat<(add GPR:$acc,
5315 (mul (sra GPR:$a, (i32 16)),
5316 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5317 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5318 def : ARMV5MOPat<(add GPR:$acc,
5319 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5320 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5321 def : ARMV5MOPat<(add GPR:$acc,
5322 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5324 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5325 def : ARMV5MOPat<(add GPR:$acc,
5326 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5327 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5330 // Pre-v7 uses MCR for synchronization barriers.
5331 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5332 Requires<[IsARM, HasV6]>;
5334 // SXT/UXT with no rotate
5335 let AddedComplexity = 16 in {
5336 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5337 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5338 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5339 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5340 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5341 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5342 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5345 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5346 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5348 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5349 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5350 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5351 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5353 // Atomic load/store patterns
5354 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5355 (LDRBrs ldst_so_reg:$src)>;
5356 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5357 (LDRBi12 addrmode_imm12:$src)>;
5358 def : ARMPat<(atomic_load_16 addrmode3:$src),
5359 (LDRH addrmode3:$src)>;
5360 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5361 (LDRrs ldst_so_reg:$src)>;
5362 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5363 (LDRi12 addrmode_imm12:$src)>;
5364 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5365 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5366 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5367 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5368 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5369 (STRH GPR:$val, addrmode3:$ptr)>;
5370 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5371 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5372 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5373 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5376 //===----------------------------------------------------------------------===//
5380 include "ARMInstrThumb.td"
5382 //===----------------------------------------------------------------------===//
5386 include "ARMInstrThumb2.td"
5388 //===----------------------------------------------------------------------===//
5389 // Floating Point Support
5392 include "ARMInstrVFP.td"
5394 //===----------------------------------------------------------------------===//
5395 // Advanced SIMD (NEON) Support
5398 include "ARMInstrNEON.td"
5400 //===----------------------------------------------------------------------===//
5401 // Assembler aliases
5405 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5406 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5407 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5409 // System instructions
5410 def : MnemonicAlias<"swi", "svc">;
5412 // Load / Store Multiple
5413 def : MnemonicAlias<"ldmfd", "ldm">;
5414 def : MnemonicAlias<"ldmia", "ldm">;
5415 def : MnemonicAlias<"ldmea", "ldmdb">;
5416 def : MnemonicAlias<"stmfd", "stmdb">;
5417 def : MnemonicAlias<"stmia", "stm">;
5418 def : MnemonicAlias<"stmea", "stm">;
5420 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5421 // shift amount is zero (i.e., unspecified).
5422 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5423 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5424 Requires<[IsARM, HasV6]>;
5425 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5426 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5427 Requires<[IsARM, HasV6]>;
5429 // PUSH/POP aliases for STM/LDM
5430 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5431 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5433 // SSAT/USAT optional shift operand.
5434 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5435 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5436 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5437 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5440 // Extend instruction optional rotate operand.
5441 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5442 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5443 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5444 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5445 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5446 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5447 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5448 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5449 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5450 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5451 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5452 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5454 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5455 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5456 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5457 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5458 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5459 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5460 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5461 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5462 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5463 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5464 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5465 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5469 def : MnemonicAlias<"rfefa", "rfeda">;
5470 def : MnemonicAlias<"rfeea", "rfedb">;
5471 def : MnemonicAlias<"rfefd", "rfeia">;
5472 def : MnemonicAlias<"rfeed", "rfeib">;
5473 def : MnemonicAlias<"rfe", "rfeia">;
5476 def : MnemonicAlias<"srsfa", "srsib">;
5477 def : MnemonicAlias<"srsea", "srsia">;
5478 def : MnemonicAlias<"srsfd", "srsdb">;
5479 def : MnemonicAlias<"srsed", "srsda">;
5480 def : MnemonicAlias<"srs", "srsia">;
5483 def : MnemonicAlias<"qsubaddx", "qsax">;
5485 def : MnemonicAlias<"saddsubx", "sasx">;
5486 // SHASX == SHADDSUBX
5487 def : MnemonicAlias<"shaddsubx", "shasx">;
5488 // SHSAX == SHSUBADDX
5489 def : MnemonicAlias<"shsubaddx", "shsax">;
5491 def : MnemonicAlias<"ssubaddx", "ssax">;
5493 def : MnemonicAlias<"uaddsubx", "uasx">;
5494 // UHASX == UHADDSUBX
5495 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5496 // UHSAX == UHSUBADDX
5497 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5498 // UQASX == UQADDSUBX
5499 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5500 // UQSAX == UQSUBADDX
5501 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5503 def : MnemonicAlias<"usubaddx", "usax">;
5505 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5507 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5508 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5509 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5510 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5511 // Same for AND <--> BIC
5512 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5513 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5514 pred:$p, cc_out:$s)>;
5515 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5516 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5517 pred:$p, cc_out:$s)>;
5518 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5519 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5520 pred:$p, cc_out:$s)>;
5521 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5522 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5523 pred:$p, cc_out:$s)>;
5525 // Likewise, "add Rd, so_imm_neg" -> sub
5526 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5527 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5528 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5529 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5530 // Same for CMP <--> CMN via so_imm_neg
5531 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5532 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5533 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5534 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5536 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5537 // LSR, ROR, and RRX instructions.
5538 // FIXME: We need C++ parser hooks to map the alias to the MOV
5539 // encoding. It seems we should be able to do that sort of thing
5540 // in tblgen, but it could get ugly.
5541 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5542 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5543 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5545 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5546 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5548 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5549 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5551 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5552 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5555 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5556 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5557 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5558 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5559 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5561 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5562 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5564 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5565 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5567 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5568 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5572 // "neg" is and alias for "rsb rd, rn, #0"
5573 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5574 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5576 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5577 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5578 Requires<[IsARM, NoV6]>;
5580 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5581 // the instruction definitions need difference constraints pre-v6.
5582 // Use these aliases for the assembly parsing on pre-v6.
5583 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5584 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5585 Requires<[IsARM, NoV6]>;
5586 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5587 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5588 Requires<[IsARM, NoV6]>;
5589 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5590 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5591 Requires<[IsARM, NoV6]>;
5592 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5593 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5594 Requires<[IsARM, NoV6]>;
5595 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5596 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5597 Requires<[IsARM, NoV6]>;
5599 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5601 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5602 ComplexDeprecationPredicate<"IT">;