1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
49 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
50 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
52 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
53 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
55 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
57 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 0, []>;
58 def SDT_ARMSYNCBARRIER : SDTypeProfile<0, 0, []>;
59 def SDT_ARMMEMBARRIERMCR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
60 def SDT_ARMSYNCBARRIERMCR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
62 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
64 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
65 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
68 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
69 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
71 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
72 [SDNPHasChain, SDNPOutFlag]>;
73 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
74 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
76 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
79 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
86 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
87 [SDNPHasChain, SDNPOptInFlag]>;
89 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
91 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
94 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
95 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
97 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
99 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
102 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
105 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
108 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
109 [SDNPOutFlag,SDNPCommutative]>;
111 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
113 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
114 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
115 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
117 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
118 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
119 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
120 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
121 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
123 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
125 def ARMSyncBarrier : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIER,
127 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERMCR,
129 def ARMSyncBarrierMCR : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERMCR,
132 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
134 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
135 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
138 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
140 //===----------------------------------------------------------------------===//
141 // ARM Instruction Predicate Definitions.
143 def HasV4T : Predicate<"Subtarget->hasV4TOps()">;
144 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
145 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
146 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
147 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
148 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
149 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
150 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
151 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
152 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
153 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
154 def HasNEON : Predicate<"Subtarget->hasNEON()">;
155 def HasDivide : Predicate<"Subtarget->hasDivide()">;
156 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">;
157 def HasDB : Predicate<"Subtarget->hasDataBarrier()">;
158 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
159 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
160 def IsThumb : Predicate<"Subtarget->isThumb()">;
161 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
162 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
163 def IsARM : Predicate<"!Subtarget->isThumb()">;
164 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
165 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
167 // FIXME: Eventually this will be just "hasV6T2Ops".
168 def UseMovt : Predicate<"Subtarget->useMovt()">;
169 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
171 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
173 //===----------------------------------------------------------------------===//
174 // ARM Flag Definitions.
176 class RegConstraint<string C> {
177 string Constraints = C;
180 //===----------------------------------------------------------------------===//
181 // ARM specific transformation functions and pattern fragments.
184 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
185 // so_imm_neg def below.
186 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
187 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
190 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
191 // so_imm_not def below.
192 def so_imm_not_XFORM : SDNodeXForm<imm, [{
193 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
196 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
197 def rot_imm : PatLeaf<(i32 imm), [{
198 int32_t v = (int32_t)N->getZExtValue();
199 return v == 8 || v == 16 || v == 24;
202 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
203 def imm1_15 : PatLeaf<(i32 imm), [{
204 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
207 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
208 def imm16_31 : PatLeaf<(i32 imm), [{
209 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
214 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
215 }], so_imm_neg_XFORM>;
219 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
220 }], so_imm_not_XFORM>;
222 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
223 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
224 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
227 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
229 def bf_inv_mask_imm : Operand<i32>,
231 return ARM::isBitFieldInvertedMask(N->getZExtValue());
233 let PrintMethod = "printBitfieldInvMaskImmOperand";
236 /// Split a 32-bit immediate into two 16 bit parts.
237 def hi16 : SDNodeXForm<imm, [{
238 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
241 def lo16AllZero : PatLeaf<(i32 imm), [{
242 // Returns true if all low 16-bits are 0.
243 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
246 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
248 def imm0_65535 : PatLeaf<(i32 imm), [{
249 return (uint32_t)N->getZExtValue() < 65536;
252 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
253 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
255 /// adde and sube predicates - True based on whether the carry flag output
256 /// will be needed or not.
257 def adde_dead_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return !N->hasAnyUseOfValue(1);}]>;
260 def sube_dead_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return !N->hasAnyUseOfValue(1);}]>;
263 def adde_live_carry :
264 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
265 [{return N->hasAnyUseOfValue(1);}]>;
266 def sube_live_carry :
267 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
268 [{return N->hasAnyUseOfValue(1);}]>;
270 //===----------------------------------------------------------------------===//
271 // Operand Definitions.
275 def brtarget : Operand<OtherVT>;
277 // A list of registers separated by comma. Used by load/store multiple.
278 def reglist : Operand<i32> {
279 let PrintMethod = "printRegisterList";
282 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
283 def cpinst_operand : Operand<i32> {
284 let PrintMethod = "printCPInstOperand";
287 def jtblock_operand : Operand<i32> {
288 let PrintMethod = "printJTBlockOperand";
290 def jt2block_operand : Operand<i32> {
291 let PrintMethod = "printJT2BlockOperand";
295 def pclabel : Operand<i32> {
296 let PrintMethod = "printPCLabel";
299 // shift_imm: An integer that encodes a shift amount and the type of shift
300 // (currently either asr or lsl) using the same encoding used for the
301 // immediates in so_reg operands.
302 def shift_imm : Operand<i32> {
303 let PrintMethod = "printShiftImmOperand";
306 // shifter_operand operands: so_reg and so_imm.
307 def so_reg : Operand<i32>, // reg reg imm
308 ComplexPattern<i32, 3, "SelectShifterOperandReg",
309 [shl,srl,sra,rotr]> {
310 let PrintMethod = "printSORegOperand";
311 let MIOperandInfo = (ops GPR, GPR, i32imm);
314 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
315 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
316 // represented in the imm field in the same 12-bit form that they are encoded
317 // into so_imm instructions: the 8-bit immediate is the least significant bits
318 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
319 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
320 let PrintMethod = "printSOImmOperand";
323 // Break so_imm's up into two pieces. This handles immediates with up to 16
324 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
325 // get the first/second pieces.
326 def so_imm2part : Operand<i32>,
328 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
330 let PrintMethod = "printSOImm2PartOperand";
333 def so_imm2part_1 : SDNodeXForm<imm, [{
334 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
335 return CurDAG->getTargetConstant(V, MVT::i32);
338 def so_imm2part_2 : SDNodeXForm<imm, [{
339 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
340 return CurDAG->getTargetConstant(V, MVT::i32);
343 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
344 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
346 let PrintMethod = "printSOImm2PartOperand";
349 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
350 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
351 return CurDAG->getTargetConstant(V, MVT::i32);
354 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
355 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
356 return CurDAG->getTargetConstant(V, MVT::i32);
359 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
360 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
361 return (int32_t)N->getZExtValue() < 32;
364 // Define ARM specific addressing modes.
366 // addrmode2 := reg +/- reg shop imm
367 // addrmode2 := reg +/- imm12
369 def addrmode2 : Operand<i32>,
370 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
371 let PrintMethod = "printAddrMode2Operand";
372 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
375 def am2offset : Operand<i32>,
376 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
377 let PrintMethod = "printAddrMode2OffsetOperand";
378 let MIOperandInfo = (ops GPR, i32imm);
381 // addrmode3 := reg +/- reg
382 // addrmode3 := reg +/- imm8
384 def addrmode3 : Operand<i32>,
385 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
386 let PrintMethod = "printAddrMode3Operand";
387 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
390 def am3offset : Operand<i32>,
391 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
392 let PrintMethod = "printAddrMode3OffsetOperand";
393 let MIOperandInfo = (ops GPR, i32imm);
396 // addrmode4 := reg, <mode|W>
398 def addrmode4 : Operand<i32>,
399 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
400 let PrintMethod = "printAddrMode4Operand";
401 let MIOperandInfo = (ops GPR:$addr, i32imm);
404 // addrmode5 := reg +/- imm8*4
406 def addrmode5 : Operand<i32>,
407 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
408 let PrintMethod = "printAddrMode5Operand";
409 let MIOperandInfo = (ops GPR:$base, i32imm);
412 // addrmode6 := reg with optional writeback
414 def addrmode6 : Operand<i32>,
415 ComplexPattern<i32, 2, "SelectAddrMode6", []> {
416 let PrintMethod = "printAddrMode6Operand";
417 let MIOperandInfo = (ops GPR:$addr, i32imm);
420 def am6offset : Operand<i32> {
421 let PrintMethod = "printAddrMode6OffsetOperand";
422 let MIOperandInfo = (ops GPR);
425 // addrmodepc := pc + reg
427 def addrmodepc : Operand<i32>,
428 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
429 let PrintMethod = "printAddrModePCOperand";
430 let MIOperandInfo = (ops GPR, i32imm);
433 def nohash_imm : Operand<i32> {
434 let PrintMethod = "printNoHashImmediate";
437 //===----------------------------------------------------------------------===//
439 include "ARMInstrFormats.td"
441 //===----------------------------------------------------------------------===//
442 // Multiclass helpers...
445 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
446 /// binop that produces a value.
447 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
448 bit Commutable = 0> {
449 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
450 IIC_iALUi, opc, "\t$dst, $a, $b",
451 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
454 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
455 IIC_iALUr, opc, "\t$dst, $a, $b",
456 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
457 let Inst{11-4} = 0b00000000;
459 let isCommutable = Commutable;
461 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
462 IIC_iALUsr, opc, "\t$dst, $a, $b",
463 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
468 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
469 /// instruction modifies the CPSR register.
470 let Defs = [CPSR] in {
471 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
472 bit Commutable = 0> {
473 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
474 IIC_iALUi, opc, "\t$dst, $a, $b",
475 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
479 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
480 IIC_iALUr, opc, "\t$dst, $a, $b",
481 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
482 let isCommutable = Commutable;
483 let Inst{11-4} = 0b00000000;
487 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
488 IIC_iALUsr, opc, "\t$dst, $a, $b",
489 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
496 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
497 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
498 /// a explicit result, only implicitly set CPSR.
499 let isCompare = 1, Defs = [CPSR] in {
500 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
501 bit Commutable = 0> {
502 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
504 [(opnode GPR:$a, so_imm:$b)]> {
508 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
510 [(opnode GPR:$a, GPR:$b)]> {
511 let Inst{11-4} = 0b00000000;
514 let isCommutable = Commutable;
516 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
518 [(opnode GPR:$a, so_reg:$b)]> {
525 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
526 /// register and one whose operand is a register rotated by 8/16/24.
527 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
528 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
529 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
530 IIC_iUNAr, opc, "\t$dst, $src",
531 [(set GPR:$dst, (opnode GPR:$src))]>,
532 Requires<[IsARM, HasV6]> {
533 let Inst{11-10} = 0b00;
534 let Inst{19-16} = 0b1111;
536 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
537 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
538 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
539 Requires<[IsARM, HasV6]> {
540 let Inst{19-16} = 0b1111;
544 multiclass AI_unary_rrot_np<bits<8> opcod, string opc> {
545 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
546 IIC_iUNAr, opc, "\t$dst, $src",
547 [/* For disassembly only; pattern left blank */]>,
548 Requires<[IsARM, HasV6]> {
549 let Inst{11-10} = 0b00;
550 let Inst{19-16} = 0b1111;
552 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
553 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
554 [/* For disassembly only; pattern left blank */]>,
555 Requires<[IsARM, HasV6]> {
556 let Inst{19-16} = 0b1111;
560 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
561 /// register and one whose operand is a register rotated by 8/16/24.
562 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
563 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
564 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
565 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
566 Requires<[IsARM, HasV6]> {
567 let Inst{11-10} = 0b00;
569 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
571 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
572 [(set GPR:$dst, (opnode GPR:$LHS,
573 (rotr GPR:$RHS, rot_imm:$rot)))]>,
574 Requires<[IsARM, HasV6]>;
577 // For disassembly only.
578 multiclass AI_bin_rrot_np<bits<8> opcod, string opc> {
579 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
580 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
581 [/* For disassembly only; pattern left blank */]>,
582 Requires<[IsARM, HasV6]> {
583 let Inst{11-10} = 0b00;
585 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
587 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
588 [/* For disassembly only; pattern left blank */]>,
589 Requires<[IsARM, HasV6]>;
592 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
593 let Uses = [CPSR] in {
594 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
595 bit Commutable = 0> {
596 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
597 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
598 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
602 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
603 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
604 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
606 let isCommutable = Commutable;
607 let Inst{11-4} = 0b00000000;
610 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
611 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
612 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
617 // Carry setting variants
618 let Defs = [CPSR] in {
619 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
620 bit Commutable = 0> {
621 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
622 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
623 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
628 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
629 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
630 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
632 let Inst{11-4} = 0b00000000;
636 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
637 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
638 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 //===----------------------------------------------------------------------===//
652 // Miscellaneous Instructions.
655 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
656 /// the function. The first operand is the ID# for this instruction, the second
657 /// is the index into the MachineConstantPool that this is, the third is the
658 /// size in bytes of this constant pool entry.
659 let neverHasSideEffects = 1, isNotDuplicable = 1 in
660 def CONSTPOOL_ENTRY :
661 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
662 i32imm:$size), NoItinerary,
663 "${instid:label} ${cpidx:cpentry}", []>;
665 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
666 // from removing one half of the matched pairs. That breaks PEI, which assumes
667 // these will always be in pairs, and asserts if it finds otherwise. Better way?
668 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
670 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
671 "${:comment} ADJCALLSTACKUP $amt1",
672 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
674 def ADJCALLSTACKDOWN :
675 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
676 "${:comment} ADJCALLSTACKDOWN $amt",
677 [(ARMcallseq_start timm:$amt)]>;
680 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
681 [/* For disassembly only; pattern left blank */]>,
682 Requires<[IsARM, HasV6T2]> {
683 let Inst{27-16} = 0b001100100000;
684 let Inst{7-0} = 0b00000000;
687 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
688 [/* For disassembly only; pattern left blank */]>,
689 Requires<[IsARM, HasV6T2]> {
690 let Inst{27-16} = 0b001100100000;
691 let Inst{7-0} = 0b00000001;
694 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
695 [/* For disassembly only; pattern left blank */]>,
696 Requires<[IsARM, HasV6T2]> {
697 let Inst{27-16} = 0b001100100000;
698 let Inst{7-0} = 0b00000010;
701 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
702 [/* For disassembly only; pattern left blank */]>,
703 Requires<[IsARM, HasV6T2]> {
704 let Inst{27-16} = 0b001100100000;
705 let Inst{7-0} = 0b00000011;
708 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
710 [/* For disassembly only; pattern left blank */]>,
711 Requires<[IsARM, HasV6]> {
712 let Inst{27-20} = 0b01101000;
713 let Inst{7-4} = 0b1011;
716 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
717 [/* For disassembly only; pattern left blank */]>,
718 Requires<[IsARM, HasV6T2]> {
719 let Inst{27-16} = 0b001100100000;
720 let Inst{7-0} = 0b00000100;
723 // The i32imm operand $val can be used by a debugger to store more information
724 // about the breakpoint.
725 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
726 [/* For disassembly only; pattern left blank */]>,
728 let Inst{27-20} = 0b00010010;
729 let Inst{7-4} = 0b0111;
732 // Change Processor State is a system instruction -- for disassembly only.
733 // The singleton $opt operand contains the following information:
734 // opt{4-0} = mode from Inst{4-0}
735 // opt{5} = changemode from Inst{17}
736 // opt{8-6} = AIF from Inst{8-6}
737 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
738 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
739 [/* For disassembly only; pattern left blank */]>,
741 let Inst{31-28} = 0b1111;
742 let Inst{27-20} = 0b00010000;
747 // Preload signals the memory system of possible future data/instruction access.
748 // These are for disassembly only.
750 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
751 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
752 multiclass APreLoad<bit data, bit read, string opc> {
754 def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary,
755 !strconcat(opc, "\t[$base, $imm]"), []> {
756 let Inst{31-26} = 0b111101;
757 let Inst{25} = 0; // 0 for immediate form
760 let Inst{21-20} = 0b01;
763 def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary,
764 !strconcat(opc, "\t$addr"), []> {
765 let Inst{31-26} = 0b111101;
766 let Inst{25} = 1; // 1 for register form
769 let Inst{21-20} = 0b01;
774 defm PLD : APreLoad<1, 1, "pld">;
775 defm PLDW : APreLoad<1, 0, "pldw">;
776 defm PLI : APreLoad<0, 1, "pli">;
778 def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
779 [/* For disassembly only; pattern left blank */]>,
781 let Inst{31-28} = 0b1111;
782 let Inst{27-20} = 0b00010000;
785 let Inst{7-4} = 0b0000;
788 def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
789 [/* For disassembly only; pattern left blank */]>,
791 let Inst{31-28} = 0b1111;
792 let Inst{27-20} = 0b00010000;
795 let Inst{7-4} = 0b0000;
798 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
799 [/* For disassembly only; pattern left blank */]>,
800 Requires<[IsARM, HasV7]> {
801 let Inst{27-16} = 0b001100100000;
802 let Inst{7-4} = 0b1111;
805 // A5.4 Permanently UNDEFINED instructions.
806 // FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
808 let isBarrier = 1, isTerminator = 1 in
809 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
810 ".long 0xe7ffdefe ${:comment} trap", [(trap)]>,
812 let Inst{27-25} = 0b011;
813 let Inst{24-20} = 0b11111;
814 let Inst{7-5} = 0b111;
818 // Address computation and loads and stores in PIC mode.
819 let isNotDuplicable = 1 in {
820 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
821 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
822 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
824 let AddedComplexity = 10 in {
825 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
826 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
827 [(set GPR:$dst, (load addrmodepc:$addr))]>;
829 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
830 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr",
831 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
833 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
834 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr",
835 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
837 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
838 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr",
839 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
841 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
842 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr",
843 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
845 let AddedComplexity = 10 in {
846 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
847 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
848 [(store GPR:$src, addrmodepc:$addr)]>;
850 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
851 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
852 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
854 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
855 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
856 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
858 } // isNotDuplicable = 1
861 // LEApcrel - Load a pc-relative address into a register without offending the
863 let neverHasSideEffects = 1 in {
864 let isReMaterializable = 1 in
865 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
867 "adr$p\t$dst, #$label", []>;
869 } // neverHasSideEffects
870 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
871 (ins i32imm:$label, nohash_imm:$id, pred:$p),
873 "adr$p\t$dst, #${label}_${id}", []> {
877 //===----------------------------------------------------------------------===//
878 // Control Flow Instructions.
881 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
883 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
884 "bx", "\tlr", [(ARMretflag)]>,
885 Requires<[IsARM, HasV4T]> {
886 let Inst{3-0} = 0b1110;
887 let Inst{7-4} = 0b0001;
888 let Inst{19-8} = 0b111111111111;
889 let Inst{27-20} = 0b00010010;
893 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
894 "mov", "\tpc, lr", [(ARMretflag)]>,
895 Requires<[IsARM, NoV4T]> {
896 let Inst{11-0} = 0b000000001110;
897 let Inst{15-12} = 0b1111;
898 let Inst{19-16} = 0b0000;
899 let Inst{27-20} = 0b00011010;
904 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
906 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
908 Requires<[IsARM, HasV4T]> {
909 let Inst{7-4} = 0b0001;
910 let Inst{19-8} = 0b111111111111;
911 let Inst{27-20} = 0b00010010;
912 let Inst{31-28} = 0b1110;
916 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
918 Requires<[IsARM, NoV4T]> {
919 let Inst{11-4} = 0b00000000;
920 let Inst{15-12} = 0b1111;
921 let Inst{19-16} = 0b0000;
922 let Inst{27-20} = 0b00011010;
923 let Inst{31-28} = 0b1110;
927 // FIXME: remove when we have a way to marking a MI with these properties.
928 // FIXME: Should pc be an implicit operand like PICADD, etc?
929 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
930 hasExtraDefRegAllocReq = 1 in
931 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
932 reglist:$dsts, variable_ops),
933 IndexModeUpd, LdStMulFrm, IIC_Br,
934 "ldm${addr:submode}${p}\t$addr!, $dsts",
935 "$addr.addr = $wb", []>;
937 // On non-Darwin platforms R9 is callee-saved.
939 Defs = [R0, R1, R2, R3, R12, LR,
940 D0, D1, D2, D3, D4, D5, D6, D7,
941 D16, D17, D18, D19, D20, D21, D22, D23,
942 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
943 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
944 IIC_Br, "bl\t${func:call}",
945 [(ARMcall tglobaladdr:$func)]>,
946 Requires<[IsARM, IsNotDarwin]> {
947 let Inst{31-28} = 0b1110;
950 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
951 IIC_Br, "bl", "\t${func:call}",
952 [(ARMcall_pred tglobaladdr:$func)]>,
953 Requires<[IsARM, IsNotDarwin]>;
956 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
957 IIC_Br, "blx\t$func",
958 [(ARMcall GPR:$func)]>,
959 Requires<[IsARM, HasV5T, IsNotDarwin]> {
960 let Inst{7-4} = 0b0011;
961 let Inst{19-8} = 0b111111111111;
962 let Inst{27-20} = 0b00010010;
966 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
967 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
968 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
969 [(ARMcall_nolink tGPR:$func)]>,
970 Requires<[IsARM, HasV4T, IsNotDarwin]> {
971 let Inst{7-4} = 0b0001;
972 let Inst{19-8} = 0b111111111111;
973 let Inst{27-20} = 0b00010010;
977 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
978 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
979 [(ARMcall_nolink tGPR:$func)]>,
980 Requires<[IsARM, NoV4T, IsNotDarwin]> {
981 let Inst{11-4} = 0b00000000;
982 let Inst{15-12} = 0b1111;
983 let Inst{19-16} = 0b0000;
984 let Inst{27-20} = 0b00011010;
988 // On Darwin R9 is call-clobbered.
990 Defs = [R0, R1, R2, R3, R9, R12, LR,
991 D0, D1, D2, D3, D4, D5, D6, D7,
992 D16, D17, D18, D19, D20, D21, D22, D23,
993 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
994 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
995 IIC_Br, "bl\t${func:call}",
996 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
997 let Inst{31-28} = 0b1110;
1000 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1001 IIC_Br, "bl", "\t${func:call}",
1002 [(ARMcall_pred tglobaladdr:$func)]>,
1003 Requires<[IsARM, IsDarwin]>;
1006 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1007 IIC_Br, "blx\t$func",
1008 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1009 let Inst{7-4} = 0b0011;
1010 let Inst{19-8} = 0b111111111111;
1011 let Inst{27-20} = 0b00010010;
1015 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1016 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1017 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1018 [(ARMcall_nolink tGPR:$func)]>,
1019 Requires<[IsARM, HasV4T, IsDarwin]> {
1020 let Inst{7-4} = 0b0001;
1021 let Inst{19-8} = 0b111111111111;
1022 let Inst{27-20} = 0b00010010;
1026 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1027 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1028 [(ARMcall_nolink tGPR:$func)]>,
1029 Requires<[IsARM, NoV4T, IsDarwin]> {
1030 let Inst{11-4} = 0b00000000;
1031 let Inst{15-12} = 0b1111;
1032 let Inst{19-16} = 0b0000;
1033 let Inst{27-20} = 0b00011010;
1039 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1041 let Defs = [R0, R1, R2, R3, R9, R12,
1042 D0, D1, D2, D3, D4, D5, D6, D7,
1043 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1044 D27, D28, D29, D30, D31, PC],
1046 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1048 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1050 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1052 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1054 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1055 IIC_Br, "b\t$dst @ TAILCALL",
1056 []>, Requires<[IsDarwin]>;
1058 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1059 IIC_Br, "b.w\t$dst @ TAILCALL",
1060 []>, Requires<[IsDarwin]>;
1062 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1063 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1064 []>, Requires<[IsDarwin]> {
1065 let Inst{7-4} = 0b0001;
1066 let Inst{19-8} = 0b111111111111;
1067 let Inst{27-20} = 0b00010010;
1068 let Inst{31-28} = 0b1110;
1072 // Non-Darwin versions (the difference is R9).
1073 let Defs = [R0, R1, R2, R3, R12,
1074 D0, D1, D2, D3, D4, D5, D6, D7,
1075 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1076 D27, D28, D29, D30, D31, PC],
1078 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1080 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1082 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1084 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1086 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1087 IIC_Br, "b\t$dst @ TAILCALL",
1088 []>, Requires<[IsARM, IsNotDarwin]>;
1090 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1091 IIC_Br, "b.w\t$dst @ TAILCALL",
1092 []>, Requires<[IsThumb, IsNotDarwin]>;
1094 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1095 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1096 []>, Requires<[IsNotDarwin]> {
1097 let Inst{7-4} = 0b0001;
1098 let Inst{19-8} = 0b111111111111;
1099 let Inst{27-20} = 0b00010010;
1100 let Inst{31-28} = 0b1110;
1105 let isBranch = 1, isTerminator = 1 in {
1106 // B is "predicable" since it can be xformed into a Bcc.
1107 let isBarrier = 1 in {
1108 let isPredicable = 1 in
1109 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1110 "b\t$target", [(br bb:$target)]>;
1112 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1113 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1114 IIC_Br, "mov\tpc, $target$jt",
1115 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1116 let Inst{11-4} = 0b00000000;
1117 let Inst{15-12} = 0b1111;
1118 let Inst{20} = 0; // S Bit
1119 let Inst{24-21} = 0b1101;
1120 let Inst{27-25} = 0b000;
1122 def BR_JTm : JTI<(outs),
1123 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1124 IIC_Br, "ldr\tpc, $target$jt",
1125 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1127 let Inst{15-12} = 0b1111;
1128 let Inst{20} = 1; // L bit
1129 let Inst{21} = 0; // W bit
1130 let Inst{22} = 0; // B bit
1131 let Inst{24} = 1; // P bit
1132 let Inst{27-25} = 0b011;
1134 def BR_JTadd : JTI<(outs),
1135 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1136 IIC_Br, "add\tpc, $target, $idx$jt",
1137 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1139 let Inst{15-12} = 0b1111;
1140 let Inst{20} = 0; // S bit
1141 let Inst{24-21} = 0b0100;
1142 let Inst{27-25} = 0b000;
1144 } // isNotDuplicable = 1, isIndirectBranch = 1
1147 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1148 // a two-value operand where a dag node expects two operands. :(
1149 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1150 IIC_Br, "b", "\t$target",
1151 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1154 // Branch and Exchange Jazelle -- for disassembly only
1155 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1156 [/* For disassembly only; pattern left blank */]> {
1157 let Inst{23-20} = 0b0010;
1158 //let Inst{19-8} = 0xfff;
1159 let Inst{7-4} = 0b0010;
1162 // Secure Monitor Call is a system instruction -- for disassembly only
1163 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1164 [/* For disassembly only; pattern left blank */]> {
1165 let Inst{23-20} = 0b0110;
1166 let Inst{7-4} = 0b0111;
1169 // Supervisor Call (Software Interrupt) -- for disassembly only
1171 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1172 [/* For disassembly only; pattern left blank */]>;
1175 // Store Return State is a system instruction -- for disassembly only
1176 def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1177 NoItinerary, "srs${addr:submode}\tsp!, $mode",
1178 [/* For disassembly only; pattern left blank */]> {
1179 let Inst{31-28} = 0b1111;
1180 let Inst{22-20} = 0b110; // W = 1
1183 def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1184 NoItinerary, "srs${addr:submode}\tsp, $mode",
1185 [/* For disassembly only; pattern left blank */]> {
1186 let Inst{31-28} = 0b1111;
1187 let Inst{22-20} = 0b100; // W = 0
1190 // Return From Exception is a system instruction -- for disassembly only
1191 def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1192 NoItinerary, "rfe${addr:submode}\t$base!",
1193 [/* For disassembly only; pattern left blank */]> {
1194 let Inst{31-28} = 0b1111;
1195 let Inst{22-20} = 0b011; // W = 1
1198 def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1199 NoItinerary, "rfe${addr:submode}\t$base",
1200 [/* For disassembly only; pattern left blank */]> {
1201 let Inst{31-28} = 0b1111;
1202 let Inst{22-20} = 0b001; // W = 0
1205 //===----------------------------------------------------------------------===//
1206 // Load / store Instructions.
1210 let canFoldAsLoad = 1, isReMaterializable = 1 in
1211 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1212 "ldr", "\t$dst, $addr",
1213 [(set GPR:$dst, (load addrmode2:$addr))]>;
1215 // Special LDR for loads from non-pc-relative constpools.
1216 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1217 isReMaterializable = 1 in
1218 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1219 "ldr", "\t$dst, $addr", []>;
1221 // Loads with zero extension
1222 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1223 IIC_iLoadr, "ldrh", "\t$dst, $addr",
1224 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1226 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
1227 IIC_iLoadr, "ldrb", "\t$dst, $addr",
1228 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
1230 // Loads with sign extension
1231 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1232 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
1233 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1235 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1236 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
1237 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1239 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1241 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1242 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
1243 []>, Requires<[IsARM, HasV5TE]>;
1246 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1247 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1248 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1250 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1251 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1252 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1254 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1255 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1256 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1258 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1259 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1260 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1262 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1263 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1264 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1266 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1267 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1268 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1270 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1271 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1272 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1274 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1275 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1276 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1278 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1279 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1280 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1282 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1283 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1284 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1286 // For disassembly only
1287 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1288 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadr,
1289 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1290 Requires<[IsARM, HasV5TE]>;
1292 // For disassembly only
1293 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1294 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadr,
1295 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1296 Requires<[IsARM, HasV5TE]>;
1298 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1300 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1302 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1303 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1304 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1305 let Inst{21} = 1; // overwrite
1308 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1309 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1310 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1311 let Inst{21} = 1; // overwrite
1314 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1315 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1316 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1317 let Inst{21} = 1; // overwrite
1320 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1321 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1322 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1323 let Inst{21} = 1; // overwrite
1326 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1327 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1328 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1329 let Inst{21} = 1; // overwrite
1333 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1334 "str", "\t$src, $addr",
1335 [(store GPR:$src, addrmode2:$addr)]>;
1337 // Stores with truncate
1338 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1339 IIC_iStorer, "strh", "\t$src, $addr",
1340 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1342 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1343 "strb", "\t$src, $addr",
1344 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
1347 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1348 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1349 StMiscFrm, IIC_iStorer,
1350 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1353 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1354 (ins GPR:$src, GPR:$base, am2offset:$offset),
1355 StFrm, IIC_iStoreru,
1356 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1358 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1360 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1361 (ins GPR:$src, GPR:$base,am2offset:$offset),
1362 StFrm, IIC_iStoreru,
1363 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1365 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1367 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1368 (ins GPR:$src, GPR:$base,am3offset:$offset),
1369 StMiscFrm, IIC_iStoreru,
1370 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1372 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1374 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1375 (ins GPR:$src, GPR:$base,am3offset:$offset),
1376 StMiscFrm, IIC_iStoreru,
1377 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1378 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1379 GPR:$base, am3offset:$offset))]>;
1381 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1382 (ins GPR:$src, GPR:$base,am2offset:$offset),
1383 StFrm, IIC_iStoreru,
1384 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1385 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1386 GPR:$base, am2offset:$offset))]>;
1388 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1389 (ins GPR:$src, GPR:$base,am2offset:$offset),
1390 StFrm, IIC_iStoreru,
1391 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1392 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1393 GPR:$base, am2offset:$offset))]>;
1395 // For disassembly only
1396 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1397 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1398 StMiscFrm, IIC_iStoreru,
1399 "strd", "\t$src1, $src2, [$base, $offset]!",
1400 "$base = $base_wb", []>;
1402 // For disassembly only
1403 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1404 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1405 StMiscFrm, IIC_iStoreru,
1406 "strd", "\t$src1, $src2, [$base], $offset",
1407 "$base = $base_wb", []>;
1409 // STRT, STRBT, and STRHT are for disassembly only.
1411 def STRT : AI2stwpo<(outs GPR:$base_wb),
1412 (ins GPR:$src, GPR:$base,am2offset:$offset),
1413 StFrm, IIC_iStoreru,
1414 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1415 [/* For disassembly only; pattern left blank */]> {
1416 let Inst{21} = 1; // overwrite
1419 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1420 (ins GPR:$src, GPR:$base,am2offset:$offset),
1421 StFrm, IIC_iStoreru,
1422 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1423 [/* For disassembly only; pattern left blank */]> {
1424 let Inst{21} = 1; // overwrite
1427 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1428 (ins GPR:$src, GPR:$base,am3offset:$offset),
1429 StMiscFrm, IIC_iStoreru,
1430 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1431 [/* For disassembly only; pattern left blank */]> {
1432 let Inst{21} = 1; // overwrite
1435 //===----------------------------------------------------------------------===//
1436 // Load / store multiple Instructions.
1439 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1440 def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
1441 reglist:$dsts, variable_ops),
1442 IndexModeNone, LdStMulFrm, IIC_iLoadm,
1443 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
1445 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1446 reglist:$dsts, variable_ops),
1447 IndexModeUpd, LdStMulFrm, IIC_iLoadm,
1448 "ldm${addr:submode}${p}\t$addr!, $dsts",
1449 "$addr.addr = $wb", []>;
1450 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1452 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1453 def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
1454 reglist:$srcs, variable_ops),
1455 IndexModeNone, LdStMulFrm, IIC_iStorem,
1456 "stm${addr:submode}${p}\t$addr, $srcs", "", []>;
1458 def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1459 reglist:$srcs, variable_ops),
1460 IndexModeUpd, LdStMulFrm, IIC_iStorem,
1461 "stm${addr:submode}${p}\t$addr!, $srcs",
1462 "$addr.addr = $wb", []>;
1463 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1465 //===----------------------------------------------------------------------===//
1466 // Move Instructions.
1469 let neverHasSideEffects = 1 in
1470 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1471 "mov", "\t$dst, $src", []>, UnaryDP {
1472 let Inst{11-4} = 0b00000000;
1476 // A version for the smaller set of tail call registers.
1477 let neverHasSideEffects = 1 in
1478 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$dst), (ins tcGPR:$src), DPFrm,
1479 IIC_iMOVr, "mov", "\t$dst, $src", []>, UnaryDP {
1480 let Inst{11-4} = 0b00000000;
1484 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
1485 DPSoRegFrm, IIC_iMOVsr,
1486 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
1490 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1491 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
1492 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
1496 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1497 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
1499 "movw", "\t$dst, $src",
1500 [(set GPR:$dst, imm0_65535:$src)]>,
1501 Requires<[IsARM, HasV6T2]>, UnaryDP {
1506 let Constraints = "$src = $dst" in
1507 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
1509 "movt", "\t$dst, $imm",
1511 (or (and GPR:$src, 0xffff),
1512 lo16AllZero:$imm))]>, UnaryDP,
1513 Requires<[IsARM, HasV6T2]> {
1518 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1519 Requires<[IsARM, HasV6T2]>;
1521 let Uses = [CPSR] in
1522 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1523 "mov", "\t$dst, $src, rrx",
1524 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1526 // These aren't really mov instructions, but we have to define them this way
1527 // due to flag operands.
1529 let Defs = [CPSR] in {
1530 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1531 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1532 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1533 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1534 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1535 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1538 //===----------------------------------------------------------------------===//
1539 // Extend Instructions.
1544 defm SXTB : AI_unary_rrot<0b01101010,
1545 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1546 defm SXTH : AI_unary_rrot<0b01101011,
1547 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1549 defm SXTAB : AI_bin_rrot<0b01101010,
1550 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1551 defm SXTAH : AI_bin_rrot<0b01101011,
1552 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1554 // For disassembly only
1555 defm SXTB16 : AI_unary_rrot_np<0b01101000, "sxtb16">;
1557 // For disassembly only
1558 defm SXTAB16 : AI_bin_rrot_np<0b01101000, "sxtab16">;
1562 let AddedComplexity = 16 in {
1563 defm UXTB : AI_unary_rrot<0b01101110,
1564 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1565 defm UXTH : AI_unary_rrot<0b01101111,
1566 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1567 defm UXTB16 : AI_unary_rrot<0b01101100,
1568 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1570 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1571 // The transformation should probably be done as a combiner action
1572 // instead so we can include a check for masking back in the upper
1573 // eight bits of the source into the lower eight bits of the result.
1574 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1575 // (UXTB16r_rot GPR:$Src, 24)>;
1576 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1577 (UXTB16r_rot GPR:$Src, 8)>;
1579 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1580 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1581 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1582 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1585 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1586 // For disassembly only
1587 defm UXTAB16 : AI_bin_rrot_np<0b01101100, "uxtab16">;
1590 def SBFX : I<(outs GPR:$dst),
1591 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1592 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1593 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1594 Requires<[IsARM, HasV6T2]> {
1595 let Inst{27-21} = 0b0111101;
1596 let Inst{6-4} = 0b101;
1599 def UBFX : I<(outs GPR:$dst),
1600 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1601 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1602 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1603 Requires<[IsARM, HasV6T2]> {
1604 let Inst{27-21} = 0b0111111;
1605 let Inst{6-4} = 0b101;
1608 //===----------------------------------------------------------------------===//
1609 // Arithmetic Instructions.
1612 defm ADD : AsI1_bin_irs<0b0100, "add",
1613 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1614 defm SUB : AsI1_bin_irs<0b0010, "sub",
1615 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1617 // ADD and SUB with 's' bit set.
1618 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1619 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1620 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1621 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1623 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1624 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1625 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1626 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1627 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1628 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1629 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1630 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1632 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1633 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1634 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1638 // The reg/reg form is only defined for the disassembler; for codegen it is
1639 // equivalent to SUBrr.
1640 def RSBrr : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
1641 IIC_iALUr, "rsb", "\t$dst, $a, $b",
1642 [/* For disassembly only; pattern left blank */]> {
1644 let Inst{11-4} = 0b00000000;
1647 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1648 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1649 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1653 // RSB with 's' bit set.
1654 let Defs = [CPSR] in {
1655 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1656 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1657 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1661 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1662 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1663 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1669 let Uses = [CPSR] in {
1670 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1671 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1672 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1676 // The reg/reg form is only defined for the disassembler; for codegen it is
1677 // equivalent to SUBrr.
1678 def RSCrr : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1679 DPFrm, IIC_iALUr, "rsc", "\t$dst, $a, $b",
1680 [/* For disassembly only; pattern left blank */]> {
1682 let Inst{11-4} = 0b00000000;
1684 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1685 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1686 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1692 // FIXME: Allow these to be predicated.
1693 let Defs = [CPSR], Uses = [CPSR] in {
1694 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1695 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1696 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1701 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1702 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1703 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1710 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1711 // The assume-no-carry-in form uses the negation of the input since add/sub
1712 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1713 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1715 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1716 (SUBri GPR:$src, so_imm_neg:$imm)>;
1717 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1718 (SUBSri GPR:$src, so_imm_neg:$imm)>;
1719 // The with-carry-in form matches bitwise not instead of the negation.
1720 // Effectively, the inverse interpretation of the carry flag already accounts
1721 // for part of the negation.
1722 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
1723 (SBCri GPR:$src, so_imm_not:$imm)>;
1725 // Note: These are implemented in C++ code, because they have to generate
1726 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1728 // (mul X, 2^n+1) -> (add (X << n), X)
1729 // (mul X, 2^n-1) -> (rsb X, (X << n))
1731 // ARM Arithmetic Instruction -- for disassembly only
1732 // GPR:$dst = GPR:$a op GPR:$b
1733 class AAI<bits<8> op27_20, bits<4> op7_4, string opc,
1734 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
1735 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
1736 opc, "\t$dst, $a, $b", pattern> {
1737 let Inst{27-20} = op27_20;
1738 let Inst{7-4} = op7_4;
1741 // Saturating add/subtract -- for disassembly only
1743 def QADD : AAI<0b00010000, 0b0101, "qadd",
1744 [(set GPR:$dst, (int_arm_qadd GPR:$a, GPR:$b))]>;
1745 def QADD16 : AAI<0b01100010, 0b0001, "qadd16">;
1746 def QADD8 : AAI<0b01100010, 0b1001, "qadd8">;
1747 def QASX : AAI<0b01100010, 0b0011, "qasx">;
1748 def QDADD : AAI<0b00010100, 0b0101, "qdadd">;
1749 def QDSUB : AAI<0b00010110, 0b0101, "qdsub">;
1750 def QSAX : AAI<0b01100010, 0b0101, "qsax">;
1751 def QSUB : AAI<0b00010010, 0b0101, "qsub",
1752 [(set GPR:$dst, (int_arm_qsub GPR:$a, GPR:$b))]>;
1753 def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">;
1754 def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">;
1755 def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">;
1756 def UQADD8 : AAI<0b01100110, 0b1001, "uqadd8">;
1757 def UQASX : AAI<0b01100110, 0b0011, "uqasx">;
1758 def UQSAX : AAI<0b01100110, 0b0101, "uqsax">;
1759 def UQSUB16 : AAI<0b01100110, 0b0111, "uqsub16">;
1760 def UQSUB8 : AAI<0b01100110, 0b1111, "uqsub8">;
1762 // Signed/Unsigned add/subtract -- for disassembly only
1764 def SASX : AAI<0b01100001, 0b0011, "sasx">;
1765 def SADD16 : AAI<0b01100001, 0b0001, "sadd16">;
1766 def SADD8 : AAI<0b01100001, 0b1001, "sadd8">;
1767 def SSAX : AAI<0b01100001, 0b0101, "ssax">;
1768 def SSUB16 : AAI<0b01100001, 0b0111, "ssub16">;
1769 def SSUB8 : AAI<0b01100001, 0b1111, "ssub8">;
1770 def UASX : AAI<0b01100101, 0b0011, "uasx">;
1771 def UADD16 : AAI<0b01100101, 0b0001, "uadd16">;
1772 def UADD8 : AAI<0b01100101, 0b1001, "uadd8">;
1773 def USAX : AAI<0b01100101, 0b0101, "usax">;
1774 def USUB16 : AAI<0b01100101, 0b0111, "usub16">;
1775 def USUB8 : AAI<0b01100101, 0b1111, "usub8">;
1777 // Signed/Unsigned halving add/subtract -- for disassembly only
1779 def SHASX : AAI<0b01100011, 0b0011, "shasx">;
1780 def SHADD16 : AAI<0b01100011, 0b0001, "shadd16">;
1781 def SHADD8 : AAI<0b01100011, 0b1001, "shadd8">;
1782 def SHSAX : AAI<0b01100011, 0b0101, "shsax">;
1783 def SHSUB16 : AAI<0b01100011, 0b0111, "shsub16">;
1784 def SHSUB8 : AAI<0b01100011, 0b1111, "shsub8">;
1785 def UHASX : AAI<0b01100111, 0b0011, "uhasx">;
1786 def UHADD16 : AAI<0b01100111, 0b0001, "uhadd16">;
1787 def UHADD8 : AAI<0b01100111, 0b1001, "uhadd8">;
1788 def UHSAX : AAI<0b01100111, 0b0101, "uhsax">;
1789 def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">;
1790 def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">;
1792 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1794 def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1795 MulFrm /* for convenience */, NoItinerary, "usad8",
1796 "\t$dst, $a, $b", []>,
1797 Requires<[IsARM, HasV6]> {
1798 let Inst{27-20} = 0b01111000;
1799 let Inst{15-12} = 0b1111;
1800 let Inst{7-4} = 0b0001;
1802 def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1803 MulFrm /* for convenience */, NoItinerary, "usada8",
1804 "\t$dst, $a, $b, $acc", []>,
1805 Requires<[IsARM, HasV6]> {
1806 let Inst{27-20} = 0b01111000;
1807 let Inst{7-4} = 0b0001;
1810 // Signed/Unsigned saturate -- for disassembly only
1812 def SSAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, shift_imm:$sh),
1813 SatFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
1814 [/* For disassembly only; pattern left blank */]> {
1815 let Inst{27-21} = 0b0110101;
1816 let Inst{5-4} = 0b01;
1819 def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm,
1820 NoItinerary, "ssat16", "\t$dst, $bit_pos, $a",
1821 [/* For disassembly only; pattern left blank */]> {
1822 let Inst{27-20} = 0b01101010;
1823 let Inst{7-4} = 0b0011;
1826 def USAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, shift_imm:$sh),
1827 SatFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
1828 [/* For disassembly only; pattern left blank */]> {
1829 let Inst{27-21} = 0b0110111;
1830 let Inst{5-4} = 0b01;
1833 def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm,
1834 NoItinerary, "usat16", "\t$dst, $bit_pos, $a",
1835 [/* For disassembly only; pattern left blank */]> {
1836 let Inst{27-20} = 0b01101110;
1837 let Inst{7-4} = 0b0011;
1840 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
1841 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
1843 //===----------------------------------------------------------------------===//
1844 // Bitwise Instructions.
1847 defm AND : AsI1_bin_irs<0b0000, "and",
1848 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1849 defm ORR : AsI1_bin_irs<0b1100, "orr",
1850 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1851 defm EOR : AsI1_bin_irs<0b0001, "eor",
1852 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1853 defm BIC : AsI1_bin_irs<0b1110, "bic",
1854 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1856 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1857 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1858 "bfc", "\t$dst, $imm", "$src = $dst",
1859 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1860 Requires<[IsARM, HasV6T2]> {
1861 let Inst{27-21} = 0b0111110;
1862 let Inst{6-0} = 0b0011111;
1865 // A8.6.18 BFI - Bitfield insert (Encoding A1)
1866 def BFI : I<(outs GPR:$dst), (ins GPR:$src, GPR:$val, bf_inv_mask_imm:$imm),
1867 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1868 "bfi", "\t$dst, $val, $imm", "$src = $dst",
1869 [(set GPR:$dst, (ARMbfi GPR:$src, GPR:$val,
1870 bf_inv_mask_imm:$imm))]>,
1871 Requires<[IsARM, HasV6T2]> {
1872 let Inst{27-21} = 0b0111110;
1873 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
1876 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1877 "mvn", "\t$dst, $src",
1878 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1880 let Inst{11-4} = 0b00000000;
1882 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1883 IIC_iMOVsr, "mvn", "\t$dst, $src",
1884 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1887 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1888 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1889 IIC_iMOVi, "mvn", "\t$dst, $imm",
1890 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1894 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1895 (BICri GPR:$src, so_imm_not:$imm)>;
1897 //===----------------------------------------------------------------------===//
1898 // Multiply Instructions.
1901 let isCommutable = 1 in
1902 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1903 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1904 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1906 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1907 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1908 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1910 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1911 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1912 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1913 Requires<[IsARM, HasV6T2]>;
1915 // Extra precision multiplies with low / high results
1916 let neverHasSideEffects = 1 in {
1917 let isCommutable = 1 in {
1918 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1919 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1920 "smull", "\t$ldst, $hdst, $a, $b", []>;
1922 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1923 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1924 "umull", "\t$ldst, $hdst, $a, $b", []>;
1927 // Multiply + accumulate
1928 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1929 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1930 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1932 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1933 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1934 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1936 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1937 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1938 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1939 Requires<[IsARM, HasV6]>;
1940 } // neverHasSideEffects
1942 // Most significant word multiply
1943 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1944 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1945 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1946 Requires<[IsARM, HasV6]> {
1947 let Inst{7-4} = 0b0001;
1948 let Inst{15-12} = 0b1111;
1951 def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1952 IIC_iMUL32, "smmulr", "\t$dst, $a, $b",
1953 [/* For disassembly only; pattern left blank */]>,
1954 Requires<[IsARM, HasV6]> {
1955 let Inst{7-4} = 0b0011; // R = 1
1956 let Inst{15-12} = 0b1111;
1959 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1960 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1961 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1962 Requires<[IsARM, HasV6]> {
1963 let Inst{7-4} = 0b0001;
1966 def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1967 IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c",
1968 [/* For disassembly only; pattern left blank */]>,
1969 Requires<[IsARM, HasV6]> {
1970 let Inst{7-4} = 0b0011; // R = 1
1973 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1974 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1975 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1976 Requires<[IsARM, HasV6]> {
1977 let Inst{7-4} = 0b1101;
1980 def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1981 IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c",
1982 [/* For disassembly only; pattern left blank */]>,
1983 Requires<[IsARM, HasV6]> {
1984 let Inst{7-4} = 0b1111; // R = 1
1987 multiclass AI_smul<string opc, PatFrag opnode> {
1988 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1989 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1990 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1991 (sext_inreg GPR:$b, i16)))]>,
1992 Requires<[IsARM, HasV5TE]> {
1997 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1998 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1999 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
2000 (sra GPR:$b, (i32 16))))]>,
2001 Requires<[IsARM, HasV5TE]> {
2006 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2007 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
2008 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
2009 (sext_inreg GPR:$b, i16)))]>,
2010 Requires<[IsARM, HasV5TE]> {
2015 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2016 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
2017 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
2018 (sra GPR:$b, (i32 16))))]>,
2019 Requires<[IsARM, HasV5TE]> {
2024 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2025 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
2026 [(set GPR:$dst, (sra (opnode GPR:$a,
2027 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
2028 Requires<[IsARM, HasV5TE]> {
2033 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2034 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
2035 [(set GPR:$dst, (sra (opnode GPR:$a,
2036 (sra GPR:$b, (i32 16))), (i32 16)))]>,
2037 Requires<[IsARM, HasV5TE]> {
2044 multiclass AI_smla<string opc, PatFrag opnode> {
2045 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2046 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
2047 [(set GPR:$dst, (add GPR:$acc,
2048 (opnode (sext_inreg GPR:$a, i16),
2049 (sext_inreg GPR:$b, i16))))]>,
2050 Requires<[IsARM, HasV5TE]> {
2055 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2056 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
2057 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
2058 (sra GPR:$b, (i32 16)))))]>,
2059 Requires<[IsARM, HasV5TE]> {
2064 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2065 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
2066 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
2067 (sext_inreg GPR:$b, i16))))]>,
2068 Requires<[IsARM, HasV5TE]> {
2073 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2074 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
2075 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
2076 (sra GPR:$b, (i32 16)))))]>,
2077 Requires<[IsARM, HasV5TE]> {
2082 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2083 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
2084 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
2085 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
2086 Requires<[IsARM, HasV5TE]> {
2091 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2092 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
2093 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
2094 (sra GPR:$b, (i32 16))), (i32 16))))]>,
2095 Requires<[IsARM, HasV5TE]> {
2101 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2102 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2104 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2105 def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2106 IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
2107 [/* For disassembly only; pattern left blank */]>,
2108 Requires<[IsARM, HasV5TE]> {
2113 def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2114 IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2115 [/* For disassembly only; pattern left blank */]>,
2116 Requires<[IsARM, HasV5TE]> {
2121 def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2122 IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2123 [/* For disassembly only; pattern left blank */]>,
2124 Requires<[IsARM, HasV5TE]> {
2129 def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2130 IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2131 [/* For disassembly only; pattern left blank */]>,
2132 Requires<[IsARM, HasV5TE]> {
2137 // Helper class for AI_smld -- for disassembly only
2138 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2139 InstrItinClass itin, string opc, string asm>
2140 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2145 let Inst{21-20} = 0b00;
2146 let Inst{22} = long;
2147 let Inst{27-23} = 0b01110;
2150 multiclass AI_smld<bit sub, string opc> {
2152 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2153 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b, $acc">;
2155 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2156 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b, $acc">;
2158 def LD : AMulDualI<1, sub, 0, (outs GPR:$ldst,GPR:$hdst), (ins GPR:$a,GPR:$b),
2159 NoItinerary, !strconcat(opc, "ld"), "\t$ldst, $hdst, $a, $b">;
2161 def LDX : AMulDualI<1, sub, 1, (outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2162 NoItinerary, !strconcat(opc, "ldx"),"\t$ldst, $hdst, $a, $b">;
2166 defm SMLA : AI_smld<0, "smla">;
2167 defm SMLS : AI_smld<1, "smls">;
2169 multiclass AI_sdml<bit sub, string opc> {
2171 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2172 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b"> {
2173 let Inst{15-12} = 0b1111;
2176 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2177 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b"> {
2178 let Inst{15-12} = 0b1111;
2183 defm SMUA : AI_sdml<0, "smua">;
2184 defm SMUS : AI_sdml<1, "smus">;
2186 //===----------------------------------------------------------------------===//
2187 // Misc. Arithmetic Instructions.
2190 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2191 "clz", "\t$dst, $src",
2192 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
2193 let Inst{7-4} = 0b0001;
2194 let Inst{11-8} = 0b1111;
2195 let Inst{19-16} = 0b1111;
2198 def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2199 "rbit", "\t$dst, $src",
2200 [(set GPR:$dst, (ARMrbit GPR:$src))]>,
2201 Requires<[IsARM, HasV6T2]> {
2202 let Inst{7-4} = 0b0011;
2203 let Inst{11-8} = 0b1111;
2204 let Inst{19-16} = 0b1111;
2207 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2208 "rev", "\t$dst, $src",
2209 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
2210 let Inst{7-4} = 0b0011;
2211 let Inst{11-8} = 0b1111;
2212 let Inst{19-16} = 0b1111;
2215 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2216 "rev16", "\t$dst, $src",
2218 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2219 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2220 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2221 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
2222 Requires<[IsARM, HasV6]> {
2223 let Inst{7-4} = 0b1011;
2224 let Inst{11-8} = 0b1111;
2225 let Inst{19-16} = 0b1111;
2228 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2229 "revsh", "\t$dst, $src",
2232 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2233 (shl GPR:$src, (i32 8))), i16))]>,
2234 Requires<[IsARM, HasV6]> {
2235 let Inst{7-4} = 0b1011;
2236 let Inst{11-8} = 0b1111;
2237 let Inst{19-16} = 0b1111;
2240 def lsl_shift_imm : SDNodeXForm<imm, [{
2241 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2242 return CurDAG->getTargetConstant(Sh, MVT::i32);
2245 def lsl_amt : PatLeaf<(i32 imm), [{
2246 return (N->getZExtValue() < 32);
2249 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
2250 (ins GPR:$src1, GPR:$src2, shift_imm:$sh),
2251 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh",
2252 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2253 (and (shl GPR:$src2, lsl_amt:$sh),
2255 Requires<[IsARM, HasV6]> {
2256 let Inst{6-4} = 0b001;
2259 // Alternate cases for PKHBT where identities eliminate some nodes.
2260 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2261 (PKHBT GPR:$src1, GPR:$src2, 0)>;
2262 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$sh)),
2263 (PKHBT GPR:$src1, GPR:$src2, (lsl_shift_imm imm16_31:$sh))>;
2265 def asr_shift_imm : SDNodeXForm<imm, [{
2266 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2267 return CurDAG->getTargetConstant(Sh, MVT::i32);
2270 def asr_amt : PatLeaf<(i32 imm), [{
2271 return (N->getZExtValue() <= 32);
2274 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2275 // will match the pattern below.
2276 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
2277 (ins GPR:$src1, GPR:$src2, shift_imm:$sh),
2278 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh",
2279 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2280 (and (sra GPR:$src2, asr_amt:$sh),
2282 Requires<[IsARM, HasV6]> {
2283 let Inst{6-4} = 0b101;
2286 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2287 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2288 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2289 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2290 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2291 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2292 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2294 //===----------------------------------------------------------------------===//
2295 // Comparison Instructions...
2298 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2299 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2301 // FIXME: There seems to be a (potential) hardware bug with the CMN instruction
2302 // and comparison with 0. These two pieces of code should give identical
2318 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2319 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2320 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2321 // value of r0 and the carry bit (because the "carry bit" parameter to
2322 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2323 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2324 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2325 // parameter to AddWithCarry is defined as 0).
2327 // The AddWithCarry in the CMP case seems to be relying upon the identity:
2331 // However when x is 0 and unsigned, this doesn't hold:
2335 // ~x + 1 = 0x1 0000 0000
2336 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2338 // Therefore, we should disable *all* versions of CMN, especially when comparing
2339 // against zero, until we can limit when the CMN instruction is used (when we
2340 // know that the RHS is not 0) or when we have a hardware fix for this.
2342 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2344 // This is related to <rdar://problem/7569620>.
2346 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2347 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2349 // Note that TST/TEQ don't set all the same flags that CMP does!
2350 defm TST : AI1_cmp_irs<0b1000, "tst",
2351 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2352 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2353 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2355 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2356 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2357 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2358 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2360 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2361 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2363 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2364 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2366 // Pseudo i64 compares for some floating point compares.
2367 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2369 def BCCi64 : PseudoInst<(outs),
2370 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2372 "${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, imm:$cc",
2373 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2375 def BCCZi64 : PseudoInst<(outs),
2376 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst),
2378 "${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, 0, 0, imm:$cc",
2379 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2380 } // usesCustomInserter
2383 // Conditional moves
2384 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2385 // a two-value operand where a dag node expects two operands. :(
2386 let neverHasSideEffects = 1 in {
2387 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
2388 IIC_iCMOVr, "mov", "\t$dst, $true",
2389 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2390 RegConstraint<"$false = $dst">, UnaryDP {
2391 let Inst{11-4} = 0b00000000;
2395 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
2396 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
2397 "mov", "\t$dst, $true",
2398 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
2399 RegConstraint<"$false = $dst">, UnaryDP {
2403 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
2404 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
2405 "mov", "\t$dst, $true",
2406 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2407 RegConstraint<"$false = $dst">, UnaryDP {
2410 } // neverHasSideEffects
2412 //===----------------------------------------------------------------------===//
2413 // Atomic operations intrinsics
2416 // memory barriers protect the atomic sequences
2417 let hasSideEffects = 1 in {
2418 def DMBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dmb", "",
2419 [(ARMMemBarrier)]>, Requires<[IsARM, HasDB]> {
2420 let Inst{31-4} = 0xf57ff05;
2421 // FIXME: add support for options other than a full system DMB
2422 // See DMB disassembly-only variants below.
2423 let Inst{3-0} = 0b1111;
2426 def DSBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dsb", "",
2427 [(ARMSyncBarrier)]>, Requires<[IsARM, HasDB]> {
2428 let Inst{31-4} = 0xf57ff04;
2429 // FIXME: add support for options other than a full system DSB
2430 // See DSB disassembly-only variants below.
2431 let Inst{3-0} = 0b1111;
2434 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2435 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2436 [(ARMMemBarrierMCR GPR:$zero)]>,
2437 Requires<[IsARM, HasV6]> {
2438 // FIXME: add support for options other than a full system DMB
2439 // FIXME: add encoding
2442 def DSB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2443 "mcr", "\tp15, 0, $zero, c7, c10, 4",
2444 [(ARMSyncBarrierMCR GPR:$zero)]>,
2445 Requires<[IsARM, HasV6]> {
2446 // FIXME: add support for options other than a full system DSB
2447 // FIXME: add encoding
2451 // Memory Barrier Operations Variants -- for disassembly only
2453 def memb_opt : Operand<i32> {
2454 let PrintMethod = "printMemBOption";
2457 class AMBI<bits<4> op7_4, string opc>
2458 : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, opc, "\t$opt",
2459 [/* For disassembly only; pattern left blank */]>,
2460 Requires<[IsARM, HasDB]> {
2461 let Inst{31-8} = 0xf57ff0;
2462 let Inst{7-4} = op7_4;
2465 // These DMB variants are for disassembly only.
2466 def DMBvar : AMBI<0b0101, "dmb">;
2468 // These DSB variants are for disassembly only.
2469 def DSBvar : AMBI<0b0100, "dsb">;
2471 // ISB has only full system option -- for disassembly only
2472 def ISBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2473 Requires<[IsARM, HasDB]> {
2474 let Inst{31-4} = 0xf57ff06;
2475 let Inst{3-0} = 0b1111;
2478 let usesCustomInserter = 1 in {
2479 let Uses = [CPSR] in {
2480 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2481 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2482 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
2483 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2484 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2485 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2486 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
2487 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2488 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2489 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2490 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
2491 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2492 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2493 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2494 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
2495 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2496 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2497 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2498 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
2499 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2500 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2501 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2502 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
2503 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2504 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2505 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2506 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
2507 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2508 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2509 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2510 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
2511 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2512 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2513 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2514 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
2515 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2516 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2517 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2518 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
2519 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2520 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2521 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2522 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
2523 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2524 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2525 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2526 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
2527 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2528 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2529 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2530 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
2531 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2532 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2533 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2534 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
2535 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2536 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2537 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2538 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
2539 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2540 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2541 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2542 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
2543 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2544 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2545 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2546 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
2547 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2548 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2549 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2550 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
2551 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2553 def ATOMIC_SWAP_I8 : PseudoInst<
2554 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2555 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
2556 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2557 def ATOMIC_SWAP_I16 : PseudoInst<
2558 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2559 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
2560 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2561 def ATOMIC_SWAP_I32 : PseudoInst<
2562 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2563 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
2564 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
2566 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
2567 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2568 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
2569 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
2570 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
2571 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2572 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
2573 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
2574 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
2575 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2576 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
2577 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
2581 let mayLoad = 1 in {
2582 def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2583 "ldrexb", "\t$dest, [$ptr]",
2585 def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2586 "ldrexh", "\t$dest, [$ptr]",
2588 def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2589 "ldrex", "\t$dest, [$ptr]",
2591 def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2593 "ldrexd", "\t$dest, $dest2, [$ptr]",
2597 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2598 def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2600 "strexb", "\t$success, $src, [$ptr]",
2602 def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2604 "strexh", "\t$success, $src, [$ptr]",
2606 def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2608 "strex", "\t$success, $src, [$ptr]",
2610 def STREXD : AIstrex<0b01, (outs GPR:$success),
2611 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2613 "strexd", "\t$success, $src, $src2, [$ptr]",
2617 // Clear-Exclusive is for disassembly only.
2618 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
2619 [/* For disassembly only; pattern left blank */]>,
2620 Requires<[IsARM, HasV7]> {
2621 let Inst{31-20} = 0xf57;
2622 let Inst{7-4} = 0b0001;
2625 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
2626 let mayLoad = 1 in {
2627 def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2628 "swp", "\t$dst, $src, [$ptr]",
2629 [/* For disassembly only; pattern left blank */]> {
2630 let Inst{27-23} = 0b00010;
2631 let Inst{22} = 0; // B = 0
2632 let Inst{21-20} = 0b00;
2633 let Inst{7-4} = 0b1001;
2636 def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2637 "swpb", "\t$dst, $src, [$ptr]",
2638 [/* For disassembly only; pattern left blank */]> {
2639 let Inst{27-23} = 0b00010;
2640 let Inst{22} = 1; // B = 1
2641 let Inst{21-20} = 0b00;
2642 let Inst{7-4} = 0b1001;
2646 //===----------------------------------------------------------------------===//
2650 // __aeabi_read_tp preserves the registers r1-r3.
2652 Defs = [R0, R12, LR, CPSR] in {
2653 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
2654 "bl\t__aeabi_read_tp",
2655 [(set R0, ARMthread_pointer)]>;
2658 //===----------------------------------------------------------------------===//
2659 // SJLJ Exception handling intrinsics
2660 // eh_sjlj_setjmp() is an instruction sequence to store the return
2661 // address and save #0 in R0 for the non-longjmp case.
2662 // Since by its nature we may be coming from some other function to get
2663 // here, and we're using the stack frame for the containing function to
2664 // save/restore registers, we can't keep anything live in regs across
2665 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2666 // when we get here from a longjmp(). We force everthing out of registers
2667 // except for our own input by listing the relevant registers in Defs. By
2668 // doing so, we also cause the prologue/epilogue code to actively preserve
2669 // all of the callee-saved resgisters, which is exactly what we want.
2670 // A constant value is passed in $val, and we use the location as a scratch.
2672 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2673 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2674 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2675 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2676 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
2677 AddrModeNone, SizeSpecial, IndexModeNone,
2678 Pseudo, NoItinerary,
2679 "add\t$val, pc, #8\t${:comment} eh_setjmp begin\n\t"
2680 "str\t$val, [$src, #+4]\n\t"
2682 "add\tpc, pc, #0\n\t"
2683 "mov\tr0, #1 ${:comment} eh_setjmp end", "",
2684 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
2685 Requires<[IsARM, HasVFP2]>;
2689 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2690 hasSideEffects = 1, isBarrier = 1 in {
2691 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
2692 AddrModeNone, SizeSpecial, IndexModeNone,
2693 Pseudo, NoItinerary,
2694 "add\t$val, pc, #8\n ${:comment} eh_setjmp begin\n\t"
2695 "str\t$val, [$src, #+4]\n\t"
2697 "add\tpc, pc, #0\n\t"
2698 "mov\tr0, #1 ${:comment} eh_setjmp end", "",
2699 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
2700 Requires<[IsARM, NoVFP]>;
2703 // FIXME: Non-Darwin version(s)
2704 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
2705 Defs = [ R7, LR, SP ] in {
2706 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
2707 AddrModeNone, SizeSpecial, IndexModeNone,
2708 Pseudo, NoItinerary,
2709 "ldr\tsp, [$src, #8]\n\t"
2710 "ldr\t$scratch, [$src, #4]\n\t"
2711 "ldr\tr7, [$src]\n\t"
2713 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
2714 Requires<[IsARM, IsDarwin]>;
2717 //===----------------------------------------------------------------------===//
2718 // Non-Instruction Patterns
2721 // Large immediate handling.
2723 // Two piece so_imms.
2724 let isReMaterializable = 1 in
2725 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
2727 "mov", "\t$dst, $src",
2728 [(set GPR:$dst, so_imm2part:$src)]>,
2729 Requires<[IsARM, NoV6T2]>;
2731 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
2732 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2733 (so_imm2part_2 imm:$RHS))>;
2734 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
2735 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2736 (so_imm2part_2 imm:$RHS))>;
2737 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
2738 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2739 (so_imm2part_2 imm:$RHS))>;
2740 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
2741 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
2742 (so_neg_imm2part_2 imm:$RHS))>;
2744 // 32-bit immediate using movw + movt.
2745 // This is a single pseudo instruction, the benefit is that it can be remat'd
2746 // as a single unit instead of having to handle reg inputs.
2747 // FIXME: Remove this when we can do generalized remat.
2748 let isReMaterializable = 1 in
2749 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
2750 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2751 [(set GPR:$dst, (i32 imm:$src))]>,
2752 Requires<[IsARM, HasV6T2]>;
2754 // ConstantPool, GlobalAddress, and JumpTable
2755 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
2756 Requires<[IsARM, DontUseMovt]>;
2757 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
2758 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
2759 Requires<[IsARM, UseMovt]>;
2760 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2761 (LEApcrelJT tjumptable:$dst, imm:$id)>;
2763 // TODO: add,sub,and, 3-instr forms?
2766 def : ARMPat<(ARMtcret tcGPR:$dst),
2767 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
2769 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
2770 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
2772 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
2773 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
2775 def : ARMPat<(ARMtcret tcGPR:$dst),
2776 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
2778 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
2779 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
2781 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
2782 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
2785 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
2786 Requires<[IsARM, IsNotDarwin]>;
2787 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
2788 Requires<[IsARM, IsDarwin]>;
2790 // zextload i1 -> zextload i8
2791 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2793 // extload -> zextload
2794 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2795 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2796 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
2798 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
2799 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
2802 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2803 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2804 (SMULBB GPR:$a, GPR:$b)>;
2805 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
2806 (SMULBB GPR:$a, GPR:$b)>;
2807 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2808 (sra GPR:$b, (i32 16))),
2809 (SMULBT GPR:$a, GPR:$b)>;
2810 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
2811 (SMULBT GPR:$a, GPR:$b)>;
2812 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
2813 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2814 (SMULTB GPR:$a, GPR:$b)>;
2815 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
2816 (SMULTB GPR:$a, GPR:$b)>;
2817 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2819 (SMULWB GPR:$a, GPR:$b)>;
2820 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
2821 (SMULWB GPR:$a, GPR:$b)>;
2823 def : ARMV5TEPat<(add GPR:$acc,
2824 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2825 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2826 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2827 def : ARMV5TEPat<(add GPR:$acc,
2828 (mul sext_16_node:$a, sext_16_node:$b)),
2829 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2830 def : ARMV5TEPat<(add GPR:$acc,
2831 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2832 (sra GPR:$b, (i32 16)))),
2833 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2834 def : ARMV5TEPat<(add GPR:$acc,
2835 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
2836 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2837 def : ARMV5TEPat<(add GPR:$acc,
2838 (mul (sra GPR:$a, (i32 16)),
2839 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2840 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2841 def : ARMV5TEPat<(add GPR:$acc,
2842 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
2843 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2844 def : ARMV5TEPat<(add GPR:$acc,
2845 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2847 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2848 def : ARMV5TEPat<(add GPR:$acc,
2849 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
2850 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2852 //===----------------------------------------------------------------------===//
2856 include "ARMInstrThumb.td"
2858 //===----------------------------------------------------------------------===//
2862 include "ARMInstrThumb2.td"
2864 //===----------------------------------------------------------------------===//
2865 // Floating Point Support
2868 include "ARMInstrVFP.td"
2870 //===----------------------------------------------------------------------===//
2871 // Advanced SIMD (NEON) Support
2874 include "ARMInstrNEON.td"
2876 //===----------------------------------------------------------------------===//
2877 // Coprocessor Instructions. For disassembly only.
2880 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2881 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2882 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2883 [/* For disassembly only; pattern left blank */]> {
2887 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2888 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2889 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2890 [/* For disassembly only; pattern left blank */]> {
2891 let Inst{31-28} = 0b1111;
2895 class ACI<dag oops, dag iops, string opc, string asm>
2896 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
2897 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
2898 let Inst{27-25} = 0b110;
2901 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
2903 def _OFFSET : ACI<(outs),
2904 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2905 opc, "\tp$cop, cr$CRd, $addr"> {
2906 let Inst{31-28} = op31_28;
2907 let Inst{24} = 1; // P = 1
2908 let Inst{21} = 0; // W = 0
2909 let Inst{22} = 0; // D = 0
2910 let Inst{20} = load;
2913 def _PRE : ACI<(outs),
2914 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2915 opc, "\tp$cop, cr$CRd, $addr!"> {
2916 let Inst{31-28} = op31_28;
2917 let Inst{24} = 1; // P = 1
2918 let Inst{21} = 1; // W = 1
2919 let Inst{22} = 0; // D = 0
2920 let Inst{20} = load;
2923 def _POST : ACI<(outs),
2924 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2925 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
2926 let Inst{31-28} = op31_28;
2927 let Inst{24} = 0; // P = 0
2928 let Inst{21} = 1; // W = 1
2929 let Inst{22} = 0; // D = 0
2930 let Inst{20} = load;
2933 def _OPTION : ACI<(outs),
2934 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
2935 opc, "\tp$cop, cr$CRd, [$base], $option"> {
2936 let Inst{31-28} = op31_28;
2937 let Inst{24} = 0; // P = 0
2938 let Inst{23} = 1; // U = 1
2939 let Inst{21} = 0; // W = 0
2940 let Inst{22} = 0; // D = 0
2941 let Inst{20} = load;
2944 def L_OFFSET : ACI<(outs),
2945 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2946 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
2947 let Inst{31-28} = op31_28;
2948 let Inst{24} = 1; // P = 1
2949 let Inst{21} = 0; // W = 0
2950 let Inst{22} = 1; // D = 1
2951 let Inst{20} = load;
2954 def L_PRE : ACI<(outs),
2955 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2956 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
2957 let Inst{31-28} = op31_28;
2958 let Inst{24} = 1; // P = 1
2959 let Inst{21} = 1; // W = 1
2960 let Inst{22} = 1; // D = 1
2961 let Inst{20} = load;
2964 def L_POST : ACI<(outs),
2965 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2966 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
2967 let Inst{31-28} = op31_28;
2968 let Inst{24} = 0; // P = 0
2969 let Inst{21} = 1; // W = 1
2970 let Inst{22} = 1; // D = 1
2971 let Inst{20} = load;
2974 def L_OPTION : ACI<(outs),
2975 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
2976 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
2977 let Inst{31-28} = op31_28;
2978 let Inst{24} = 0; // P = 0
2979 let Inst{23} = 1; // U = 1
2980 let Inst{21} = 0; // W = 0
2981 let Inst{22} = 1; // D = 1
2982 let Inst{20} = load;
2986 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
2987 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
2988 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
2989 defm STC2 : LdStCop<0b1111, 0, "stc2">;
2991 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2992 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2993 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2994 [/* For disassembly only; pattern left blank */]> {
2999 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3000 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3001 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3002 [/* For disassembly only; pattern left blank */]> {
3003 let Inst{31-28} = 0b1111;
3008 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3009 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3010 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3011 [/* For disassembly only; pattern left blank */]> {
3016 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3017 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3018 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3019 [/* For disassembly only; pattern left blank */]> {
3020 let Inst{31-28} = 0b1111;
3025 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3026 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3027 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3028 [/* For disassembly only; pattern left blank */]> {
3029 let Inst{23-20} = 0b0100;
3032 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3033 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3034 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3035 [/* For disassembly only; pattern left blank */]> {
3036 let Inst{31-28} = 0b1111;
3037 let Inst{23-20} = 0b0100;
3040 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3041 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3042 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3043 [/* For disassembly only; pattern left blank */]> {
3044 let Inst{23-20} = 0b0101;
3047 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3048 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3049 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3050 [/* For disassembly only; pattern left blank */]> {
3051 let Inst{31-28} = 0b1111;
3052 let Inst{23-20} = 0b0101;
3055 //===----------------------------------------------------------------------===//
3056 // Move between special register and ARM core register -- for disassembly only
3059 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3060 [/* For disassembly only; pattern left blank */]> {
3061 let Inst{23-20} = 0b0000;
3062 let Inst{7-4} = 0b0000;
3065 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3066 [/* For disassembly only; pattern left blank */]> {
3067 let Inst{23-20} = 0b0100;
3068 let Inst{7-4} = 0b0000;
3071 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3072 "msr", "\tcpsr$mask, $src",
3073 [/* For disassembly only; pattern left blank */]> {
3074 let Inst{23-20} = 0b0010;
3075 let Inst{7-4} = 0b0000;
3078 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3079 "msr", "\tcpsr$mask, $a",
3080 [/* For disassembly only; pattern left blank */]> {
3081 let Inst{23-20} = 0b0010;
3082 let Inst{7-4} = 0b0000;
3085 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3086 "msr", "\tspsr$mask, $src",
3087 [/* For disassembly only; pattern left blank */]> {
3088 let Inst{23-20} = 0b0110;
3089 let Inst{7-4} = 0b0000;
3092 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3093 "msr", "\tspsr$mask, $a",
3094 [/* For disassembly only; pattern left blank */]> {
3095 let Inst{23-20} = 0b0110;
3096 let Inst{7-4} = 0b0000;