1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
76 SDTCisInt<0>, SDTCisVT<1, i32>]>;
78 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
79 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
86 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
87 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
88 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
89 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
91 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
92 [SDNPHasChain, SDNPOutGlue]>;
93 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
94 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
96 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
97 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
99 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
102 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
106 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
107 [SDNPHasChain, SDNPOptInGlue]>;
109 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
112 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
113 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
115 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
117 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
120 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
123 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
126 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
127 [SDNPOutGlue, SDNPCommutative]>;
129 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
131 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
132 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
133 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
135 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
137 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
138 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
139 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
141 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
142 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
143 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
144 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
145 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
146 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
147 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
150 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
152 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
154 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
155 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
157 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
159 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
160 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
163 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
165 //===----------------------------------------------------------------------===//
166 // ARM Instruction Predicate Definitions.
168 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
169 AssemblerPredicate<"HasV4TOps">;
170 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
171 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
172 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
173 AssemblerPredicate<"HasV5TEOps">;
174 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
175 AssemblerPredicate<"HasV6Ops">;
176 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
177 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
178 AssemblerPredicate<"HasV6T2Ops">;
179 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
180 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
181 AssemblerPredicate<"HasV7Ops">;
182 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
183 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
184 AssemblerPredicate<"FeatureVFP2">;
185 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
186 AssemblerPredicate<"FeatureVFP3">;
187 def HasNEON : Predicate<"Subtarget->hasNEON()">,
188 AssemblerPredicate<"FeatureNEON">;
189 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
190 AssemblerPredicate<"FeatureFP16">;
191 def HasDivide : Predicate<"Subtarget->hasDivide()">,
192 AssemblerPredicate<"FeatureHWDiv">;
193 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
194 AssemblerPredicate<"FeatureT2XtPk">;
195 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
196 AssemblerPredicate<"FeatureDSPThumb2">;
197 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
198 AssemblerPredicate<"FeatureDB">;
199 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
200 AssemblerPredicate<"FeatureMP">;
201 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
202 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
203 def IsThumb : Predicate<"Subtarget->isThumb()">,
204 AssemblerPredicate<"ModeThumb">;
205 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
206 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
207 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
208 def IsARM : Predicate<"!Subtarget->isThumb()">,
209 AssemblerPredicate<"!ModeThumb">;
210 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
211 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
212 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">,
213 AssemblerPredicate<"ModeNaCl">;
215 // FIXME: Eventually this will be just "hasV6T2Ops".
216 def UseMovt : Predicate<"Subtarget->useMovt()">;
217 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
218 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
220 //===----------------------------------------------------------------------===//
221 // ARM Flag Definitions.
223 class RegConstraint<string C> {
224 string Constraints = C;
227 //===----------------------------------------------------------------------===//
228 // ARM specific transformation functions and pattern fragments.
231 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
232 // so_imm_neg def below.
233 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
234 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
237 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
238 // so_imm_not def below.
239 def so_imm_not_XFORM : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
243 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
244 def imm1_15 : ImmLeaf<i32, [{
245 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
248 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
249 def imm16_31 : ImmLeaf<i32, [{
250 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
255 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
256 }], so_imm_neg_XFORM>;
260 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
261 }], so_imm_not_XFORM>;
263 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
264 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
265 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
268 /// Split a 32-bit immediate into two 16 bit parts.
269 def hi16 : SDNodeXForm<imm, [{
270 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
273 def lo16AllZero : PatLeaf<(i32 imm), [{
274 // Returns true if all low 16-bits are 0.
275 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
278 /// imm0_65535 - An immediate is in the range [0.65535].
279 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
280 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
281 return Imm >= 0 && Imm < 65536;
283 let ParserMatchClass = Imm0_65535AsmOperand;
286 class BinOpWithFlagFrag<dag res> :
287 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
288 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
289 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
291 // An 'and' node with a single use.
292 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
293 return N->hasOneUse();
296 // An 'xor' node with a single use.
297 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
298 return N->hasOneUse();
301 // An 'fmul' node with a single use.
302 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
303 return N->hasOneUse();
306 // An 'fadd' node which checks for single non-hazardous use.
307 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
308 return hasNoVMLxHazardUse(N);
311 // An 'fsub' node which checks for single non-hazardous use.
312 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
313 return hasNoVMLxHazardUse(N);
316 //===----------------------------------------------------------------------===//
317 // Operand Definitions.
321 // FIXME: rename brtarget to t2_brtarget
322 def brtarget : Operand<OtherVT> {
323 let EncoderMethod = "getBranchTargetOpValue";
324 let OperandType = "OPERAND_PCREL";
325 let DecoderMethod = "DecodeT2BROperand";
328 // FIXME: get rid of this one?
329 def uncondbrtarget : Operand<OtherVT> {
330 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
331 let OperandType = "OPERAND_PCREL";
334 // Branch target for ARM. Handles conditional/unconditional
335 def br_target : Operand<OtherVT> {
336 let EncoderMethod = "getARMBranchTargetOpValue";
337 let OperandType = "OPERAND_PCREL";
341 // FIXME: rename bltarget to t2_bl_target?
342 def bltarget : Operand<i32> {
343 // Encoded the same as branch targets.
344 let EncoderMethod = "getBranchTargetOpValue";
345 let OperandType = "OPERAND_PCREL";
348 // Call target for ARM. Handles conditional/unconditional
349 // FIXME: rename bl_target to t2_bltarget?
350 def bl_target : Operand<i32> {
351 // Encoded the same as branch targets.
352 let EncoderMethod = "getARMBranchTargetOpValue";
353 let OperandType = "OPERAND_PCREL";
356 def blx_target : Operand<i32> {
357 // Encoded the same as branch targets.
358 let EncoderMethod = "getARMBLXTargetOpValue";
359 let OperandType = "OPERAND_PCREL";
362 // A list of registers separated by comma. Used by load/store multiple.
363 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
364 def reglist : Operand<i32> {
365 let EncoderMethod = "getRegisterListOpValue";
366 let ParserMatchClass = RegListAsmOperand;
367 let PrintMethod = "printRegisterList";
368 let DecoderMethod = "DecodeRegListOperand";
371 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
372 def dpr_reglist : Operand<i32> {
373 let EncoderMethod = "getRegisterListOpValue";
374 let ParserMatchClass = DPRRegListAsmOperand;
375 let PrintMethod = "printRegisterList";
376 let DecoderMethod = "DecodeDPRRegListOperand";
379 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
380 def spr_reglist : Operand<i32> {
381 let EncoderMethod = "getRegisterListOpValue";
382 let ParserMatchClass = SPRRegListAsmOperand;
383 let PrintMethod = "printRegisterList";
384 let DecoderMethod = "DecodeSPRRegListOperand";
387 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
388 def cpinst_operand : Operand<i32> {
389 let PrintMethod = "printCPInstOperand";
393 def pclabel : Operand<i32> {
394 let PrintMethod = "printPCLabel";
397 // ADR instruction labels.
398 def adrlabel : Operand<i32> {
399 let EncoderMethod = "getAdrLabelOpValue";
402 def neon_vcvt_imm32 : Operand<i32> {
403 let EncoderMethod = "getNEONVcvtImm32OpValue";
404 let DecoderMethod = "DecodeVCVTImmOperand";
407 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
408 def rot_imm_XFORM: SDNodeXForm<imm, [{
409 switch (N->getZExtValue()){
411 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
412 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
413 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
414 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
417 def RotImmAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseRotImm";
421 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
422 int32_t v = N->getZExtValue();
423 return v == 8 || v == 16 || v == 24; }],
425 let PrintMethod = "printRotImmOperand";
426 let ParserMatchClass = RotImmAsmOperand;
429 // shift_imm: An integer that encodes a shift amount and the type of shift
430 // (asr or lsl). The 6-bit immediate encodes as:
433 // {4-0} imm5 shift amount.
434 // asr #32 encoded as imm5 == 0.
435 def ShifterImmAsmOperand : AsmOperandClass {
436 let Name = "ShifterImm";
437 let ParserMethod = "parseShifterImm";
439 def shift_imm : Operand<i32> {
440 let PrintMethod = "printShiftImmOperand";
441 let ParserMatchClass = ShifterImmAsmOperand;
444 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
445 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
446 def so_reg_reg : Operand<i32>, // reg reg imm
447 ComplexPattern<i32, 3, "SelectRegShifterOperand",
448 [shl, srl, sra, rotr]> {
449 let EncoderMethod = "getSORegRegOpValue";
450 let PrintMethod = "printSORegRegOperand";
451 let DecoderMethod = "DecodeSORegRegOperand";
452 let ParserMatchClass = ShiftedRegAsmOperand;
453 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
456 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
457 def so_reg_imm : Operand<i32>, // reg imm
458 ComplexPattern<i32, 2, "SelectImmShifterOperand",
459 [shl, srl, sra, rotr]> {
460 let EncoderMethod = "getSORegImmOpValue";
461 let PrintMethod = "printSORegImmOperand";
462 let DecoderMethod = "DecodeSORegImmOperand";
463 let ParserMatchClass = ShiftedImmAsmOperand;
464 let MIOperandInfo = (ops GPR, i32imm);
467 // FIXME: Does this need to be distinct from so_reg?
468 def shift_so_reg_reg : Operand<i32>, // reg reg imm
469 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
470 [shl,srl,sra,rotr]> {
471 let EncoderMethod = "getSORegRegOpValue";
472 let PrintMethod = "printSORegRegOperand";
473 let DecoderMethod = "DecodeSORegRegOperand";
474 let MIOperandInfo = (ops GPR, GPR, i32imm);
477 // FIXME: Does this need to be distinct from so_reg?
478 def shift_so_reg_imm : Operand<i32>, // reg reg imm
479 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
480 [shl,srl,sra,rotr]> {
481 let EncoderMethod = "getSORegImmOpValue";
482 let PrintMethod = "printSORegImmOperand";
483 let DecoderMethod = "DecodeSORegImmOperand";
484 let MIOperandInfo = (ops GPR, i32imm);
488 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
489 // 8-bit immediate rotated by an arbitrary number of bits.
490 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
491 def so_imm : Operand<i32>, ImmLeaf<i32, [{
492 return ARM_AM::getSOImmVal(Imm) != -1;
494 let EncoderMethod = "getSOImmOpValue";
495 let ParserMatchClass = SOImmAsmOperand;
496 let DecoderMethod = "DecodeSOImmOperand";
499 // Break so_imm's up into two pieces. This handles immediates with up to 16
500 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
501 // get the first/second pieces.
502 def so_imm2part : PatLeaf<(imm), [{
503 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
506 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
508 def arm_i32imm : PatLeaf<(imm), [{
509 if (Subtarget->hasV6T2Ops())
511 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
514 /// imm0_7 predicate - Immediate in the range [0,7].
515 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
516 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
517 return Imm >= 0 && Imm < 8;
519 let ParserMatchClass = Imm0_7AsmOperand;
522 /// imm0_15 predicate - Immediate in the range [0,15].
523 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
524 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
525 return Imm >= 0 && Imm < 16;
527 let ParserMatchClass = Imm0_15AsmOperand;
530 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
531 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
532 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
533 return Imm >= 0 && Imm < 32;
535 let ParserMatchClass = Imm0_31AsmOperand;
538 /// imm0_255 predicate - Immediate in the range [0,255].
539 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
540 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
541 let ParserMatchClass = Imm0_255AsmOperand;
544 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
545 // a relocatable expression.
547 // FIXME: This really needs a Thumb version separate from the ARM version.
548 // While the range is the same, and can thus use the same match class,
549 // the encoding is different so it should have a different encoder method.
550 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
551 def imm0_65535_expr : Operand<i32> {
552 let EncoderMethod = "getHiLo16ImmOpValue";
553 let ParserMatchClass = Imm0_65535ExprAsmOperand;
556 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
557 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
558 def imm24b : Operand<i32>, ImmLeaf<i32, [{
559 return Imm >= 0 && Imm <= 0xffffff;
561 let ParserMatchClass = Imm24bitAsmOperand;
565 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
567 def BitfieldAsmOperand : AsmOperandClass {
568 let Name = "Bitfield";
569 let ParserMethod = "parseBitfield";
571 def bf_inv_mask_imm : Operand<i32>,
573 return ARM::isBitFieldInvertedMask(N->getZExtValue());
575 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
576 let PrintMethod = "printBitfieldInvMaskImmOperand";
577 let DecoderMethod = "DecodeBitfieldMaskOperand";
578 let ParserMatchClass = BitfieldAsmOperand;
581 def imm1_32_XFORM: SDNodeXForm<imm, [{
582 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
584 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
585 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
586 uint64_t Imm = N->getZExtValue();
587 return Imm > 0 && Imm <= 32;
590 let PrintMethod = "printImmPlusOneOperand";
591 let ParserMatchClass = Imm1_32AsmOperand;
594 def imm1_16_XFORM: SDNodeXForm<imm, [{
595 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
597 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
598 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
600 let PrintMethod = "printImmPlusOneOperand";
601 let ParserMatchClass = Imm1_16AsmOperand;
604 // Define ARM specific addressing modes.
605 // addrmode_imm12 := reg +/- imm12
607 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
608 def addrmode_imm12 : Operand<i32>,
609 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
610 // 12-bit immediate operand. Note that instructions using this encode
611 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
612 // immediate values are as normal.
614 let EncoderMethod = "getAddrModeImm12OpValue";
615 let PrintMethod = "printAddrModeImm12Operand";
616 let DecoderMethod = "DecodeAddrModeImm12Operand";
617 let ParserMatchClass = MemImm12OffsetAsmOperand;
618 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
620 // ldst_so_reg := reg +/- reg shop imm
622 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
623 def ldst_so_reg : Operand<i32>,
624 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
625 let EncoderMethod = "getLdStSORegOpValue";
626 // FIXME: Simplify the printer
627 let PrintMethod = "printAddrMode2Operand";
628 let DecoderMethod = "DecodeSORegMemOperand";
629 let ParserMatchClass = MemRegOffsetAsmOperand;
630 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
633 // postidx_imm8 := +/- [0,255]
636 // {8} 1 is imm8 is non-negative. 0 otherwise.
637 // {7-0} [0,255] imm8 value.
638 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
639 def postidx_imm8 : Operand<i32> {
640 let PrintMethod = "printPostIdxImm8Operand";
641 let ParserMatchClass = PostIdxImm8AsmOperand;
642 let MIOperandInfo = (ops i32imm);
645 // postidx_imm8s4 := +/- [0,1020]
648 // {8} 1 is imm8 is non-negative. 0 otherwise.
649 // {7-0} [0,255] imm8 value, scaled by 4.
650 def postidx_imm8s4 : Operand<i32> {
651 let PrintMethod = "printPostIdxImm8s4Operand";
652 let MIOperandInfo = (ops i32imm);
656 // postidx_reg := +/- reg
658 def PostIdxRegAsmOperand : AsmOperandClass {
659 let Name = "PostIdxReg";
660 let ParserMethod = "parsePostIdxReg";
662 def postidx_reg : Operand<i32> {
663 let EncoderMethod = "getPostIdxRegOpValue";
664 let DecoderMethod = "DecodePostIdxReg";
665 let PrintMethod = "printPostIdxRegOperand";
666 let ParserMatchClass = PostIdxRegAsmOperand;
667 let MIOperandInfo = (ops GPR, i32imm);
671 // addrmode2 := reg +/- imm12
672 // := reg +/- reg shop imm
674 // FIXME: addrmode2 should be refactored the rest of the way to always
675 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
676 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
677 def addrmode2 : Operand<i32>,
678 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
679 let EncoderMethod = "getAddrMode2OpValue";
680 let PrintMethod = "printAddrMode2Operand";
681 let ParserMatchClass = AddrMode2AsmOperand;
682 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
685 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
686 let Name = "PostIdxRegShifted";
687 let ParserMethod = "parsePostIdxReg";
689 def am2offset_reg : Operand<i32>,
690 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
691 [], [SDNPWantRoot]> {
692 let EncoderMethod = "getAddrMode2OffsetOpValue";
693 let PrintMethod = "printAddrMode2OffsetOperand";
694 // When using this for assembly, it's always as a post-index offset.
695 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
696 let MIOperandInfo = (ops GPR, i32imm);
699 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
700 // the GPR is purely vestigal at this point.
701 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
702 def am2offset_imm : Operand<i32>,
703 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
704 [], [SDNPWantRoot]> {
705 let EncoderMethod = "getAddrMode2OffsetOpValue";
706 let PrintMethod = "printAddrMode2OffsetOperand";
707 let ParserMatchClass = AM2OffsetImmAsmOperand;
708 let MIOperandInfo = (ops GPR, i32imm);
712 // addrmode3 := reg +/- reg
713 // addrmode3 := reg +/- imm8
715 // FIXME: split into imm vs. reg versions.
716 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
717 def addrmode3 : Operand<i32>,
718 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
719 let EncoderMethod = "getAddrMode3OpValue";
720 let PrintMethod = "printAddrMode3Operand";
721 let ParserMatchClass = AddrMode3AsmOperand;
722 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
725 // FIXME: split into imm vs. reg versions.
726 // FIXME: parser method to handle +/- register.
727 def AM3OffsetAsmOperand : AsmOperandClass {
728 let Name = "AM3Offset";
729 let ParserMethod = "parseAM3Offset";
731 def am3offset : Operand<i32>,
732 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
733 [], [SDNPWantRoot]> {
734 let EncoderMethod = "getAddrMode3OffsetOpValue";
735 let PrintMethod = "printAddrMode3OffsetOperand";
736 let ParserMatchClass = AM3OffsetAsmOperand;
737 let MIOperandInfo = (ops GPR, i32imm);
740 // ldstm_mode := {ia, ib, da, db}
742 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
743 let EncoderMethod = "getLdStmModeOpValue";
744 let PrintMethod = "printLdStmModeOperand";
747 // addrmode5 := reg +/- imm8*4
749 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
750 def addrmode5 : Operand<i32>,
751 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
752 let PrintMethod = "printAddrMode5Operand";
753 let EncoderMethod = "getAddrMode5OpValue";
754 let DecoderMethod = "DecodeAddrMode5Operand";
755 let ParserMatchClass = AddrMode5AsmOperand;
756 let MIOperandInfo = (ops GPR:$base, i32imm);
759 // addrmode6 := reg with optional alignment
761 def addrmode6 : Operand<i32>,
762 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
763 let PrintMethod = "printAddrMode6Operand";
764 let MIOperandInfo = (ops GPR:$addr, i32imm);
765 let EncoderMethod = "getAddrMode6AddressOpValue";
766 let DecoderMethod = "DecodeAddrMode6Operand";
769 def am6offset : Operand<i32>,
770 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
771 [], [SDNPWantRoot]> {
772 let PrintMethod = "printAddrMode6OffsetOperand";
773 let MIOperandInfo = (ops GPR);
774 let EncoderMethod = "getAddrMode6OffsetOpValue";
775 let DecoderMethod = "DecodeGPRRegisterClass";
778 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
779 // (single element from one lane) for size 32.
780 def addrmode6oneL32 : Operand<i32>,
781 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
782 let PrintMethod = "printAddrMode6Operand";
783 let MIOperandInfo = (ops GPR:$addr, i32imm);
784 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
787 // Special version of addrmode6 to handle alignment encoding for VLD-dup
788 // instructions, specifically VLD4-dup.
789 def addrmode6dup : Operand<i32>,
790 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
791 let PrintMethod = "printAddrMode6Operand";
792 let MIOperandInfo = (ops GPR:$addr, i32imm);
793 let EncoderMethod = "getAddrMode6DupAddressOpValue";
796 // addrmodepc := pc + reg
798 def addrmodepc : Operand<i32>,
799 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
800 let PrintMethod = "printAddrModePCOperand";
801 let MIOperandInfo = (ops GPR, i32imm);
804 // addr_offset_none := reg
806 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
807 def addr_offset_none : Operand<i32>,
808 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
809 let PrintMethod = "printAddrMode7Operand";
810 let DecoderMethod = "DecodeAddrMode7Operand";
811 let ParserMatchClass = MemNoOffsetAsmOperand;
812 let MIOperandInfo = (ops GPR:$base);
815 def nohash_imm : Operand<i32> {
816 let PrintMethod = "printNoHashImmediate";
819 def CoprocNumAsmOperand : AsmOperandClass {
820 let Name = "CoprocNum";
821 let ParserMethod = "parseCoprocNumOperand";
823 def p_imm : Operand<i32> {
824 let PrintMethod = "printPImmediate";
825 let ParserMatchClass = CoprocNumAsmOperand;
826 let DecoderMethod = "DecodeCoprocessor";
829 def CoprocRegAsmOperand : AsmOperandClass {
830 let Name = "CoprocReg";
831 let ParserMethod = "parseCoprocRegOperand";
833 def c_imm : Operand<i32> {
834 let PrintMethod = "printCImmediate";
835 let ParserMatchClass = CoprocRegAsmOperand;
838 //===----------------------------------------------------------------------===//
840 include "ARMInstrFormats.td"
842 //===----------------------------------------------------------------------===//
843 // Multiclass helpers...
846 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
847 /// binop that produces a value.
848 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
849 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
850 PatFrag opnode, string baseOpc, bit Commutable = 0> {
851 // The register-immediate version is re-materializable. This is useful
852 // in particular for taking the address of a local.
853 let isReMaterializable = 1 in {
854 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
855 iii, opc, "\t$Rd, $Rn, $imm",
856 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
861 let Inst{19-16} = Rn;
862 let Inst{15-12} = Rd;
863 let Inst{11-0} = imm;
866 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
867 iir, opc, "\t$Rd, $Rn, $Rm",
868 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
873 let isCommutable = Commutable;
874 let Inst{19-16} = Rn;
875 let Inst{15-12} = Rd;
876 let Inst{11-4} = 0b00000000;
880 def rsi : AsI1<opcod, (outs GPR:$Rd),
881 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
882 iis, opc, "\t$Rd, $Rn, $shift",
883 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
888 let Inst{19-16} = Rn;
889 let Inst{15-12} = Rd;
890 let Inst{11-5} = shift{11-5};
892 let Inst{3-0} = shift{3-0};
895 def rsr : AsI1<opcod, (outs GPR:$Rd),
896 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
897 iis, opc, "\t$Rd, $Rn, $shift",
898 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
903 let Inst{19-16} = Rn;
904 let Inst{15-12} = Rd;
905 let Inst{11-8} = shift{11-8};
907 let Inst{6-5} = shift{6-5};
909 let Inst{3-0} = shift{3-0};
912 // Assembly aliases for optional destination operand when it's the same
913 // as the source operand.
914 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
915 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
916 so_imm:$imm, pred:$p,
919 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
920 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
924 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
925 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
926 so_reg_imm:$shift, pred:$p,
929 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
930 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
931 so_reg_reg:$shift, pred:$p,
937 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
938 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
939 /// it is equivalent to the AsI1_bin_irs counterpart.
940 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
941 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
942 PatFrag opnode, string baseOpc, bit Commutable = 0> {
943 // The register-immediate version is re-materializable. This is useful
944 // in particular for taking the address of a local.
945 let isReMaterializable = 1 in {
946 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
947 iii, opc, "\t$Rd, $Rn, $imm",
948 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
953 let Inst{19-16} = Rn;
954 let Inst{15-12} = Rd;
955 let Inst{11-0} = imm;
958 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
959 iir, opc, "\t$Rd, $Rn, $Rm",
960 [/* pattern left blank */]> {
964 let Inst{11-4} = 0b00000000;
967 let Inst{15-12} = Rd;
968 let Inst{19-16} = Rn;
971 def rsi : AsI1<opcod, (outs GPR:$Rd),
972 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
973 iis, opc, "\t$Rd, $Rn, $shift",
974 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
979 let Inst{19-16} = Rn;
980 let Inst{15-12} = Rd;
981 let Inst{11-5} = shift{11-5};
983 let Inst{3-0} = shift{3-0};
986 def rsr : AsI1<opcod, (outs GPR:$Rd),
987 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
988 iis, opc, "\t$Rd, $Rn, $shift",
989 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
994 let Inst{19-16} = Rn;
995 let Inst{15-12} = Rd;
996 let Inst{11-8} = shift{11-8};
998 let Inst{6-5} = shift{6-5};
1000 let Inst{3-0} = shift{3-0};
1003 // Assembly aliases for optional destination operand when it's the same
1004 // as the source operand.
1005 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1006 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1007 so_imm:$imm, pred:$p,
1010 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1011 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1015 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1016 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1017 so_reg_imm:$shift, pred:$p,
1020 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1021 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1022 so_reg_reg:$shift, pred:$p,
1028 /// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
1029 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
1030 multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
1031 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1032 PatFrag opnode, bit Commutable = 0> {
1033 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1034 iii, opc, "\t$Rd, $Rn, $imm",
1035 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]> {
1040 let Inst{19-16} = Rn;
1041 let Inst{15-12} = Rd;
1042 let Inst{11-0} = imm;
1045 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1046 iir, opc, "\t$Rd, $Rn, $Rm",
1047 [/* pattern left blank */]> {
1051 let Inst{11-4} = 0b00000000;
1054 let Inst{15-12} = Rd;
1055 let Inst{19-16} = Rn;
1058 def rsi : AsI1<opcod, (outs GPR:$Rd),
1059 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1060 iis, opc, "\t$Rd, $Rn, $shift",
1061 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1066 let Inst{19-16} = Rn;
1067 let Inst{15-12} = Rd;
1068 let Inst{11-5} = shift{11-5};
1070 let Inst{3-0} = shift{3-0};
1073 def rsr : AsI1<opcod, (outs GPR:$Rd),
1074 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1075 iis, opc, "\t$Rd, $Rn, $shift",
1076 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1081 let Inst{19-16} = Rn;
1082 let Inst{15-12} = Rd;
1083 let Inst{11-8} = shift{11-8};
1085 let Inst{6-5} = shift{6-5};
1087 let Inst{3-0} = shift{3-0};
1092 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1093 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
1094 multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
1095 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1096 PatFrag opnode, bit Commutable = 0> {
1097 let isReMaterializable = 1 in {
1098 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1099 iii, opc, "\t$Rd, $Rn, $imm",
1100 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> {
1105 let Inst{19-16} = Rn;
1106 let Inst{15-12} = Rd;
1107 let Inst{11-0} = imm;
1110 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1111 iir, opc, "\t$Rd, $Rn, $Rm",
1112 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1116 let isCommutable = Commutable;
1118 let Inst{19-16} = Rn;
1119 let Inst{15-12} = Rd;
1120 let Inst{11-4} = 0b00000000;
1123 def rsi : AsI1<opcod, (outs GPR:$Rd),
1124 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1125 iis, opc, "\t$Rd, $Rn, $shift",
1126 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1131 let Inst{19-16} = Rn;
1132 let Inst{15-12} = Rd;
1133 let Inst{11-5} = shift{11-5};
1135 let Inst{3-0} = shift{3-0};
1138 def rsr : AsI1<opcod, (outs GPR:$Rd),
1139 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1140 iis, opc, "\t$Rd, $Rn, $shift",
1141 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1147 let Inst{19-16} = Rn;
1148 let Inst{15-12} = Rd;
1149 let Inst{11-8} = shift{11-8};
1151 let Inst{6-5} = shift{6-5};
1153 let Inst{3-0} = shift{3-0};
1158 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1159 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1160 /// a explicit result, only implicitly set CPSR.
1161 let isCompare = 1, Defs = [CPSR] in {
1162 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1163 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1164 PatFrag opnode, bit Commutable = 0> {
1165 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1167 [(opnode GPR:$Rn, so_imm:$imm)]> {
1172 let Inst{19-16} = Rn;
1173 let Inst{15-12} = 0b0000;
1174 let Inst{11-0} = imm;
1176 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1178 [(opnode GPR:$Rn, GPR:$Rm)]> {
1181 let isCommutable = Commutable;
1184 let Inst{19-16} = Rn;
1185 let Inst{15-12} = 0b0000;
1186 let Inst{11-4} = 0b00000000;
1189 def rsi : AI1<opcod, (outs),
1190 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1191 opc, "\t$Rn, $shift",
1192 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1197 let Inst{19-16} = Rn;
1198 let Inst{15-12} = 0b0000;
1199 let Inst{11-5} = shift{11-5};
1201 let Inst{3-0} = shift{3-0};
1203 def rsr : AI1<opcod, (outs),
1204 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1205 opc, "\t$Rn, $shift",
1206 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1211 let Inst{19-16} = Rn;
1212 let Inst{15-12} = 0b0000;
1213 let Inst{11-8} = shift{11-8};
1215 let Inst{6-5} = shift{6-5};
1217 let Inst{3-0} = shift{3-0};
1223 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1224 /// register and one whose operand is a register rotated by 8/16/24.
1225 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1226 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1227 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1228 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1229 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1230 Requires<[IsARM, HasV6]> {
1234 let Inst{19-16} = 0b1111;
1235 let Inst{15-12} = Rd;
1236 let Inst{11-10} = rot;
1240 class AI_ext_rrot_np<bits<8> opcod, string opc>
1241 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1242 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1243 Requires<[IsARM, HasV6]> {
1245 let Inst{19-16} = 0b1111;
1246 let Inst{11-10} = rot;
1249 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1250 /// register and one whose operand is a register rotated by 8/16/24.
1251 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1252 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1253 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1254 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1255 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1256 Requires<[IsARM, HasV6]> {
1261 let Inst{19-16} = Rn;
1262 let Inst{15-12} = Rd;
1263 let Inst{11-10} = rot;
1264 let Inst{9-4} = 0b000111;
1268 class AI_exta_rrot_np<bits<8> opcod, string opc>
1269 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1270 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1271 Requires<[IsARM, HasV6]> {
1274 let Inst{19-16} = Rn;
1275 let Inst{11-10} = rot;
1278 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1279 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1280 string baseOpc, bit Commutable = 0> {
1281 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1282 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1283 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1284 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1290 let Inst{15-12} = Rd;
1291 let Inst{19-16} = Rn;
1292 let Inst{11-0} = imm;
1294 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1295 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1296 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1301 let Inst{11-4} = 0b00000000;
1303 let isCommutable = Commutable;
1305 let Inst{15-12} = Rd;
1306 let Inst{19-16} = Rn;
1308 def rsi : AsI1<opcod, (outs GPR:$Rd),
1309 (ins GPR:$Rn, so_reg_imm:$shift),
1310 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1311 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1317 let Inst{19-16} = Rn;
1318 let Inst{15-12} = Rd;
1319 let Inst{11-5} = shift{11-5};
1321 let Inst{3-0} = shift{3-0};
1323 def rsr : AsI1<opcod, (outs GPR:$Rd),
1324 (ins GPR:$Rn, so_reg_reg:$shift),
1325 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1326 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1332 let Inst{19-16} = Rn;
1333 let Inst{15-12} = Rd;
1334 let Inst{11-8} = shift{11-8};
1336 let Inst{6-5} = shift{6-5};
1338 let Inst{3-0} = shift{3-0};
1342 // Assembly aliases for optional destination operand when it's the same
1343 // as the source operand.
1344 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1345 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1346 so_imm:$imm, pred:$p,
1349 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1350 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1354 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1355 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1356 so_reg_imm:$shift, pred:$p,
1359 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1360 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1361 so_reg_reg:$shift, pred:$p,
1366 /// AI1_rsc_irs - Define instructions and patterns for rsc
1367 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1369 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1370 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1371 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1372 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1378 let Inst{15-12} = Rd;
1379 let Inst{19-16} = Rn;
1380 let Inst{11-0} = imm;
1382 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1383 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1384 [/* pattern left blank */]> {
1388 let Inst{11-4} = 0b00000000;
1391 let Inst{15-12} = Rd;
1392 let Inst{19-16} = Rn;
1394 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1395 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1396 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1402 let Inst{19-16} = Rn;
1403 let Inst{15-12} = Rd;
1404 let Inst{11-5} = shift{11-5};
1406 let Inst{3-0} = shift{3-0};
1408 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1409 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1410 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1416 let Inst{19-16} = Rn;
1417 let Inst{15-12} = Rd;
1418 let Inst{11-8} = shift{11-8};
1420 let Inst{6-5} = shift{6-5};
1422 let Inst{3-0} = shift{3-0};
1426 // Assembly aliases for optional destination operand when it's the same
1427 // as the source operand.
1428 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1429 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1430 so_imm:$imm, pred:$p,
1433 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1434 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1438 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1439 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1440 so_reg_imm:$shift, pred:$p,
1443 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1444 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1445 so_reg_reg:$shift, pred:$p,
1450 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1451 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1452 InstrItinClass iir, PatFrag opnode> {
1453 // Note: We use the complex addrmode_imm12 rather than just an input
1454 // GPR and a constrained immediate so that we can use this to match
1455 // frame index references and avoid matching constant pool references.
1456 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1457 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1458 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1461 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1462 let Inst{19-16} = addr{16-13}; // Rn
1463 let Inst{15-12} = Rt;
1464 let Inst{11-0} = addr{11-0}; // imm12
1466 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1467 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1468 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1471 let shift{4} = 0; // Inst{4} = 0
1472 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1473 let Inst{19-16} = shift{16-13}; // Rn
1474 let Inst{15-12} = Rt;
1475 let Inst{11-0} = shift{11-0};
1480 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1481 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1482 InstrItinClass iir, PatFrag opnode> {
1483 // Note: We use the complex addrmode_imm12 rather than just an input
1484 // GPR and a constrained immediate so that we can use this to match
1485 // frame index references and avoid matching constant pool references.
1486 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1487 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1488 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1491 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1492 let Inst{19-16} = addr{16-13}; // Rn
1493 let Inst{15-12} = Rt;
1494 let Inst{11-0} = addr{11-0}; // imm12
1496 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1497 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1498 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1501 let shift{4} = 0; // Inst{4} = 0
1502 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1503 let Inst{19-16} = shift{16-13}; // Rn
1504 let Inst{15-12} = Rt;
1505 let Inst{11-0} = shift{11-0};
1511 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1512 InstrItinClass iir, PatFrag opnode> {
1513 // Note: We use the complex addrmode_imm12 rather than just an input
1514 // GPR and a constrained immediate so that we can use this to match
1515 // frame index references and avoid matching constant pool references.
1516 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1517 (ins GPR:$Rt, addrmode_imm12:$addr),
1518 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1519 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1522 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1523 let Inst{19-16} = addr{16-13}; // Rn
1524 let Inst{15-12} = Rt;
1525 let Inst{11-0} = addr{11-0}; // imm12
1527 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1528 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1529 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1532 let shift{4} = 0; // Inst{4} = 0
1533 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1534 let Inst{19-16} = shift{16-13}; // Rn
1535 let Inst{15-12} = Rt;
1536 let Inst{11-0} = shift{11-0};
1540 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1541 InstrItinClass iir, PatFrag opnode> {
1542 // Note: We use the complex addrmode_imm12 rather than just an input
1543 // GPR and a constrained immediate so that we can use this to match
1544 // frame index references and avoid matching constant pool references.
1545 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1546 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1547 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1548 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1551 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1552 let Inst{19-16} = addr{16-13}; // Rn
1553 let Inst{15-12} = Rt;
1554 let Inst{11-0} = addr{11-0}; // imm12
1556 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1557 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1558 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1561 let shift{4} = 0; // Inst{4} = 0
1562 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1563 let Inst{19-16} = shift{16-13}; // Rn
1564 let Inst{15-12} = Rt;
1565 let Inst{11-0} = shift{11-0};
1570 //===----------------------------------------------------------------------===//
1572 //===----------------------------------------------------------------------===//
1574 //===----------------------------------------------------------------------===//
1575 // Miscellaneous Instructions.
1578 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1579 /// the function. The first operand is the ID# for this instruction, the second
1580 /// is the index into the MachineConstantPool that this is, the third is the
1581 /// size in bytes of this constant pool entry.
1582 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1583 def CONSTPOOL_ENTRY :
1584 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1585 i32imm:$size), NoItinerary, []>;
1587 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1588 // from removing one half of the matched pairs. That breaks PEI, which assumes
1589 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1590 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1591 def ADJCALLSTACKUP :
1592 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1593 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1595 def ADJCALLSTACKDOWN :
1596 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1597 [(ARMcallseq_start timm:$amt)]>;
1600 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1601 // (These psuedos use a hand-written selection code).
1602 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1603 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1604 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1606 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1607 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1609 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1610 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1612 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1613 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1615 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1616 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1618 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1619 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1621 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1622 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1624 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1625 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1626 GPR:$set1, GPR:$set2),
1630 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1631 Requires<[IsARM, HasV6T2]> {
1632 let Inst{27-16} = 0b001100100000;
1633 let Inst{15-8} = 0b11110000;
1634 let Inst{7-0} = 0b00000000;
1637 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1638 Requires<[IsARM, HasV6T2]> {
1639 let Inst{27-16} = 0b001100100000;
1640 let Inst{15-8} = 0b11110000;
1641 let Inst{7-0} = 0b00000001;
1644 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1645 Requires<[IsARM, HasV6T2]> {
1646 let Inst{27-16} = 0b001100100000;
1647 let Inst{15-8} = 0b11110000;
1648 let Inst{7-0} = 0b00000010;
1651 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1652 Requires<[IsARM, HasV6T2]> {
1653 let Inst{27-16} = 0b001100100000;
1654 let Inst{15-8} = 0b11110000;
1655 let Inst{7-0} = 0b00000011;
1658 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1659 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1664 let Inst{15-12} = Rd;
1665 let Inst{19-16} = Rn;
1666 let Inst{27-20} = 0b01101000;
1667 let Inst{7-4} = 0b1011;
1668 let Inst{11-8} = 0b1111;
1671 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1672 []>, Requires<[IsARM, HasV6T2]> {
1673 let Inst{27-16} = 0b001100100000;
1674 let Inst{15-8} = 0b11110000;
1675 let Inst{7-0} = 0b00000100;
1678 // The i32imm operand $val can be used by a debugger to store more information
1679 // about the breakpoint.
1680 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1681 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1683 let Inst{3-0} = val{3-0};
1684 let Inst{19-8} = val{15-4};
1685 let Inst{27-20} = 0b00010010;
1686 let Inst{7-4} = 0b0111;
1689 // Change Processor State
1690 // FIXME: We should use InstAlias to handle the optional operands.
1691 class CPS<dag iops, string asm_ops>
1692 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1693 []>, Requires<[IsARM]> {
1699 let Inst{31-28} = 0b1111;
1700 let Inst{27-20} = 0b00010000;
1701 let Inst{19-18} = imod;
1702 let Inst{17} = M; // Enabled if mode is set;
1704 let Inst{8-6} = iflags;
1706 let Inst{4-0} = mode;
1709 let DecoderMethod = "DecodeCPSInstruction" in {
1711 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1712 "$imod\t$iflags, $mode">;
1713 let mode = 0, M = 0 in
1714 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1716 let imod = 0, iflags = 0, M = 1 in
1717 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1720 // Preload signals the memory system of possible future data/instruction access.
1721 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1723 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1724 !strconcat(opc, "\t$addr"),
1725 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1728 let Inst{31-26} = 0b111101;
1729 let Inst{25} = 0; // 0 for immediate form
1730 let Inst{24} = data;
1731 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1732 let Inst{22} = read;
1733 let Inst{21-20} = 0b01;
1734 let Inst{19-16} = addr{16-13}; // Rn
1735 let Inst{15-12} = 0b1111;
1736 let Inst{11-0} = addr{11-0}; // imm12
1739 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1740 !strconcat(opc, "\t$shift"),
1741 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1743 let Inst{31-26} = 0b111101;
1744 let Inst{25} = 1; // 1 for register form
1745 let Inst{24} = data;
1746 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1747 let Inst{22} = read;
1748 let Inst{21-20} = 0b01;
1749 let Inst{19-16} = shift{16-13}; // Rn
1750 let Inst{15-12} = 0b1111;
1751 let Inst{11-0} = shift{11-0};
1756 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1757 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1758 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1760 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1761 "setend\t$end", []>, Requires<[IsARM]> {
1763 let Inst{31-10} = 0b1111000100000001000000;
1768 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1769 []>, Requires<[IsARM, HasV7]> {
1771 let Inst{27-4} = 0b001100100000111100001111;
1772 let Inst{3-0} = opt;
1775 // A5.4 Permanently UNDEFINED instructions.
1776 let isBarrier = 1, isTerminator = 1 in
1777 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1780 let Inst = 0xe7ffdefe;
1783 // Address computation and loads and stores in PIC mode.
1784 let isNotDuplicable = 1 in {
1785 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1787 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1789 let AddedComplexity = 10 in {
1790 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1792 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1794 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1796 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1798 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1800 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1802 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1804 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1806 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1808 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1810 let AddedComplexity = 10 in {
1811 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1812 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1814 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1815 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1816 addrmodepc:$addr)]>;
1818 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1819 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1821 } // isNotDuplicable = 1
1824 // LEApcrel - Load a pc-relative address into a register without offending the
1826 let neverHasSideEffects = 1, isReMaterializable = 1 in
1827 // The 'adr' mnemonic encodes differently if the label is before or after
1828 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1829 // know until then which form of the instruction will be used.
1830 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1831 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1834 let Inst{27-25} = 0b001;
1836 let Inst{23-22} = label{13-12};
1839 let Inst{19-16} = 0b1111;
1840 let Inst{15-12} = Rd;
1841 let Inst{11-0} = label{11-0};
1843 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1846 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1847 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1850 //===----------------------------------------------------------------------===//
1851 // Control Flow Instructions.
1854 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1856 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1857 "bx", "\tlr", [(ARMretflag)]>,
1858 Requires<[IsARM, HasV4T]> {
1859 let Inst{27-0} = 0b0001001011111111111100011110;
1863 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1864 "mov", "\tpc, lr", [(ARMretflag)]>,
1865 Requires<[IsARM, NoV4T]> {
1866 let Inst{27-0} = 0b0001101000001111000000001110;
1870 // Indirect branches
1871 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1873 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1874 [(brind GPR:$dst)]>,
1875 Requires<[IsARM, HasV4T]> {
1877 let Inst{31-4} = 0b1110000100101111111111110001;
1878 let Inst{3-0} = dst;
1881 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1882 "bx", "\t$dst", [/* pattern left blank */]>,
1883 Requires<[IsARM, HasV4T]> {
1885 let Inst{27-4} = 0b000100101111111111110001;
1886 let Inst{3-0} = dst;
1890 // All calls clobber the non-callee saved registers. SP is marked as
1891 // a use to prevent stack-pointer assignments that appear immediately
1892 // before calls from potentially appearing dead.
1894 // On non-Darwin platforms R9 is callee-saved.
1895 // FIXME: Do we really need a non-predicated version? If so, it should
1896 // at least be a pseudo instruction expanding to the predicated version
1897 // at MC lowering time.
1898 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1900 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1901 IIC_Br, "bl\t$func",
1902 [(ARMcall tglobaladdr:$func)]>,
1903 Requires<[IsARM, IsNotDarwin]> {
1904 let Inst{31-28} = 0b1110;
1906 let Inst{23-0} = func;
1907 let DecoderMethod = "DecodeBranchImmInstruction";
1910 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1911 IIC_Br, "bl", "\t$func",
1912 [(ARMcall_pred tglobaladdr:$func)]>,
1913 Requires<[IsARM, IsNotDarwin]> {
1915 let Inst{23-0} = func;
1916 let DecoderMethod = "DecodeBranchImmInstruction";
1920 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1921 IIC_Br, "blx\t$func",
1922 [(ARMcall GPR:$func)]>,
1923 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1925 let Inst{31-4} = 0b1110000100101111111111110011;
1926 let Inst{3-0} = func;
1929 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1930 IIC_Br, "blx", "\t$func",
1931 [(ARMcall_pred GPR:$func)]>,
1932 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1934 let Inst{27-4} = 0b000100101111111111110011;
1935 let Inst{3-0} = func;
1939 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1940 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1941 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1942 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1945 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1946 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1947 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1951 // On Darwin R9 is call-clobbered.
1952 // R7 is marked as a use to prevent frame-pointer assignments from being
1953 // moved above / below calls.
1954 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1955 Uses = [R7, SP] in {
1956 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1958 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1959 Requires<[IsARM, IsDarwin]>;
1961 def BLr9_pred : ARMPseudoExpand<(outs),
1962 (ins bl_target:$func, pred:$p, variable_ops),
1964 [(ARMcall_pred tglobaladdr:$func)],
1965 (BL_pred bl_target:$func, pred:$p)>,
1966 Requires<[IsARM, IsDarwin]>;
1969 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1971 [(ARMcall GPR:$func)],
1973 Requires<[IsARM, HasV5T, IsDarwin]>;
1975 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1977 [(ARMcall_pred GPR:$func)],
1978 (BLX_pred GPR:$func, pred:$p)>,
1979 Requires<[IsARM, HasV5T, IsDarwin]>;
1982 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1983 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1984 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1985 Requires<[IsARM, HasV4T, IsDarwin]>;
1988 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1989 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1990 Requires<[IsARM, NoV4T, IsDarwin]>;
1993 let isBranch = 1, isTerminator = 1 in {
1994 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1995 // a two-value operand where a dag node expects two operands. :(
1996 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1997 IIC_Br, "b", "\t$target",
1998 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2000 let Inst{23-0} = target;
2001 let DecoderMethod = "DecodeBranchImmInstruction";
2004 let isBarrier = 1 in {
2005 // B is "predicable" since it's just a Bcc with an 'always' condition.
2006 let isPredicable = 1 in
2007 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2008 // should be sufficient.
2009 // FIXME: Is B really a Barrier? That doesn't seem right.
2010 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2011 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2013 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2014 def BR_JTr : ARMPseudoInst<(outs),
2015 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2017 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2018 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2019 // into i12 and rs suffixed versions.
2020 def BR_JTm : ARMPseudoInst<(outs),
2021 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2023 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2025 def BR_JTadd : ARMPseudoInst<(outs),
2026 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2028 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2030 } // isNotDuplicable = 1, isIndirectBranch = 1
2036 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2037 "blx\t$target", []>,
2038 Requires<[IsARM, HasV5T]> {
2039 let Inst{31-25} = 0b1111101;
2041 let Inst{23-0} = target{24-1};
2042 let Inst{24} = target{0};
2045 // Branch and Exchange Jazelle
2046 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2047 [/* pattern left blank */]> {
2049 let Inst{23-20} = 0b0010;
2050 let Inst{19-8} = 0xfff;
2051 let Inst{7-4} = 0b0010;
2052 let Inst{3-0} = func;
2057 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2059 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2061 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2062 IIC_Br, []>, Requires<[IsDarwin]>;
2064 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2065 IIC_Br, []>, Requires<[IsDarwin]>;
2067 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2069 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2070 Requires<[IsARM, IsDarwin]>;
2072 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2075 Requires<[IsARM, IsDarwin]>;
2079 // Non-Darwin versions (the difference is R9).
2080 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2082 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2083 IIC_Br, []>, Requires<[IsNotDarwin]>;
2085 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2086 IIC_Br, []>, Requires<[IsNotDarwin]>;
2088 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2090 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2091 Requires<[IsARM, IsNotDarwin]>;
2093 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2096 Requires<[IsARM, IsNotDarwin]>;
2100 // Secure Monitor Call is a system instruction.
2101 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2104 let Inst{23-4} = 0b01100000000000000111;
2105 let Inst{3-0} = opt;
2108 // Supervisor Call (Software Interrupt)
2109 let isCall = 1, Uses = [SP] in {
2110 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2112 let Inst{23-0} = svc;
2116 // Store Return State
2117 class SRSI<bit wb, string asm>
2118 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2119 NoItinerary, asm, "", []> {
2121 let Inst{31-28} = 0b1111;
2122 let Inst{27-25} = 0b100;
2126 let Inst{19-16} = 0b1101; // SP
2127 let Inst{15-5} = 0b00000101000;
2128 let Inst{4-0} = mode;
2131 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2132 let Inst{24-23} = 0;
2134 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2135 let Inst{24-23} = 0;
2137 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2138 let Inst{24-23} = 0b10;
2140 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2141 let Inst{24-23} = 0b10;
2143 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2144 let Inst{24-23} = 0b01;
2146 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2147 let Inst{24-23} = 0b01;
2149 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2150 let Inst{24-23} = 0b11;
2152 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2153 let Inst{24-23} = 0b11;
2156 // Return From Exception
2157 class RFEI<bit wb, string asm>
2158 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2159 NoItinerary, asm, "", []> {
2161 let Inst{31-28} = 0b1111;
2162 let Inst{27-25} = 0b100;
2166 let Inst{19-16} = Rn;
2167 let Inst{15-0} = 0xa00;
2170 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2171 let Inst{24-23} = 0;
2173 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2174 let Inst{24-23} = 0;
2176 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2177 let Inst{24-23} = 0b10;
2179 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2180 let Inst{24-23} = 0b10;
2182 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2183 let Inst{24-23} = 0b01;
2185 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2186 let Inst{24-23} = 0b01;
2188 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2189 let Inst{24-23} = 0b11;
2191 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2192 let Inst{24-23} = 0b11;
2195 //===----------------------------------------------------------------------===//
2196 // Load / store Instructions.
2202 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2203 UnOpFrag<(load node:$Src)>>;
2204 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2205 UnOpFrag<(zextloadi8 node:$Src)>>;
2206 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2207 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2208 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2209 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2211 // Special LDR for loads from non-pc-relative constpools.
2212 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2213 isReMaterializable = 1, isCodeGenOnly = 1 in
2214 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2215 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2219 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2220 let Inst{19-16} = 0b1111;
2221 let Inst{15-12} = Rt;
2222 let Inst{11-0} = addr{11-0}; // imm12
2225 // Loads with zero extension
2226 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2227 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2228 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2230 // Loads with sign extension
2231 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2232 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2233 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2235 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2236 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2237 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2239 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2241 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2242 (ins addrmode3:$addr), LdMiscFrm,
2243 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2244 []>, Requires<[IsARM, HasV5TE]>;
2248 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
2249 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2250 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, itin,
2251 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2254 let Inst{23} = addr{12};
2255 let Inst{19-16} = addr{16-13};
2256 let Inst{11-0} = addr{11-0};
2257 let DecoderMethod = "DecodeLDRPreImm";
2258 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2261 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2262 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, itin,
2263 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2266 let Inst{23} = addr{12};
2267 let Inst{19-16} = addr{16-13};
2268 let Inst{11-0} = addr{11-0};
2270 let DecoderMethod = "DecodeLDRPreReg";
2271 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2274 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2275 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2276 IndexModePost, LdFrm, itin,
2277 opc, "\t$Rt, $addr, $offset",
2278 "$addr.base = $Rn_wb", []> {
2284 let Inst{23} = offset{12};
2285 let Inst{19-16} = addr;
2286 let Inst{11-0} = offset{11-0};
2288 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2291 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2292 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2293 IndexModePost, LdFrm, itin,
2294 opc, "\t$Rt, $addr, $offset",
2295 "$addr.base = $Rn_wb", []> {
2301 let Inst{23} = offset{12};
2302 let Inst{19-16} = addr;
2303 let Inst{11-0} = offset{11-0};
2305 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2310 let mayLoad = 1, neverHasSideEffects = 1 in {
2311 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
2312 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
2315 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2316 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2317 (ins addrmode3:$addr), IndexModePre,
2319 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2321 let Inst{23} = addr{8}; // U bit
2322 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2323 let Inst{19-16} = addr{12-9}; // Rn
2324 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2325 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2326 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2327 let DecoderMethod = "DecodeAddrMode3Instruction";
2329 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2330 (ins addr_offset_none:$addr, am3offset:$offset),
2331 IndexModePost, LdMiscFrm, itin,
2332 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2336 let Inst{23} = offset{8}; // U bit
2337 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2338 let Inst{19-16} = addr;
2339 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2340 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2341 let DecoderMethod = "DecodeAddrMode3Instruction";
2345 let mayLoad = 1, neverHasSideEffects = 1 in {
2346 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2347 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2348 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2349 let hasExtraDefRegAllocReq = 1 in {
2350 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2351 (ins addrmode3:$addr), IndexModePre,
2352 LdMiscFrm, IIC_iLoad_d_ru,
2353 "ldrd", "\t$Rt, $Rt2, $addr!",
2354 "$addr.base = $Rn_wb", []> {
2356 let Inst{23} = addr{8}; // U bit
2357 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2358 let Inst{19-16} = addr{12-9}; // Rn
2359 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2360 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2361 let DecoderMethod = "DecodeAddrMode3Instruction";
2362 let AsmMatchConverter = "cvtLdrdPre";
2364 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2365 (ins addr_offset_none:$addr, am3offset:$offset),
2366 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2367 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2368 "$addr.base = $Rn_wb", []> {
2371 let Inst{23} = offset{8}; // U bit
2372 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2373 let Inst{19-16} = addr;
2374 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2375 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2376 let DecoderMethod = "DecodeAddrMode3Instruction";
2378 } // hasExtraDefRegAllocReq = 1
2379 } // mayLoad = 1, neverHasSideEffects = 1
2381 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2382 let mayLoad = 1, neverHasSideEffects = 1 in {
2383 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2384 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2385 IndexModePost, LdFrm, IIC_iLoad_ru,
2386 "ldrt", "\t$Rt, $addr, $offset",
2387 "$addr.base = $Rn_wb", []> {
2393 let Inst{23} = offset{12};
2394 let Inst{21} = 1; // overwrite
2395 let Inst{19-16} = addr;
2396 let Inst{11-5} = offset{11-5};
2398 let Inst{3-0} = offset{3-0};
2399 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2402 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2403 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2404 IndexModePost, LdFrm, IIC_iLoad_ru,
2405 "ldrt", "\t$Rt, $addr, $offset",
2406 "$addr.base = $Rn_wb", []> {
2412 let Inst{23} = offset{12};
2413 let Inst{21} = 1; // overwrite
2414 let Inst{19-16} = addr;
2415 let Inst{11-0} = offset{11-0};
2416 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2419 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2420 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2421 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2422 "ldrbt", "\t$Rt, $addr, $offset",
2423 "$addr.base = $Rn_wb", []> {
2429 let Inst{23} = offset{12};
2430 let Inst{21} = 1; // overwrite
2431 let Inst{19-16} = addr;
2432 let Inst{11-5} = offset{11-5};
2434 let Inst{3-0} = offset{3-0};
2435 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2438 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2439 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2440 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2441 "ldrbt", "\t$Rt, $addr, $offset",
2442 "$addr.base = $Rn_wb", []> {
2448 let Inst{23} = offset{12};
2449 let Inst{21} = 1; // overwrite
2450 let Inst{19-16} = addr;
2451 let Inst{11-0} = offset{11-0};
2452 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2455 multiclass AI3ldrT<bits<4> op, string opc> {
2456 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2457 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2458 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2459 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2461 let Inst{23} = offset{8};
2463 let Inst{11-8} = offset{7-4};
2464 let Inst{3-0} = offset{3-0};
2465 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2467 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2468 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2469 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2470 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2472 let Inst{23} = Rm{4};
2475 let Inst{3-0} = Rm{3-0};
2476 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2480 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2481 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2482 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2487 // Stores with truncate
2488 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2489 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2490 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2493 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2494 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2495 StMiscFrm, IIC_iStore_d_r,
2496 "strd", "\t$Rt, $src2, $addr", []>,
2497 Requires<[IsARM, HasV5TE]> {
2502 multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
2503 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2504 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2506 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2509 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2510 let Inst{19-16} = addr{16-13}; // Rn
2511 let Inst{11-0} = addr{11-0}; // imm12
2512 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2513 let DecoderMethod = "DecodeSTRPreImm";
2516 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2517 (ins GPR:$Rt, ldst_so_reg:$addr),
2518 IndexModePre, StFrm, itin,
2519 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2522 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2523 let Inst{19-16} = addr{16-13}; // Rn
2524 let Inst{11-0} = addr{11-0};
2525 let Inst{4} = 0; // Inst{4} = 0
2526 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2527 let DecoderMethod = "DecodeSTRPreReg";
2529 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2530 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2531 IndexModePost, StFrm, itin,
2532 opc, "\t$Rt, $addr, $offset",
2533 "$addr.base = $Rn_wb", []> {
2539 let Inst{23} = offset{12};
2540 let Inst{19-16} = addr;
2541 let Inst{11-0} = offset{11-0};
2543 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2546 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2547 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2548 IndexModePost, StFrm, itin,
2549 opc, "\t$Rt, $addr, $offset",
2550 "$addr.base = $Rn_wb", []> {
2556 let Inst{23} = offset{12};
2557 let Inst{19-16} = addr;
2558 let Inst{11-0} = offset{11-0};
2560 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2564 let mayStore = 1, neverHasSideEffects = 1 in {
2565 defm STR : AI2_stridx<0, "str", IIC_iStore_ru>;
2566 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_ru>;
2569 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2570 am2offset_reg:$offset),
2571 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2572 am2offset_reg:$offset)>;
2573 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2574 am2offset_imm:$offset),
2575 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2576 am2offset_imm:$offset)>;
2577 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2578 am2offset_reg:$offset),
2579 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2580 am2offset_reg:$offset)>;
2581 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2582 am2offset_imm:$offset),
2583 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2584 am2offset_imm:$offset)>;
2586 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2587 // put the patterns on the instruction definitions directly as ISel wants
2588 // the address base and offset to be separate operands, not a single
2589 // complex operand like we represent the instructions themselves. The
2590 // pseudos map between the two.
2591 let usesCustomInserter = 1,
2592 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2593 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2594 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2597 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2598 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2599 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2602 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2603 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2604 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2607 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2608 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2609 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2612 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2613 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2614 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2617 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2622 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2623 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2624 StMiscFrm, IIC_iStore_bh_ru,
2625 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2627 let Inst{23} = addr{8}; // U bit
2628 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2629 let Inst{19-16} = addr{12-9}; // Rn
2630 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2631 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2632 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2633 let DecoderMethod = "DecodeAddrMode3Instruction";
2636 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2637 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2638 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2639 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2640 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2641 addr_offset_none:$addr,
2642 am3offset:$offset))]> {
2645 let Inst{23} = offset{8}; // U bit
2646 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2647 let Inst{19-16} = addr;
2648 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2649 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2650 let DecoderMethod = "DecodeAddrMode3Instruction";
2653 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2654 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2655 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2656 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2657 "strd", "\t$Rt, $Rt2, $addr!",
2658 "$addr.base = $Rn_wb", []> {
2660 let Inst{23} = addr{8}; // U bit
2661 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2662 let Inst{19-16} = addr{12-9}; // Rn
2663 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2664 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2665 let DecoderMethod = "DecodeAddrMode3Instruction";
2666 let AsmMatchConverter = "cvtStrdPre";
2669 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2670 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2672 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2673 "strd", "\t$Rt, $Rt2, $addr, $offset",
2674 "$addr.base = $Rn_wb", []> {
2677 let Inst{23} = offset{8}; // U bit
2678 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2679 let Inst{19-16} = addr;
2680 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2681 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2682 let DecoderMethod = "DecodeAddrMode3Instruction";
2684 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2686 // STRT, STRBT, and STRHT
2688 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2689 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2690 IndexModePost, StFrm, IIC_iStore_bh_ru,
2691 "strbt", "\t$Rt, $addr, $offset",
2692 "$addr.base = $Rn_wb", []> {
2698 let Inst{23} = offset{12};
2699 let Inst{21} = 1; // overwrite
2700 let Inst{19-16} = addr;
2701 let Inst{11-5} = offset{11-5};
2703 let Inst{3-0} = offset{3-0};
2704 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2707 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2708 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2709 IndexModePost, StFrm, IIC_iStore_bh_ru,
2710 "strbt", "\t$Rt, $addr, $offset",
2711 "$addr.base = $Rn_wb", []> {
2717 let Inst{23} = offset{12};
2718 let Inst{21} = 1; // overwrite
2719 let Inst{19-16} = addr;
2720 let Inst{11-0} = offset{11-0};
2721 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2724 let mayStore = 1, neverHasSideEffects = 1 in {
2725 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2726 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2727 IndexModePost, StFrm, IIC_iStore_ru,
2728 "strt", "\t$Rt, $addr, $offset",
2729 "$addr.base = $Rn_wb", []> {
2735 let Inst{23} = offset{12};
2736 let Inst{21} = 1; // overwrite
2737 let Inst{19-16} = addr;
2738 let Inst{11-5} = offset{11-5};
2740 let Inst{3-0} = offset{3-0};
2741 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2744 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2745 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2746 IndexModePost, StFrm, IIC_iStore_ru,
2747 "strt", "\t$Rt, $addr, $offset",
2748 "$addr.base = $Rn_wb", []> {
2754 let Inst{23} = offset{12};
2755 let Inst{21} = 1; // overwrite
2756 let Inst{19-16} = addr;
2757 let Inst{11-0} = offset{11-0};
2758 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2763 multiclass AI3strT<bits<4> op, string opc> {
2764 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2765 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2766 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2767 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2769 let Inst{23} = offset{8};
2771 let Inst{11-8} = offset{7-4};
2772 let Inst{3-0} = offset{3-0};
2773 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2775 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2776 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2777 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2778 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2780 let Inst{23} = Rm{4};
2783 let Inst{3-0} = Rm{3-0};
2784 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2789 defm STRHT : AI3strT<0b1011, "strht">;
2792 //===----------------------------------------------------------------------===//
2793 // Load / store multiple Instructions.
2796 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2797 InstrItinClass itin, InstrItinClass itin_upd> {
2798 // IA is the default, so no need for an explicit suffix on the
2799 // mnemonic here. Without it is the cannonical spelling.
2801 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2802 IndexModeNone, f, itin,
2803 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2804 let Inst{24-23} = 0b01; // Increment After
2805 let Inst{21} = 0; // No writeback
2806 let Inst{20} = L_bit;
2809 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2810 IndexModeUpd, f, itin_upd,
2811 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2812 let Inst{24-23} = 0b01; // Increment After
2813 let Inst{21} = 1; // Writeback
2814 let Inst{20} = L_bit;
2816 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2819 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2820 IndexModeNone, f, itin,
2821 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2822 let Inst{24-23} = 0b00; // Decrement After
2823 let Inst{21} = 0; // No writeback
2824 let Inst{20} = L_bit;
2827 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2828 IndexModeUpd, f, itin_upd,
2829 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2830 let Inst{24-23} = 0b00; // Decrement After
2831 let Inst{21} = 1; // Writeback
2832 let Inst{20} = L_bit;
2834 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2837 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2838 IndexModeNone, f, itin,
2839 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2840 let Inst{24-23} = 0b10; // Decrement Before
2841 let Inst{21} = 0; // No writeback
2842 let Inst{20} = L_bit;
2845 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2846 IndexModeUpd, f, itin_upd,
2847 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2848 let Inst{24-23} = 0b10; // Decrement Before
2849 let Inst{21} = 1; // Writeback
2850 let Inst{20} = L_bit;
2852 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2855 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2856 IndexModeNone, f, itin,
2857 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2858 let Inst{24-23} = 0b11; // Increment Before
2859 let Inst{21} = 0; // No writeback
2860 let Inst{20} = L_bit;
2863 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2864 IndexModeUpd, f, itin_upd,
2865 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2866 let Inst{24-23} = 0b11; // Increment Before
2867 let Inst{21} = 1; // Writeback
2868 let Inst{20} = L_bit;
2870 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2874 let neverHasSideEffects = 1 in {
2876 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2877 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2879 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2880 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2882 } // neverHasSideEffects
2884 // FIXME: remove when we have a way to marking a MI with these properties.
2885 // FIXME: Should pc be an implicit operand like PICADD, etc?
2886 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2887 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2888 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2889 reglist:$regs, variable_ops),
2890 4, IIC_iLoad_mBr, [],
2891 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2892 RegConstraint<"$Rn = $wb">;
2894 //===----------------------------------------------------------------------===//
2895 // Move Instructions.
2898 let neverHasSideEffects = 1 in
2899 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2900 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2904 let Inst{19-16} = 0b0000;
2905 let Inst{11-4} = 0b00000000;
2908 let Inst{15-12} = Rd;
2911 // A version for the smaller set of tail call registers.
2912 let neverHasSideEffects = 1 in
2913 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2914 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2918 let Inst{11-4} = 0b00000000;
2921 let Inst{15-12} = Rd;
2924 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2925 DPSoRegRegFrm, IIC_iMOVsr,
2926 "mov", "\t$Rd, $src",
2927 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2930 let Inst{15-12} = Rd;
2931 let Inst{19-16} = 0b0000;
2932 let Inst{11-8} = src{11-8};
2934 let Inst{6-5} = src{6-5};
2936 let Inst{3-0} = src{3-0};
2940 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2941 DPSoRegImmFrm, IIC_iMOVsr,
2942 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2946 let Inst{15-12} = Rd;
2947 let Inst{19-16} = 0b0000;
2948 let Inst{11-5} = src{11-5};
2950 let Inst{3-0} = src{3-0};
2954 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2955 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2956 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2960 let Inst{15-12} = Rd;
2961 let Inst{19-16} = 0b0000;
2962 let Inst{11-0} = imm;
2965 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2966 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2968 "movw", "\t$Rd, $imm",
2969 [(set GPR:$Rd, imm0_65535:$imm)]>,
2970 Requires<[IsARM, HasV6T2]>, UnaryDP {
2973 let Inst{15-12} = Rd;
2974 let Inst{11-0} = imm{11-0};
2975 let Inst{19-16} = imm{15-12};
2980 def : InstAlias<"mov${p} $Rd, $imm",
2981 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2984 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2985 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2987 let Constraints = "$src = $Rd" in {
2988 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2989 (ins GPR:$src, imm0_65535_expr:$imm),
2991 "movt", "\t$Rd, $imm",
2993 (or (and GPR:$src, 0xffff),
2994 lo16AllZero:$imm))]>, UnaryDP,
2995 Requires<[IsARM, HasV6T2]> {
2998 let Inst{15-12} = Rd;
2999 let Inst{11-0} = imm{11-0};
3000 let Inst{19-16} = imm{15-12};
3005 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3006 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3010 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3011 Requires<[IsARM, HasV6T2]>;
3013 let Uses = [CPSR] in
3014 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3015 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3018 // These aren't really mov instructions, but we have to define them this way
3019 // due to flag operands.
3021 let Defs = [CPSR] in {
3022 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3023 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3025 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3026 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3030 //===----------------------------------------------------------------------===//
3031 // Extend Instructions.
3036 def SXTB : AI_ext_rrot<0b01101010,
3037 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3038 def SXTH : AI_ext_rrot<0b01101011,
3039 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3041 def SXTAB : AI_exta_rrot<0b01101010,
3042 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3043 def SXTAH : AI_exta_rrot<0b01101011,
3044 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3046 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3048 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3052 let AddedComplexity = 16 in {
3053 def UXTB : AI_ext_rrot<0b01101110,
3054 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3055 def UXTH : AI_ext_rrot<0b01101111,
3056 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3057 def UXTB16 : AI_ext_rrot<0b01101100,
3058 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3060 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3061 // The transformation should probably be done as a combiner action
3062 // instead so we can include a check for masking back in the upper
3063 // eight bits of the source into the lower eight bits of the result.
3064 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3065 // (UXTB16r_rot GPR:$Src, 3)>;
3066 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3067 (UXTB16 GPR:$Src, 1)>;
3069 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3070 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3071 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3072 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3075 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3076 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3079 def SBFX : I<(outs GPRnopc:$Rd),
3080 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3081 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3082 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3083 Requires<[IsARM, HasV6T2]> {
3088 let Inst{27-21} = 0b0111101;
3089 let Inst{6-4} = 0b101;
3090 let Inst{20-16} = width;
3091 let Inst{15-12} = Rd;
3092 let Inst{11-7} = lsb;
3096 def UBFX : I<(outs GPR:$Rd),
3097 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3098 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3099 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3100 Requires<[IsARM, HasV6T2]> {
3105 let Inst{27-21} = 0b0111111;
3106 let Inst{6-4} = 0b101;
3107 let Inst{20-16} = width;
3108 let Inst{15-12} = Rd;
3109 let Inst{11-7} = lsb;
3113 //===----------------------------------------------------------------------===//
3114 // Arithmetic Instructions.
3117 defm ADD : AsI1_bin_irs<0b0100, "add",
3118 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3119 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3120 defm SUB : AsI1_bin_irs<0b0010, "sub",
3121 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3122 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3124 // ADD and SUB with 's' bit set.
3125 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3126 // CPSR and the implicit def of CPSR is not needed.
3127 defm ADDS : AsI1_bin_s_irs<0b0100, "add",
3128 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3129 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3130 defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
3131 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3132 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3134 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3135 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3137 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3138 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3141 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3142 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3143 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3145 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3146 // CPSR and the implicit def of CPSR is not needed.
3147 defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
3148 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3149 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3151 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3152 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3155 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3156 // The assume-no-carry-in form uses the negation of the input since add/sub
3157 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3158 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3160 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3161 (SUBri GPR:$src, so_imm_neg:$imm)>;
3162 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3163 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3165 // The with-carry-in form matches bitwise not instead of the negation.
3166 // Effectively, the inverse interpretation of the carry flag already accounts
3167 // for part of the negation.
3168 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3169 (SBCri GPR:$src, so_imm_not:$imm)>;
3171 // Note: These are implemented in C++ code, because they have to generate
3172 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3174 // (mul X, 2^n+1) -> (add (X << n), X)
3175 // (mul X, 2^n-1) -> (rsb X, (X << n))
3177 // ARM Arithmetic Instruction
3178 // GPR:$dst = GPR:$a op GPR:$b
3179 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3180 list<dag> pattern = [],
3181 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3182 string asm = "\t$Rd, $Rn, $Rm">
3183 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3187 let Inst{27-20} = op27_20;
3188 let Inst{11-4} = op11_4;
3189 let Inst{19-16} = Rn;
3190 let Inst{15-12} = Rd;
3194 // Saturating add/subtract
3196 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3197 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3198 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3199 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3200 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3201 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3202 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3203 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3205 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3206 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3209 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3210 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3211 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3212 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3213 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3214 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3215 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3216 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3217 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3218 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3219 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3220 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3222 // Signed/Unsigned add/subtract
3224 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3225 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3226 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3227 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3228 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3229 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3230 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3231 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3232 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3233 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3234 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3235 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3237 // Signed/Unsigned halving add/subtract
3239 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3240 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3241 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3242 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3243 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3244 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3245 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3246 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3247 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3248 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3249 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3250 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3252 // Unsigned Sum of Absolute Differences [and Accumulate].
3254 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3255 MulFrm /* for convenience */, NoItinerary, "usad8",
3256 "\t$Rd, $Rn, $Rm", []>,
3257 Requires<[IsARM, HasV6]> {
3261 let Inst{27-20} = 0b01111000;
3262 let Inst{15-12} = 0b1111;
3263 let Inst{7-4} = 0b0001;
3264 let Inst{19-16} = Rd;
3265 let Inst{11-8} = Rm;
3268 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3269 MulFrm /* for convenience */, NoItinerary, "usada8",
3270 "\t$Rd, $Rn, $Rm, $Ra", []>,
3271 Requires<[IsARM, HasV6]> {
3276 let Inst{27-20} = 0b01111000;
3277 let Inst{7-4} = 0b0001;
3278 let Inst{19-16} = Rd;
3279 let Inst{15-12} = Ra;
3280 let Inst{11-8} = Rm;
3284 // Signed/Unsigned saturate
3286 def SSAT : AI<(outs GPRnopc:$Rd),
3287 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3288 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3293 let Inst{27-21} = 0b0110101;
3294 let Inst{5-4} = 0b01;
3295 let Inst{20-16} = sat_imm;
3296 let Inst{15-12} = Rd;
3297 let Inst{11-7} = sh{4-0};
3298 let Inst{6} = sh{5};
3302 def SSAT16 : AI<(outs GPRnopc:$Rd),
3303 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3304 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3308 let Inst{27-20} = 0b01101010;
3309 let Inst{11-4} = 0b11110011;
3310 let Inst{15-12} = Rd;
3311 let Inst{19-16} = sat_imm;
3315 def USAT : AI<(outs GPRnopc:$Rd),
3316 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3317 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3322 let Inst{27-21} = 0b0110111;
3323 let Inst{5-4} = 0b01;
3324 let Inst{15-12} = Rd;
3325 let Inst{11-7} = sh{4-0};
3326 let Inst{6} = sh{5};
3327 let Inst{20-16} = sat_imm;
3331 def USAT16 : AI<(outs GPRnopc:$Rd),
3332 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3333 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3337 let Inst{27-20} = 0b01101110;
3338 let Inst{11-4} = 0b11110011;
3339 let Inst{15-12} = Rd;
3340 let Inst{19-16} = sat_imm;
3344 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3345 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3346 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3347 (USAT imm:$pos, GPRnopc:$a, 0)>;
3349 //===----------------------------------------------------------------------===//
3350 // Bitwise Instructions.
3353 defm AND : AsI1_bin_irs<0b0000, "and",
3354 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3355 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3356 defm ORR : AsI1_bin_irs<0b1100, "orr",
3357 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3358 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3359 defm EOR : AsI1_bin_irs<0b0001, "eor",
3360 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3361 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3362 defm BIC : AsI1_bin_irs<0b1110, "bic",
3363 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3364 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3366 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3367 // like in the actual instruction encoding. The complexity of mapping the mask
3368 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3369 // instruction description.
3370 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3371 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3372 "bfc", "\t$Rd, $imm", "$src = $Rd",
3373 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3374 Requires<[IsARM, HasV6T2]> {
3377 let Inst{27-21} = 0b0111110;
3378 let Inst{6-0} = 0b0011111;
3379 let Inst{15-12} = Rd;
3380 let Inst{11-7} = imm{4-0}; // lsb
3381 let Inst{20-16} = imm{9-5}; // msb
3384 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3385 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3386 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3387 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3388 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3389 bf_inv_mask_imm:$imm))]>,
3390 Requires<[IsARM, HasV6T2]> {
3394 let Inst{27-21} = 0b0111110;
3395 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3396 let Inst{15-12} = Rd;
3397 let Inst{11-7} = imm{4-0}; // lsb
3398 let Inst{20-16} = imm{9-5}; // width
3402 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3403 "mvn", "\t$Rd, $Rm",
3404 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3408 let Inst{19-16} = 0b0000;
3409 let Inst{11-4} = 0b00000000;
3410 let Inst{15-12} = Rd;
3413 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3414 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3415 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3419 let Inst{19-16} = 0b0000;
3420 let Inst{15-12} = Rd;
3421 let Inst{11-5} = shift{11-5};
3423 let Inst{3-0} = shift{3-0};
3425 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3426 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3427 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3431 let Inst{19-16} = 0b0000;
3432 let Inst{15-12} = Rd;
3433 let Inst{11-8} = shift{11-8};
3435 let Inst{6-5} = shift{6-5};
3437 let Inst{3-0} = shift{3-0};
3439 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3440 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3441 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3442 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3446 let Inst{19-16} = 0b0000;
3447 let Inst{15-12} = Rd;
3448 let Inst{11-0} = imm;
3451 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3452 (BICri GPR:$src, so_imm_not:$imm)>;
3454 //===----------------------------------------------------------------------===//
3455 // Multiply Instructions.
3457 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3458 string opc, string asm, list<dag> pattern>
3459 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3463 let Inst{19-16} = Rd;
3464 let Inst{11-8} = Rm;
3467 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3468 string opc, string asm, list<dag> pattern>
3469 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3474 let Inst{19-16} = RdHi;
3475 let Inst{15-12} = RdLo;
3476 let Inst{11-8} = Rm;
3480 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3481 // property. Remove them when it's possible to add those properties
3482 // on an individual MachineInstr, not just an instuction description.
3483 let isCommutable = 1 in {
3484 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3485 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3486 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3487 Requires<[IsARM, HasV6]> {
3488 let Inst{15-12} = 0b0000;
3491 let Constraints = "@earlyclobber $Rd" in
3492 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3493 pred:$p, cc_out:$s),
3495 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3496 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3497 Requires<[IsARM, NoV6]>;
3500 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3501 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3502 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3503 Requires<[IsARM, HasV6]> {
3505 let Inst{15-12} = Ra;
3508 let Constraints = "@earlyclobber $Rd" in
3509 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3510 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3512 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3513 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3514 Requires<[IsARM, NoV6]>;
3516 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3517 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3518 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3519 Requires<[IsARM, HasV6T2]> {
3524 let Inst{19-16} = Rd;
3525 let Inst{15-12} = Ra;
3526 let Inst{11-8} = Rm;
3530 // Extra precision multiplies with low / high results
3531 let neverHasSideEffects = 1 in {
3532 let isCommutable = 1 in {
3533 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3534 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3535 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3536 Requires<[IsARM, HasV6]>;
3538 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3539 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3540 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3541 Requires<[IsARM, HasV6]>;
3543 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3544 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3545 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3547 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3548 Requires<[IsARM, NoV6]>;
3550 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3551 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3553 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3554 Requires<[IsARM, NoV6]>;
3558 // Multiply + accumulate
3559 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3560 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3561 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3562 Requires<[IsARM, HasV6]>;
3563 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3564 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3565 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3566 Requires<[IsARM, HasV6]>;
3568 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3569 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3570 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3571 Requires<[IsARM, HasV6]> {
3576 let Inst{19-16} = RdHi;
3577 let Inst{15-12} = RdLo;
3578 let Inst{11-8} = Rm;
3582 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3583 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3584 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3586 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3587 Requires<[IsARM, NoV6]>;
3588 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3589 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3591 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3592 Requires<[IsARM, NoV6]>;
3593 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3594 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3596 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3597 Requires<[IsARM, NoV6]>;
3600 } // neverHasSideEffects
3602 // Most significant word multiply
3603 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3604 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3605 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3606 Requires<[IsARM, HasV6]> {
3607 let Inst{15-12} = 0b1111;
3610 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3611 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3612 Requires<[IsARM, HasV6]> {
3613 let Inst{15-12} = 0b1111;
3616 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3617 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3618 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3619 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3620 Requires<[IsARM, HasV6]>;
3622 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3623 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3624 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3625 Requires<[IsARM, HasV6]>;
3627 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3628 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3629 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3630 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3631 Requires<[IsARM, HasV6]>;
3633 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3634 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3635 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3636 Requires<[IsARM, HasV6]>;
3638 multiclass AI_smul<string opc, PatFrag opnode> {
3639 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3640 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3641 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3642 (sext_inreg GPR:$Rm, i16)))]>,
3643 Requires<[IsARM, HasV5TE]>;
3645 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3646 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3647 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3648 (sra GPR:$Rm, (i32 16))))]>,
3649 Requires<[IsARM, HasV5TE]>;
3651 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3652 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3653 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3654 (sext_inreg GPR:$Rm, i16)))]>,
3655 Requires<[IsARM, HasV5TE]>;
3657 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3658 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3659 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3660 (sra GPR:$Rm, (i32 16))))]>,
3661 Requires<[IsARM, HasV5TE]>;
3663 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3664 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3665 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3666 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3667 Requires<[IsARM, HasV5TE]>;
3669 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3670 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3671 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3672 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3673 Requires<[IsARM, HasV5TE]>;
3677 multiclass AI_smla<string opc, PatFrag opnode> {
3678 let DecoderMethod = "DecodeSMLAInstruction" in {
3679 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3680 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3681 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3682 [(set GPRnopc:$Rd, (add GPR:$Ra,
3683 (opnode (sext_inreg GPRnopc:$Rn, i16),
3684 (sext_inreg GPRnopc:$Rm, i16))))]>,
3685 Requires<[IsARM, HasV5TE]>;
3687 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3688 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3689 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3691 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3692 (sra GPRnopc:$Rm, (i32 16)))))]>,
3693 Requires<[IsARM, HasV5TE]>;
3695 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3696 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3697 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3699 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3700 (sext_inreg GPRnopc:$Rm, i16))))]>,
3701 Requires<[IsARM, HasV5TE]>;
3703 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3704 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3705 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3707 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3708 (sra GPRnopc:$Rm, (i32 16)))))]>,
3709 Requires<[IsARM, HasV5TE]>;
3711 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3712 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3713 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3715 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3716 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3717 Requires<[IsARM, HasV5TE]>;
3719 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3720 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3721 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3723 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3724 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3725 Requires<[IsARM, HasV5TE]>;
3729 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3730 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3732 // Halfword multiply accumulate long: SMLAL<x><y>.
3733 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3734 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3735 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3736 Requires<[IsARM, HasV5TE]>;
3738 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3739 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3740 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3741 Requires<[IsARM, HasV5TE]>;
3743 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3744 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3745 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3746 Requires<[IsARM, HasV5TE]>;
3748 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3749 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3750 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3751 Requires<[IsARM, HasV5TE]>;
3753 // Helper class for AI_smld.
3754 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3755 InstrItinClass itin, string opc, string asm>
3756 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3759 let Inst{27-23} = 0b01110;
3760 let Inst{22} = long;
3761 let Inst{21-20} = 0b00;
3762 let Inst{11-8} = Rm;
3769 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3770 InstrItinClass itin, string opc, string asm>
3771 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3773 let Inst{15-12} = 0b1111;
3774 let Inst{19-16} = Rd;
3776 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3777 InstrItinClass itin, string opc, string asm>
3778 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3781 let Inst{19-16} = Rd;
3782 let Inst{15-12} = Ra;
3784 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3785 InstrItinClass itin, string opc, string asm>
3786 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3789 let Inst{19-16} = RdHi;
3790 let Inst{15-12} = RdLo;
3793 multiclass AI_smld<bit sub, string opc> {
3795 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3796 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3797 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3799 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3800 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3801 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3803 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3804 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3805 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3807 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3808 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3809 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3813 defm SMLA : AI_smld<0, "smla">;
3814 defm SMLS : AI_smld<1, "smls">;
3816 multiclass AI_sdml<bit sub, string opc> {
3818 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3819 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3820 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3821 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3824 defm SMUA : AI_sdml<0, "smua">;
3825 defm SMUS : AI_sdml<1, "smus">;
3827 //===----------------------------------------------------------------------===//
3828 // Misc. Arithmetic Instructions.
3831 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3832 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3833 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3835 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3836 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3837 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3838 Requires<[IsARM, HasV6T2]>;
3840 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3841 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3842 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3844 let AddedComplexity = 5 in
3845 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3846 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3847 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3848 Requires<[IsARM, HasV6]>;
3850 let AddedComplexity = 5 in
3851 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3852 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3853 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3854 Requires<[IsARM, HasV6]>;
3856 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3857 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3860 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3861 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3862 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3863 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3864 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3866 Requires<[IsARM, HasV6]>;
3868 // Alternate cases for PKHBT where identities eliminate some nodes.
3869 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3870 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3871 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3872 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3874 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3875 // will match the pattern below.
3876 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3877 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3878 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3879 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3880 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3882 Requires<[IsARM, HasV6]>;
3884 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3885 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3886 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3887 (srl GPRnopc:$src2, imm16_31:$sh)),
3888 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3889 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3890 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3891 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3893 //===----------------------------------------------------------------------===//
3894 // Comparison Instructions...
3897 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3898 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3899 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3901 // ARMcmpZ can re-use the above instruction definitions.
3902 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3903 (CMPri GPR:$src, so_imm:$imm)>;
3904 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3905 (CMPrr GPR:$src, GPR:$rhs)>;
3906 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3907 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3908 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3909 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3911 // FIXME: We have to be careful when using the CMN instruction and comparison
3912 // with 0. One would expect these two pieces of code should give identical
3928 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3929 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3930 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3931 // value of r0 and the carry bit (because the "carry bit" parameter to
3932 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3933 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3934 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3935 // parameter to AddWithCarry is defined as 0).
3937 // When x is 0 and unsigned:
3941 // ~x + 1 = 0x1 0000 0000
3942 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3944 // Therefore, we should disable CMN when comparing against zero, until we can
3945 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3946 // when it's a comparison which doesn't look at the 'carry' flag).
3948 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3950 // This is related to <rdar://problem/7569620>.
3952 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3953 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3955 // Note that TST/TEQ don't set all the same flags that CMP does!
3956 defm TST : AI1_cmp_irs<0b1000, "tst",
3957 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3958 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3959 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3960 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3961 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3963 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3964 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3965 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3967 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3968 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3970 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3971 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3973 // Pseudo i64 compares for some floating point compares.
3974 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3976 def BCCi64 : PseudoInst<(outs),
3977 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3979 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3981 def BCCZi64 : PseudoInst<(outs),
3982 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3983 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3984 } // usesCustomInserter
3987 // Conditional moves
3988 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3989 // a two-value operand where a dag node expects two operands. :(
3990 let neverHasSideEffects = 1 in {
3991 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3993 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3994 RegConstraint<"$false = $Rd">;
3995 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3996 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3998 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3999 imm:$cc, CCR:$ccr))*/]>,
4000 RegConstraint<"$false = $Rd">;
4001 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4002 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4004 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4005 imm:$cc, CCR:$ccr))*/]>,
4006 RegConstraint<"$false = $Rd">;
4009 let isMoveImm = 1 in
4010 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4011 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4014 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4016 let isMoveImm = 1 in
4017 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4018 (ins GPR:$false, so_imm:$imm, pred:$p),
4020 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4021 RegConstraint<"$false = $Rd">;
4023 // Two instruction predicate mov immediate.
4024 let isMoveImm = 1 in
4025 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4026 (ins GPR:$false, i32imm:$src, pred:$p),
4027 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4029 let isMoveImm = 1 in
4030 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4031 (ins GPR:$false, so_imm:$imm, pred:$p),
4033 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4034 RegConstraint<"$false = $Rd">;
4035 } // neverHasSideEffects
4037 //===----------------------------------------------------------------------===//
4038 // Atomic operations intrinsics
4041 def MemBarrierOptOperand : AsmOperandClass {
4042 let Name = "MemBarrierOpt";
4043 let ParserMethod = "parseMemBarrierOptOperand";
4045 def memb_opt : Operand<i32> {
4046 let PrintMethod = "printMemBOption";
4047 let ParserMatchClass = MemBarrierOptOperand;
4048 let DecoderMethod = "DecodeMemBarrierOption";
4051 // memory barriers protect the atomic sequences
4052 let hasSideEffects = 1 in {
4053 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4054 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4055 Requires<[IsARM, HasDB]> {
4057 let Inst{31-4} = 0xf57ff05;
4058 let Inst{3-0} = opt;
4062 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4063 "dsb", "\t$opt", []>,
4064 Requires<[IsARM, HasDB]> {
4066 let Inst{31-4} = 0xf57ff04;
4067 let Inst{3-0} = opt;
4070 // ISB has only full system option
4071 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4072 "isb", "\t$opt", []>,
4073 Requires<[IsARM, HasDB]> {
4075 let Inst{31-4} = 0xf57ff06;
4076 let Inst{3-0} = opt;
4079 let usesCustomInserter = 1 in {
4080 let Defs = [CPSR] in {
4081 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4082 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4083 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4084 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4085 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4086 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4087 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4088 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4089 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4090 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4091 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4092 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4093 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4094 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4095 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4096 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4097 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4098 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4099 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4100 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4101 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4102 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4103 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4104 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4105 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4106 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4107 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4108 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4109 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4110 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4111 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4112 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4113 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4114 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4115 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4116 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4117 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4118 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4119 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4120 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4121 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4122 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4123 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4125 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4126 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4128 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4129 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4131 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4132 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4135 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4137 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4138 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4140 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4141 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4143 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4144 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4146 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4147 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4149 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4150 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4152 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4153 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4156 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4159 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4162 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4164 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4165 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4167 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4168 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4170 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4172 def ATOMIC_SWAP_I8 : PseudoInst<
4173 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4174 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4175 def ATOMIC_SWAP_I16 : PseudoInst<
4176 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4177 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4178 def ATOMIC_SWAP_I32 : PseudoInst<
4179 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4180 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4182 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4183 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4184 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4185 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4186 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4187 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4188 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4189 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4190 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4194 let mayLoad = 1 in {
4195 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4197 "ldrexb", "\t$Rt, $addr", []>;
4198 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4199 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4200 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4201 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4202 let hasExtraDefRegAllocReq = 1 in
4203 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4204 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4205 let DecoderMethod = "DecodeDoubleRegLoad";
4209 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4210 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4211 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4212 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4213 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4214 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4215 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4218 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4219 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4220 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4221 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4222 let DecoderMethod = "DecodeDoubleRegStore";
4225 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4226 Requires<[IsARM, HasV7]> {
4227 let Inst{31-0} = 0b11110101011111111111000000011111;
4230 // SWP/SWPB are deprecated in V6/V7.
4231 let mayLoad = 1, mayStore = 1 in {
4232 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4234 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4238 //===----------------------------------------------------------------------===//
4239 // Coprocessor Instructions.
4242 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4243 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4244 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4245 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4246 imm:$CRm, imm:$opc2)]> {
4254 let Inst{3-0} = CRm;
4256 let Inst{7-5} = opc2;
4257 let Inst{11-8} = cop;
4258 let Inst{15-12} = CRd;
4259 let Inst{19-16} = CRn;
4260 let Inst{23-20} = opc1;
4263 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4264 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4265 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4266 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4267 imm:$CRm, imm:$opc2)]> {
4268 let Inst{31-28} = 0b1111;
4276 let Inst{3-0} = CRm;
4278 let Inst{7-5} = opc2;
4279 let Inst{11-8} = cop;
4280 let Inst{15-12} = CRd;
4281 let Inst{19-16} = CRn;
4282 let Inst{23-20} = opc1;
4285 class ACI<dag oops, dag iops, string opc, string asm,
4286 IndexMode im = IndexModeNone>
4287 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4289 let Inst{27-25} = 0b110;
4292 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
4293 def _OFFSET : ACI<(outs),
4294 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4295 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
4296 let Inst{31-28} = op31_28;
4297 let Inst{24} = 1; // P = 1
4298 let Inst{21} = 0; // W = 0
4299 let Inst{22} = 0; // D = 0
4300 let Inst{20} = load;
4301 let DecoderMethod = "DecodeCopMemInstruction";
4304 def _PRE : ACI<(outs),
4305 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4306 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
4307 let Inst{31-28} = op31_28;
4308 let Inst{24} = 1; // P = 1
4309 let Inst{21} = 1; // W = 1
4310 let Inst{22} = 0; // D = 0
4311 let Inst{20} = load;
4312 let DecoderMethod = "DecodeCopMemInstruction";
4315 def _POST : ACI<(outs),
4316 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4317 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
4318 let Inst{31-28} = op31_28;
4319 let Inst{24} = 0; // P = 0
4320 let Inst{21} = 1; // W = 1
4321 let Inst{22} = 0; // D = 0
4322 let Inst{20} = load;
4323 let DecoderMethod = "DecodeCopMemInstruction";
4326 def _OPTION : ACI<(outs),
4327 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
4329 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4330 let Inst{31-28} = op31_28;
4331 let Inst{24} = 0; // P = 0
4332 let Inst{23} = 1; // U = 1
4333 let Inst{21} = 0; // W = 0
4334 let Inst{22} = 0; // D = 0
4335 let Inst{20} = load;
4336 let DecoderMethod = "DecodeCopMemInstruction";
4339 def L_OFFSET : ACI<(outs),
4340 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4341 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
4342 let Inst{31-28} = op31_28;
4343 let Inst{24} = 1; // P = 1
4344 let Inst{21} = 0; // W = 0
4345 let Inst{22} = 1; // D = 1
4346 let Inst{20} = load;
4347 let DecoderMethod = "DecodeCopMemInstruction";
4350 def L_PRE : ACI<(outs),
4351 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4352 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
4354 let Inst{31-28} = op31_28;
4355 let Inst{24} = 1; // P = 1
4356 let Inst{21} = 1; // W = 1
4357 let Inst{22} = 1; // D = 1
4358 let Inst{20} = load;
4359 let DecoderMethod = "DecodeCopMemInstruction";
4362 def L_POST : ACI<(outs),
4363 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
4364 postidx_imm8s4:$offset), ops),
4365 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset",
4367 let Inst{31-28} = op31_28;
4368 let Inst{24} = 0; // P = 0
4369 let Inst{21} = 1; // W = 1
4370 let Inst{22} = 1; // D = 1
4371 let Inst{20} = load;
4372 let DecoderMethod = "DecodeCopMemInstruction";
4375 def L_OPTION : ACI<(outs),
4376 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
4378 !strconcat(!strconcat(opc, "l"), cond),
4379 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4380 let Inst{31-28} = op31_28;
4381 let Inst{24} = 0; // P = 0
4382 let Inst{23} = 1; // U = 1
4383 let Inst{21} = 0; // W = 0
4384 let Inst{22} = 1; // D = 1
4385 let Inst{20} = load;
4386 let DecoderMethod = "DecodeCopMemInstruction";
4390 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
4391 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
4392 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
4393 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
4395 //===----------------------------------------------------------------------===//
4396 // Move between coprocessor and ARM core register.
4399 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4401 : ABI<0b1110, oops, iops, NoItinerary, opc,
4402 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4403 let Inst{20} = direction;
4413 let Inst{15-12} = Rt;
4414 let Inst{11-8} = cop;
4415 let Inst{23-21} = opc1;
4416 let Inst{7-5} = opc2;
4417 let Inst{3-0} = CRm;
4418 let Inst{19-16} = CRn;
4421 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4423 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4424 c_imm:$CRm, imm0_7:$opc2),
4425 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4426 imm:$CRm, imm:$opc2)]>;
4427 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4429 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4432 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4433 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4435 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4437 : ABXI<0b1110, oops, iops, NoItinerary,
4438 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4439 let Inst{31-28} = 0b1111;
4440 let Inst{20} = direction;
4450 let Inst{15-12} = Rt;
4451 let Inst{11-8} = cop;
4452 let Inst{23-21} = opc1;
4453 let Inst{7-5} = opc2;
4454 let Inst{3-0} = CRm;
4455 let Inst{19-16} = CRn;
4458 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4460 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4461 c_imm:$CRm, imm0_7:$opc2),
4462 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4463 imm:$CRm, imm:$opc2)]>;
4464 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4466 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4469 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4470 imm:$CRm, imm:$opc2),
4471 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4473 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4474 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4475 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4476 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4477 let Inst{23-21} = 0b010;
4478 let Inst{20} = direction;
4486 let Inst{15-12} = Rt;
4487 let Inst{19-16} = Rt2;
4488 let Inst{11-8} = cop;
4489 let Inst{7-4} = opc1;
4490 let Inst{3-0} = CRm;
4493 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4494 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4496 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4498 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4499 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4500 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4501 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4502 let Inst{31-28} = 0b1111;
4503 let Inst{23-21} = 0b010;
4504 let Inst{20} = direction;
4512 let Inst{15-12} = Rt;
4513 let Inst{19-16} = Rt2;
4514 let Inst{11-8} = cop;
4515 let Inst{7-4} = opc1;
4516 let Inst{3-0} = CRm;
4519 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4520 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4522 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4524 //===----------------------------------------------------------------------===//
4525 // Move between special register and ARM core register
4528 // Move to ARM core register from Special Register
4529 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4530 "mrs", "\t$Rd, apsr", []> {
4532 let Inst{23-16} = 0b00001111;
4533 let Inst{15-12} = Rd;
4534 let Inst{7-4} = 0b0000;
4537 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4539 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4540 "mrs", "\t$Rd, spsr", []> {
4542 let Inst{23-16} = 0b01001111;
4543 let Inst{15-12} = Rd;
4544 let Inst{7-4} = 0b0000;
4547 // Move from ARM core register to Special Register
4549 // No need to have both system and application versions, the encodings are the
4550 // same and the assembly parser has no way to distinguish between them. The mask
4551 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4552 // the mask with the fields to be accessed in the special register.
4553 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4554 "msr", "\t$mask, $Rn", []> {
4559 let Inst{22} = mask{4}; // R bit
4560 let Inst{21-20} = 0b10;
4561 let Inst{19-16} = mask{3-0};
4562 let Inst{15-12} = 0b1111;
4563 let Inst{11-4} = 0b00000000;
4567 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4568 "msr", "\t$mask, $a", []> {
4573 let Inst{22} = mask{4}; // R bit
4574 let Inst{21-20} = 0b10;
4575 let Inst{19-16} = mask{3-0};
4576 let Inst{15-12} = 0b1111;
4580 //===----------------------------------------------------------------------===//
4584 // __aeabi_read_tp preserves the registers r1-r3.
4585 // This is a pseudo inst so that we can get the encoding right,
4586 // complete with fixup for the aeabi_read_tp function.
4588 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4589 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4590 [(set R0, ARMthread_pointer)]>;
4593 //===----------------------------------------------------------------------===//
4594 // SJLJ Exception handling intrinsics
4595 // eh_sjlj_setjmp() is an instruction sequence to store the return
4596 // address and save #0 in R0 for the non-longjmp case.
4597 // Since by its nature we may be coming from some other function to get
4598 // here, and we're using the stack frame for the containing function to
4599 // save/restore registers, we can't keep anything live in regs across
4600 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4601 // when we get here from a longjmp(). We force everything out of registers
4602 // except for our own input by listing the relevant registers in Defs. By
4603 // doing so, we also cause the prologue/epilogue code to actively preserve
4604 // all of the callee-saved resgisters, which is exactly what we want.
4605 // A constant value is passed in $val, and we use the location as a scratch.
4607 // These are pseudo-instructions and are lowered to individual MC-insts, so
4608 // no encoding information is necessary.
4610 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4611 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4612 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4614 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4615 Requires<[IsARM, HasVFP2]>;
4619 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4620 hasSideEffects = 1, isBarrier = 1 in {
4621 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4623 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4624 Requires<[IsARM, NoVFP]>;
4627 // FIXME: Non-Darwin version(s)
4628 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4629 Defs = [ R7, LR, SP ] in {
4630 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4632 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4633 Requires<[IsARM, IsDarwin]>;
4636 // eh.sjlj.dispatchsetup pseudo-instruction.
4637 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4638 // handled when the pseudo is expanded (which happens before any passes
4639 // that need the instruction size).
4640 let isBarrier = 1, hasSideEffects = 1 in
4641 def Int_eh_sjlj_dispatchsetup :
4642 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4643 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4644 Requires<[IsDarwin]>;
4646 //===----------------------------------------------------------------------===//
4647 // Non-Instruction Patterns
4650 // ARMv4 indirect branch using (MOVr PC, dst)
4651 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4652 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4653 4, IIC_Br, [(brind GPR:$dst)],
4654 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4655 Requires<[IsARM, NoV4T]>;
4657 // Large immediate handling.
4659 // 32-bit immediate using two piece so_imms or movw + movt.
4660 // This is a single pseudo instruction, the benefit is that it can be remat'd
4661 // as a single unit instead of having to handle reg inputs.
4662 // FIXME: Remove this when we can do generalized remat.
4663 let isReMaterializable = 1, isMoveImm = 1 in
4664 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4665 [(set GPR:$dst, (arm_i32imm:$src))]>,
4668 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4669 // It also makes it possible to rematerialize the instructions.
4670 // FIXME: Remove this when we can do generalized remat and when machine licm
4671 // can properly the instructions.
4672 let isReMaterializable = 1 in {
4673 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4675 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4676 Requires<[IsARM, UseMovt]>;
4678 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4680 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4681 Requires<[IsARM, UseMovt]>;
4683 let AddedComplexity = 10 in
4684 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4686 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4687 Requires<[IsARM, UseMovt]>;
4688 } // isReMaterializable
4690 // ConstantPool, GlobalAddress, and JumpTable
4691 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4692 Requires<[IsARM, DontUseMovt]>;
4693 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4694 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4695 Requires<[IsARM, UseMovt]>;
4696 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4697 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4699 // TODO: add,sub,and, 3-instr forms?
4702 def : ARMPat<(ARMtcret tcGPR:$dst),
4703 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4705 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4706 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4708 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4709 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4711 def : ARMPat<(ARMtcret tcGPR:$dst),
4712 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4714 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4715 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4717 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4718 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4721 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4722 Requires<[IsARM, IsNotDarwin]>;
4723 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4724 Requires<[IsARM, IsDarwin]>;
4726 // zextload i1 -> zextload i8
4727 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4728 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4730 // extload -> zextload
4731 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4732 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4733 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4734 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4736 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4738 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4739 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4742 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4743 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4744 (SMULBB GPR:$a, GPR:$b)>;
4745 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4746 (SMULBB GPR:$a, GPR:$b)>;
4747 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4748 (sra GPR:$b, (i32 16))),
4749 (SMULBT GPR:$a, GPR:$b)>;
4750 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4751 (SMULBT GPR:$a, GPR:$b)>;
4752 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4753 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4754 (SMULTB GPR:$a, GPR:$b)>;
4755 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4756 (SMULTB GPR:$a, GPR:$b)>;
4757 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4759 (SMULWB GPR:$a, GPR:$b)>;
4760 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4761 (SMULWB GPR:$a, GPR:$b)>;
4763 def : ARMV5TEPat<(add GPR:$acc,
4764 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4765 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4766 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4767 def : ARMV5TEPat<(add GPR:$acc,
4768 (mul sext_16_node:$a, sext_16_node:$b)),
4769 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4770 def : ARMV5TEPat<(add GPR:$acc,
4771 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4772 (sra GPR:$b, (i32 16)))),
4773 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4774 def : ARMV5TEPat<(add GPR:$acc,
4775 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4776 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4777 def : ARMV5TEPat<(add GPR:$acc,
4778 (mul (sra GPR:$a, (i32 16)),
4779 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4780 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4781 def : ARMV5TEPat<(add GPR:$acc,
4782 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4783 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4784 def : ARMV5TEPat<(add GPR:$acc,
4785 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4787 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4788 def : ARMV5TEPat<(add GPR:$acc,
4789 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4790 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4793 // Pre-v7 uses MCR for synchronization barriers.
4794 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4795 Requires<[IsARM, HasV6]>;
4797 // SXT/UXT with no rotate
4798 let AddedComplexity = 16 in {
4799 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4800 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4801 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4802 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4803 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4804 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4805 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4808 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4809 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4811 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4812 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4813 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4814 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4816 // Atomic load/store patterns
4817 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4818 (LDRBrs ldst_so_reg:$src)>;
4819 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4820 (LDRBi12 addrmode_imm12:$src)>;
4821 def : ARMPat<(atomic_load_16 addrmode3:$src),
4822 (LDRH addrmode3:$src)>;
4823 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4824 (LDRrs ldst_so_reg:$src)>;
4825 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4826 (LDRi12 addrmode_imm12:$src)>;
4827 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4828 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4829 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4830 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4831 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4832 (STRH GPR:$val, addrmode3:$ptr)>;
4833 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4834 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4835 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4836 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4839 //===----------------------------------------------------------------------===//
4843 include "ARMInstrThumb.td"
4845 //===----------------------------------------------------------------------===//
4849 include "ARMInstrThumb2.td"
4851 //===----------------------------------------------------------------------===//
4852 // Floating Point Support
4855 include "ARMInstrVFP.td"
4857 //===----------------------------------------------------------------------===//
4858 // Advanced SIMD (NEON) Support
4861 include "ARMInstrNEON.td"
4863 //===----------------------------------------------------------------------===//
4864 // Assembler aliases
4868 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4869 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4870 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4872 // System instructions
4873 def : MnemonicAlias<"swi", "svc">;
4875 // Load / Store Multiple
4876 def : MnemonicAlias<"ldmfd", "ldm">;
4877 def : MnemonicAlias<"ldmia", "ldm">;
4878 def : MnemonicAlias<"ldmea", "ldmdb">;
4879 def : MnemonicAlias<"stmfd", "stmdb">;
4880 def : MnemonicAlias<"stmia", "stm">;
4881 def : MnemonicAlias<"stmea", "stm">;
4883 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4884 // shift amount is zero (i.e., unspecified).
4885 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4886 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4887 Requires<[IsARM, HasV6]>;
4888 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4889 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4890 Requires<[IsARM, HasV6]>;
4892 // PUSH/POP aliases for STM/LDM
4893 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4894 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4896 // SSAT/USAT optional shift operand.
4897 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4898 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4899 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4900 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4903 // Extend instruction optional rotate operand.
4904 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4905 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4906 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4907 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4908 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4909 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4910 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4911 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4912 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4913 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4914 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4915 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4917 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4918 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4919 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4920 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4921 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4922 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4923 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4924 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4925 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4926 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4927 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4928 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4932 def : MnemonicAlias<"rfefa", "rfeda">;
4933 def : MnemonicAlias<"rfeea", "rfedb">;
4934 def : MnemonicAlias<"rfefd", "rfeia">;
4935 def : MnemonicAlias<"rfeed", "rfeib">;
4936 def : MnemonicAlias<"rfe", "rfeia">;
4939 def : MnemonicAlias<"srsfa", "srsda">;
4940 def : MnemonicAlias<"srsea", "srsdb">;
4941 def : MnemonicAlias<"srsfd", "srsia">;
4942 def : MnemonicAlias<"srsed", "srsib">;
4943 def : MnemonicAlias<"srs", "srsia">;
4946 def : MnemonicAlias<"qsubaddx", "qsax">;
4948 def : MnemonicAlias<"saddsubx", "sasx">;
4949 // SHASX == SHADDSUBX
4950 def : MnemonicAlias<"shaddsubx", "shasx">;
4951 // SHSAX == SHSUBADDX
4952 def : MnemonicAlias<"shsubaddx", "shsax">;
4954 def : MnemonicAlias<"ssubaddx", "ssax">;
4956 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
4957 // Note that the write-back output register is a dummy operand for MC (it's
4958 // only meaningful for codegen), so we just pass zero here.
4959 // FIXME: tblgen not cooperating with argument conversions.
4960 //def : InstAlias<"ldrsbt${p} $Rt, $addr",
4961 // (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>;
4962 //def : InstAlias<"ldrht${p} $Rt, $addr",
4963 // (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
4964 //def : InstAlias<"ldrsht${p} $Rt, $addr",
4965 // (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;