1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
198 AssemblerPredicate<"HasV8Ops", "armv8">;
199 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
200 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
201 AssemblerPredicate<"FeatureVFP2", "VFP2">;
202 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
203 AssemblerPredicate<"FeatureVFP3", "VFP3">;
204 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
205 AssemblerPredicate<"FeatureVFP4", "VFP4">;
206 def HasNEON : Predicate<"Subtarget->hasNEON()">,
207 AssemblerPredicate<"FeatureNEON", "NEON">;
208 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
209 AssemblerPredicate<"FeatureFP16","half-float">;
210 def HasDivide : Predicate<"Subtarget->hasDivide()">,
211 AssemblerPredicate<"FeatureHWDiv", "divide">;
212 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
213 AssemblerPredicate<"FeatureHWDivARM">;
214 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
215 AssemblerPredicate<"FeatureT2XtPk",
217 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
218 AssemblerPredicate<"FeatureDSPThumb2",
220 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
221 AssemblerPredicate<"FeatureDB",
223 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
224 AssemblerPredicate<"FeatureMP",
226 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
227 AssemblerPredicate<"FeatureTrustZone",
229 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
230 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
231 def IsThumb : Predicate<"Subtarget->isThumb()">,
232 AssemblerPredicate<"ModeThumb", "thumb">;
233 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
234 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
235 AssemblerPredicate<"ModeThumb,FeatureThumb2",
237 def IsMClass : Predicate<"Subtarget->isMClass()">,
238 AssemblerPredicate<"FeatureMClass", "armv7m">;
239 def IsARClass : Predicate<"!Subtarget->isMClass()">,
240 AssemblerPredicate<"!FeatureMClass",
242 def IsARM : Predicate<"!Subtarget->isThumb()">,
243 AssemblerPredicate<"!ModeThumb", "arm-mode">;
244 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
245 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
246 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
247 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
248 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
249 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
251 // FIXME: Eventually this will be just "hasV6T2Ops".
252 def UseMovt : Predicate<"Subtarget->useMovt()">;
253 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
254 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
255 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
257 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
258 // But only select them if more precision in FP computation is allowed.
259 // Do not use them for Darwin platforms.
260 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
261 " FPOpFusion::Fast) && "
262 "!Subtarget->isTargetDarwin()">;
263 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
264 "Subtarget->isTargetDarwin()">;
266 // VGETLNi32 is microcoded on Swift - prefer VMOV.
267 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
268 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
270 // VDUP.32 is microcoded on Swift - prefer VMOV.
271 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
272 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
274 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
275 // this allows more effective execution domain optimization. See
276 // setExecutionDomain().
277 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
278 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
280 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
281 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
283 //===----------------------------------------------------------------------===//
284 // ARM Flag Definitions.
286 class RegConstraint<string C> {
287 string Constraints = C;
290 //===----------------------------------------------------------------------===//
291 // ARM specific transformation functions and pattern fragments.
294 // imm_neg_XFORM - Return the negation of an i32 immediate value.
295 def imm_neg_XFORM : SDNodeXForm<imm, [{
296 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
299 // imm_not_XFORM - Return the complement of a i32 immediate value.
300 def imm_not_XFORM : SDNodeXForm<imm, [{
301 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
304 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
305 def imm16_31 : ImmLeaf<i32, [{
306 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
309 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
310 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
311 unsigned Value = -(unsigned)N->getZExtValue();
312 return Value && ARM_AM::getSOImmVal(Value) != -1;
314 let ParserMatchClass = so_imm_neg_asmoperand;
317 // Note: this pattern doesn't require an encoder method and such, as it's
318 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
319 // is handled by the destination instructions, which use so_imm.
320 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
321 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
322 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
324 let ParserMatchClass = so_imm_not_asmoperand;
327 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
328 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
329 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
332 /// Split a 32-bit immediate into two 16 bit parts.
333 def hi16 : SDNodeXForm<imm, [{
334 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
337 def lo16AllZero : PatLeaf<(i32 imm), [{
338 // Returns true if all low 16-bits are 0.
339 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
342 class BinOpWithFlagFrag<dag res> :
343 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
344 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
345 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
347 // An 'and' node with a single use.
348 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
349 return N->hasOneUse();
352 // An 'xor' node with a single use.
353 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
354 return N->hasOneUse();
357 // An 'fmul' node with a single use.
358 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
359 return N->hasOneUse();
362 // An 'fadd' node which checks for single non-hazardous use.
363 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
364 return hasNoVMLxHazardUse(N);
367 // An 'fsub' node which checks for single non-hazardous use.
368 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
369 return hasNoVMLxHazardUse(N);
372 //===----------------------------------------------------------------------===//
373 // Operand Definitions.
376 // Immediate operands with a shared generic asm render method.
377 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
380 // FIXME: rename brtarget to t2_brtarget
381 def brtarget : Operand<OtherVT> {
382 let EncoderMethod = "getBranchTargetOpValue";
383 let OperandType = "OPERAND_PCREL";
384 let DecoderMethod = "DecodeT2BROperand";
387 // FIXME: get rid of this one?
388 def uncondbrtarget : Operand<OtherVT> {
389 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
390 let OperandType = "OPERAND_PCREL";
393 // Branch target for ARM. Handles conditional/unconditional
394 def br_target : Operand<OtherVT> {
395 let EncoderMethod = "getARMBranchTargetOpValue";
396 let OperandType = "OPERAND_PCREL";
400 // FIXME: rename bltarget to t2_bl_target?
401 def bltarget : Operand<i32> {
402 // Encoded the same as branch targets.
403 let EncoderMethod = "getBranchTargetOpValue";
404 let OperandType = "OPERAND_PCREL";
407 // Call target for ARM. Handles conditional/unconditional
408 // FIXME: rename bl_target to t2_bltarget?
409 def bl_target : Operand<i32> {
410 let EncoderMethod = "getARMBLTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
414 def blx_target : Operand<i32> {
415 let EncoderMethod = "getARMBLXTargetOpValue";
416 let OperandType = "OPERAND_PCREL";
419 // A list of registers separated by comma. Used by load/store multiple.
420 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
421 def reglist : Operand<i32> {
422 let EncoderMethod = "getRegisterListOpValue";
423 let ParserMatchClass = RegListAsmOperand;
424 let PrintMethod = "printRegisterList";
425 let DecoderMethod = "DecodeRegListOperand";
428 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
430 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
431 def dpr_reglist : Operand<i32> {
432 let EncoderMethod = "getRegisterListOpValue";
433 let ParserMatchClass = DPRRegListAsmOperand;
434 let PrintMethod = "printRegisterList";
435 let DecoderMethod = "DecodeDPRRegListOperand";
438 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
439 def spr_reglist : Operand<i32> {
440 let EncoderMethod = "getRegisterListOpValue";
441 let ParserMatchClass = SPRRegListAsmOperand;
442 let PrintMethod = "printRegisterList";
443 let DecoderMethod = "DecodeSPRRegListOperand";
446 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
447 def cpinst_operand : Operand<i32> {
448 let PrintMethod = "printCPInstOperand";
452 def pclabel : Operand<i32> {
453 let PrintMethod = "printPCLabel";
456 // ADR instruction labels.
457 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
458 def adrlabel : Operand<i32> {
459 let EncoderMethod = "getAdrLabelOpValue";
460 let ParserMatchClass = AdrLabelAsmOperand;
461 let PrintMethod = "printAdrLabelOperand";
464 def neon_vcvt_imm32 : Operand<i32> {
465 let EncoderMethod = "getNEONVcvtImm32OpValue";
466 let DecoderMethod = "DecodeVCVTImmOperand";
469 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
470 def rot_imm_XFORM: SDNodeXForm<imm, [{
471 switch (N->getZExtValue()){
473 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
474 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
475 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
476 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
479 def RotImmAsmOperand : AsmOperandClass {
481 let ParserMethod = "parseRotImm";
483 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
484 int32_t v = N->getZExtValue();
485 return v == 8 || v == 16 || v == 24; }],
487 let PrintMethod = "printRotImmOperand";
488 let ParserMatchClass = RotImmAsmOperand;
491 // shift_imm: An integer that encodes a shift amount and the type of shift
492 // (asr or lsl). The 6-bit immediate encodes as:
495 // {4-0} imm5 shift amount.
496 // asr #32 encoded as imm5 == 0.
497 def ShifterImmAsmOperand : AsmOperandClass {
498 let Name = "ShifterImm";
499 let ParserMethod = "parseShifterImm";
501 def shift_imm : Operand<i32> {
502 let PrintMethod = "printShiftImmOperand";
503 let ParserMatchClass = ShifterImmAsmOperand;
506 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
507 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
508 def so_reg_reg : Operand<i32>, // reg reg imm
509 ComplexPattern<i32, 3, "SelectRegShifterOperand",
510 [shl, srl, sra, rotr]> {
511 let EncoderMethod = "getSORegRegOpValue";
512 let PrintMethod = "printSORegRegOperand";
513 let DecoderMethod = "DecodeSORegRegOperand";
514 let ParserMatchClass = ShiftedRegAsmOperand;
515 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
518 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
519 def so_reg_imm : Operand<i32>, // reg imm
520 ComplexPattern<i32, 2, "SelectImmShifterOperand",
521 [shl, srl, sra, rotr]> {
522 let EncoderMethod = "getSORegImmOpValue";
523 let PrintMethod = "printSORegImmOperand";
524 let DecoderMethod = "DecodeSORegImmOperand";
525 let ParserMatchClass = ShiftedImmAsmOperand;
526 let MIOperandInfo = (ops GPR, i32imm);
529 // FIXME: Does this need to be distinct from so_reg?
530 def shift_so_reg_reg : Operand<i32>, // reg reg imm
531 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
532 [shl,srl,sra,rotr]> {
533 let EncoderMethod = "getSORegRegOpValue";
534 let PrintMethod = "printSORegRegOperand";
535 let DecoderMethod = "DecodeSORegRegOperand";
536 let ParserMatchClass = ShiftedRegAsmOperand;
537 let MIOperandInfo = (ops GPR, GPR, i32imm);
540 // FIXME: Does this need to be distinct from so_reg?
541 def shift_so_reg_imm : Operand<i32>, // reg reg imm
542 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
543 [shl,srl,sra,rotr]> {
544 let EncoderMethod = "getSORegImmOpValue";
545 let PrintMethod = "printSORegImmOperand";
546 let DecoderMethod = "DecodeSORegImmOperand";
547 let ParserMatchClass = ShiftedImmAsmOperand;
548 let MIOperandInfo = (ops GPR, i32imm);
552 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
553 // 8-bit immediate rotated by an arbitrary number of bits.
554 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
555 def so_imm : Operand<i32>, ImmLeaf<i32, [{
556 return ARM_AM::getSOImmVal(Imm) != -1;
558 let EncoderMethod = "getSOImmOpValue";
559 let ParserMatchClass = SOImmAsmOperand;
560 let DecoderMethod = "DecodeSOImmOperand";
563 // Break so_imm's up into two pieces. This handles immediates with up to 16
564 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
565 // get the first/second pieces.
566 def so_imm2part : PatLeaf<(imm), [{
567 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
570 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
572 def arm_i32imm : PatLeaf<(imm), [{
573 if (Subtarget->hasV6T2Ops())
575 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
578 /// imm0_1 predicate - Immediate in the range [0,1].
579 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
580 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
582 /// imm0_3 predicate - Immediate in the range [0,3].
583 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
584 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
586 /// imm0_4 predicate - Immediate in the range [0,4].
587 def Imm0_4AsmOperand : ImmAsmOperand
590 let DiagnosticType = "ImmRange0_4";
592 def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
593 let ParserMatchClass = Imm0_4AsmOperand;
594 let DecoderMethod = "DecodeImm0_4";
597 /// imm0_7 predicate - Immediate in the range [0,7].
598 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
599 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
600 return Imm >= 0 && Imm < 8;
602 let ParserMatchClass = Imm0_7AsmOperand;
605 /// imm8 predicate - Immediate is exactly 8.
606 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
607 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
608 let ParserMatchClass = Imm8AsmOperand;
611 /// imm16 predicate - Immediate is exactly 16.
612 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
613 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
614 let ParserMatchClass = Imm16AsmOperand;
617 /// imm32 predicate - Immediate is exactly 32.
618 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
619 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
620 let ParserMatchClass = Imm32AsmOperand;
623 /// imm1_7 predicate - Immediate in the range [1,7].
624 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
625 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
626 let ParserMatchClass = Imm1_7AsmOperand;
629 /// imm1_15 predicate - Immediate in the range [1,15].
630 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
631 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
632 let ParserMatchClass = Imm1_15AsmOperand;
635 /// imm1_31 predicate - Immediate in the range [1,31].
636 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
637 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
638 let ParserMatchClass = Imm1_31AsmOperand;
641 /// imm0_15 predicate - Immediate in the range [0,15].
642 def Imm0_15AsmOperand: ImmAsmOperand {
643 let Name = "Imm0_15";
644 let DiagnosticType = "ImmRange0_15";
646 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
647 return Imm >= 0 && Imm < 16;
649 let ParserMatchClass = Imm0_15AsmOperand;
652 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
653 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
654 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
655 return Imm >= 0 && Imm < 32;
657 let ParserMatchClass = Imm0_31AsmOperand;
660 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
661 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
662 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
663 return Imm >= 0 && Imm < 32;
665 let ParserMatchClass = Imm0_32AsmOperand;
668 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
669 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
670 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
671 return Imm >= 0 && Imm < 64;
673 let ParserMatchClass = Imm0_63AsmOperand;
676 /// imm0_255 predicate - Immediate in the range [0,255].
677 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
678 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
679 let ParserMatchClass = Imm0_255AsmOperand;
682 /// imm0_65535 - An immediate is in the range [0.65535].
683 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
684 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
685 return Imm >= 0 && Imm < 65536;
687 let ParserMatchClass = Imm0_65535AsmOperand;
690 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
691 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
692 return -Imm >= 0 && -Imm < 65536;
695 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
696 // a relocatable expression.
698 // FIXME: This really needs a Thumb version separate from the ARM version.
699 // While the range is the same, and can thus use the same match class,
700 // the encoding is different so it should have a different encoder method.
701 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
702 def imm0_65535_expr : Operand<i32> {
703 let EncoderMethod = "getHiLo16ImmOpValue";
704 let ParserMatchClass = Imm0_65535ExprAsmOperand;
707 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
708 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
709 def imm24b : Operand<i32>, ImmLeaf<i32, [{
710 return Imm >= 0 && Imm <= 0xffffff;
712 let ParserMatchClass = Imm24bitAsmOperand;
716 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
718 def BitfieldAsmOperand : AsmOperandClass {
719 let Name = "Bitfield";
720 let ParserMethod = "parseBitfield";
723 def bf_inv_mask_imm : Operand<i32>,
725 return ARM::isBitFieldInvertedMask(N->getZExtValue());
727 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
728 let PrintMethod = "printBitfieldInvMaskImmOperand";
729 let DecoderMethod = "DecodeBitfieldMaskOperand";
730 let ParserMatchClass = BitfieldAsmOperand;
733 def imm1_32_XFORM: SDNodeXForm<imm, [{
734 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
736 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
737 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
738 uint64_t Imm = N->getZExtValue();
739 return Imm > 0 && Imm <= 32;
742 let PrintMethod = "printImmPlusOneOperand";
743 let ParserMatchClass = Imm1_32AsmOperand;
746 def imm1_16_XFORM: SDNodeXForm<imm, [{
747 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
749 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
750 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
752 let PrintMethod = "printImmPlusOneOperand";
753 let ParserMatchClass = Imm1_16AsmOperand;
756 // Define ARM specific addressing modes.
757 // addrmode_imm12 := reg +/- imm12
759 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
760 class AddrMode_Imm12 : Operand<i32>,
761 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
762 // 12-bit immediate operand. Note that instructions using this encode
763 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
764 // immediate values are as normal.
766 let EncoderMethod = "getAddrModeImm12OpValue";
767 let DecoderMethod = "DecodeAddrModeImm12Operand";
768 let ParserMatchClass = MemImm12OffsetAsmOperand;
769 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
772 def addrmode_imm12 : AddrMode_Imm12 {
773 let PrintMethod = "printAddrModeImm12Operand<false>";
776 def addrmode_imm12_pre : AddrMode_Imm12 {
777 let PrintMethod = "printAddrModeImm12Operand<true>";
780 // ldst_so_reg := reg +/- reg shop imm
782 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
783 def ldst_so_reg : Operand<i32>,
784 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
785 let EncoderMethod = "getLdStSORegOpValue";
786 // FIXME: Simplify the printer
787 let PrintMethod = "printAddrMode2Operand";
788 let DecoderMethod = "DecodeSORegMemOperand";
789 let ParserMatchClass = MemRegOffsetAsmOperand;
790 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
793 // postidx_imm8 := +/- [0,255]
796 // {8} 1 is imm8 is non-negative. 0 otherwise.
797 // {7-0} [0,255] imm8 value.
798 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
799 def postidx_imm8 : Operand<i32> {
800 let PrintMethod = "printPostIdxImm8Operand";
801 let ParserMatchClass = PostIdxImm8AsmOperand;
802 let MIOperandInfo = (ops i32imm);
805 // postidx_imm8s4 := +/- [0,1020]
808 // {8} 1 is imm8 is non-negative. 0 otherwise.
809 // {7-0} [0,255] imm8 value, scaled by 4.
810 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
811 def postidx_imm8s4 : Operand<i32> {
812 let PrintMethod = "printPostIdxImm8s4Operand";
813 let ParserMatchClass = PostIdxImm8s4AsmOperand;
814 let MIOperandInfo = (ops i32imm);
818 // postidx_reg := +/- reg
820 def PostIdxRegAsmOperand : AsmOperandClass {
821 let Name = "PostIdxReg";
822 let ParserMethod = "parsePostIdxReg";
824 def postidx_reg : Operand<i32> {
825 let EncoderMethod = "getPostIdxRegOpValue";
826 let DecoderMethod = "DecodePostIdxReg";
827 let PrintMethod = "printPostIdxRegOperand";
828 let ParserMatchClass = PostIdxRegAsmOperand;
829 let MIOperandInfo = (ops GPRnopc, i32imm);
833 // addrmode2 := reg +/- imm12
834 // := reg +/- reg shop imm
836 // FIXME: addrmode2 should be refactored the rest of the way to always
837 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
838 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
839 def addrmode2 : Operand<i32>,
840 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
841 let EncoderMethod = "getAddrMode2OpValue";
842 let PrintMethod = "printAddrMode2Operand";
843 let ParserMatchClass = AddrMode2AsmOperand;
844 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
847 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
848 let Name = "PostIdxRegShifted";
849 let ParserMethod = "parsePostIdxReg";
851 def am2offset_reg : Operand<i32>,
852 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
853 [], [SDNPWantRoot]> {
854 let EncoderMethod = "getAddrMode2OffsetOpValue";
855 let PrintMethod = "printAddrMode2OffsetOperand";
856 // When using this for assembly, it's always as a post-index offset.
857 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
858 let MIOperandInfo = (ops GPRnopc, i32imm);
861 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
862 // the GPR is purely vestigal at this point.
863 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
864 def am2offset_imm : Operand<i32>,
865 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
866 [], [SDNPWantRoot]> {
867 let EncoderMethod = "getAddrMode2OffsetOpValue";
868 let PrintMethod = "printAddrMode2OffsetOperand";
869 let ParserMatchClass = AM2OffsetImmAsmOperand;
870 let MIOperandInfo = (ops GPRnopc, i32imm);
874 // addrmode3 := reg +/- reg
875 // addrmode3 := reg +/- imm8
877 // FIXME: split into imm vs. reg versions.
878 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
879 class AddrMode3 : Operand<i32>,
880 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
881 let EncoderMethod = "getAddrMode3OpValue";
882 let ParserMatchClass = AddrMode3AsmOperand;
883 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
886 def addrmode3 : AddrMode3
888 let PrintMethod = "printAddrMode3Operand<false>";
891 def addrmode3_pre : AddrMode3
893 let PrintMethod = "printAddrMode3Operand<true>";
896 // FIXME: split into imm vs. reg versions.
897 // FIXME: parser method to handle +/- register.
898 def AM3OffsetAsmOperand : AsmOperandClass {
899 let Name = "AM3Offset";
900 let ParserMethod = "parseAM3Offset";
902 def am3offset : Operand<i32>,
903 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
904 [], [SDNPWantRoot]> {
905 let EncoderMethod = "getAddrMode3OffsetOpValue";
906 let PrintMethod = "printAddrMode3OffsetOperand";
907 let ParserMatchClass = AM3OffsetAsmOperand;
908 let MIOperandInfo = (ops GPR, i32imm);
911 // ldstm_mode := {ia, ib, da, db}
913 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
914 let EncoderMethod = "getLdStmModeOpValue";
915 let PrintMethod = "printLdStmModeOperand";
918 // addrmode5 := reg +/- imm8*4
920 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
921 class AddrMode5 : Operand<i32>,
922 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
923 let EncoderMethod = "getAddrMode5OpValue";
924 let DecoderMethod = "DecodeAddrMode5Operand";
925 let ParserMatchClass = AddrMode5AsmOperand;
926 let MIOperandInfo = (ops GPR:$base, i32imm);
929 def addrmode5 : AddrMode5 {
930 let PrintMethod = "printAddrMode5Operand<false>";
933 def addrmode5_pre : AddrMode5 {
934 let PrintMethod = "printAddrMode5Operand<true>";
937 // addrmode6 := reg with optional alignment
939 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
940 def addrmode6 : Operand<i32>,
941 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
942 let PrintMethod = "printAddrMode6Operand";
943 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
944 let EncoderMethod = "getAddrMode6AddressOpValue";
945 let DecoderMethod = "DecodeAddrMode6Operand";
946 let ParserMatchClass = AddrMode6AsmOperand;
949 def am6offset : Operand<i32>,
950 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
951 [], [SDNPWantRoot]> {
952 let PrintMethod = "printAddrMode6OffsetOperand";
953 let MIOperandInfo = (ops GPR);
954 let EncoderMethod = "getAddrMode6OffsetOpValue";
955 let DecoderMethod = "DecodeGPRRegisterClass";
958 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
959 // (single element from one lane) for size 32.
960 def addrmode6oneL32 : Operand<i32>,
961 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
962 let PrintMethod = "printAddrMode6Operand";
963 let MIOperandInfo = (ops GPR:$addr, i32imm);
964 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
967 // Special version of addrmode6 to handle alignment encoding for VLD-dup
968 // instructions, specifically VLD4-dup.
969 def addrmode6dup : Operand<i32>,
970 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
971 let PrintMethod = "printAddrMode6Operand";
972 let MIOperandInfo = (ops GPR:$addr, i32imm);
973 let EncoderMethod = "getAddrMode6DupAddressOpValue";
974 // FIXME: This is close, but not quite right. The alignment specifier is
976 let ParserMatchClass = AddrMode6AsmOperand;
979 // addrmodepc := pc + reg
981 def addrmodepc : Operand<i32>,
982 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
983 let PrintMethod = "printAddrModePCOperand";
984 let MIOperandInfo = (ops GPR, i32imm);
987 // addr_offset_none := reg
989 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
990 def addr_offset_none : Operand<i32>,
991 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
992 let PrintMethod = "printAddrMode7Operand";
993 let DecoderMethod = "DecodeAddrMode7Operand";
994 let ParserMatchClass = MemNoOffsetAsmOperand;
995 let MIOperandInfo = (ops GPR:$base);
998 def nohash_imm : Operand<i32> {
999 let PrintMethod = "printNoHashImmediate";
1002 def CoprocNumAsmOperand : AsmOperandClass {
1003 let Name = "CoprocNum";
1004 let ParserMethod = "parseCoprocNumOperand";
1006 def p_imm : Operand<i32> {
1007 let PrintMethod = "printPImmediate";
1008 let ParserMatchClass = CoprocNumAsmOperand;
1009 let DecoderMethod = "DecodeCoprocessor";
1012 def CoprocRegAsmOperand : AsmOperandClass {
1013 let Name = "CoprocReg";
1014 let ParserMethod = "parseCoprocRegOperand";
1016 def c_imm : Operand<i32> {
1017 let PrintMethod = "printCImmediate";
1018 let ParserMatchClass = CoprocRegAsmOperand;
1020 def CoprocOptionAsmOperand : AsmOperandClass {
1021 let Name = "CoprocOption";
1022 let ParserMethod = "parseCoprocOptionOperand";
1024 def coproc_option_imm : Operand<i32> {
1025 let PrintMethod = "printCoprocOptionImm";
1026 let ParserMatchClass = CoprocOptionAsmOperand;
1029 //===----------------------------------------------------------------------===//
1031 include "ARMInstrFormats.td"
1033 //===----------------------------------------------------------------------===//
1034 // Multiclass helpers...
1037 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1038 /// binop that produces a value.
1039 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1040 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1041 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1042 PatFrag opnode, bit Commutable = 0> {
1043 // The register-immediate version is re-materializable. This is useful
1044 // in particular for taking the address of a local.
1045 let isReMaterializable = 1 in {
1046 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1047 iii, opc, "\t$Rd, $Rn, $imm",
1048 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1049 Sched<[WriteALU, ReadALU]> {
1054 let Inst{19-16} = Rn;
1055 let Inst{15-12} = Rd;
1056 let Inst{11-0} = imm;
1059 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1060 iir, opc, "\t$Rd, $Rn, $Rm",
1061 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1062 Sched<[WriteALU, ReadALU, ReadALU]> {
1067 let isCommutable = Commutable;
1068 let Inst{19-16} = Rn;
1069 let Inst{15-12} = Rd;
1070 let Inst{11-4} = 0b00000000;
1074 def rsi : AsI1<opcod, (outs GPR:$Rd),
1075 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1076 iis, opc, "\t$Rd, $Rn, $shift",
1077 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1078 Sched<[WriteALUsi, ReadALU]> {
1083 let Inst{19-16} = Rn;
1084 let Inst{15-12} = Rd;
1085 let Inst{11-5} = shift{11-5};
1087 let Inst{3-0} = shift{3-0};
1090 def rsr : AsI1<opcod, (outs GPR:$Rd),
1091 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1092 iis, opc, "\t$Rd, $Rn, $shift",
1093 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1094 Sched<[WriteALUsr, ReadALUsr]> {
1099 let Inst{19-16} = Rn;
1100 let Inst{15-12} = Rd;
1101 let Inst{11-8} = shift{11-8};
1103 let Inst{6-5} = shift{6-5};
1105 let Inst{3-0} = shift{3-0};
1109 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1110 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1111 /// it is equivalent to the AsI1_bin_irs counterpart.
1112 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1113 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1114 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1115 PatFrag opnode, bit Commutable = 0> {
1116 // The register-immediate version is re-materializable. This is useful
1117 // in particular for taking the address of a local.
1118 let isReMaterializable = 1 in {
1119 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1120 iii, opc, "\t$Rd, $Rn, $imm",
1121 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1122 Sched<[WriteALU, ReadALU]> {
1127 let Inst{19-16} = Rn;
1128 let Inst{15-12} = Rd;
1129 let Inst{11-0} = imm;
1132 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1133 iir, opc, "\t$Rd, $Rn, $Rm",
1134 [/* pattern left blank */]>,
1135 Sched<[WriteALU, ReadALU, ReadALU]> {
1139 let Inst{11-4} = 0b00000000;
1142 let Inst{15-12} = Rd;
1143 let Inst{19-16} = Rn;
1146 def rsi : AsI1<opcod, (outs GPR:$Rd),
1147 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1148 iis, opc, "\t$Rd, $Rn, $shift",
1149 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1150 Sched<[WriteALUsi, ReadALU]> {
1155 let Inst{19-16} = Rn;
1156 let Inst{15-12} = Rd;
1157 let Inst{11-5} = shift{11-5};
1159 let Inst{3-0} = shift{3-0};
1162 def rsr : AsI1<opcod, (outs GPR:$Rd),
1163 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1164 iis, opc, "\t$Rd, $Rn, $shift",
1165 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1166 Sched<[WriteALUsr, ReadALUsr]> {
1171 let Inst{19-16} = Rn;
1172 let Inst{15-12} = Rd;
1173 let Inst{11-8} = shift{11-8};
1175 let Inst{6-5} = shift{6-5};
1177 let Inst{3-0} = shift{3-0};
1181 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1183 /// These opcodes will be converted to the real non-S opcodes by
1184 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1185 let hasPostISelHook = 1, Defs = [CPSR] in {
1186 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1187 InstrItinClass iis, PatFrag opnode,
1188 bit Commutable = 0> {
1189 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1191 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1192 Sched<[WriteALU, ReadALU]>;
1194 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1196 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1197 Sched<[WriteALU, ReadALU, ReadALU]> {
1198 let isCommutable = Commutable;
1200 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1201 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1203 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1204 so_reg_imm:$shift))]>,
1205 Sched<[WriteALUsi, ReadALU]>;
1207 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1208 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1210 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1211 so_reg_reg:$shift))]>,
1212 Sched<[WriteALUSsr, ReadALUsr]>;
1216 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1217 /// operands are reversed.
1218 let hasPostISelHook = 1, Defs = [CPSR] in {
1219 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1220 InstrItinClass iis, PatFrag opnode,
1221 bit Commutable = 0> {
1222 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1224 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1225 Sched<[WriteALU, ReadALU]>;
1227 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1228 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1230 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1232 Sched<[WriteALUsi, ReadALU]>;
1234 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1235 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1237 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1239 Sched<[WriteALUSsr, ReadALUsr]>;
1243 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1244 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1245 /// a explicit result, only implicitly set CPSR.
1246 let isCompare = 1, Defs = [CPSR] in {
1247 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1248 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1249 PatFrag opnode, bit Commutable = 0> {
1250 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1252 [(opnode GPR:$Rn, so_imm:$imm)]>,
1253 Sched<[WriteCMP, ReadALU]> {
1258 let Inst{19-16} = Rn;
1259 let Inst{15-12} = 0b0000;
1260 let Inst{11-0} = imm;
1262 let Unpredictable{15-12} = 0b1111;
1264 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1266 [(opnode GPR:$Rn, GPR:$Rm)]>,
1267 Sched<[WriteCMP, ReadALU, ReadALU]> {
1270 let isCommutable = Commutable;
1273 let Inst{19-16} = Rn;
1274 let Inst{15-12} = 0b0000;
1275 let Inst{11-4} = 0b00000000;
1278 let Unpredictable{15-12} = 0b1111;
1280 def rsi : AI1<opcod, (outs),
1281 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1282 opc, "\t$Rn, $shift",
1283 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1284 Sched<[WriteCMPsi, ReadALU]> {
1289 let Inst{19-16} = Rn;
1290 let Inst{15-12} = 0b0000;
1291 let Inst{11-5} = shift{11-5};
1293 let Inst{3-0} = shift{3-0};
1295 let Unpredictable{15-12} = 0b1111;
1297 def rsr : AI1<opcod, (outs),
1298 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1299 opc, "\t$Rn, $shift",
1300 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1301 Sched<[WriteCMPsr, ReadALU]> {
1306 let Inst{19-16} = Rn;
1307 let Inst{15-12} = 0b0000;
1308 let Inst{11-8} = shift{11-8};
1310 let Inst{6-5} = shift{6-5};
1312 let Inst{3-0} = shift{3-0};
1314 let Unpredictable{15-12} = 0b1111;
1320 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1321 /// register and one whose operand is a register rotated by 8/16/24.
1322 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1323 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1324 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1325 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1326 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1327 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1331 let Inst{19-16} = 0b1111;
1332 let Inst{15-12} = Rd;
1333 let Inst{11-10} = rot;
1337 class AI_ext_rrot_np<bits<8> opcod, string opc>
1338 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1339 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1340 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1342 let Inst{19-16} = 0b1111;
1343 let Inst{11-10} = rot;
1346 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1347 /// register and one whose operand is a register rotated by 8/16/24.
1348 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1349 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1350 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1351 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1352 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1353 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1358 let Inst{19-16} = Rn;
1359 let Inst{15-12} = Rd;
1360 let Inst{11-10} = rot;
1361 let Inst{9-4} = 0b000111;
1365 class AI_exta_rrot_np<bits<8> opcod, string opc>
1366 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1367 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1368 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1371 let Inst{19-16} = Rn;
1372 let Inst{11-10} = rot;
1375 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1376 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1377 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1378 bit Commutable = 0> {
1379 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1380 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1381 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1382 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1384 Sched<[WriteALU, ReadALU]> {
1389 let Inst{15-12} = Rd;
1390 let Inst{19-16} = Rn;
1391 let Inst{11-0} = imm;
1393 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1394 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1395 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1397 Sched<[WriteALU, ReadALU, ReadALU]> {
1401 let Inst{11-4} = 0b00000000;
1403 let isCommutable = Commutable;
1405 let Inst{15-12} = Rd;
1406 let Inst{19-16} = Rn;
1408 def rsi : AsI1<opcod, (outs GPR:$Rd),
1409 (ins GPR:$Rn, so_reg_imm:$shift),
1410 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1411 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1413 Sched<[WriteALUsi, ReadALU]> {
1418 let Inst{19-16} = Rn;
1419 let Inst{15-12} = Rd;
1420 let Inst{11-5} = shift{11-5};
1422 let Inst{3-0} = shift{3-0};
1424 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1425 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1426 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1427 [(set GPRnopc:$Rd, CPSR,
1428 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1430 Sched<[WriteALUsr, ReadALUsr]> {
1435 let Inst{19-16} = Rn;
1436 let Inst{15-12} = Rd;
1437 let Inst{11-8} = shift{11-8};
1439 let Inst{6-5} = shift{6-5};
1441 let Inst{3-0} = shift{3-0};
1446 /// AI1_rsc_irs - Define instructions and patterns for rsc
1447 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1448 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1449 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1450 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1451 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1452 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1454 Sched<[WriteALU, ReadALU]> {
1459 let Inst{15-12} = Rd;
1460 let Inst{19-16} = Rn;
1461 let Inst{11-0} = imm;
1463 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1464 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1465 [/* pattern left blank */]>,
1466 Sched<[WriteALU, ReadALU, ReadALU]> {
1470 let Inst{11-4} = 0b00000000;
1473 let Inst{15-12} = Rd;
1474 let Inst{19-16} = Rn;
1476 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1477 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1478 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1480 Sched<[WriteALUsi, ReadALU]> {
1485 let Inst{19-16} = Rn;
1486 let Inst{15-12} = Rd;
1487 let Inst{11-5} = shift{11-5};
1489 let Inst{3-0} = shift{3-0};
1491 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1492 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1493 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1495 Sched<[WriteALUsr, ReadALUsr]> {
1500 let Inst{19-16} = Rn;
1501 let Inst{15-12} = Rd;
1502 let Inst{11-8} = shift{11-8};
1504 let Inst{6-5} = shift{6-5};
1506 let Inst{3-0} = shift{3-0};
1511 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1512 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1513 InstrItinClass iir, PatFrag opnode> {
1514 // Note: We use the complex addrmode_imm12 rather than just an input
1515 // GPR and a constrained immediate so that we can use this to match
1516 // frame index references and avoid matching constant pool references.
1517 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1518 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1519 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1522 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1523 let Inst{19-16} = addr{16-13}; // Rn
1524 let Inst{15-12} = Rt;
1525 let Inst{11-0} = addr{11-0}; // imm12
1527 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1528 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1529 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1532 let shift{4} = 0; // Inst{4} = 0
1533 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1534 let Inst{19-16} = shift{16-13}; // Rn
1535 let Inst{15-12} = Rt;
1536 let Inst{11-0} = shift{11-0};
1541 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1542 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1543 InstrItinClass iir, PatFrag opnode> {
1544 // Note: We use the complex addrmode_imm12 rather than just an input
1545 // GPR and a constrained immediate so that we can use this to match
1546 // frame index references and avoid matching constant pool references.
1547 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1548 (ins addrmode_imm12:$addr),
1549 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1550 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1553 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1554 let Inst{19-16} = addr{16-13}; // Rn
1555 let Inst{15-12} = Rt;
1556 let Inst{11-0} = addr{11-0}; // imm12
1558 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1559 (ins ldst_so_reg:$shift),
1560 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1561 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1564 let shift{4} = 0; // Inst{4} = 0
1565 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1566 let Inst{19-16} = shift{16-13}; // Rn
1567 let Inst{15-12} = Rt;
1568 let Inst{11-0} = shift{11-0};
1574 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1575 InstrItinClass iir, PatFrag opnode> {
1576 // Note: We use the complex addrmode_imm12 rather than just an input
1577 // GPR and a constrained immediate so that we can use this to match
1578 // frame index references and avoid matching constant pool references.
1579 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1580 (ins GPR:$Rt, addrmode_imm12:$addr),
1581 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1582 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1585 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1586 let Inst{19-16} = addr{16-13}; // Rn
1587 let Inst{15-12} = Rt;
1588 let Inst{11-0} = addr{11-0}; // imm12
1590 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1591 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1592 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1595 let shift{4} = 0; // Inst{4} = 0
1596 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1597 let Inst{19-16} = shift{16-13}; // Rn
1598 let Inst{15-12} = Rt;
1599 let Inst{11-0} = shift{11-0};
1603 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1604 InstrItinClass iir, PatFrag opnode> {
1605 // Note: We use the complex addrmode_imm12 rather than just an input
1606 // GPR and a constrained immediate so that we can use this to match
1607 // frame index references and avoid matching constant pool references.
1608 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1609 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1610 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1611 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1614 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1615 let Inst{19-16} = addr{16-13}; // Rn
1616 let Inst{15-12} = Rt;
1617 let Inst{11-0} = addr{11-0}; // imm12
1619 def rs : AI2ldst<0b011, 0, isByte, (outs),
1620 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1621 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1622 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1625 let shift{4} = 0; // Inst{4} = 0
1626 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1627 let Inst{19-16} = shift{16-13}; // Rn
1628 let Inst{15-12} = Rt;
1629 let Inst{11-0} = shift{11-0};
1634 //===----------------------------------------------------------------------===//
1636 //===----------------------------------------------------------------------===//
1638 //===----------------------------------------------------------------------===//
1639 // Miscellaneous Instructions.
1642 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1643 /// the function. The first operand is the ID# for this instruction, the second
1644 /// is the index into the MachineConstantPool that this is, the third is the
1645 /// size in bytes of this constant pool entry.
1646 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1647 def CONSTPOOL_ENTRY :
1648 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1649 i32imm:$size), NoItinerary, []>;
1651 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1652 // from removing one half of the matched pairs. That breaks PEI, which assumes
1653 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1654 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1655 def ADJCALLSTACKUP :
1656 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1657 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1659 def ADJCALLSTACKDOWN :
1660 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1661 [(ARMcallseq_start timm:$amt)]>;
1664 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1665 // (These pseudos use a hand-written selection code).
1666 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1667 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1668 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1670 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1671 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1673 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1674 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1676 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1677 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1679 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1680 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1682 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1683 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1685 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1686 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1688 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1689 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1690 GPR:$set1, GPR:$set2),
1692 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1693 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1695 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1696 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1698 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1699 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1701 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1702 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1706 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1707 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1709 let Inst{27-3} = 0b0011001000001111000000000;
1710 let Inst{2-0} = imm;
1713 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1714 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1715 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1716 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1717 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1719 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1720 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1725 let Inst{15-12} = Rd;
1726 let Inst{19-16} = Rn;
1727 let Inst{27-20} = 0b01101000;
1728 let Inst{7-4} = 0b1011;
1729 let Inst{11-8} = 0b1111;
1730 let Unpredictable{11-8} = 0b1111;
1733 // The 16-bit operand $val can be used by a debugger to store more information
1734 // about the breakpoint.
1735 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1736 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1738 let Inst{3-0} = val{3-0};
1739 let Inst{19-8} = val{15-4};
1740 let Inst{27-20} = 0b00010010;
1741 let Inst{31-28} = 0xe; // AL
1742 let Inst{7-4} = 0b0111;
1745 // Change Processor State
1746 // FIXME: We should use InstAlias to handle the optional operands.
1747 class CPS<dag iops, string asm_ops>
1748 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1749 []>, Requires<[IsARM]> {
1755 let Inst{31-28} = 0b1111;
1756 let Inst{27-20} = 0b00010000;
1757 let Inst{19-18} = imod;
1758 let Inst{17} = M; // Enabled if mode is set;
1759 let Inst{16-9} = 0b00000000;
1760 let Inst{8-6} = iflags;
1762 let Inst{4-0} = mode;
1765 let DecoderMethod = "DecodeCPSInstruction" in {
1767 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1768 "$imod\t$iflags, $mode">;
1769 let mode = 0, M = 0 in
1770 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1772 let imod = 0, iflags = 0, M = 1 in
1773 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1776 // Preload signals the memory system of possible future data/instruction access.
1777 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1779 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1780 !strconcat(opc, "\t$addr"),
1781 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1782 Sched<[WritePreLd]> {
1785 let Inst{31-26} = 0b111101;
1786 let Inst{25} = 0; // 0 for immediate form
1787 let Inst{24} = data;
1788 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1789 let Inst{22} = read;
1790 let Inst{21-20} = 0b01;
1791 let Inst{19-16} = addr{16-13}; // Rn
1792 let Inst{15-12} = 0b1111;
1793 let Inst{11-0} = addr{11-0}; // imm12
1796 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1797 !strconcat(opc, "\t$shift"),
1798 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1799 Sched<[WritePreLd]> {
1801 let Inst{31-26} = 0b111101;
1802 let Inst{25} = 1; // 1 for register form
1803 let Inst{24} = data;
1804 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1805 let Inst{22} = read;
1806 let Inst{21-20} = 0b01;
1807 let Inst{19-16} = shift{16-13}; // Rn
1808 let Inst{15-12} = 0b1111;
1809 let Inst{11-0} = shift{11-0};
1814 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1815 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1816 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1818 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1819 "setend\t$end", []>, Requires<[IsARM]> {
1821 let Inst{31-10} = 0b1111000100000001000000;
1826 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1827 []>, Requires<[IsARM, HasV7]> {
1829 let Inst{27-4} = 0b001100100000111100001111;
1830 let Inst{3-0} = opt;
1834 * A5.4 Permanently UNDEFINED instructions.
1836 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1837 * Other UDF encodings generate SIGILL.
1839 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1841 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1843 * 1101 1110 iiii iiii
1844 * It uses the following encoding:
1845 * 1110 0111 1111 1110 1101 1110 1111 0000
1846 * - In ARM: UDF #60896;
1847 * - In Thumb: UDF #254 followed by a branch-to-self.
1849 let isBarrier = 1, isTerminator = 1 in
1850 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1852 Requires<[IsARM,UseNaClTrap]> {
1853 let Inst = 0xe7fedef0;
1855 let isBarrier = 1, isTerminator = 1 in
1856 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1858 Requires<[IsARM,DontUseNaClTrap]> {
1859 let Inst = 0xe7ffdefe;
1862 // Address computation and loads and stores in PIC mode.
1863 let isNotDuplicable = 1 in {
1864 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1866 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1867 Sched<[WriteALU, ReadALU]>;
1869 let AddedComplexity = 10 in {
1870 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1872 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1874 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1876 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1878 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1880 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1882 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1884 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1886 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1888 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1890 let AddedComplexity = 10 in {
1891 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1892 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1894 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1895 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1896 addrmodepc:$addr)]>;
1898 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1899 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1901 } // isNotDuplicable = 1
1904 // LEApcrel - Load a pc-relative address into a register without offending the
1906 let neverHasSideEffects = 1, isReMaterializable = 1 in
1907 // The 'adr' mnemonic encodes differently if the label is before or after
1908 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1909 // know until then which form of the instruction will be used.
1910 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1911 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1912 Sched<[WriteALU, ReadALU]> {
1915 let Inst{27-25} = 0b001;
1917 let Inst{23-22} = label{13-12};
1920 let Inst{19-16} = 0b1111;
1921 let Inst{15-12} = Rd;
1922 let Inst{11-0} = label{11-0};
1925 let hasSideEffects = 1 in {
1926 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1927 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1929 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1930 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1931 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1934 //===----------------------------------------------------------------------===//
1935 // Control Flow Instructions.
1938 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1940 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1941 "bx", "\tlr", [(ARMretflag)]>,
1942 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1943 let Inst{27-0} = 0b0001001011111111111100011110;
1947 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1948 "mov", "\tpc, lr", [(ARMretflag)]>,
1949 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1950 let Inst{27-0} = 0b0001101000001111000000001110;
1954 // Indirect branches
1955 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1957 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1958 [(brind GPR:$dst)]>,
1959 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1961 let Inst{31-4} = 0b1110000100101111111111110001;
1962 let Inst{3-0} = dst;
1965 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1966 "bx", "\t$dst", [/* pattern left blank */]>,
1967 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1969 let Inst{27-4} = 0b000100101111111111110001;
1970 let Inst{3-0} = dst;
1974 // SP is marked as a use to prevent stack-pointer assignments that appear
1975 // immediately before calls from potentially appearing dead.
1977 // FIXME: Do we really need a non-predicated version? If so, it should
1978 // at least be a pseudo instruction expanding to the predicated version
1979 // at MC lowering time.
1980 Defs = [LR], Uses = [SP] in {
1981 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1982 IIC_Br, "bl\t$func",
1983 [(ARMcall tglobaladdr:$func)]>,
1984 Requires<[IsARM]>, Sched<[WriteBrL]> {
1985 let Inst{31-28} = 0b1110;
1987 let Inst{23-0} = func;
1988 let DecoderMethod = "DecodeBranchImmInstruction";
1991 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1992 IIC_Br, "bl", "\t$func",
1993 [(ARMcall_pred tglobaladdr:$func)]>,
1994 Requires<[IsARM]>, Sched<[WriteBrL]> {
1996 let Inst{23-0} = func;
1997 let DecoderMethod = "DecodeBranchImmInstruction";
2001 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2002 IIC_Br, "blx\t$func",
2003 [(ARMcall GPR:$func)]>,
2004 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2006 let Inst{31-4} = 0b1110000100101111111111110011;
2007 let Inst{3-0} = func;
2010 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2011 IIC_Br, "blx", "\t$func",
2012 [(ARMcall_pred GPR:$func)]>,
2013 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2015 let Inst{27-4} = 0b000100101111111111110011;
2016 let Inst{3-0} = func;
2020 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2021 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2022 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2023 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2026 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2027 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2028 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2030 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2031 // return stack predictor.
2032 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2033 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2034 Requires<[IsARM]>, Sched<[WriteBr]>;
2037 let isBranch = 1, isTerminator = 1 in {
2038 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2039 // a two-value operand where a dag node expects two operands. :(
2040 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2041 IIC_Br, "b", "\t$target",
2042 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2045 let Inst{23-0} = target;
2046 let DecoderMethod = "DecodeBranchImmInstruction";
2049 let isBarrier = 1 in {
2050 // B is "predicable" since it's just a Bcc with an 'always' condition.
2051 let isPredicable = 1 in
2052 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2053 // should be sufficient.
2054 // FIXME: Is B really a Barrier? That doesn't seem right.
2055 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2056 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2059 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2060 def BR_JTr : ARMPseudoInst<(outs),
2061 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2063 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2065 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2066 // into i12 and rs suffixed versions.
2067 def BR_JTm : ARMPseudoInst<(outs),
2068 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2070 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2071 imm:$id)]>, Sched<[WriteBrTbl]>;
2072 def BR_JTadd : ARMPseudoInst<(outs),
2073 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2075 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2076 imm:$id)]>, Sched<[WriteBrTbl]>;
2077 } // isNotDuplicable = 1, isIndirectBranch = 1
2083 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2084 "blx\t$target", []>,
2085 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2086 let Inst{31-25} = 0b1111101;
2088 let Inst{23-0} = target{24-1};
2089 let Inst{24} = target{0};
2092 // Branch and Exchange Jazelle
2093 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2094 [/* pattern left blank */]>, Sched<[WriteBr]> {
2096 let Inst{23-20} = 0b0010;
2097 let Inst{19-8} = 0xfff;
2098 let Inst{7-4} = 0b0010;
2099 let Inst{3-0} = func;
2104 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2105 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2108 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2111 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2113 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2114 Requires<[IsARM]>, Sched<[WriteBr]>;
2116 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2118 (BX GPR:$dst)>, Sched<[WriteBr]>,
2122 // Secure Monitor Call is a system instruction.
2123 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2124 []>, Requires<[IsARM, HasTrustZone]> {
2126 let Inst{23-4} = 0b01100000000000000111;
2127 let Inst{3-0} = opt;
2130 // Supervisor Call (Software Interrupt)
2131 let isCall = 1, Uses = [SP] in {
2132 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2135 let Inst{23-0} = svc;
2139 // Store Return State
2140 class SRSI<bit wb, string asm>
2141 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2142 NoItinerary, asm, "", []> {
2144 let Inst{31-28} = 0b1111;
2145 let Inst{27-25} = 0b100;
2149 let Inst{19-16} = 0b1101; // SP
2150 let Inst{15-5} = 0b00000101000;
2151 let Inst{4-0} = mode;
2154 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2155 let Inst{24-23} = 0;
2157 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2158 let Inst{24-23} = 0;
2160 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2161 let Inst{24-23} = 0b10;
2163 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2164 let Inst{24-23} = 0b10;
2166 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2167 let Inst{24-23} = 0b01;
2169 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2170 let Inst{24-23} = 0b01;
2172 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2173 let Inst{24-23} = 0b11;
2175 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2176 let Inst{24-23} = 0b11;
2179 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2180 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2182 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2183 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2185 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2186 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2188 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2189 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2191 // Return From Exception
2192 class RFEI<bit wb, string asm>
2193 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2194 NoItinerary, asm, "", []> {
2196 let Inst{31-28} = 0b1111;
2197 let Inst{27-25} = 0b100;
2201 let Inst{19-16} = Rn;
2202 let Inst{15-0} = 0xa00;
2205 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2206 let Inst{24-23} = 0;
2208 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2209 let Inst{24-23} = 0;
2211 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2212 let Inst{24-23} = 0b10;
2214 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2215 let Inst{24-23} = 0b10;
2217 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2218 let Inst{24-23} = 0b01;
2220 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2221 let Inst{24-23} = 0b01;
2223 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2224 let Inst{24-23} = 0b11;
2226 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2227 let Inst{24-23} = 0b11;
2230 //===----------------------------------------------------------------------===//
2231 // Load / Store Instructions.
2237 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2238 UnOpFrag<(load node:$Src)>>;
2239 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2240 UnOpFrag<(zextloadi8 node:$Src)>>;
2241 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2242 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2243 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2244 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2246 // Special LDR for loads from non-pc-relative constpools.
2247 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2248 isReMaterializable = 1, isCodeGenOnly = 1 in
2249 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2250 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2254 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2255 let Inst{19-16} = 0b1111;
2256 let Inst{15-12} = Rt;
2257 let Inst{11-0} = addr{11-0}; // imm12
2260 // Loads with zero extension
2261 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2262 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2263 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2265 // Loads with sign extension
2266 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2267 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2268 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2270 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2271 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2272 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2274 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2276 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2277 (ins addrmode3:$addr), LdMiscFrm,
2278 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2279 []>, Requires<[IsARM, HasV5TE]>;
2283 multiclass AI2_ldridx<bit isByte, string opc,
2284 InstrItinClass iii, InstrItinClass iir> {
2285 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2286 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2287 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2290 let Inst{23} = addr{12};
2291 let Inst{19-16} = addr{16-13};
2292 let Inst{11-0} = addr{11-0};
2293 let DecoderMethod = "DecodeLDRPreImm";
2294 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2297 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2298 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2299 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2302 let Inst{23} = addr{12};
2303 let Inst{19-16} = addr{16-13};
2304 let Inst{11-0} = addr{11-0};
2306 let DecoderMethod = "DecodeLDRPreReg";
2307 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2310 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2311 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2312 IndexModePost, LdFrm, iir,
2313 opc, "\t$Rt, $addr, $offset",
2314 "$addr.base = $Rn_wb", []> {
2320 let Inst{23} = offset{12};
2321 let Inst{19-16} = addr;
2322 let Inst{11-0} = offset{11-0};
2325 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2328 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2329 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2330 IndexModePost, LdFrm, iii,
2331 opc, "\t$Rt, $addr, $offset",
2332 "$addr.base = $Rn_wb", []> {
2338 let Inst{23} = offset{12};
2339 let Inst{19-16} = addr;
2340 let Inst{11-0} = offset{11-0};
2342 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2347 let mayLoad = 1, neverHasSideEffects = 1 in {
2348 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2349 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2350 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2351 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2354 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2355 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2356 (ins addrmode3_pre:$addr), IndexModePre,
2358 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2360 let Inst{23} = addr{8}; // U bit
2361 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2362 let Inst{19-16} = addr{12-9}; // Rn
2363 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2364 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2365 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2366 let DecoderMethod = "DecodeAddrMode3Instruction";
2368 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2369 (ins addr_offset_none:$addr, am3offset:$offset),
2370 IndexModePost, LdMiscFrm, itin,
2371 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2375 let Inst{23} = offset{8}; // U bit
2376 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2377 let Inst{19-16} = addr;
2378 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2379 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2380 let DecoderMethod = "DecodeAddrMode3Instruction";
2384 let mayLoad = 1, neverHasSideEffects = 1 in {
2385 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2386 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2387 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2388 let hasExtraDefRegAllocReq = 1 in {
2389 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2390 (ins addrmode3_pre:$addr), IndexModePre,
2391 LdMiscFrm, IIC_iLoad_d_ru,
2392 "ldrd", "\t$Rt, $Rt2, $addr!",
2393 "$addr.base = $Rn_wb", []> {
2395 let Inst{23} = addr{8}; // U bit
2396 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2397 let Inst{19-16} = addr{12-9}; // Rn
2398 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2399 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2400 let DecoderMethod = "DecodeAddrMode3Instruction";
2401 let AsmMatchConverter = "cvtLdrdPre";
2403 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2404 (ins addr_offset_none:$addr, am3offset:$offset),
2405 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2406 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2407 "$addr.base = $Rn_wb", []> {
2410 let Inst{23} = offset{8}; // U bit
2411 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2412 let Inst{19-16} = addr;
2413 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2414 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2415 let DecoderMethod = "DecodeAddrMode3Instruction";
2417 } // hasExtraDefRegAllocReq = 1
2418 } // mayLoad = 1, neverHasSideEffects = 1
2420 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2421 let mayLoad = 1, neverHasSideEffects = 1 in {
2422 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2423 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2424 IndexModePost, LdFrm, IIC_iLoad_ru,
2425 "ldrt", "\t$Rt, $addr, $offset",
2426 "$addr.base = $Rn_wb", []> {
2432 let Inst{23} = offset{12};
2433 let Inst{21} = 1; // overwrite
2434 let Inst{19-16} = addr;
2435 let Inst{11-5} = offset{11-5};
2437 let Inst{3-0} = offset{3-0};
2438 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2441 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2442 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2443 IndexModePost, LdFrm, IIC_iLoad_ru,
2444 "ldrt", "\t$Rt, $addr, $offset",
2445 "$addr.base = $Rn_wb", []> {
2451 let Inst{23} = offset{12};
2452 let Inst{21} = 1; // overwrite
2453 let Inst{19-16} = addr;
2454 let Inst{11-0} = offset{11-0};
2455 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2458 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2459 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2460 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2461 "ldrbt", "\t$Rt, $addr, $offset",
2462 "$addr.base = $Rn_wb", []> {
2468 let Inst{23} = offset{12};
2469 let Inst{21} = 1; // overwrite
2470 let Inst{19-16} = addr;
2471 let Inst{11-5} = offset{11-5};
2473 let Inst{3-0} = offset{3-0};
2474 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2477 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2478 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2479 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2480 "ldrbt", "\t$Rt, $addr, $offset",
2481 "$addr.base = $Rn_wb", []> {
2487 let Inst{23} = offset{12};
2488 let Inst{21} = 1; // overwrite
2489 let Inst{19-16} = addr;
2490 let Inst{11-0} = offset{11-0};
2491 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2494 multiclass AI3ldrT<bits<4> op, string opc> {
2495 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2496 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2497 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2498 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2500 let Inst{23} = offset{8};
2502 let Inst{11-8} = offset{7-4};
2503 let Inst{3-0} = offset{3-0};
2504 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2506 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2507 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2508 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2509 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2511 let Inst{23} = Rm{4};
2514 let Unpredictable{11-8} = 0b1111;
2515 let Inst{3-0} = Rm{3-0};
2516 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2517 let DecoderMethod = "DecodeLDR";
2521 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2522 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2523 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2528 // Stores with truncate
2529 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2530 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2531 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2534 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2535 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2536 StMiscFrm, IIC_iStore_d_r,
2537 "strd", "\t$Rt, $src2, $addr", []>,
2538 Requires<[IsARM, HasV5TE]> {
2543 multiclass AI2_stridx<bit isByte, string opc,
2544 InstrItinClass iii, InstrItinClass iir> {
2545 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2546 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2548 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2551 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2552 let Inst{19-16} = addr{16-13}; // Rn
2553 let Inst{11-0} = addr{11-0}; // imm12
2554 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2555 let DecoderMethod = "DecodeSTRPreImm";
2558 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2559 (ins GPR:$Rt, ldst_so_reg:$addr),
2560 IndexModePre, StFrm, iir,
2561 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2564 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2565 let Inst{19-16} = addr{16-13}; // Rn
2566 let Inst{11-0} = addr{11-0};
2567 let Inst{4} = 0; // Inst{4} = 0
2568 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2569 let DecoderMethod = "DecodeSTRPreReg";
2571 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2572 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2573 IndexModePost, StFrm, iir,
2574 opc, "\t$Rt, $addr, $offset",
2575 "$addr.base = $Rn_wb", []> {
2581 let Inst{23} = offset{12};
2582 let Inst{19-16} = addr;
2583 let Inst{11-0} = offset{11-0};
2586 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2589 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2590 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2591 IndexModePost, StFrm, iii,
2592 opc, "\t$Rt, $addr, $offset",
2593 "$addr.base = $Rn_wb", []> {
2599 let Inst{23} = offset{12};
2600 let Inst{19-16} = addr;
2601 let Inst{11-0} = offset{11-0};
2603 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2607 let mayStore = 1, neverHasSideEffects = 1 in {
2608 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2609 // IIC_iStore_siu depending on whether it the offset register is shifted.
2610 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2611 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2614 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2615 am2offset_reg:$offset),
2616 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2617 am2offset_reg:$offset)>;
2618 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2619 am2offset_imm:$offset),
2620 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2621 am2offset_imm:$offset)>;
2622 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2623 am2offset_reg:$offset),
2624 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2625 am2offset_reg:$offset)>;
2626 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2627 am2offset_imm:$offset),
2628 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2629 am2offset_imm:$offset)>;
2631 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2632 // put the patterns on the instruction definitions directly as ISel wants
2633 // the address base and offset to be separate operands, not a single
2634 // complex operand like we represent the instructions themselves. The
2635 // pseudos map between the two.
2636 let usesCustomInserter = 1,
2637 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2638 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2639 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2642 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2643 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2644 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2647 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2648 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2649 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2652 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2653 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2654 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2657 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2658 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2659 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2662 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2667 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2668 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2669 StMiscFrm, IIC_iStore_bh_ru,
2670 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2672 let Inst{23} = addr{8}; // U bit
2673 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2674 let Inst{19-16} = addr{12-9}; // Rn
2675 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2676 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2677 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2678 let DecoderMethod = "DecodeAddrMode3Instruction";
2681 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2682 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2683 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2684 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2685 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2686 addr_offset_none:$addr,
2687 am3offset:$offset))]> {
2690 let Inst{23} = offset{8}; // U bit
2691 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2692 let Inst{19-16} = addr;
2693 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2694 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2695 let DecoderMethod = "DecodeAddrMode3Instruction";
2698 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2699 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2700 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2701 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2702 "strd", "\t$Rt, $Rt2, $addr!",
2703 "$addr.base = $Rn_wb", []> {
2705 let Inst{23} = addr{8}; // U bit
2706 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2707 let Inst{19-16} = addr{12-9}; // Rn
2708 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2709 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2710 let DecoderMethod = "DecodeAddrMode3Instruction";
2711 let AsmMatchConverter = "cvtStrdPre";
2714 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2715 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2717 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2718 "strd", "\t$Rt, $Rt2, $addr, $offset",
2719 "$addr.base = $Rn_wb", []> {
2722 let Inst{23} = offset{8}; // U bit
2723 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2724 let Inst{19-16} = addr;
2725 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2726 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2727 let DecoderMethod = "DecodeAddrMode3Instruction";
2729 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2731 // STRT, STRBT, and STRHT
2733 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2734 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2735 IndexModePost, StFrm, IIC_iStore_bh_ru,
2736 "strbt", "\t$Rt, $addr, $offset",
2737 "$addr.base = $Rn_wb", []> {
2743 let Inst{23} = offset{12};
2744 let Inst{21} = 1; // overwrite
2745 let Inst{19-16} = addr;
2746 let Inst{11-5} = offset{11-5};
2748 let Inst{3-0} = offset{3-0};
2749 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2752 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2753 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2754 IndexModePost, StFrm, IIC_iStore_bh_ru,
2755 "strbt", "\t$Rt, $addr, $offset",
2756 "$addr.base = $Rn_wb", []> {
2762 let Inst{23} = offset{12};
2763 let Inst{21} = 1; // overwrite
2764 let Inst{19-16} = addr;
2765 let Inst{11-0} = offset{11-0};
2766 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2769 let mayStore = 1, neverHasSideEffects = 1 in {
2770 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2771 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2772 IndexModePost, StFrm, IIC_iStore_ru,
2773 "strt", "\t$Rt, $addr, $offset",
2774 "$addr.base = $Rn_wb", []> {
2780 let Inst{23} = offset{12};
2781 let Inst{21} = 1; // overwrite
2782 let Inst{19-16} = addr;
2783 let Inst{11-5} = offset{11-5};
2785 let Inst{3-0} = offset{3-0};
2786 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2789 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2790 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2791 IndexModePost, StFrm, IIC_iStore_ru,
2792 "strt", "\t$Rt, $addr, $offset",
2793 "$addr.base = $Rn_wb", []> {
2799 let Inst{23} = offset{12};
2800 let Inst{21} = 1; // overwrite
2801 let Inst{19-16} = addr;
2802 let Inst{11-0} = offset{11-0};
2803 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2808 multiclass AI3strT<bits<4> op, string opc> {
2809 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2810 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2811 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2812 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2814 let Inst{23} = offset{8};
2816 let Inst{11-8} = offset{7-4};
2817 let Inst{3-0} = offset{3-0};
2818 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2820 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2821 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2822 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2823 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2825 let Inst{23} = Rm{4};
2828 let Inst{3-0} = Rm{3-0};
2829 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2834 defm STRHT : AI3strT<0b1011, "strht">;
2837 //===----------------------------------------------------------------------===//
2838 // Load / store multiple Instructions.
2841 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2842 InstrItinClass itin, InstrItinClass itin_upd> {
2843 // IA is the default, so no need for an explicit suffix on the
2844 // mnemonic here. Without it is the canonical spelling.
2846 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2847 IndexModeNone, f, itin,
2848 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2849 let Inst{24-23} = 0b01; // Increment After
2850 let Inst{22} = P_bit;
2851 let Inst{21} = 0; // No writeback
2852 let Inst{20} = L_bit;
2855 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2856 IndexModeUpd, f, itin_upd,
2857 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2858 let Inst{24-23} = 0b01; // Increment After
2859 let Inst{22} = P_bit;
2860 let Inst{21} = 1; // Writeback
2861 let Inst{20} = L_bit;
2863 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2866 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2867 IndexModeNone, f, itin,
2868 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2869 let Inst{24-23} = 0b00; // Decrement After
2870 let Inst{22} = P_bit;
2871 let Inst{21} = 0; // No writeback
2872 let Inst{20} = L_bit;
2875 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2876 IndexModeUpd, f, itin_upd,
2877 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2878 let Inst{24-23} = 0b00; // Decrement After
2879 let Inst{22} = P_bit;
2880 let Inst{21} = 1; // Writeback
2881 let Inst{20} = L_bit;
2883 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2886 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2887 IndexModeNone, f, itin,
2888 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2889 let Inst{24-23} = 0b10; // Decrement Before
2890 let Inst{22} = P_bit;
2891 let Inst{21} = 0; // No writeback
2892 let Inst{20} = L_bit;
2895 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2896 IndexModeUpd, f, itin_upd,
2897 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2898 let Inst{24-23} = 0b10; // Decrement Before
2899 let Inst{22} = P_bit;
2900 let Inst{21} = 1; // Writeback
2901 let Inst{20} = L_bit;
2903 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2906 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2907 IndexModeNone, f, itin,
2908 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2909 let Inst{24-23} = 0b11; // Increment Before
2910 let Inst{22} = P_bit;
2911 let Inst{21} = 0; // No writeback
2912 let Inst{20} = L_bit;
2915 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2916 IndexModeUpd, f, itin_upd,
2917 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2918 let Inst{24-23} = 0b11; // Increment Before
2919 let Inst{22} = P_bit;
2920 let Inst{21} = 1; // Writeback
2921 let Inst{20} = L_bit;
2923 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2927 let neverHasSideEffects = 1 in {
2929 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2930 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2933 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2934 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2937 } // neverHasSideEffects
2939 // FIXME: remove when we have a way to marking a MI with these properties.
2940 // FIXME: Should pc be an implicit operand like PICADD, etc?
2941 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2942 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2943 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2944 reglist:$regs, variable_ops),
2945 4, IIC_iLoad_mBr, [],
2946 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2947 RegConstraint<"$Rn = $wb">;
2949 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2950 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2953 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2954 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2959 //===----------------------------------------------------------------------===//
2960 // Move Instructions.
2963 let neverHasSideEffects = 1 in
2964 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2965 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2969 let Inst{19-16} = 0b0000;
2970 let Inst{11-4} = 0b00000000;
2973 let Inst{15-12} = Rd;
2976 // A version for the smaller set of tail call registers.
2977 let neverHasSideEffects = 1 in
2978 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2979 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2983 let Inst{11-4} = 0b00000000;
2986 let Inst{15-12} = Rd;
2989 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2990 DPSoRegRegFrm, IIC_iMOVsr,
2991 "mov", "\t$Rd, $src",
2992 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
2996 let Inst{15-12} = Rd;
2997 let Inst{19-16} = 0b0000;
2998 let Inst{11-8} = src{11-8};
3000 let Inst{6-5} = src{6-5};
3002 let Inst{3-0} = src{3-0};
3006 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3007 DPSoRegImmFrm, IIC_iMOVsr,
3008 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3009 UnaryDP, Sched<[WriteALU]> {
3012 let Inst{15-12} = Rd;
3013 let Inst{19-16} = 0b0000;
3014 let Inst{11-5} = src{11-5};
3016 let Inst{3-0} = src{3-0};
3020 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3021 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3022 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3027 let Inst{15-12} = Rd;
3028 let Inst{19-16} = 0b0000;
3029 let Inst{11-0} = imm;
3032 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3033 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3035 "movw", "\t$Rd, $imm",
3036 [(set GPR:$Rd, imm0_65535:$imm)]>,
3037 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3040 let Inst{15-12} = Rd;
3041 let Inst{11-0} = imm{11-0};
3042 let Inst{19-16} = imm{15-12};
3045 let DecoderMethod = "DecodeArmMOVTWInstruction";
3048 def : InstAlias<"mov${p} $Rd, $imm",
3049 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3052 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3053 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3056 let Constraints = "$src = $Rd" in {
3057 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3058 (ins GPR:$src, imm0_65535_expr:$imm),
3060 "movt", "\t$Rd, $imm",
3062 (or (and GPR:$src, 0xffff),
3063 lo16AllZero:$imm))]>, UnaryDP,
3064 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3067 let Inst{15-12} = Rd;
3068 let Inst{11-0} = imm{11-0};
3069 let Inst{19-16} = imm{15-12};
3072 let DecoderMethod = "DecodeArmMOVTWInstruction";
3075 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3076 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3081 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3082 Requires<[IsARM, HasV6T2]>;
3084 let Uses = [CPSR] in
3085 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3086 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3087 Requires<[IsARM]>, Sched<[WriteALU]>;
3089 // These aren't really mov instructions, but we have to define them this way
3090 // due to flag operands.
3092 let Defs = [CPSR] in {
3093 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3094 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3095 Sched<[WriteALU]>, Requires<[IsARM]>;
3096 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3097 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3098 Sched<[WriteALU]>, Requires<[IsARM]>;
3101 //===----------------------------------------------------------------------===//
3102 // Extend Instructions.
3107 def SXTB : AI_ext_rrot<0b01101010,
3108 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3109 def SXTH : AI_ext_rrot<0b01101011,
3110 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3112 def SXTAB : AI_exta_rrot<0b01101010,
3113 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3114 def SXTAH : AI_exta_rrot<0b01101011,
3115 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3117 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3119 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3123 let AddedComplexity = 16 in {
3124 def UXTB : AI_ext_rrot<0b01101110,
3125 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3126 def UXTH : AI_ext_rrot<0b01101111,
3127 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3128 def UXTB16 : AI_ext_rrot<0b01101100,
3129 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3131 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3132 // The transformation should probably be done as a combiner action
3133 // instead so we can include a check for masking back in the upper
3134 // eight bits of the source into the lower eight bits of the result.
3135 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3136 // (UXTB16r_rot GPR:$Src, 3)>;
3137 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3138 (UXTB16 GPR:$Src, 1)>;
3140 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3141 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3142 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3143 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3146 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3147 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3150 def SBFX : I<(outs GPRnopc:$Rd),
3151 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3152 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3153 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3154 Requires<[IsARM, HasV6T2]> {
3159 let Inst{27-21} = 0b0111101;
3160 let Inst{6-4} = 0b101;
3161 let Inst{20-16} = width;
3162 let Inst{15-12} = Rd;
3163 let Inst{11-7} = lsb;
3167 def UBFX : I<(outs GPR:$Rd),
3168 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3169 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3170 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3171 Requires<[IsARM, HasV6T2]> {
3176 let Inst{27-21} = 0b0111111;
3177 let Inst{6-4} = 0b101;
3178 let Inst{20-16} = width;
3179 let Inst{15-12} = Rd;
3180 let Inst{11-7} = lsb;
3184 //===----------------------------------------------------------------------===//
3185 // Arithmetic Instructions.
3188 defm ADD : AsI1_bin_irs<0b0100, "add",
3189 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3190 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3191 defm SUB : AsI1_bin_irs<0b0010, "sub",
3192 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3193 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3195 // ADD and SUB with 's' bit set.
3197 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3198 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3199 // AdjustInstrPostInstrSelection where we determine whether or not to
3200 // set the "s" bit based on CPSR liveness.
3202 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3203 // support for an optional CPSR definition that corresponds to the DAG
3204 // node's second value. We can then eliminate the implicit def of CPSR.
3205 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3206 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3207 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3208 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3210 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3211 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3212 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3213 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3215 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3216 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3217 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3219 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3220 // CPSR and the implicit def of CPSR is not needed.
3221 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3222 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3224 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3225 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3227 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3228 // The assume-no-carry-in form uses the negation of the input since add/sub
3229 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3230 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3232 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3233 (SUBri GPR:$src, so_imm_neg:$imm)>;
3234 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3235 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3237 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3238 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3239 Requires<[IsARM, HasV6T2]>;
3240 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3241 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3242 Requires<[IsARM, HasV6T2]>;
3244 // The with-carry-in form matches bitwise not instead of the negation.
3245 // Effectively, the inverse interpretation of the carry flag already accounts
3246 // for part of the negation.
3247 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3248 (SBCri GPR:$src, so_imm_not:$imm)>;
3249 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3250 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3252 // Note: These are implemented in C++ code, because they have to generate
3253 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3255 // (mul X, 2^n+1) -> (add (X << n), X)
3256 // (mul X, 2^n-1) -> (rsb X, (X << n))
3258 // ARM Arithmetic Instruction
3259 // GPR:$dst = GPR:$a op GPR:$b
3260 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3261 list<dag> pattern = [],
3262 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3263 string asm = "\t$Rd, $Rn, $Rm">
3264 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3265 Sched<[WriteALU, ReadALU, ReadALU]> {
3269 let Inst{27-20} = op27_20;
3270 let Inst{11-4} = op11_4;
3271 let Inst{19-16} = Rn;
3272 let Inst{15-12} = Rd;
3275 let Unpredictable{11-8} = 0b1111;
3278 // Saturating add/subtract
3280 let DecoderMethod = "DecodeQADDInstruction" in
3281 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3282 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3283 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3285 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3286 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3287 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3288 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3289 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3291 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3292 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3295 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3296 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3297 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3298 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3299 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3300 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3301 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3302 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3303 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3304 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3305 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3306 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3308 // Signed/Unsigned add/subtract
3310 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3311 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3312 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3313 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3314 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3315 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3316 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3317 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3318 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3319 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3320 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3321 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3323 // Signed/Unsigned halving add/subtract
3325 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3326 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3327 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3328 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3329 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3330 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3331 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3332 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3333 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3334 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3335 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3336 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3338 // Unsigned Sum of Absolute Differences [and Accumulate].
3340 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3341 MulFrm /* for convenience */, NoItinerary, "usad8",
3342 "\t$Rd, $Rn, $Rm", []>,
3343 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3347 let Inst{27-20} = 0b01111000;
3348 let Inst{15-12} = 0b1111;
3349 let Inst{7-4} = 0b0001;
3350 let Inst{19-16} = Rd;
3351 let Inst{11-8} = Rm;
3354 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3355 MulFrm /* for convenience */, NoItinerary, "usada8",
3356 "\t$Rd, $Rn, $Rm, $Ra", []>,
3357 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3362 let Inst{27-20} = 0b01111000;
3363 let Inst{7-4} = 0b0001;
3364 let Inst{19-16} = Rd;
3365 let Inst{15-12} = Ra;
3366 let Inst{11-8} = Rm;
3370 // Signed/Unsigned saturate
3372 def SSAT : AI<(outs GPRnopc:$Rd),
3373 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3374 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3379 let Inst{27-21} = 0b0110101;
3380 let Inst{5-4} = 0b01;
3381 let Inst{20-16} = sat_imm;
3382 let Inst{15-12} = Rd;
3383 let Inst{11-7} = sh{4-0};
3384 let Inst{6} = sh{5};
3388 def SSAT16 : AI<(outs GPRnopc:$Rd),
3389 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3390 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3394 let Inst{27-20} = 0b01101010;
3395 let Inst{11-4} = 0b11110011;
3396 let Inst{15-12} = Rd;
3397 let Inst{19-16} = sat_imm;
3401 def USAT : AI<(outs GPRnopc:$Rd),
3402 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3403 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3408 let Inst{27-21} = 0b0110111;
3409 let Inst{5-4} = 0b01;
3410 let Inst{15-12} = Rd;
3411 let Inst{11-7} = sh{4-0};
3412 let Inst{6} = sh{5};
3413 let Inst{20-16} = sat_imm;
3417 def USAT16 : AI<(outs GPRnopc:$Rd),
3418 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3419 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3423 let Inst{27-20} = 0b01101110;
3424 let Inst{11-4} = 0b11110011;
3425 let Inst{15-12} = Rd;
3426 let Inst{19-16} = sat_imm;
3430 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3431 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3432 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3433 (USAT imm:$pos, GPRnopc:$a, 0)>;
3435 //===----------------------------------------------------------------------===//
3436 // Bitwise Instructions.
3439 defm AND : AsI1_bin_irs<0b0000, "and",
3440 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3441 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3442 defm ORR : AsI1_bin_irs<0b1100, "orr",
3443 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3444 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3445 defm EOR : AsI1_bin_irs<0b0001, "eor",
3446 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3447 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3448 defm BIC : AsI1_bin_irs<0b1110, "bic",
3449 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3450 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3452 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3453 // like in the actual instruction encoding. The complexity of mapping the mask
3454 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3455 // instruction description.
3456 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3457 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3458 "bfc", "\t$Rd, $imm", "$src = $Rd",
3459 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3460 Requires<[IsARM, HasV6T2]> {
3463 let Inst{27-21} = 0b0111110;
3464 let Inst{6-0} = 0b0011111;
3465 let Inst{15-12} = Rd;
3466 let Inst{11-7} = imm{4-0}; // lsb
3467 let Inst{20-16} = imm{9-5}; // msb
3470 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3471 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3472 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3473 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3474 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3475 bf_inv_mask_imm:$imm))]>,
3476 Requires<[IsARM, HasV6T2]> {
3480 let Inst{27-21} = 0b0111110;
3481 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3482 let Inst{15-12} = Rd;
3483 let Inst{11-7} = imm{4-0}; // lsb
3484 let Inst{20-16} = imm{9-5}; // width
3488 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3489 "mvn", "\t$Rd, $Rm",
3490 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3494 let Inst{19-16} = 0b0000;
3495 let Inst{11-4} = 0b00000000;
3496 let Inst{15-12} = Rd;
3499 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3500 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3501 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3506 let Inst{19-16} = 0b0000;
3507 let Inst{15-12} = Rd;
3508 let Inst{11-5} = shift{11-5};
3510 let Inst{3-0} = shift{3-0};
3512 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3513 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3514 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3519 let Inst{19-16} = 0b0000;
3520 let Inst{15-12} = Rd;
3521 let Inst{11-8} = shift{11-8};
3523 let Inst{6-5} = shift{6-5};
3525 let Inst{3-0} = shift{3-0};
3527 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3528 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3529 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3530 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3534 let Inst{19-16} = 0b0000;
3535 let Inst{15-12} = Rd;
3536 let Inst{11-0} = imm;
3539 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3540 (BICri GPR:$src, so_imm_not:$imm)>;
3542 //===----------------------------------------------------------------------===//
3543 // Multiply Instructions.
3545 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3546 string opc, string asm, list<dag> pattern>
3547 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3551 let Inst{19-16} = Rd;
3552 let Inst{11-8} = Rm;
3555 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3556 string opc, string asm, list<dag> pattern>
3557 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3562 let Inst{19-16} = RdHi;
3563 let Inst{15-12} = RdLo;
3564 let Inst{11-8} = Rm;
3567 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3568 string opc, string asm, list<dag> pattern>
3569 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3574 let Inst{19-16} = RdHi;
3575 let Inst{15-12} = RdLo;
3576 let Inst{11-8} = Rm;
3580 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3581 // property. Remove them when it's possible to add those properties
3582 // on an individual MachineInstr, not just an instruction description.
3583 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3584 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3585 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3586 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3587 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3588 Requires<[IsARM, HasV6]> {
3589 let Inst{15-12} = 0b0000;
3590 let Unpredictable{15-12} = 0b1111;
3593 let Constraints = "@earlyclobber $Rd" in
3594 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3595 pred:$p, cc_out:$s),
3597 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3598 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3599 Requires<[IsARM, NoV6, UseMulOps]>;
3602 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3603 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3604 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3605 Requires<[IsARM, HasV6, UseMulOps]> {
3607 let Inst{15-12} = Ra;
3610 let Constraints = "@earlyclobber $Rd" in
3611 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3612 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3614 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3615 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3616 Requires<[IsARM, NoV6]>;
3618 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3619 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3620 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3621 Requires<[IsARM, HasV6T2, UseMulOps]> {
3626 let Inst{19-16} = Rd;
3627 let Inst{15-12} = Ra;
3628 let Inst{11-8} = Rm;
3632 // Extra precision multiplies with low / high results
3633 let neverHasSideEffects = 1 in {
3634 let isCommutable = 1 in {
3635 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3636 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3637 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3638 Requires<[IsARM, HasV6]>;
3640 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3641 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3642 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3643 Requires<[IsARM, HasV6]>;
3645 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3646 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3647 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3649 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3650 Requires<[IsARM, NoV6]>;
3652 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3653 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3655 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3656 Requires<[IsARM, NoV6]>;
3660 // Multiply + accumulate
3661 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3662 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3663 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3664 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3665 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3666 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3667 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3668 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3670 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3671 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3672 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3673 Requires<[IsARM, HasV6]> {
3678 let Inst{19-16} = RdHi;
3679 let Inst{15-12} = RdLo;
3680 let Inst{11-8} = Rm;
3684 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3685 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3686 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3688 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3689 pred:$p, cc_out:$s)>,
3690 Requires<[IsARM, NoV6]>;
3691 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3692 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3694 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3695 pred:$p, cc_out:$s)>,
3696 Requires<[IsARM, NoV6]>;
3699 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3700 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3701 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3703 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3704 Requires<[IsARM, NoV6]>;
3707 } // neverHasSideEffects
3709 // Most significant word multiply
3710 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3711 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3712 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3713 Requires<[IsARM, HasV6]> {
3714 let Inst{15-12} = 0b1111;
3717 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3718 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3719 Requires<[IsARM, HasV6]> {
3720 let Inst{15-12} = 0b1111;
3723 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3724 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3725 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3726 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3727 Requires<[IsARM, HasV6, UseMulOps]>;
3729 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3730 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3731 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3732 Requires<[IsARM, HasV6]>;
3734 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3735 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3736 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3737 Requires<[IsARM, HasV6, UseMulOps]>;
3739 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3740 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3741 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3742 Requires<[IsARM, HasV6]>;
3744 multiclass AI_smul<string opc, PatFrag opnode> {
3745 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3746 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3747 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3748 (sext_inreg GPR:$Rm, i16)))]>,
3749 Requires<[IsARM, HasV5TE]>;
3751 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3752 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3753 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3754 (sra GPR:$Rm, (i32 16))))]>,
3755 Requires<[IsARM, HasV5TE]>;
3757 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3758 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3759 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3760 (sext_inreg GPR:$Rm, i16)))]>,
3761 Requires<[IsARM, HasV5TE]>;
3763 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3764 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3765 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3766 (sra GPR:$Rm, (i32 16))))]>,
3767 Requires<[IsARM, HasV5TE]>;
3769 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3770 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3771 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3772 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3773 Requires<[IsARM, HasV5TE]>;
3775 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3776 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3777 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3778 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3779 Requires<[IsARM, HasV5TE]>;
3783 multiclass AI_smla<string opc, PatFrag opnode> {
3784 let DecoderMethod = "DecodeSMLAInstruction" in {
3785 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3786 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3787 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3788 [(set GPRnopc:$Rd, (add GPR:$Ra,
3789 (opnode (sext_inreg GPRnopc:$Rn, i16),
3790 (sext_inreg GPRnopc:$Rm, i16))))]>,
3791 Requires<[IsARM, HasV5TE, UseMulOps]>;
3793 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3794 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3795 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3797 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3798 (sra GPRnopc:$Rm, (i32 16)))))]>,
3799 Requires<[IsARM, HasV5TE, UseMulOps]>;
3801 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3802 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3803 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3805 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3806 (sext_inreg GPRnopc:$Rm, i16))))]>,
3807 Requires<[IsARM, HasV5TE, UseMulOps]>;
3809 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3810 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3811 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3813 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3814 (sra GPRnopc:$Rm, (i32 16)))))]>,
3815 Requires<[IsARM, HasV5TE, UseMulOps]>;
3817 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3818 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3819 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3821 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3822 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3823 Requires<[IsARM, HasV5TE, UseMulOps]>;
3825 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3826 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3827 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3829 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3830 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3831 Requires<[IsARM, HasV5TE, UseMulOps]>;
3835 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3836 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3838 // Halfword multiply accumulate long: SMLAL<x><y>.
3839 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3840 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3841 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3842 Requires<[IsARM, HasV5TE]>;
3844 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3845 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3846 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3847 Requires<[IsARM, HasV5TE]>;
3849 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3850 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3851 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3852 Requires<[IsARM, HasV5TE]>;
3854 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3855 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3856 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3857 Requires<[IsARM, HasV5TE]>;
3859 // Helper class for AI_smld.
3860 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3861 InstrItinClass itin, string opc, string asm>
3862 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3865 let Inst{27-23} = 0b01110;
3866 let Inst{22} = long;
3867 let Inst{21-20} = 0b00;
3868 let Inst{11-8} = Rm;
3875 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3876 InstrItinClass itin, string opc, string asm>
3877 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3879 let Inst{15-12} = 0b1111;
3880 let Inst{19-16} = Rd;
3882 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3883 InstrItinClass itin, string opc, string asm>
3884 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3887 let Inst{19-16} = Rd;
3888 let Inst{15-12} = Ra;
3890 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3891 InstrItinClass itin, string opc, string asm>
3892 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3895 let Inst{19-16} = RdHi;
3896 let Inst{15-12} = RdLo;
3899 multiclass AI_smld<bit sub, string opc> {
3901 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3902 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3903 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3905 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3906 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3907 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3909 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3910 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3911 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3913 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3914 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3915 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3919 defm SMLA : AI_smld<0, "smla">;
3920 defm SMLS : AI_smld<1, "smls">;
3922 multiclass AI_sdml<bit sub, string opc> {
3924 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3925 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3926 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3927 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3930 defm SMUA : AI_sdml<0, "smua">;
3931 defm SMUS : AI_sdml<1, "smus">;
3933 //===----------------------------------------------------------------------===//
3934 // Division Instructions (ARMv7-A with virtualization extension)
3936 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3937 "sdiv", "\t$Rd, $Rn, $Rm",
3938 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3939 Requires<[IsARM, HasDivideInARM]>;
3941 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3942 "udiv", "\t$Rd, $Rn, $Rm",
3943 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3944 Requires<[IsARM, HasDivideInARM]>;
3946 //===----------------------------------------------------------------------===//
3947 // Misc. Arithmetic Instructions.
3950 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3951 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3952 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3955 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3956 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3957 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3958 Requires<[IsARM, HasV6T2]>,
3961 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3962 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3963 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3966 let AddedComplexity = 5 in
3967 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3968 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3969 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3970 Requires<[IsARM, HasV6]>,
3973 let AddedComplexity = 5 in
3974 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3975 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3976 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3977 Requires<[IsARM, HasV6]>,
3980 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3981 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3984 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3985 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3986 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3987 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3988 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3990 Requires<[IsARM, HasV6]>,
3991 Sched<[WriteALUsi, ReadALU]>;
3993 // Alternate cases for PKHBT where identities eliminate some nodes.
3994 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3995 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3996 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3997 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3999 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4000 // will match the pattern below.
4001 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4002 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4003 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4004 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4005 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4007 Requires<[IsARM, HasV6]>,
4008 Sched<[WriteALUsi, ReadALU]>;
4010 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4011 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4012 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4013 (srl GPRnopc:$src2, imm16_31:$sh)),
4014 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4015 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4016 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4017 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4019 //===----------------------------------------------------------------------===//
4020 // Comparison Instructions...
4023 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4024 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4025 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4027 // ARMcmpZ can re-use the above instruction definitions.
4028 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4029 (CMPri GPR:$src, so_imm:$imm)>;
4030 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4031 (CMPrr GPR:$src, GPR:$rhs)>;
4032 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4033 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4034 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4035 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4037 // CMN register-integer
4038 let isCompare = 1, Defs = [CPSR] in {
4039 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4040 "cmn", "\t$Rn, $imm",
4041 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4042 Sched<[WriteCMP, ReadALU]> {
4047 let Inst{19-16} = Rn;
4048 let Inst{15-12} = 0b0000;
4049 let Inst{11-0} = imm;
4051 let Unpredictable{15-12} = 0b1111;
4054 // CMN register-register/shift
4055 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4056 "cmn", "\t$Rn, $Rm",
4057 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4058 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4061 let isCommutable = 1;
4064 let Inst{19-16} = Rn;
4065 let Inst{15-12} = 0b0000;
4066 let Inst{11-4} = 0b00000000;
4069 let Unpredictable{15-12} = 0b1111;
4072 def CMNzrsi : AI1<0b1011, (outs),
4073 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4074 "cmn", "\t$Rn, $shift",
4075 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4076 GPR:$Rn, so_reg_imm:$shift)]>,
4077 Sched<[WriteCMPsi, ReadALU]> {
4082 let Inst{19-16} = Rn;
4083 let Inst{15-12} = 0b0000;
4084 let Inst{11-5} = shift{11-5};
4086 let Inst{3-0} = shift{3-0};
4088 let Unpredictable{15-12} = 0b1111;
4091 def CMNzrsr : AI1<0b1011, (outs),
4092 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4093 "cmn", "\t$Rn, $shift",
4094 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4095 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4096 Sched<[WriteCMPsr, ReadALU]> {
4101 let Inst{19-16} = Rn;
4102 let Inst{15-12} = 0b0000;
4103 let Inst{11-8} = shift{11-8};
4105 let Inst{6-5} = shift{6-5};
4107 let Inst{3-0} = shift{3-0};
4109 let Unpredictable{15-12} = 0b1111;
4114 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4115 (CMNri GPR:$src, so_imm_neg:$imm)>;
4117 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4118 (CMNri GPR:$src, so_imm_neg:$imm)>;
4120 // Note that TST/TEQ don't set all the same flags that CMP does!
4121 defm TST : AI1_cmp_irs<0b1000, "tst",
4122 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4123 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4124 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4125 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4126 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4128 // Pseudo i64 compares for some floating point compares.
4129 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4131 def BCCi64 : PseudoInst<(outs),
4132 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4134 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4137 def BCCZi64 : PseudoInst<(outs),
4138 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4139 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4141 } // usesCustomInserter
4144 // Conditional moves
4145 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4146 // a two-value operand where a dag node expects two operands. :(
4147 let neverHasSideEffects = 1 in {
4149 let isCommutable = 1, isSelect = 1 in
4150 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4152 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4153 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4155 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4156 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4158 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4159 imm:$cc, CCR:$ccr))*/]>,
4160 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4161 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4162 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4164 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4165 imm:$cc, CCR:$ccr))*/]>,
4166 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4169 let isMoveImm = 1 in
4170 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4171 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4174 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4177 let isMoveImm = 1 in
4178 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4179 (ins GPR:$false, so_imm:$imm, pred:$p),
4181 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4182 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4184 // Two instruction predicate mov immediate.
4185 let isMoveImm = 1 in
4186 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4187 (ins GPR:$false, i32imm:$src, pred:$p),
4188 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4190 let isMoveImm = 1 in
4191 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4192 (ins GPR:$false, so_imm:$imm, pred:$p),
4194 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4195 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4197 } // neverHasSideEffects
4200 //===----------------------------------------------------------------------===//
4201 // Atomic operations intrinsics
4204 def MemBarrierOptOperand : AsmOperandClass {
4205 let Name = "MemBarrierOpt";
4206 let ParserMethod = "parseMemBarrierOptOperand";
4208 def memb_opt : Operand<i32> {
4209 let PrintMethod = "printMemBOption";
4210 let ParserMatchClass = MemBarrierOptOperand;
4211 let DecoderMethod = "DecodeMemBarrierOption";
4214 def InstSyncBarrierOptOperand : AsmOperandClass {
4215 let Name = "InstSyncBarrierOpt";
4216 let ParserMethod = "parseInstSyncBarrierOptOperand";
4218 def instsyncb_opt : Operand<i32> {
4219 let PrintMethod = "printInstSyncBOption";
4220 let ParserMatchClass = InstSyncBarrierOptOperand;
4221 let DecoderMethod = "DecodeInstSyncBarrierOption";
4224 // memory barriers protect the atomic sequences
4225 let hasSideEffects = 1 in {
4226 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4227 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4228 Requires<[IsARM, HasDB]> {
4230 let Inst{31-4} = 0xf57ff05;
4231 let Inst{3-0} = opt;
4235 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4236 "dsb", "\t$opt", []>,
4237 Requires<[IsARM, HasDB]> {
4239 let Inst{31-4} = 0xf57ff04;
4240 let Inst{3-0} = opt;
4243 // ISB has only full system option
4244 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4245 "isb", "\t$opt", []>,
4246 Requires<[IsARM, HasDB]> {
4248 let Inst{31-4} = 0xf57ff06;
4249 let Inst{3-0} = opt;
4252 // Pseudo instruction that combines movs + predicated rsbmi
4253 // to implement integer ABS
4254 let usesCustomInserter = 1, Defs = [CPSR] in
4255 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4257 let usesCustomInserter = 1 in {
4258 let Defs = [CPSR] in {
4259 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4261 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4262 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4264 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4265 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4267 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4268 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4270 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4271 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4273 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4274 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4276 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4277 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4279 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4280 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4282 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4283 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4285 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4286 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4288 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4289 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4291 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4292 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4294 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4295 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4297 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4298 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4300 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4301 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4303 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4304 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4306 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4307 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4309 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4310 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4312 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4313 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4315 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4316 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4318 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4319 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4321 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4322 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4324 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4325 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4327 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4328 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4330 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4331 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4333 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4334 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4336 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4337 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4339 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4340 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4342 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4343 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4345 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4346 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4348 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4350 def ATOMIC_SWAP_I8 : PseudoInst<
4351 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4352 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4353 def ATOMIC_SWAP_I16 : PseudoInst<
4354 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4355 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4356 def ATOMIC_SWAP_I32 : PseudoInst<
4357 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4358 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4360 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4361 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4362 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4363 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4364 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4365 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4366 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4367 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4368 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4372 let usesCustomInserter = 1 in {
4373 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4374 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4376 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4379 let mayLoad = 1 in {
4380 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4382 "ldrexb", "\t$Rt, $addr", []>;
4383 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4384 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4385 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4386 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4387 let hasExtraDefRegAllocReq = 1 in
4388 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4389 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4390 let DecoderMethod = "DecodeDoubleRegLoad";
4394 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4395 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4396 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4397 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4398 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4399 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4400 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4401 let hasExtraSrcRegAllocReq = 1 in
4402 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4403 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4404 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4405 let DecoderMethod = "DecodeDoubleRegStore";
4410 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4411 Requires<[IsARM, HasV7]> {
4412 let Inst{31-0} = 0b11110101011111111111000000011111;
4415 // SWP/SWPB are deprecated in V6/V7.
4416 let mayLoad = 1, mayStore = 1 in {
4417 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4418 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4419 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4420 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4423 //===----------------------------------------------------------------------===//
4424 // Coprocessor Instructions.
4427 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4428 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4429 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4430 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4431 imm:$CRm, imm:$opc2)]> {
4439 let Inst{3-0} = CRm;
4441 let Inst{7-5} = opc2;
4442 let Inst{11-8} = cop;
4443 let Inst{15-12} = CRd;
4444 let Inst{19-16} = CRn;
4445 let Inst{23-20} = opc1;
4448 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4449 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4450 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4451 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4452 imm:$CRm, imm:$opc2)]> {
4453 let Inst{31-28} = 0b1111;
4461 let Inst{3-0} = CRm;
4463 let Inst{7-5} = opc2;
4464 let Inst{11-8} = cop;
4465 let Inst{15-12} = CRd;
4466 let Inst{19-16} = CRn;
4467 let Inst{23-20} = opc1;
4470 class ACI<dag oops, dag iops, string opc, string asm,
4471 IndexMode im = IndexModeNone>
4472 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4474 let Inst{27-25} = 0b110;
4476 class ACInoP<dag oops, dag iops, string opc, string asm,
4477 IndexMode im = IndexModeNone>
4478 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4480 let Inst{31-28} = 0b1111;
4481 let Inst{27-25} = 0b110;
4483 multiclass LdStCop<bit load, bit Dbit, string asm> {
4484 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4485 asm, "\t$cop, $CRd, $addr"> {
4489 let Inst{24} = 1; // P = 1
4490 let Inst{23} = addr{8};
4491 let Inst{22} = Dbit;
4492 let Inst{21} = 0; // W = 0
4493 let Inst{20} = load;
4494 let Inst{19-16} = addr{12-9};
4495 let Inst{15-12} = CRd;
4496 let Inst{11-8} = cop;
4497 let Inst{7-0} = addr{7-0};
4498 let DecoderMethod = "DecodeCopMemInstruction";
4500 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4501 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4505 let Inst{24} = 1; // P = 1
4506 let Inst{23} = addr{8};
4507 let Inst{22} = Dbit;
4508 let Inst{21} = 1; // W = 1
4509 let Inst{20} = load;
4510 let Inst{19-16} = addr{12-9};
4511 let Inst{15-12} = CRd;
4512 let Inst{11-8} = cop;
4513 let Inst{7-0} = addr{7-0};
4514 let DecoderMethod = "DecodeCopMemInstruction";
4516 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4517 postidx_imm8s4:$offset),
4518 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4523 let Inst{24} = 0; // P = 0
4524 let Inst{23} = offset{8};
4525 let Inst{22} = Dbit;
4526 let Inst{21} = 1; // W = 1
4527 let Inst{20} = load;
4528 let Inst{19-16} = addr;
4529 let Inst{15-12} = CRd;
4530 let Inst{11-8} = cop;
4531 let Inst{7-0} = offset{7-0};
4532 let DecoderMethod = "DecodeCopMemInstruction";
4534 def _OPTION : ACI<(outs),
4535 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4536 coproc_option_imm:$option),
4537 asm, "\t$cop, $CRd, $addr, $option"> {
4542 let Inst{24} = 0; // P = 0
4543 let Inst{23} = 1; // U = 1
4544 let Inst{22} = Dbit;
4545 let Inst{21} = 0; // W = 0
4546 let Inst{20} = load;
4547 let Inst{19-16} = addr;
4548 let Inst{15-12} = CRd;
4549 let Inst{11-8} = cop;
4550 let Inst{7-0} = option;
4551 let DecoderMethod = "DecodeCopMemInstruction";
4554 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4555 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4556 asm, "\t$cop, $CRd, $addr"> {
4560 let Inst{24} = 1; // P = 1
4561 let Inst{23} = addr{8};
4562 let Inst{22} = Dbit;
4563 let Inst{21} = 0; // W = 0
4564 let Inst{20} = load;
4565 let Inst{19-16} = addr{12-9};
4566 let Inst{15-12} = CRd;
4567 let Inst{11-8} = cop;
4568 let Inst{7-0} = addr{7-0};
4569 let DecoderMethod = "DecodeCopMemInstruction";
4571 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4572 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4576 let Inst{24} = 1; // P = 1
4577 let Inst{23} = addr{8};
4578 let Inst{22} = Dbit;
4579 let Inst{21} = 1; // W = 1
4580 let Inst{20} = load;
4581 let Inst{19-16} = addr{12-9};
4582 let Inst{15-12} = CRd;
4583 let Inst{11-8} = cop;
4584 let Inst{7-0} = addr{7-0};
4585 let DecoderMethod = "DecodeCopMemInstruction";
4587 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4588 postidx_imm8s4:$offset),
4589 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4594 let Inst{24} = 0; // P = 0
4595 let Inst{23} = offset{8};
4596 let Inst{22} = Dbit;
4597 let Inst{21} = 1; // W = 1
4598 let Inst{20} = load;
4599 let Inst{19-16} = addr;
4600 let Inst{15-12} = CRd;
4601 let Inst{11-8} = cop;
4602 let Inst{7-0} = offset{7-0};
4603 let DecoderMethod = "DecodeCopMemInstruction";
4605 def _OPTION : ACInoP<(outs),
4606 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4607 coproc_option_imm:$option),
4608 asm, "\t$cop, $CRd, $addr, $option"> {
4613 let Inst{24} = 0; // P = 0
4614 let Inst{23} = 1; // U = 1
4615 let Inst{22} = Dbit;
4616 let Inst{21} = 0; // W = 0
4617 let Inst{20} = load;
4618 let Inst{19-16} = addr;
4619 let Inst{15-12} = CRd;
4620 let Inst{11-8} = cop;
4621 let Inst{7-0} = option;
4622 let DecoderMethod = "DecodeCopMemInstruction";
4626 defm LDC : LdStCop <1, 0, "ldc">;
4627 defm LDCL : LdStCop <1, 1, "ldcl">;
4628 defm STC : LdStCop <0, 0, "stc">;
4629 defm STCL : LdStCop <0, 1, "stcl">;
4630 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4631 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4632 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4633 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4635 //===----------------------------------------------------------------------===//
4636 // Move between coprocessor and ARM core register.
4639 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4641 : ABI<0b1110, oops, iops, NoItinerary, opc,
4642 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4643 let Inst{20} = direction;
4653 let Inst{15-12} = Rt;
4654 let Inst{11-8} = cop;
4655 let Inst{23-21} = opc1;
4656 let Inst{7-5} = opc2;
4657 let Inst{3-0} = CRm;
4658 let Inst{19-16} = CRn;
4661 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4663 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4664 c_imm:$CRm, imm0_7:$opc2),
4665 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4666 imm:$CRm, imm:$opc2)]>;
4667 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4668 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4669 c_imm:$CRm, 0, pred:$p)>;
4670 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4671 (outs GPRwithAPSR:$Rt),
4672 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4674 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4675 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4676 c_imm:$CRm, 0, pred:$p)>;
4678 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4679 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4681 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4683 : ABXI<0b1110, oops, iops, NoItinerary,
4684 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4685 let Inst{31-24} = 0b11111110;
4686 let Inst{20} = direction;
4696 let Inst{15-12} = Rt;
4697 let Inst{11-8} = cop;
4698 let Inst{23-21} = opc1;
4699 let Inst{7-5} = opc2;
4700 let Inst{3-0} = CRm;
4701 let Inst{19-16} = CRn;
4704 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4706 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4707 c_imm:$CRm, imm0_7:$opc2),
4708 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4709 imm:$CRm, imm:$opc2)]>;
4710 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4711 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4713 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4714 (outs GPRwithAPSR:$Rt),
4715 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4717 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4718 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4721 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4722 imm:$CRm, imm:$opc2),
4723 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4725 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4726 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4727 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4728 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4729 let Inst{23-21} = 0b010;
4730 let Inst{20} = direction;
4738 let Inst{15-12} = Rt;
4739 let Inst{19-16} = Rt2;
4740 let Inst{11-8} = cop;
4741 let Inst{7-4} = opc1;
4742 let Inst{3-0} = CRm;
4745 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4746 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4747 GPRnopc:$Rt2, imm:$CRm)]>;
4748 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4750 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4751 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4752 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4753 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4754 let Inst{31-28} = 0b1111;
4755 let Inst{23-21} = 0b010;
4756 let Inst{20} = direction;
4764 let Inst{15-12} = Rt;
4765 let Inst{19-16} = Rt2;
4766 let Inst{11-8} = cop;
4767 let Inst{7-4} = opc1;
4768 let Inst{3-0} = CRm;
4770 let DecoderMethod = "DecodeMRRC2";
4773 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4774 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4775 GPRnopc:$Rt2, imm:$CRm)]>;
4776 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4778 //===----------------------------------------------------------------------===//
4779 // Move between special register and ARM core register
4782 // Move to ARM core register from Special Register
4783 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4784 "mrs", "\t$Rd, apsr", []> {
4786 let Inst{23-16} = 0b00001111;
4787 let Unpredictable{19-17} = 0b111;
4789 let Inst{15-12} = Rd;
4791 let Inst{11-0} = 0b000000000000;
4792 let Unpredictable{11-0} = 0b110100001111;
4795 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4798 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4799 // section B9.3.9, with the R bit set to 1.
4800 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4801 "mrs", "\t$Rd, spsr", []> {
4803 let Inst{23-16} = 0b01001111;
4804 let Unpredictable{19-16} = 0b1111;
4806 let Inst{15-12} = Rd;
4808 let Inst{11-0} = 0b000000000000;
4809 let Unpredictable{11-0} = 0b110100001111;
4812 // Move from ARM core register to Special Register
4814 // No need to have both system and application versions, the encodings are the
4815 // same and the assembly parser has no way to distinguish between them. The mask
4816 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4817 // the mask with the fields to be accessed in the special register.
4818 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4819 "msr", "\t$mask, $Rn", []> {
4824 let Inst{22} = mask{4}; // R bit
4825 let Inst{21-20} = 0b10;
4826 let Inst{19-16} = mask{3-0};
4827 let Inst{15-12} = 0b1111;
4828 let Inst{11-4} = 0b00000000;
4832 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4833 "msr", "\t$mask, $a", []> {
4838 let Inst{22} = mask{4}; // R bit
4839 let Inst{21-20} = 0b10;
4840 let Inst{19-16} = mask{3-0};
4841 let Inst{15-12} = 0b1111;
4845 //===----------------------------------------------------------------------===//
4849 // __aeabi_read_tp preserves the registers r1-r3.
4850 // This is a pseudo inst so that we can get the encoding right,
4851 // complete with fixup for the aeabi_read_tp function.
4853 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4854 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4855 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
4858 //===----------------------------------------------------------------------===//
4859 // SJLJ Exception handling intrinsics
4860 // eh_sjlj_setjmp() is an instruction sequence to store the return
4861 // address and save #0 in R0 for the non-longjmp case.
4862 // Since by its nature we may be coming from some other function to get
4863 // here, and we're using the stack frame for the containing function to
4864 // save/restore registers, we can't keep anything live in regs across
4865 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4866 // when we get here from a longjmp(). We force everything out of registers
4867 // except for our own input by listing the relevant registers in Defs. By
4868 // doing so, we also cause the prologue/epilogue code to actively preserve
4869 // all of the callee-saved resgisters, which is exactly what we want.
4870 // A constant value is passed in $val, and we use the location as a scratch.
4872 // These are pseudo-instructions and are lowered to individual MC-insts, so
4873 // no encoding information is necessary.
4875 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4876 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4877 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4878 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4880 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4881 Requires<[IsARM, HasVFP2]>;
4885 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4886 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4887 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4889 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4890 Requires<[IsARM, NoVFP]>;
4893 // FIXME: Non-IOS version(s)
4894 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4895 Defs = [ R7, LR, SP ] in {
4896 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4898 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4899 Requires<[IsARM, IsIOS]>;
4902 // eh.sjlj.dispatchsetup pseudo-instruction.
4903 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4904 // the pseudo is expanded (which happens before any passes that need the
4905 // instruction size).
4906 let isBarrier = 1 in
4907 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4910 //===----------------------------------------------------------------------===//
4911 // Non-Instruction Patterns
4914 // ARMv4 indirect branch using (MOVr PC, dst)
4915 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4916 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4917 4, IIC_Br, [(brind GPR:$dst)],
4918 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4919 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
4921 // Large immediate handling.
4923 // 32-bit immediate using two piece so_imms or movw + movt.
4924 // This is a single pseudo instruction, the benefit is that it can be remat'd
4925 // as a single unit instead of having to handle reg inputs.
4926 // FIXME: Remove this when we can do generalized remat.
4927 let isReMaterializable = 1, isMoveImm = 1 in
4928 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4929 [(set GPR:$dst, (arm_i32imm:$src))]>,
4932 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4933 // It also makes it possible to rematerialize the instructions.
4934 // FIXME: Remove this when we can do generalized remat and when machine licm
4935 // can properly the instructions.
4936 let isReMaterializable = 1 in {
4937 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4939 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4940 Requires<[IsARM, UseMovt]>;
4942 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4944 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4945 Requires<[IsARM, UseMovt]>;
4947 let AddedComplexity = 10 in
4948 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4950 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4951 Requires<[IsARM, UseMovt]>;
4952 } // isReMaterializable
4954 // ConstantPool, GlobalAddress, and JumpTable
4955 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4956 Requires<[IsARM, DontUseMovt]>;
4957 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4958 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4959 Requires<[IsARM, UseMovt]>;
4960 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4961 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4963 // TODO: add,sub,and, 3-instr forms?
4965 // Tail calls. These patterns also apply to Thumb mode.
4966 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4967 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4968 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4971 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4972 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4973 (BMOVPCB_CALL texternalsym:$func)>;
4975 // zextload i1 -> zextload i8
4976 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4977 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4979 // extload -> zextload
4980 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4981 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4982 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4983 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4985 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4987 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4988 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4991 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4992 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4993 (SMULBB GPR:$a, GPR:$b)>;
4994 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4995 (SMULBB GPR:$a, GPR:$b)>;
4996 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4997 (sra GPR:$b, (i32 16))),
4998 (SMULBT GPR:$a, GPR:$b)>;
4999 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5000 (SMULBT GPR:$a, GPR:$b)>;
5001 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5002 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5003 (SMULTB GPR:$a, GPR:$b)>;
5004 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5005 (SMULTB GPR:$a, GPR:$b)>;
5006 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5008 (SMULWB GPR:$a, GPR:$b)>;
5009 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5010 (SMULWB GPR:$a, GPR:$b)>;
5012 def : ARMV5MOPat<(add GPR:$acc,
5013 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5014 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5015 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5016 def : ARMV5MOPat<(add GPR:$acc,
5017 (mul sext_16_node:$a, sext_16_node:$b)),
5018 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5019 def : ARMV5MOPat<(add GPR:$acc,
5020 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5021 (sra GPR:$b, (i32 16)))),
5022 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5023 def : ARMV5MOPat<(add GPR:$acc,
5024 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5025 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5026 def : ARMV5MOPat<(add GPR:$acc,
5027 (mul (sra GPR:$a, (i32 16)),
5028 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5029 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5030 def : ARMV5MOPat<(add GPR:$acc,
5031 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5032 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5033 def : ARMV5MOPat<(add GPR:$acc,
5034 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5036 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5037 def : ARMV5MOPat<(add GPR:$acc,
5038 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5039 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5042 // Pre-v7 uses MCR for synchronization barriers.
5043 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5044 Requires<[IsARM, HasV6]>;
5046 // SXT/UXT with no rotate
5047 let AddedComplexity = 16 in {
5048 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5049 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5050 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5051 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5052 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5053 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5054 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5057 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5058 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5060 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5061 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5062 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5063 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5065 // Atomic load/store patterns
5066 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5067 (LDRBrs ldst_so_reg:$src)>;
5068 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5069 (LDRBi12 addrmode_imm12:$src)>;
5070 def : ARMPat<(atomic_load_16 addrmode3:$src),
5071 (LDRH addrmode3:$src)>;
5072 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5073 (LDRrs ldst_so_reg:$src)>;
5074 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5075 (LDRi12 addrmode_imm12:$src)>;
5076 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5077 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5078 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5079 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5080 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5081 (STRH GPR:$val, addrmode3:$ptr)>;
5082 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5083 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5084 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5085 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5088 //===----------------------------------------------------------------------===//
5092 include "ARMInstrThumb.td"
5094 //===----------------------------------------------------------------------===//
5098 include "ARMInstrThumb2.td"
5100 //===----------------------------------------------------------------------===//
5101 // Floating Point Support
5104 include "ARMInstrVFP.td"
5106 //===----------------------------------------------------------------------===//
5107 // Advanced SIMD (NEON) Support
5110 include "ARMInstrNEON.td"
5112 //===----------------------------------------------------------------------===//
5113 // Assembler aliases
5117 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5118 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5119 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5121 // System instructions
5122 def : MnemonicAlias<"swi", "svc">;
5124 // Load / Store Multiple
5125 def : MnemonicAlias<"ldmfd", "ldm">;
5126 def : MnemonicAlias<"ldmia", "ldm">;
5127 def : MnemonicAlias<"ldmea", "ldmdb">;
5128 def : MnemonicAlias<"stmfd", "stmdb">;
5129 def : MnemonicAlias<"stmia", "stm">;
5130 def : MnemonicAlias<"stmea", "stm">;
5132 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5133 // shift amount is zero (i.e., unspecified).
5134 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5135 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5136 Requires<[IsARM, HasV6]>;
5137 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5138 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5139 Requires<[IsARM, HasV6]>;
5141 // PUSH/POP aliases for STM/LDM
5142 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5143 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5145 // SSAT/USAT optional shift operand.
5146 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5147 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5148 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5149 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5152 // Extend instruction optional rotate operand.
5153 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5154 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5155 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5156 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5157 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5158 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5159 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5160 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5161 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5162 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5163 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5164 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5166 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5167 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5168 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5169 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5170 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5171 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5172 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5173 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5174 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5175 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5176 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5177 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5181 def : MnemonicAlias<"rfefa", "rfeda">;
5182 def : MnemonicAlias<"rfeea", "rfedb">;
5183 def : MnemonicAlias<"rfefd", "rfeia">;
5184 def : MnemonicAlias<"rfeed", "rfeib">;
5185 def : MnemonicAlias<"rfe", "rfeia">;
5188 def : MnemonicAlias<"srsfa", "srsib">;
5189 def : MnemonicAlias<"srsea", "srsia">;
5190 def : MnemonicAlias<"srsfd", "srsdb">;
5191 def : MnemonicAlias<"srsed", "srsda">;
5192 def : MnemonicAlias<"srs", "srsia">;
5195 def : MnemonicAlias<"qsubaddx", "qsax">;
5197 def : MnemonicAlias<"saddsubx", "sasx">;
5198 // SHASX == SHADDSUBX
5199 def : MnemonicAlias<"shaddsubx", "shasx">;
5200 // SHSAX == SHSUBADDX
5201 def : MnemonicAlias<"shsubaddx", "shsax">;
5203 def : MnemonicAlias<"ssubaddx", "ssax">;
5205 def : MnemonicAlias<"uaddsubx", "uasx">;
5206 // UHASX == UHADDSUBX
5207 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5208 // UHSAX == UHSUBADDX
5209 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5210 // UQASX == UQADDSUBX
5211 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5212 // UQSAX == UQSUBADDX
5213 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5215 def : MnemonicAlias<"usubaddx", "usax">;
5217 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5219 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5220 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5221 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5222 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5223 // Same for AND <--> BIC
5224 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5225 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5226 pred:$p, cc_out:$s)>;
5227 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5228 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5229 pred:$p, cc_out:$s)>;
5230 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5231 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5232 pred:$p, cc_out:$s)>;
5233 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5234 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5235 pred:$p, cc_out:$s)>;
5237 // Likewise, "add Rd, so_imm_neg" -> sub
5238 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5239 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5240 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5241 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5242 // Same for CMP <--> CMN via so_imm_neg
5243 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5244 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5245 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5246 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5248 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5249 // LSR, ROR, and RRX instructions.
5250 // FIXME: We need C++ parser hooks to map the alias to the MOV
5251 // encoding. It seems we should be able to do that sort of thing
5252 // in tblgen, but it could get ugly.
5253 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5254 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5255 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5257 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5258 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5260 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5261 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5263 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5264 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5267 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5268 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5269 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5270 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5271 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5273 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5274 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5276 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5277 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5279 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5280 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5284 // "neg" is and alias for "rsb rd, rn, #0"
5285 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5286 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5288 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5289 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5290 Requires<[IsARM, NoV6]>;
5292 // UMULL/SMULL are available on all arches, but the instruction definitions
5293 // need difference constraints pre-v6. Use these aliases for the assembly
5294 // parsing on pre-v6.
5295 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5296 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5297 Requires<[IsARM, NoV6]>;
5298 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5299 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5300 Requires<[IsARM, NoV6]>;
5302 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5304 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;