1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
479 // addrmode_imm12 := reg +/- imm12
481 def addrmode_imm12 : Operand<i32>,
482 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
483 // 12-bit immediate operand. Note that instructions using this encode
484 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
485 // immediate values are as normal.
487 let EncoderMethod = "getAddrModeImm12OpValue";
488 let PrintMethod = "printAddrModeImm12Operand";
489 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
491 // ldst_so_reg := reg +/- reg shop imm
493 def ldst_so_reg : Operand<i32>,
494 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
495 let EncoderMethod = "getLdStSORegOpValue";
496 // FIXME: Simplify the printer
497 let PrintMethod = "printAddrMode2Operand";
498 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
501 // addrmode2 := reg +/- imm12
502 // := reg +/- reg shop imm
504 def addrmode2 : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
506 let EncoderMethod = "getAddrMode2OpValue";
507 let PrintMethod = "printAddrMode2Operand";
508 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
511 def am2offset : Operand<i32>,
512 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
513 [], [SDNPWantRoot]> {
514 let EncoderMethod = "getAddrMode2OffsetOpValue";
515 let PrintMethod = "printAddrMode2OffsetOperand";
516 let MIOperandInfo = (ops GPR, i32imm);
519 // addrmode3 := reg +/- reg
520 // addrmode3 := reg +/- imm8
522 def addrmode3 : Operand<i32>,
523 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
524 let EncoderMethod = "getAddrMode3OpValue";
525 let PrintMethod = "printAddrMode3Operand";
526 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
529 def am3offset : Operand<i32>,
530 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
531 [], [SDNPWantRoot]> {
532 let EncoderMethod = "getAddrMode3OffsetOpValue";
533 let PrintMethod = "printAddrMode3OffsetOperand";
534 let MIOperandInfo = (ops GPR, i32imm);
537 // ldstm_mode := {ia, ib, da, db}
539 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
540 let EncoderMethod = "getLdStmModeOpValue";
541 let PrintMethod = "printLdStmModeOperand";
544 def MemMode5AsmOperand : AsmOperandClass {
545 let Name = "MemMode5";
546 let SuperClasses = [];
549 // addrmode5 := reg +/- imm8*4
551 def addrmode5 : Operand<i32>,
552 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
553 let PrintMethod = "printAddrMode5Operand";
554 let MIOperandInfo = (ops GPR:$base, i32imm);
555 let ParserMatchClass = MemMode5AsmOperand;
556 let EncoderMethod = "getAddrMode5OpValue";
559 // addrmode6 := reg with optional alignment
561 def addrmode6 : Operand<i32>,
562 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
563 let PrintMethod = "printAddrMode6Operand";
564 let MIOperandInfo = (ops GPR:$addr, i32imm);
565 let EncoderMethod = "getAddrMode6AddressOpValue";
568 def am6offset : Operand<i32>,
569 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
570 [], [SDNPWantRoot]> {
571 let PrintMethod = "printAddrMode6OffsetOperand";
572 let MIOperandInfo = (ops GPR);
573 let EncoderMethod = "getAddrMode6OffsetOpValue";
576 // Special version of addrmode6 to handle alignment encoding for VLD-dup
577 // instructions, specifically VLD4-dup.
578 def addrmode6dup : Operand<i32>,
579 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
580 let PrintMethod = "printAddrMode6Operand";
581 let MIOperandInfo = (ops GPR:$addr, i32imm);
582 let EncoderMethod = "getAddrMode6DupAddressOpValue";
585 // addrmodepc := pc + reg
587 def addrmodepc : Operand<i32>,
588 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
589 let PrintMethod = "printAddrModePCOperand";
590 let MIOperandInfo = (ops GPR, i32imm);
593 def MemMode7AsmOperand : AsmOperandClass {
594 let Name = "MemMode7";
595 let SuperClasses = [];
599 // Used by load/store exclusive instructions. Useful to enable right assembly
600 // parsing and printing. Not used for any codegen matching.
602 def addrmode7 : Operand<i32> {
603 let PrintMethod = "printAddrMode7Operand";
604 let MIOperandInfo = (ops GPR);
605 let ParserMatchClass = MemMode7AsmOperand;
608 def nohash_imm : Operand<i32> {
609 let PrintMethod = "printNoHashImmediate";
612 def CoprocNumAsmOperand : AsmOperandClass {
613 let Name = "CoprocNum";
614 let SuperClasses = [];
615 let ParserMethod = "tryParseCoprocNumOperand";
618 def CoprocRegAsmOperand : AsmOperandClass {
619 let Name = "CoprocReg";
620 let SuperClasses = [];
621 let ParserMethod = "tryParseCoprocRegOperand";
624 def p_imm : Operand<i32> {
625 let PrintMethod = "printPImmediate";
626 let ParserMatchClass = CoprocNumAsmOperand;
629 def c_imm : Operand<i32> {
630 let PrintMethod = "printCImmediate";
631 let ParserMatchClass = CoprocRegAsmOperand;
634 //===----------------------------------------------------------------------===//
636 include "ARMInstrFormats.td"
638 //===----------------------------------------------------------------------===//
639 // Multiclass helpers...
642 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
643 /// binop that produces a value.
644 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
645 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
646 PatFrag opnode, bit Commutable = 0> {
647 // The register-immediate version is re-materializable. This is useful
648 // in particular for taking the address of a local.
649 let isReMaterializable = 1 in {
650 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
651 iii, opc, "\t$Rd, $Rn, $imm",
652 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
657 let Inst{19-16} = Rn;
658 let Inst{15-12} = Rd;
659 let Inst{11-0} = imm;
662 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
663 iir, opc, "\t$Rd, $Rn, $Rm",
664 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
669 let isCommutable = Commutable;
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-4} = 0b00000000;
675 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
676 iis, opc, "\t$Rd, $Rn, $shift",
677 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
682 let Inst{19-16} = Rn;
683 let Inst{15-12} = Rd;
684 let Inst{11-0} = shift;
688 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
689 /// instruction modifies the CPSR register.
690 let isCodeGenOnly = 1, Defs = [CPSR] in {
691 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
692 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
693 PatFrag opnode, bit Commutable = 0> {
694 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
695 iii, opc, "\t$Rd, $Rn, $imm",
696 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
702 let Inst{19-16} = Rn;
703 let Inst{15-12} = Rd;
704 let Inst{11-0} = imm;
706 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
707 iir, opc, "\t$Rd, $Rn, $Rm",
708 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
712 let isCommutable = Commutable;
715 let Inst{19-16} = Rn;
716 let Inst{15-12} = Rd;
717 let Inst{11-4} = 0b00000000;
720 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
721 iis, opc, "\t$Rd, $Rn, $shift",
722 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = Rd;
730 let Inst{11-0} = shift;
735 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
736 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
737 /// a explicit result, only implicitly set CPSR.
738 let isCompare = 1, Defs = [CPSR] in {
739 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
740 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
741 PatFrag opnode, bit Commutable = 0> {
742 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
744 [(opnode GPR:$Rn, so_imm:$imm)]> {
749 let Inst{19-16} = Rn;
750 let Inst{15-12} = 0b0000;
751 let Inst{11-0} = imm;
753 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
755 [(opnode GPR:$Rn, GPR:$Rm)]> {
758 let isCommutable = Commutable;
761 let Inst{19-16} = Rn;
762 let Inst{15-12} = 0b0000;
763 let Inst{11-4} = 0b00000000;
766 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
767 opc, "\t$Rn, $shift",
768 [(opnode GPR:$Rn, so_reg:$shift)]> {
773 let Inst{19-16} = Rn;
774 let Inst{15-12} = 0b0000;
775 let Inst{11-0} = shift;
780 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
781 /// register and one whose operand is a register rotated by 8/16/24.
782 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
783 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
784 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
785 IIC_iEXTr, opc, "\t$Rd, $Rm",
786 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
787 Requires<[IsARM, HasV6]> {
790 let Inst{19-16} = 0b1111;
791 let Inst{15-12} = Rd;
792 let Inst{11-10} = 0b00;
795 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
796 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
797 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
798 Requires<[IsARM, HasV6]> {
802 let Inst{19-16} = 0b1111;
803 let Inst{15-12} = Rd;
804 let Inst{11-10} = rot;
809 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
810 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
811 IIC_iEXTr, opc, "\t$Rd, $Rm",
812 [/* For disassembly only; pattern left blank */]>,
813 Requires<[IsARM, HasV6]> {
814 let Inst{19-16} = 0b1111;
815 let Inst{11-10} = 0b00;
817 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
818 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
819 [/* For disassembly only; pattern left blank */]>,
820 Requires<[IsARM, HasV6]> {
822 let Inst{19-16} = 0b1111;
823 let Inst{11-10} = rot;
827 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
828 /// register and one whose operand is a register rotated by 8/16/24.
829 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
830 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
831 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
832 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
833 Requires<[IsARM, HasV6]> {
837 let Inst{19-16} = Rn;
838 let Inst{15-12} = Rd;
839 let Inst{11-10} = 0b00;
840 let Inst{9-4} = 0b000111;
843 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
845 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
846 [(set GPR:$Rd, (opnode GPR:$Rn,
847 (rotr GPR:$Rm, rot_imm:$rot)))]>,
848 Requires<[IsARM, HasV6]> {
853 let Inst{19-16} = Rn;
854 let Inst{15-12} = Rd;
855 let Inst{11-10} = rot;
856 let Inst{9-4} = 0b000111;
861 // For disassembly only.
862 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
863 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
864 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
865 [/* For disassembly only; pattern left blank */]>,
866 Requires<[IsARM, HasV6]> {
867 let Inst{11-10} = 0b00;
869 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
871 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
872 [/* For disassembly only; pattern left blank */]>,
873 Requires<[IsARM, HasV6]> {
876 let Inst{19-16} = Rn;
877 let Inst{11-10} = rot;
881 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
882 let Uses = [CPSR] in {
883 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
884 bit Commutable = 0> {
885 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
886 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
887 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
893 let Inst{15-12} = Rd;
894 let Inst{19-16} = Rn;
895 let Inst{11-0} = imm;
897 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
898 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
899 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
904 let Inst{11-4} = 0b00000000;
906 let isCommutable = Commutable;
908 let Inst{15-12} = Rd;
909 let Inst{19-16} = Rn;
911 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
912 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
913 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
919 let Inst{11-0} = shift;
920 let Inst{15-12} = Rd;
921 let Inst{19-16} = Rn;
924 // Carry setting variants
925 let isCodeGenOnly = 1, Defs = [CPSR] in {
926 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
927 bit Commutable = 0> {
928 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
929 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
930 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
935 let Inst{15-12} = Rd;
936 let Inst{19-16} = Rn;
937 let Inst{11-0} = imm;
941 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
942 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
943 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
948 let Inst{11-4} = 0b00000000;
949 let isCommutable = Commutable;
951 let Inst{15-12} = Rd;
952 let Inst{19-16} = Rn;
956 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
957 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
958 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
963 let Inst{11-0} = shift;
964 let Inst{15-12} = Rd;
965 let Inst{19-16} = Rn;
973 let canFoldAsLoad = 1, isReMaterializable = 1 in {
974 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
975 InstrItinClass iir, PatFrag opnode> {
976 // Note: We use the complex addrmode_imm12 rather than just an input
977 // GPR and a constrained immediate so that we can use this to match
978 // frame index references and avoid matching constant pool references.
979 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
980 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
981 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
984 let Inst{23} = addr{12}; // U (add = ('U' == 1))
985 let Inst{19-16} = addr{16-13}; // Rn
986 let Inst{15-12} = Rt;
987 let Inst{11-0} = addr{11-0}; // imm12
989 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
990 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
991 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
994 let Inst{23} = shift{12}; // U (add = ('U' == 1))
995 let Inst{19-16} = shift{16-13}; // Rn
996 let Inst{15-12} = Rt;
997 let Inst{11-0} = shift{11-0};
1002 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1003 InstrItinClass iir, PatFrag opnode> {
1004 // Note: We use the complex addrmode_imm12 rather than just an input
1005 // GPR and a constrained immediate so that we can use this to match
1006 // frame index references and avoid matching constant pool references.
1007 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1008 (ins GPR:$Rt, addrmode_imm12:$addr),
1009 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1010 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1013 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1014 let Inst{19-16} = addr{16-13}; // Rn
1015 let Inst{15-12} = Rt;
1016 let Inst{11-0} = addr{11-0}; // imm12
1018 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1019 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1020 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1023 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1024 let Inst{19-16} = shift{16-13}; // Rn
1025 let Inst{15-12} = Rt;
1026 let Inst{11-0} = shift{11-0};
1029 //===----------------------------------------------------------------------===//
1031 //===----------------------------------------------------------------------===//
1033 //===----------------------------------------------------------------------===//
1034 // Miscellaneous Instructions.
1037 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1038 /// the function. The first operand is the ID# for this instruction, the second
1039 /// is the index into the MachineConstantPool that this is, the third is the
1040 /// size in bytes of this constant pool entry.
1041 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1042 def CONSTPOOL_ENTRY :
1043 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1044 i32imm:$size), NoItinerary, []>;
1046 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1047 // from removing one half of the matched pairs. That breaks PEI, which assumes
1048 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1049 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1050 def ADJCALLSTACKUP :
1051 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1052 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1054 def ADJCALLSTACKDOWN :
1055 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1056 [(ARMcallseq_start timm:$amt)]>;
1059 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1060 [/* For disassembly only; pattern left blank */]>,
1061 Requires<[IsARM, HasV6T2]> {
1062 let Inst{27-16} = 0b001100100000;
1063 let Inst{15-8} = 0b11110000;
1064 let Inst{7-0} = 0b00000000;
1067 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1068 [/* For disassembly only; pattern left blank */]>,
1069 Requires<[IsARM, HasV6T2]> {
1070 let Inst{27-16} = 0b001100100000;
1071 let Inst{15-8} = 0b11110000;
1072 let Inst{7-0} = 0b00000001;
1075 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1076 [/* For disassembly only; pattern left blank */]>,
1077 Requires<[IsARM, HasV6T2]> {
1078 let Inst{27-16} = 0b001100100000;
1079 let Inst{15-8} = 0b11110000;
1080 let Inst{7-0} = 0b00000010;
1083 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1084 [/* For disassembly only; pattern left blank */]>,
1085 Requires<[IsARM, HasV6T2]> {
1086 let Inst{27-16} = 0b001100100000;
1087 let Inst{15-8} = 0b11110000;
1088 let Inst{7-0} = 0b00000011;
1091 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1093 [/* For disassembly only; pattern left blank */]>,
1094 Requires<[IsARM, HasV6]> {
1099 let Inst{15-12} = Rd;
1100 let Inst{19-16} = Rn;
1101 let Inst{27-20} = 0b01101000;
1102 let Inst{7-4} = 0b1011;
1103 let Inst{11-8} = 0b1111;
1106 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1107 [/* For disassembly only; pattern left blank */]>,
1108 Requires<[IsARM, HasV6T2]> {
1109 let Inst{27-16} = 0b001100100000;
1110 let Inst{15-8} = 0b11110000;
1111 let Inst{7-0} = 0b00000100;
1114 // The i32imm operand $val can be used by a debugger to store more information
1115 // about the breakpoint.
1116 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1117 [/* For disassembly only; pattern left blank */]>,
1120 let Inst{3-0} = val{3-0};
1121 let Inst{19-8} = val{15-4};
1122 let Inst{27-20} = 0b00010010;
1123 let Inst{7-4} = 0b0111;
1126 // Change Processor State is a system instruction -- for disassembly and
1128 // FIXME: Since the asm parser has currently no clean way to handle optional
1129 // operands, create 3 versions of the same instruction. Once there's a clean
1130 // framework to represent optional operands, change this behavior.
1131 class CPS<dag iops, string asm_ops>
1132 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1133 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1139 let Inst{31-28} = 0b1111;
1140 let Inst{27-20} = 0b00010000;
1141 let Inst{19-18} = imod;
1142 let Inst{17} = M; // Enabled if mode is set;
1144 let Inst{8-6} = iflags;
1146 let Inst{4-0} = mode;
1150 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1151 "$imod\t$iflags, $mode">;
1152 let mode = 0, M = 0 in
1153 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1155 let imod = 0, iflags = 0, M = 1 in
1156 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1158 // Preload signals the memory system of possible future data/instruction access.
1159 // These are for disassembly only.
1160 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1162 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1163 !strconcat(opc, "\t$addr"),
1164 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1167 let Inst{31-26} = 0b111101;
1168 let Inst{25} = 0; // 0 for immediate form
1169 let Inst{24} = data;
1170 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1171 let Inst{22} = read;
1172 let Inst{21-20} = 0b01;
1173 let Inst{19-16} = addr{16-13}; // Rn
1174 let Inst{15-12} = 0b1111;
1175 let Inst{11-0} = addr{11-0}; // imm12
1178 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1179 !strconcat(opc, "\t$shift"),
1180 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1182 let Inst{31-26} = 0b111101;
1183 let Inst{25} = 1; // 1 for register form
1184 let Inst{24} = data;
1185 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1186 let Inst{22} = read;
1187 let Inst{21-20} = 0b01;
1188 let Inst{19-16} = shift{16-13}; // Rn
1189 let Inst{15-12} = 0b1111;
1190 let Inst{11-0} = shift{11-0};
1194 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1195 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1196 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1198 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1200 [/* For disassembly only; pattern left blank */]>,
1203 let Inst{31-10} = 0b1111000100000001000000;
1208 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1209 [/* For disassembly only; pattern left blank */]>,
1210 Requires<[IsARM, HasV7]> {
1212 let Inst{27-4} = 0b001100100000111100001111;
1213 let Inst{3-0} = opt;
1216 // A5.4 Permanently UNDEFINED instructions.
1217 let isBarrier = 1, isTerminator = 1 in
1218 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1221 let Inst = 0xe7ffdefe;
1224 // Address computation and loads and stores in PIC mode.
1225 let isNotDuplicable = 1 in {
1226 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1227 Size4Bytes, IIC_iALUr,
1228 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1230 let AddedComplexity = 10 in {
1231 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1232 Size4Bytes, IIC_iLoad_r,
1233 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1235 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1236 Size4Bytes, IIC_iLoad_bh_r,
1237 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1239 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1240 Size4Bytes, IIC_iLoad_bh_r,
1241 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1243 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1244 Size4Bytes, IIC_iLoad_bh_r,
1245 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1247 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1248 Size4Bytes, IIC_iLoad_bh_r,
1249 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1251 let AddedComplexity = 10 in {
1252 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1253 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1255 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1256 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1257 addrmodepc:$addr)]>;
1259 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1260 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1262 } // isNotDuplicable = 1
1265 // LEApcrel - Load a pc-relative address into a register without offending the
1267 let neverHasSideEffects = 1, isReMaterializable = 1 in
1268 // The 'adr' mnemonic encodes differently if the label is before or after
1269 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1270 // know until then which form of the instruction will be used.
1271 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1272 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1275 let Inst{27-25} = 0b001;
1277 let Inst{19-16} = 0b1111;
1278 let Inst{15-12} = Rd;
1279 let Inst{11-0} = label;
1281 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1282 Size4Bytes, IIC_iALUi, []>;
1284 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1285 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1286 Size4Bytes, IIC_iALUi, []>;
1288 //===----------------------------------------------------------------------===//
1289 // Control Flow Instructions.
1292 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1294 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1295 "bx", "\tlr", [(ARMretflag)]>,
1296 Requires<[IsARM, HasV4T]> {
1297 let Inst{27-0} = 0b0001001011111111111100011110;
1301 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1302 "mov", "\tpc, lr", [(ARMretflag)]>,
1303 Requires<[IsARM, NoV4T]> {
1304 let Inst{27-0} = 0b0001101000001111000000001110;
1308 // Indirect branches
1309 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1311 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1312 [(brind GPR:$dst)]>,
1313 Requires<[IsARM, HasV4T]> {
1315 let Inst{31-4} = 0b1110000100101111111111110001;
1316 let Inst{3-0} = dst;
1320 // FIXME: We would really like to define this as a vanilla ARMPat like:
1321 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1322 // With that, however, we can't set isBranch, isTerminator, etc..
1323 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1324 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1325 Requires<[IsARM, NoV4T]>;
1328 // All calls clobber the non-callee saved registers. SP is marked as
1329 // a use to prevent stack-pointer assignments that appear immediately
1330 // before calls from potentially appearing dead.
1332 // On non-Darwin platforms R9 is callee-saved.
1333 // FIXME: Do we really need a non-predicated version? If so, it should
1334 // at least be a pseudo instruction expanding to the predicated version
1335 // at MC lowering time.
1336 Defs = [R0, R1, R2, R3, R12, LR,
1337 D0, D1, D2, D3, D4, D5, D6, D7,
1338 D16, D17, D18, D19, D20, D21, D22, D23,
1339 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1341 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1342 IIC_Br, "bl\t$func",
1343 [(ARMcall tglobaladdr:$func)]>,
1344 Requires<[IsARM, IsNotDarwin]> {
1345 let Inst{31-28} = 0b1110;
1347 let Inst{23-0} = func;
1350 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1351 IIC_Br, "bl", "\t$func",
1352 [(ARMcall_pred tglobaladdr:$func)]>,
1353 Requires<[IsARM, IsNotDarwin]> {
1355 let Inst{23-0} = func;
1359 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1360 IIC_Br, "blx\t$func",
1361 [(ARMcall GPR:$func)]>,
1362 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1364 let Inst{31-4} = 0b1110000100101111111111110011;
1365 let Inst{3-0} = func;
1368 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1369 IIC_Br, "blx", "\t$func",
1370 [(ARMcall_pred GPR:$func)]>,
1371 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1373 let Inst{27-4} = 0b000100101111111111110011;
1374 let Inst{3-0} = func;
1378 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1379 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1380 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1381 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1384 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1385 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1386 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1390 // On Darwin R9 is call-clobbered.
1391 // R7 is marked as a use to prevent frame-pointer assignments from being
1392 // moved above / below calls.
1393 Defs = [R0, R1, R2, R3, R9, R12, LR,
1394 D0, D1, D2, D3, D4, D5, D6, D7,
1395 D16, D17, D18, D19, D20, D21, D22, D23,
1396 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1397 Uses = [R7, SP] in {
1398 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1400 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1402 def BLr9_pred : ARMPseudoInst<(outs),
1403 (ins bltarget:$func, pred:$p, variable_ops),
1405 [(ARMcall_pred tglobaladdr:$func)]>,
1406 Requires<[IsARM, IsDarwin]>;
1409 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1411 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1413 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1415 [(ARMcall_pred GPR:$func)]>,
1416 Requires<[IsARM, HasV5T, IsDarwin]>;
1419 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1420 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1421 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1422 Requires<[IsARM, HasV4T, IsDarwin]>;
1425 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1426 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1427 Requires<[IsARM, NoV4T, IsDarwin]>;
1432 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1433 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1435 let Defs = [R0, R1, R2, R3, R9, R12,
1436 D0, D1, D2, D3, D4, D5, D6, D7,
1437 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1438 D27, D28, D29, D30, D31, PC],
1440 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1441 IIC_Br, []>, Requires<[IsDarwin]>;
1443 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1444 IIC_Br, []>, Requires<[IsDarwin]>;
1446 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1448 []>, Requires<[IsARM, IsDarwin]>;
1450 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1452 []>, Requires<[IsThumb, IsDarwin]>;
1454 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1456 []>, Requires<[IsARM, IsDarwin]>;
1458 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1460 []>, Requires<[IsThumb, IsDarwin]>;
1463 // Non-Darwin versions (the difference is R9).
1464 let Defs = [R0, R1, R2, R3, R12,
1465 D0, D1, D2, D3, D4, D5, D6, D7,
1466 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1467 D27, D28, D29, D30, D31, PC],
1469 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1470 IIC_Br, []>, Requires<[IsNotDarwin]>;
1472 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1473 IIC_Br, []>, Requires<[IsNotDarwin]>;
1475 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1477 []>, Requires<[IsARM, IsNotDarwin]>;
1479 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1481 []>, Requires<[IsThumb, IsNotDarwin]>;
1483 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1485 []>, Requires<[IsARM, IsNotDarwin]>;
1486 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1488 []>, Requires<[IsThumb, IsNotDarwin]>;
1492 let isBranch = 1, isTerminator = 1 in {
1493 // B is "predicable" since it's just a Bcc with an 'always' condition.
1494 let isBarrier = 1 in {
1495 let isPredicable = 1 in
1496 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1497 // should be sufficient.
1498 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1501 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1502 def BR_JTr : ARMPseudoInst<(outs),
1503 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1504 SizeSpecial, IIC_Br,
1505 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1506 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1507 // into i12 and rs suffixed versions.
1508 def BR_JTm : ARMPseudoInst<(outs),
1509 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1510 SizeSpecial, IIC_Br,
1511 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1513 def BR_JTadd : ARMPseudoInst<(outs),
1514 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1515 SizeSpecial, IIC_Br,
1516 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1518 } // isNotDuplicable = 1, isIndirectBranch = 1
1521 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1522 // a two-value operand where a dag node expects two operands. :(
1523 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1524 IIC_Br, "b", "\t$target",
1525 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1527 let Inst{23-0} = target;
1531 // Branch and Exchange Jazelle -- for disassembly only
1532 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1533 [/* For disassembly only; pattern left blank */]> {
1534 let Inst{23-20} = 0b0010;
1535 //let Inst{19-8} = 0xfff;
1536 let Inst{7-4} = 0b0010;
1539 // Secure Monitor Call is a system instruction -- for disassembly only
1540 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1541 [/* For disassembly only; pattern left blank */]> {
1543 let Inst{23-4} = 0b01100000000000000111;
1544 let Inst{3-0} = opt;
1547 // Supervisor Call (Software Interrupt) -- for disassembly only
1548 let isCall = 1, Uses = [SP] in {
1549 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1550 [/* For disassembly only; pattern left blank */]> {
1552 let Inst{23-0} = svc;
1555 def : MnemonicAlias<"swi", "svc">;
1557 // Store Return State is a system instruction -- for disassembly only
1558 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1559 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1560 NoItinerary, "srs${amode}\tsp!, $mode",
1561 [/* For disassembly only; pattern left blank */]> {
1562 let Inst{31-28} = 0b1111;
1563 let Inst{22-20} = 0b110; // W = 1
1566 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1567 NoItinerary, "srs${amode}\tsp, $mode",
1568 [/* For disassembly only; pattern left blank */]> {
1569 let Inst{31-28} = 0b1111;
1570 let Inst{22-20} = 0b100; // W = 0
1573 // Return From Exception is a system instruction -- for disassembly only
1574 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1575 NoItinerary, "rfe${amode}\t$base!",
1576 [/* For disassembly only; pattern left blank */]> {
1577 let Inst{31-28} = 0b1111;
1578 let Inst{22-20} = 0b011; // W = 1
1581 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1582 NoItinerary, "rfe${amode}\t$base",
1583 [/* For disassembly only; pattern left blank */]> {
1584 let Inst{31-28} = 0b1111;
1585 let Inst{22-20} = 0b001; // W = 0
1587 } // isCodeGenOnly = 1
1589 //===----------------------------------------------------------------------===//
1590 // Load / store Instructions.
1596 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1597 UnOpFrag<(load node:$Src)>>;
1598 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1599 UnOpFrag<(zextloadi8 node:$Src)>>;
1600 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1601 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1602 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1603 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1605 // Special LDR for loads from non-pc-relative constpools.
1606 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1607 isReMaterializable = 1 in
1608 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1609 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1613 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1614 let Inst{19-16} = 0b1111;
1615 let Inst{15-12} = Rt;
1616 let Inst{11-0} = addr{11-0}; // imm12
1619 // Loads with zero extension
1620 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1621 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1622 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1624 // Loads with sign extension
1625 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1626 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1627 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1629 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1630 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1631 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1633 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1634 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1635 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1636 // how to represent that such that tblgen is happy and we don't
1637 // mark this codegen only?
1639 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1640 (ins addrmode3:$addr), LdMiscFrm,
1641 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1642 []>, Requires<[IsARM, HasV5TE]>;
1646 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1647 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1648 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1649 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1651 // {13} 1 == Rm, 0 == imm12
1655 let Inst{25} = addr{13};
1656 let Inst{23} = addr{12};
1657 let Inst{19-16} = addr{17-14};
1658 let Inst{11-0} = addr{11-0};
1660 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1661 (ins GPR:$Rn, am2offset:$offset),
1662 IndexModePost, LdFrm, itin,
1663 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1664 // {13} 1 == Rm, 0 == imm12
1669 let Inst{25} = offset{13};
1670 let Inst{23} = offset{12};
1671 let Inst{19-16} = Rn;
1672 let Inst{11-0} = offset{11-0};
1676 let mayLoad = 1, neverHasSideEffects = 1 in {
1677 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1678 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1681 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1682 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1683 (ins addrmode3:$addr), IndexModePre,
1685 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1687 let Inst{23} = addr{8}; // U bit
1688 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1689 let Inst{19-16} = addr{12-9}; // Rn
1690 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1691 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1693 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1694 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1696 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1699 let Inst{23} = offset{8}; // U bit
1700 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1701 let Inst{19-16} = Rn;
1702 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1703 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1707 let mayLoad = 1, neverHasSideEffects = 1 in {
1708 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1709 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1710 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1711 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1712 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1713 } // mayLoad = 1, neverHasSideEffects = 1
1715 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1716 let mayLoad = 1, neverHasSideEffects = 1 in {
1717 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1718 (ins GPR:$base, am2offset:$offset), IndexModePost,
1719 LdFrm, IIC_iLoad_ru,
1720 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1721 let Inst{21} = 1; // overwrite
1723 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1724 (ins GPR:$base, am2offset:$offset), IndexModePost,
1725 LdFrm, IIC_iLoad_bh_ru,
1726 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1727 let Inst{21} = 1; // overwrite
1729 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1730 (ins GPR:$base, am3offset:$offset), IndexModePost,
1731 LdMiscFrm, IIC_iLoad_bh_ru,
1732 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1733 let Inst{21} = 1; // overwrite
1735 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1736 (ins GPR:$base, am3offset:$offset), IndexModePost,
1737 LdMiscFrm, IIC_iLoad_bh_ru,
1738 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1739 let Inst{21} = 1; // overwrite
1741 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1742 (ins GPR:$base, am3offset:$offset), IndexModePost,
1743 LdMiscFrm, IIC_iLoad_bh_ru,
1744 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1745 let Inst{21} = 1; // overwrite
1751 // Stores with truncate
1752 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1753 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1754 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1757 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1758 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1759 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1760 StMiscFrm, IIC_iStore_d_r,
1761 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1764 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1765 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1766 IndexModePre, StFrm, IIC_iStore_ru,
1767 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1769 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1771 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1772 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1773 IndexModePost, StFrm, IIC_iStore_ru,
1774 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1776 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1778 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1779 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1780 IndexModePre, StFrm, IIC_iStore_bh_ru,
1781 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1782 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1783 GPR:$Rn, am2offset:$offset))]>;
1784 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1785 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1786 IndexModePost, StFrm, IIC_iStore_bh_ru,
1787 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1788 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1789 GPR:$Rn, am2offset:$offset))]>;
1791 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1792 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1793 IndexModePre, StMiscFrm, IIC_iStore_ru,
1794 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1796 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1798 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1799 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1800 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1801 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1802 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1803 GPR:$Rn, am3offset:$offset))]>;
1805 // For disassembly only
1806 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1807 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1808 StMiscFrm, IIC_iStore_d_ru,
1809 "strd", "\t$src1, $src2, [$base, $offset]!",
1810 "$base = $base_wb", []>;
1812 // For disassembly only
1813 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1814 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1815 StMiscFrm, IIC_iStore_d_ru,
1816 "strd", "\t$src1, $src2, [$base], $offset",
1817 "$base = $base_wb", []>;
1819 // STRT, STRBT, and STRHT are for disassembly only.
1821 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1822 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1823 IndexModePost, StFrm, IIC_iStore_ru,
1824 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1825 [/* For disassembly only; pattern left blank */]> {
1826 let Inst{21} = 1; // overwrite
1829 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1830 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1831 IndexModePost, StFrm, IIC_iStore_bh_ru,
1832 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1833 [/* For disassembly only; pattern left blank */]> {
1834 let Inst{21} = 1; // overwrite
1837 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1838 (ins GPR:$src, GPR:$base,am3offset:$offset),
1839 StMiscFrm, IIC_iStore_bh_ru,
1840 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1841 [/* For disassembly only; pattern left blank */]> {
1842 let Inst{21} = 1; // overwrite
1845 //===----------------------------------------------------------------------===//
1846 // Load / store multiple Instructions.
1849 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1850 InstrItinClass itin, InstrItinClass itin_upd> {
1852 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1853 IndexModeNone, f, itin,
1854 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1855 let Inst{24-23} = 0b01; // Increment After
1856 let Inst{21} = 0; // No writeback
1857 let Inst{20} = L_bit;
1860 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1861 IndexModeUpd, f, itin_upd,
1862 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1863 let Inst{24-23} = 0b01; // Increment After
1864 let Inst{21} = 1; // Writeback
1865 let Inst{20} = L_bit;
1868 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1869 IndexModeNone, f, itin,
1870 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1871 let Inst{24-23} = 0b00; // Decrement After
1872 let Inst{21} = 0; // No writeback
1873 let Inst{20} = L_bit;
1876 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1877 IndexModeUpd, f, itin_upd,
1878 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1879 let Inst{24-23} = 0b00; // Decrement After
1880 let Inst{21} = 1; // Writeback
1881 let Inst{20} = L_bit;
1884 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1885 IndexModeNone, f, itin,
1886 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1887 let Inst{24-23} = 0b10; // Decrement Before
1888 let Inst{21} = 0; // No writeback
1889 let Inst{20} = L_bit;
1892 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1893 IndexModeUpd, f, itin_upd,
1894 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1895 let Inst{24-23} = 0b10; // Decrement Before
1896 let Inst{21} = 1; // Writeback
1897 let Inst{20} = L_bit;
1900 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1901 IndexModeNone, f, itin,
1902 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1903 let Inst{24-23} = 0b11; // Increment Before
1904 let Inst{21} = 0; // No writeback
1905 let Inst{20} = L_bit;
1908 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1909 IndexModeUpd, f, itin_upd,
1910 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1911 let Inst{24-23} = 0b11; // Increment Before
1912 let Inst{21} = 1; // Writeback
1913 let Inst{20} = L_bit;
1917 let neverHasSideEffects = 1 in {
1919 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1920 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1922 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1923 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1925 } // neverHasSideEffects
1927 // Load / Store Multiple Mnemonic Aliases
1928 def : MnemonicAlias<"ldm", "ldmia">;
1929 def : MnemonicAlias<"stm", "stmia">;
1931 // FIXME: remove when we have a way to marking a MI with these properties.
1932 // FIXME: Should pc be an implicit operand like PICADD, etc?
1933 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1934 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1935 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1936 reglist:$regs, variable_ops),
1937 Size4Bytes, IIC_iLoad_mBr, []>,
1938 RegConstraint<"$Rn = $wb">;
1940 //===----------------------------------------------------------------------===//
1941 // Move Instructions.
1944 let neverHasSideEffects = 1 in
1945 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1946 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1950 let Inst{11-4} = 0b00000000;
1953 let Inst{15-12} = Rd;
1956 // A version for the smaller set of tail call registers.
1957 let neverHasSideEffects = 1 in
1958 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1959 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1963 let Inst{11-4} = 0b00000000;
1966 let Inst{15-12} = Rd;
1969 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1970 DPSoRegFrm, IIC_iMOVsr,
1971 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1975 let Inst{15-12} = Rd;
1976 let Inst{11-0} = src;
1980 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1981 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1982 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1986 let Inst{15-12} = Rd;
1987 let Inst{19-16} = 0b0000;
1988 let Inst{11-0} = imm;
1991 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1992 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
1994 "movw", "\t$Rd, $imm",
1995 [(set GPR:$Rd, imm0_65535:$imm)]>,
1996 Requires<[IsARM, HasV6T2]>, UnaryDP {
1999 let Inst{15-12} = Rd;
2000 let Inst{11-0} = imm{11-0};
2001 let Inst{19-16} = imm{15-12};
2006 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2007 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2009 let Constraints = "$src = $Rd" in {
2010 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2012 "movt", "\t$Rd, $imm",
2014 (or (and GPR:$src, 0xffff),
2015 lo16AllZero:$imm))]>, UnaryDP,
2016 Requires<[IsARM, HasV6T2]> {
2019 let Inst{15-12} = Rd;
2020 let Inst{11-0} = imm{11-0};
2021 let Inst{19-16} = imm{15-12};
2026 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2027 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2031 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2032 Requires<[IsARM, HasV6T2]>;
2034 let Uses = [CPSR] in
2035 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2036 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2039 // These aren't really mov instructions, but we have to define them this way
2040 // due to flag operands.
2042 let Defs = [CPSR] in {
2043 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2044 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2046 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2047 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2051 //===----------------------------------------------------------------------===//
2052 // Extend Instructions.
2057 defm SXTB : AI_ext_rrot<0b01101010,
2058 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2059 defm SXTH : AI_ext_rrot<0b01101011,
2060 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2062 defm SXTAB : AI_exta_rrot<0b01101010,
2063 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2064 defm SXTAH : AI_exta_rrot<0b01101011,
2065 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2067 // For disassembly only
2068 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2070 // For disassembly only
2071 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2075 let AddedComplexity = 16 in {
2076 defm UXTB : AI_ext_rrot<0b01101110,
2077 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2078 defm UXTH : AI_ext_rrot<0b01101111,
2079 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2080 defm UXTB16 : AI_ext_rrot<0b01101100,
2081 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2083 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2084 // The transformation should probably be done as a combiner action
2085 // instead so we can include a check for masking back in the upper
2086 // eight bits of the source into the lower eight bits of the result.
2087 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2088 // (UXTB16r_rot GPR:$Src, 24)>;
2089 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2090 (UXTB16r_rot GPR:$Src, 8)>;
2092 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2093 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2094 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2095 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2098 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2099 // For disassembly only
2100 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2103 def SBFX : I<(outs GPR:$Rd),
2104 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2105 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2106 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2107 Requires<[IsARM, HasV6T2]> {
2112 let Inst{27-21} = 0b0111101;
2113 let Inst{6-4} = 0b101;
2114 let Inst{20-16} = width;
2115 let Inst{15-12} = Rd;
2116 let Inst{11-7} = lsb;
2120 def UBFX : I<(outs GPR:$Rd),
2121 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2122 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2123 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2124 Requires<[IsARM, HasV6T2]> {
2129 let Inst{27-21} = 0b0111111;
2130 let Inst{6-4} = 0b101;
2131 let Inst{20-16} = width;
2132 let Inst{15-12} = Rd;
2133 let Inst{11-7} = lsb;
2137 //===----------------------------------------------------------------------===//
2138 // Arithmetic Instructions.
2141 defm ADD : AsI1_bin_irs<0b0100, "add",
2142 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2143 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2144 defm SUB : AsI1_bin_irs<0b0010, "sub",
2145 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2146 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2148 // ADD and SUB with 's' bit set.
2149 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2150 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2151 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2152 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2153 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2154 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2156 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2157 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2158 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2159 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2161 // ADC and SUBC with 's' bit set.
2162 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2163 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2164 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2165 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2167 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2168 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2169 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2174 let Inst{15-12} = Rd;
2175 let Inst{19-16} = Rn;
2176 let Inst{11-0} = imm;
2179 // The reg/reg form is only defined for the disassembler; for codegen it is
2180 // equivalent to SUBrr.
2181 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2182 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2183 [/* For disassembly only; pattern left blank */]> {
2187 let Inst{11-4} = 0b00000000;
2190 let Inst{15-12} = Rd;
2191 let Inst{19-16} = Rn;
2194 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2195 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2196 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2201 let Inst{11-0} = shift;
2202 let Inst{15-12} = Rd;
2203 let Inst{19-16} = Rn;
2206 // RSB with 's' bit set.
2207 let isCodeGenOnly = 1, Defs = [CPSR] in {
2208 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2209 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2210 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2216 let Inst{15-12} = Rd;
2217 let Inst{19-16} = Rn;
2218 let Inst{11-0} = imm;
2220 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2221 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2222 [/* For disassembly only; pattern left blank */]> {
2226 let Inst{11-4} = 0b00000000;
2230 let Inst{15-12} = Rd;
2231 let Inst{19-16} = Rn;
2233 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2234 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2235 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2241 let Inst{11-0} = shift;
2242 let Inst{15-12} = Rd;
2243 let Inst{19-16} = Rn;
2247 let Uses = [CPSR] in {
2248 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2249 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2250 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2256 let Inst{15-12} = Rd;
2257 let Inst{19-16} = Rn;
2258 let Inst{11-0} = imm;
2260 // The reg/reg form is only defined for the disassembler; for codegen it is
2261 // equivalent to SUBrr.
2262 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2263 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2264 [/* For disassembly only; pattern left blank */]> {
2268 let Inst{11-4} = 0b00000000;
2271 let Inst{15-12} = Rd;
2272 let Inst{19-16} = Rn;
2274 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2275 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2276 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2282 let Inst{11-0} = shift;
2283 let Inst{15-12} = Rd;
2284 let Inst{19-16} = Rn;
2288 // FIXME: Allow these to be predicated.
2289 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2290 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2291 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2292 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2299 let Inst{15-12} = Rd;
2300 let Inst{19-16} = Rn;
2301 let Inst{11-0} = imm;
2303 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2304 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2305 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2312 let Inst{11-0} = shift;
2313 let Inst{15-12} = Rd;
2314 let Inst{19-16} = Rn;
2318 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2319 // The assume-no-carry-in form uses the negation of the input since add/sub
2320 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2321 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2323 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2324 (SUBri GPR:$src, so_imm_neg:$imm)>;
2325 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2326 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2327 // The with-carry-in form matches bitwise not instead of the negation.
2328 // Effectively, the inverse interpretation of the carry flag already accounts
2329 // for part of the negation.
2330 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2331 (SBCri GPR:$src, so_imm_not:$imm)>;
2333 // Note: These are implemented in C++ code, because they have to generate
2334 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2336 // (mul X, 2^n+1) -> (add (X << n), X)
2337 // (mul X, 2^n-1) -> (rsb X, (X << n))
2339 // ARM Arithmetic Instruction -- for disassembly only
2340 // GPR:$dst = GPR:$a op GPR:$b
2341 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2342 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2343 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2344 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2348 let Inst{27-20} = op27_20;
2349 let Inst{11-4} = op11_4;
2350 let Inst{19-16} = Rn;
2351 let Inst{15-12} = Rd;
2355 // Saturating add/subtract -- for disassembly only
2357 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2358 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2359 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2360 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2361 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2362 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2363 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2365 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2368 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2369 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2370 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2371 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2372 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2373 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2374 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2375 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2376 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2377 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2378 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2379 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2381 // Signed/Unsigned add/subtract -- for disassembly only
2383 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2384 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2385 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2386 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2387 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2388 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2389 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2390 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2391 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2392 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2393 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2394 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2396 // Signed/Unsigned halving add/subtract -- for disassembly only
2398 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2399 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2400 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2401 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2402 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2403 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2404 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2405 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2406 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2407 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2408 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2409 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2411 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2413 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2414 MulFrm /* for convenience */, NoItinerary, "usad8",
2415 "\t$Rd, $Rn, $Rm", []>,
2416 Requires<[IsARM, HasV6]> {
2420 let Inst{27-20} = 0b01111000;
2421 let Inst{15-12} = 0b1111;
2422 let Inst{7-4} = 0b0001;
2423 let Inst{19-16} = Rd;
2424 let Inst{11-8} = Rm;
2427 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2428 MulFrm /* for convenience */, NoItinerary, "usada8",
2429 "\t$Rd, $Rn, $Rm, $Ra", []>,
2430 Requires<[IsARM, HasV6]> {
2435 let Inst{27-20} = 0b01111000;
2436 let Inst{7-4} = 0b0001;
2437 let Inst{19-16} = Rd;
2438 let Inst{15-12} = Ra;
2439 let Inst{11-8} = Rm;
2443 // Signed/Unsigned saturate -- for disassembly only
2445 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2446 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2447 [/* For disassembly only; pattern left blank */]> {
2452 let Inst{27-21} = 0b0110101;
2453 let Inst{5-4} = 0b01;
2454 let Inst{20-16} = sat_imm;
2455 let Inst{15-12} = Rd;
2456 let Inst{11-7} = sh{7-3};
2457 let Inst{6} = sh{0};
2461 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2462 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2463 [/* For disassembly only; pattern left blank */]> {
2467 let Inst{27-20} = 0b01101010;
2468 let Inst{11-4} = 0b11110011;
2469 let Inst{15-12} = Rd;
2470 let Inst{19-16} = sat_imm;
2474 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2475 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2476 [/* For disassembly only; pattern left blank */]> {
2481 let Inst{27-21} = 0b0110111;
2482 let Inst{5-4} = 0b01;
2483 let Inst{15-12} = Rd;
2484 let Inst{11-7} = sh{7-3};
2485 let Inst{6} = sh{0};
2486 let Inst{20-16} = sat_imm;
2490 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2491 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2492 [/* For disassembly only; pattern left blank */]> {
2496 let Inst{27-20} = 0b01101110;
2497 let Inst{11-4} = 0b11110011;
2498 let Inst{15-12} = Rd;
2499 let Inst{19-16} = sat_imm;
2503 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2504 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2506 //===----------------------------------------------------------------------===//
2507 // Bitwise Instructions.
2510 defm AND : AsI1_bin_irs<0b0000, "and",
2511 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2512 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2513 defm ORR : AsI1_bin_irs<0b1100, "orr",
2514 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2515 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2516 defm EOR : AsI1_bin_irs<0b0001, "eor",
2517 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2518 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2519 defm BIC : AsI1_bin_irs<0b1110, "bic",
2520 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2521 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2523 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2524 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2525 "bfc", "\t$Rd, $imm", "$src = $Rd",
2526 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2527 Requires<[IsARM, HasV6T2]> {
2530 let Inst{27-21} = 0b0111110;
2531 let Inst{6-0} = 0b0011111;
2532 let Inst{15-12} = Rd;
2533 let Inst{11-7} = imm{4-0}; // lsb
2534 let Inst{20-16} = imm{9-5}; // width
2537 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2538 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2539 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2540 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2541 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2542 bf_inv_mask_imm:$imm))]>,
2543 Requires<[IsARM, HasV6T2]> {
2547 let Inst{27-21} = 0b0111110;
2548 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2549 let Inst{15-12} = Rd;
2550 let Inst{11-7} = imm{4-0}; // lsb
2551 let Inst{20-16} = imm{9-5}; // width
2555 // GNU as only supports this form of bfi (w/ 4 arguments)
2556 let isAsmParserOnly = 1 in
2557 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2558 lsb_pos_imm:$lsb, width_imm:$width),
2559 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2560 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2561 []>, Requires<[IsARM, HasV6T2]> {
2566 let Inst{27-21} = 0b0111110;
2567 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2568 let Inst{15-12} = Rd;
2569 let Inst{11-7} = lsb;
2570 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2574 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2575 "mvn", "\t$Rd, $Rm",
2576 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2580 let Inst{19-16} = 0b0000;
2581 let Inst{11-4} = 0b00000000;
2582 let Inst{15-12} = Rd;
2585 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2586 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2587 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2591 let Inst{19-16} = 0b0000;
2592 let Inst{15-12} = Rd;
2593 let Inst{11-0} = shift;
2595 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2596 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2597 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2598 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2602 let Inst{19-16} = 0b0000;
2603 let Inst{15-12} = Rd;
2604 let Inst{11-0} = imm;
2607 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2608 (BICri GPR:$src, so_imm_not:$imm)>;
2610 //===----------------------------------------------------------------------===//
2611 // Multiply Instructions.
2613 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2614 string opc, string asm, list<dag> pattern>
2615 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2619 let Inst{19-16} = Rd;
2620 let Inst{11-8} = Rm;
2623 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2624 string opc, string asm, list<dag> pattern>
2625 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2630 let Inst{19-16} = RdHi;
2631 let Inst{15-12} = RdLo;
2632 let Inst{11-8} = Rm;
2636 let isCommutable = 1 in {
2637 let Constraints = "@earlyclobber $Rd" in
2638 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2639 pred:$p, cc_out:$s),
2640 Size4Bytes, IIC_iMUL32,
2641 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2642 Requires<[IsARM, NoV6]>;
2644 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2645 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2646 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2647 Requires<[IsARM, HasV6]>;
2650 let Constraints = "@earlyclobber $Rd" in
2651 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2652 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2653 Size4Bytes, IIC_iMAC32,
2654 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2655 Requires<[IsARM, NoV6]> {
2657 let Inst{15-12} = Ra;
2659 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2660 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2661 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2662 Requires<[IsARM, HasV6]> {
2664 let Inst{15-12} = Ra;
2667 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2668 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2669 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2670 Requires<[IsARM, HasV6T2]> {
2675 let Inst{19-16} = Rd;
2676 let Inst{15-12} = Ra;
2677 let Inst{11-8} = Rm;
2681 // Extra precision multiplies with low / high results
2683 let neverHasSideEffects = 1 in {
2684 let isCommutable = 1 in {
2685 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2686 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2687 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2688 Size4Bytes, IIC_iMUL64, []>,
2689 Requires<[IsARM, NoV6]>;
2691 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2692 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2693 Size4Bytes, IIC_iMUL64, []>,
2694 Requires<[IsARM, NoV6]>;
2697 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2698 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2699 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2700 Requires<[IsARM, HasV6]>;
2702 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2703 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2704 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2705 Requires<[IsARM, HasV6]>;
2708 // Multiply + accumulate
2709 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2710 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2711 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2712 Size4Bytes, IIC_iMAC64, []>,
2713 Requires<[IsARM, NoV6]>;
2714 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2715 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2716 Size4Bytes, IIC_iMAC64, []>,
2717 Requires<[IsARM, NoV6]>;
2718 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2719 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2720 Size4Bytes, IIC_iMAC64, []>,
2721 Requires<[IsARM, NoV6]>;
2725 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2726 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2727 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2728 Requires<[IsARM, HasV6]>;
2729 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2730 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2731 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2732 Requires<[IsARM, HasV6]>;
2734 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2735 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2736 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2737 Requires<[IsARM, HasV6]> {
2742 let Inst{19-16} = RdLo;
2743 let Inst{15-12} = RdHi;
2744 let Inst{11-8} = Rm;
2747 } // neverHasSideEffects
2749 // Most significant word multiply
2750 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2751 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2752 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2753 Requires<[IsARM, HasV6]> {
2754 let Inst{15-12} = 0b1111;
2757 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2758 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2759 [/* For disassembly only; pattern left blank */]>,
2760 Requires<[IsARM, HasV6]> {
2761 let Inst{15-12} = 0b1111;
2764 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2765 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2766 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2767 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2768 Requires<[IsARM, HasV6]>;
2770 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2771 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2772 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2773 [/* For disassembly only; pattern left blank */]>,
2774 Requires<[IsARM, HasV6]>;
2776 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2777 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2778 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2779 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2780 Requires<[IsARM, HasV6]>;
2782 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2783 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2784 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2785 [/* For disassembly only; pattern left blank */]>,
2786 Requires<[IsARM, HasV6]>;
2788 multiclass AI_smul<string opc, PatFrag opnode> {
2789 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2790 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2791 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2792 (sext_inreg GPR:$Rm, i16)))]>,
2793 Requires<[IsARM, HasV5TE]>;
2795 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2796 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2797 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2798 (sra GPR:$Rm, (i32 16))))]>,
2799 Requires<[IsARM, HasV5TE]>;
2801 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2802 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2803 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2804 (sext_inreg GPR:$Rm, i16)))]>,
2805 Requires<[IsARM, HasV5TE]>;
2807 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2808 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2809 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2810 (sra GPR:$Rm, (i32 16))))]>,
2811 Requires<[IsARM, HasV5TE]>;
2813 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2814 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2815 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2816 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2817 Requires<[IsARM, HasV5TE]>;
2819 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2820 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2821 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2822 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2823 Requires<[IsARM, HasV5TE]>;
2827 multiclass AI_smla<string opc, PatFrag opnode> {
2828 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2829 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2830 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2831 [(set GPR:$Rd, (add GPR:$Ra,
2832 (opnode (sext_inreg GPR:$Rn, i16),
2833 (sext_inreg GPR:$Rm, i16))))]>,
2834 Requires<[IsARM, HasV5TE]>;
2836 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2837 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2838 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2839 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2840 (sra GPR:$Rm, (i32 16)))))]>,
2841 Requires<[IsARM, HasV5TE]>;
2843 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2844 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2845 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2846 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2847 (sext_inreg GPR:$Rm, i16))))]>,
2848 Requires<[IsARM, HasV5TE]>;
2850 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2851 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2852 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2853 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2854 (sra GPR:$Rm, (i32 16)))))]>,
2855 Requires<[IsARM, HasV5TE]>;
2857 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2858 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2859 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2860 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2861 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2862 Requires<[IsARM, HasV5TE]>;
2864 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2865 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2866 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2867 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2868 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2869 Requires<[IsARM, HasV5TE]>;
2872 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2873 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2875 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2876 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2877 (ins GPR:$Rn, GPR:$Rm),
2878 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2879 [/* For disassembly only; pattern left blank */]>,
2880 Requires<[IsARM, HasV5TE]>;
2882 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2883 (ins GPR:$Rn, GPR:$Rm),
2884 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2885 [/* For disassembly only; pattern left blank */]>,
2886 Requires<[IsARM, HasV5TE]>;
2888 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2889 (ins GPR:$Rn, GPR:$Rm),
2890 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2891 [/* For disassembly only; pattern left blank */]>,
2892 Requires<[IsARM, HasV5TE]>;
2894 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2895 (ins GPR:$Rn, GPR:$Rm),
2896 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2897 [/* For disassembly only; pattern left blank */]>,
2898 Requires<[IsARM, HasV5TE]>;
2900 // Helper class for AI_smld -- for disassembly only
2901 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2902 InstrItinClass itin, string opc, string asm>
2903 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2910 let Inst{21-20} = 0b00;
2911 let Inst{22} = long;
2912 let Inst{27-23} = 0b01110;
2913 let Inst{11-8} = Rm;
2916 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2917 InstrItinClass itin, string opc, string asm>
2918 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2920 let Inst{15-12} = 0b1111;
2921 let Inst{19-16} = Rd;
2923 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2924 InstrItinClass itin, string opc, string asm>
2925 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2927 let Inst{15-12} = Ra;
2929 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2930 InstrItinClass itin, string opc, string asm>
2931 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2934 let Inst{19-16} = RdHi;
2935 let Inst{15-12} = RdLo;
2938 multiclass AI_smld<bit sub, string opc> {
2940 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2941 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2943 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2944 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2946 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2947 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2948 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2950 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2951 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2952 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2956 defm SMLA : AI_smld<0, "smla">;
2957 defm SMLS : AI_smld<1, "smls">;
2959 multiclass AI_sdml<bit sub, string opc> {
2961 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2962 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2963 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2964 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2967 defm SMUA : AI_sdml<0, "smua">;
2968 defm SMUS : AI_sdml<1, "smus">;
2970 //===----------------------------------------------------------------------===//
2971 // Misc. Arithmetic Instructions.
2974 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2975 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2976 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2978 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2979 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2980 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2981 Requires<[IsARM, HasV6T2]>;
2983 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2984 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2985 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2987 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2988 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2990 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2991 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2992 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2993 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2994 Requires<[IsARM, HasV6]>;
2996 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2997 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3000 (or (srl GPR:$Rm, (i32 8)),
3001 (shl GPR:$Rm, (i32 8))), i16))]>,
3002 Requires<[IsARM, HasV6]>;
3004 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3005 (shl GPR:$Rm, (i32 8))), i16),
3008 // Need the AddedComplexity or else MOVs + REV would be chosen.
3009 let AddedComplexity = 5 in
3010 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3012 def lsl_shift_imm : SDNodeXForm<imm, [{
3013 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3014 return CurDAG->getTargetConstant(Sh, MVT::i32);
3017 def lsl_amt : PatLeaf<(i32 imm), [{
3018 return (N->getZExtValue() < 32);
3021 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3022 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3023 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3024 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3025 (and (shl GPR:$Rm, lsl_amt:$sh),
3027 Requires<[IsARM, HasV6]>;
3029 // Alternate cases for PKHBT where identities eliminate some nodes.
3030 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3031 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3032 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3033 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3035 def asr_shift_imm : SDNodeXForm<imm, [{
3036 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3037 return CurDAG->getTargetConstant(Sh, MVT::i32);
3040 def asr_amt : PatLeaf<(i32 imm), [{
3041 return (N->getZExtValue() <= 32);
3044 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3045 // will match the pattern below.
3046 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3047 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3048 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3049 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3050 (and (sra GPR:$Rm, asr_amt:$sh),
3052 Requires<[IsARM, HasV6]>;
3054 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3055 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3056 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3057 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3058 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3059 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3060 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3062 //===----------------------------------------------------------------------===//
3063 // Comparison Instructions...
3066 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3067 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3068 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3070 // ARMcmpZ can re-use the above instruction definitions.
3071 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3072 (CMPri GPR:$src, so_imm:$imm)>;
3073 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3074 (CMPrr GPR:$src, GPR:$rhs)>;
3075 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3076 (CMPrs GPR:$src, so_reg:$rhs)>;
3078 // FIXME: We have to be careful when using the CMN instruction and comparison
3079 // with 0. One would expect these two pieces of code should give identical
3095 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3096 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3097 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3098 // value of r0 and the carry bit (because the "carry bit" parameter to
3099 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3100 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3101 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3102 // parameter to AddWithCarry is defined as 0).
3104 // When x is 0 and unsigned:
3108 // ~x + 1 = 0x1 0000 0000
3109 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3111 // Therefore, we should disable CMN when comparing against zero, until we can
3112 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3113 // when it's a comparison which doesn't look at the 'carry' flag).
3115 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3117 // This is related to <rdar://problem/7569620>.
3119 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3120 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3122 // Note that TST/TEQ don't set all the same flags that CMP does!
3123 defm TST : AI1_cmp_irs<0b1000, "tst",
3124 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3125 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3126 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3127 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3128 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3130 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3131 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3132 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3134 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3135 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3137 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3138 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3140 // Pseudo i64 compares for some floating point compares.
3141 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3143 def BCCi64 : PseudoInst<(outs),
3144 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3146 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3148 def BCCZi64 : PseudoInst<(outs),
3149 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3150 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3151 } // usesCustomInserter
3154 // Conditional moves
3155 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3156 // a two-value operand where a dag node expects two operands. :(
3157 let neverHasSideEffects = 1 in {
3158 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3159 Size4Bytes, IIC_iCMOVr,
3160 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3161 RegConstraint<"$false = $Rd">;
3162 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3163 (ins GPR:$false, so_reg:$shift, pred:$p),
3164 Size4Bytes, IIC_iCMOVsr,
3165 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3166 RegConstraint<"$false = $Rd">;
3168 let isMoveImm = 1 in
3169 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3170 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3171 Size4Bytes, IIC_iMOVi,
3173 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3175 let isMoveImm = 1 in
3176 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3177 (ins GPR:$false, so_imm:$imm, pred:$p),
3178 Size4Bytes, IIC_iCMOVi,
3179 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3180 RegConstraint<"$false = $Rd">;
3182 // Two instruction predicate mov immediate.
3183 let isMoveImm = 1 in
3184 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3185 (ins GPR:$false, i32imm:$src, pred:$p),
3186 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3188 let isMoveImm = 1 in
3189 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3190 (ins GPR:$false, so_imm:$imm, pred:$p),
3191 Size4Bytes, IIC_iCMOVi,
3192 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3193 RegConstraint<"$false = $Rd">;
3194 } // neverHasSideEffects
3196 //===----------------------------------------------------------------------===//
3197 // Atomic operations intrinsics
3200 def memb_opt : Operand<i32> {
3201 let PrintMethod = "printMemBOption";
3202 let ParserMatchClass = MemBarrierOptOperand;
3205 // memory barriers protect the atomic sequences
3206 let hasSideEffects = 1 in {
3207 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3208 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3209 Requires<[IsARM, HasDB]> {
3211 let Inst{31-4} = 0xf57ff05;
3212 let Inst{3-0} = opt;
3216 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3218 [/* For disassembly only; pattern left blank */]>,
3219 Requires<[IsARM, HasDB]> {
3221 let Inst{31-4} = 0xf57ff04;
3222 let Inst{3-0} = opt;
3225 // ISB has only full system option -- for disassembly only
3226 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3227 Requires<[IsARM, HasDB]> {
3228 let Inst{31-4} = 0xf57ff06;
3229 let Inst{3-0} = 0b1111;
3232 let usesCustomInserter = 1 in {
3233 let Uses = [CPSR] in {
3234 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3235 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3236 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3237 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3238 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3239 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3240 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3241 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3242 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3243 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3244 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3245 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3246 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3248 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3249 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3251 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3252 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3254 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3255 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3257 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3258 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3260 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3261 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3263 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3264 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3266 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3267 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3269 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3270 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3272 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3273 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3274 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3275 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3276 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3277 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3278 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3279 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3280 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3281 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3282 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3283 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3284 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3285 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3287 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3289 def ATOMIC_SWAP_I8 : PseudoInst<
3290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3291 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3292 def ATOMIC_SWAP_I16 : PseudoInst<
3293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3294 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3295 def ATOMIC_SWAP_I32 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3297 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3299 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3300 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3301 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3302 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3303 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3304 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3305 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3306 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3307 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3311 let mayLoad = 1 in {
3312 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3313 "ldrexb", "\t$Rt, $addr", []>;
3314 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3315 "ldrexh", "\t$Rt, $addr", []>;
3316 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3317 "ldrex", "\t$Rt, $addr", []>;
3318 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3319 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3322 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3323 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3324 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3325 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3326 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3327 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3328 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3329 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3330 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3331 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3334 // Clear-Exclusive is for disassembly only.
3335 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3336 [/* For disassembly only; pattern left blank */]>,
3337 Requires<[IsARM, HasV7]> {
3338 let Inst{31-0} = 0b11110101011111111111000000011111;
3341 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3342 let mayLoad = 1 in {
3343 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3344 [/* For disassembly only; pattern left blank */]>;
3345 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3346 [/* For disassembly only; pattern left blank */]>;
3349 //===----------------------------------------------------------------------===//
3350 // Coprocessor Instructions.
3353 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3354 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3355 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3356 [/* For disassembly only; pattern left blank */]> {
3364 let Inst{3-0} = CRm;
3366 let Inst{7-5} = opc2;
3367 let Inst{11-8} = cop;
3368 let Inst{15-12} = CRd;
3369 let Inst{19-16} = CRn;
3370 let Inst{23-20} = opc1;
3373 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3374 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3375 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3376 [/* For disassembly only; pattern left blank */]> {
3377 let Inst{31-28} = 0b1111;
3385 let Inst{3-0} = CRm;
3387 let Inst{7-5} = opc2;
3388 let Inst{11-8} = cop;
3389 let Inst{15-12} = CRd;
3390 let Inst{19-16} = CRn;
3391 let Inst{23-20} = opc1;
3394 class ACI<dag oops, dag iops, string opc, string asm>
3395 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3396 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3397 let Inst{27-25} = 0b110;
3400 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3402 def _OFFSET : ACI<(outs),
3403 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3404 opc, "\tp$cop, cr$CRd, $addr"> {
3405 let Inst{31-28} = op31_28;
3406 let Inst{24} = 1; // P = 1
3407 let Inst{21} = 0; // W = 0
3408 let Inst{22} = 0; // D = 0
3409 let Inst{20} = load;
3412 def _PRE : ACI<(outs),
3413 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3414 opc, "\tp$cop, cr$CRd, $addr!"> {
3415 let Inst{31-28} = op31_28;
3416 let Inst{24} = 1; // P = 1
3417 let Inst{21} = 1; // W = 1
3418 let Inst{22} = 0; // D = 0
3419 let Inst{20} = load;
3422 def _POST : ACI<(outs),
3423 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3424 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3425 let Inst{31-28} = op31_28;
3426 let Inst{24} = 0; // P = 0
3427 let Inst{21} = 1; // W = 1
3428 let Inst{22} = 0; // D = 0
3429 let Inst{20} = load;
3432 def _OPTION : ACI<(outs),
3433 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3434 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3435 let Inst{31-28} = op31_28;
3436 let Inst{24} = 0; // P = 0
3437 let Inst{23} = 1; // U = 1
3438 let Inst{21} = 0; // W = 0
3439 let Inst{22} = 0; // D = 0
3440 let Inst{20} = load;
3443 def L_OFFSET : ACI<(outs),
3444 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3445 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3446 let Inst{31-28} = op31_28;
3447 let Inst{24} = 1; // P = 1
3448 let Inst{21} = 0; // W = 0
3449 let Inst{22} = 1; // D = 1
3450 let Inst{20} = load;
3453 def L_PRE : ACI<(outs),
3454 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3455 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3456 let Inst{31-28} = op31_28;
3457 let Inst{24} = 1; // P = 1
3458 let Inst{21} = 1; // W = 1
3459 let Inst{22} = 1; // D = 1
3460 let Inst{20} = load;
3463 def L_POST : ACI<(outs),
3464 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3465 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3466 let Inst{31-28} = op31_28;
3467 let Inst{24} = 0; // P = 0
3468 let Inst{21} = 1; // W = 1
3469 let Inst{22} = 1; // D = 1
3470 let Inst{20} = load;
3473 def L_OPTION : ACI<(outs),
3474 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3475 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3476 let Inst{31-28} = op31_28;
3477 let Inst{24} = 0; // P = 0
3478 let Inst{23} = 1; // U = 1
3479 let Inst{21} = 0; // W = 0
3480 let Inst{22} = 1; // D = 1
3481 let Inst{20} = load;
3485 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3486 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3487 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3488 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3490 //===----------------------------------------------------------------------===//
3491 // Move between coprocessor and ARM core register -- for disassembly only
3494 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3495 : ABI<0b1110, oops, iops, NoItinerary, opc,
3496 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3497 [/* For disassembly only; pattern left blank */]> {
3498 let Inst{20} = direction;
3508 let Inst{15-12} = Rt;
3509 let Inst{11-8} = cop;
3510 let Inst{23-21} = opc1;
3511 let Inst{7-5} = opc2;
3512 let Inst{3-0} = CRm;
3513 let Inst{19-16} = CRn;
3516 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3517 (outs), (ins p_imm:$cop, i32imm:$opc1,
3518 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3520 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3521 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3522 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3524 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3525 : ABXI<0b1110, oops, iops, NoItinerary,
3526 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3527 [/* For disassembly only; pattern left blank */]> {
3528 let Inst{31-28} = 0b1111;
3529 let Inst{20} = direction;
3539 let Inst{15-12} = Rt;
3540 let Inst{11-8} = cop;
3541 let Inst{23-21} = opc1;
3542 let Inst{7-5} = opc2;
3543 let Inst{3-0} = CRm;
3544 let Inst{19-16} = CRn;
3547 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3548 (outs), (ins p_imm:$cop, i32imm:$opc1,
3549 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3551 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3552 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3553 c_imm:$CRn, c_imm:$CRm,
3556 class MovRRCopro<string opc, bit direction>
3557 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3558 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3559 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3560 [/* For disassembly only; pattern left blank */]> {
3561 let Inst{23-21} = 0b010;
3562 let Inst{20} = direction;
3570 let Inst{15-12} = Rt;
3571 let Inst{19-16} = Rt2;
3572 let Inst{11-8} = cop;
3573 let Inst{7-4} = opc1;
3574 let Inst{3-0} = CRm;
3577 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3578 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3580 class MovRRCopro2<string opc, bit direction>
3581 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3582 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3583 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3584 [/* For disassembly only; pattern left blank */]> {
3585 let Inst{31-28} = 0b1111;
3586 let Inst{23-21} = 0b010;
3587 let Inst{20} = direction;
3595 let Inst{15-12} = Rt;
3596 let Inst{19-16} = Rt2;
3597 let Inst{11-8} = cop;
3598 let Inst{7-4} = opc1;
3599 let Inst{3-0} = CRm;
3602 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3603 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3605 //===----------------------------------------------------------------------===//
3606 // Move between special register and ARM core register -- for disassembly only
3609 // Move to ARM core register from Special Register
3610 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3611 [/* For disassembly only; pattern left blank */]> {
3613 let Inst{23-16} = 0b00001111;
3614 let Inst{15-12} = Rd;
3615 let Inst{7-4} = 0b0000;
3618 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3619 [/* For disassembly only; pattern left blank */]> {
3621 let Inst{23-16} = 0b01001111;
3622 let Inst{15-12} = Rd;
3623 let Inst{7-4} = 0b0000;
3626 // Move from ARM core register to Special Register
3628 // No need to have both system and application versions, the encodings are the
3629 // same and the assembly parser has no way to distinguish between them. The mask
3630 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3631 // the mask with the fields to be accessed in the special register.
3632 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3633 "msr", "\t$mask, $Rn",
3634 [/* For disassembly only; pattern left blank */]> {
3639 let Inst{22} = mask{4}; // R bit
3640 let Inst{21-20} = 0b10;
3641 let Inst{19-16} = mask{3-0};
3642 let Inst{15-12} = 0b1111;
3643 let Inst{11-4} = 0b00000000;
3647 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3648 "msr", "\t$mask, $a",
3649 [/* For disassembly only; pattern left blank */]> {
3654 let Inst{22} = mask{4}; // R bit
3655 let Inst{21-20} = 0b10;
3656 let Inst{19-16} = mask{3-0};
3657 let Inst{15-12} = 0b1111;
3661 //===----------------------------------------------------------------------===//
3665 // __aeabi_read_tp preserves the registers r1-r3.
3666 // This is a pseudo inst so that we can get the encoding right,
3667 // complete with fixup for the aeabi_read_tp function.
3669 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3670 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3671 [(set R0, ARMthread_pointer)]>;
3674 //===----------------------------------------------------------------------===//
3675 // SJLJ Exception handling intrinsics
3676 // eh_sjlj_setjmp() is an instruction sequence to store the return
3677 // address and save #0 in R0 for the non-longjmp case.
3678 // Since by its nature we may be coming from some other function to get
3679 // here, and we're using the stack frame for the containing function to
3680 // save/restore registers, we can't keep anything live in regs across
3681 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3682 // when we get here from a longjmp(). We force everthing out of registers
3683 // except for our own input by listing the relevant registers in Defs. By
3684 // doing so, we also cause the prologue/epilogue code to actively preserve
3685 // all of the callee-saved resgisters, which is exactly what we want.
3686 // A constant value is passed in $val, and we use the location as a scratch.
3688 // These are pseudo-instructions and are lowered to individual MC-insts, so
3689 // no encoding information is necessary.
3691 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3692 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3693 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3694 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3695 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3697 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3698 Requires<[IsARM, HasVFP2]>;
3702 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3703 hasSideEffects = 1, isBarrier = 1 in {
3704 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3706 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3707 Requires<[IsARM, NoVFP]>;
3710 // FIXME: Non-Darwin version(s)
3711 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3712 Defs = [ R7, LR, SP ] in {
3713 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3715 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3716 Requires<[IsARM, IsDarwin]>;
3719 // eh.sjlj.dispatchsetup pseudo-instruction.
3720 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3721 // handled when the pseudo is expanded (which happens before any passes
3722 // that need the instruction size).
3723 let isBarrier = 1, hasSideEffects = 1 in
3724 def Int_eh_sjlj_dispatchsetup :
3725 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3726 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3727 Requires<[IsDarwin]>;
3729 //===----------------------------------------------------------------------===//
3730 // Non-Instruction Patterns
3733 // Large immediate handling.
3735 // 32-bit immediate using two piece so_imms or movw + movt.
3736 // This is a single pseudo instruction, the benefit is that it can be remat'd
3737 // as a single unit instead of having to handle reg inputs.
3738 // FIXME: Remove this when we can do generalized remat.
3739 let isReMaterializable = 1, isMoveImm = 1 in
3740 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3741 [(set GPR:$dst, (arm_i32imm:$src))]>,
3744 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3745 // It also makes it possible to rematerialize the instructions.
3746 // FIXME: Remove this when we can do generalized remat and when machine licm
3747 // can properly the instructions.
3748 let isReMaterializable = 1 in {
3749 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3751 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3752 Requires<[IsARM, UseMovt]>;
3754 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3756 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3757 Requires<[IsARM, UseMovt]>;
3759 let AddedComplexity = 10 in
3760 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3762 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3763 Requires<[IsARM, UseMovt]>;
3764 } // isReMaterializable
3766 // ConstantPool, GlobalAddress, and JumpTable
3767 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3768 Requires<[IsARM, DontUseMovt]>;
3769 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3770 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3771 Requires<[IsARM, UseMovt]>;
3772 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3773 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3775 // TODO: add,sub,and, 3-instr forms?
3778 def : ARMPat<(ARMtcret tcGPR:$dst),
3779 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3781 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3782 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3784 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3785 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3787 def : ARMPat<(ARMtcret tcGPR:$dst),
3788 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3790 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3791 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3793 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3794 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3797 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3798 Requires<[IsARM, IsNotDarwin]>;
3799 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3800 Requires<[IsARM, IsDarwin]>;
3802 // zextload i1 -> zextload i8
3803 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3804 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3806 // extload -> zextload
3807 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3808 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3809 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3810 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3812 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3814 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3815 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3818 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3819 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3820 (SMULBB GPR:$a, GPR:$b)>;
3821 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3822 (SMULBB GPR:$a, GPR:$b)>;
3823 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3824 (sra GPR:$b, (i32 16))),
3825 (SMULBT GPR:$a, GPR:$b)>;
3826 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3827 (SMULBT GPR:$a, GPR:$b)>;
3828 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3829 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3830 (SMULTB GPR:$a, GPR:$b)>;
3831 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3832 (SMULTB GPR:$a, GPR:$b)>;
3833 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3835 (SMULWB GPR:$a, GPR:$b)>;
3836 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3837 (SMULWB GPR:$a, GPR:$b)>;
3839 def : ARMV5TEPat<(add GPR:$acc,
3840 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3841 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3842 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3843 def : ARMV5TEPat<(add GPR:$acc,
3844 (mul sext_16_node:$a, sext_16_node:$b)),
3845 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3846 def : ARMV5TEPat<(add GPR:$acc,
3847 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3848 (sra GPR:$b, (i32 16)))),
3849 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3850 def : ARMV5TEPat<(add GPR:$acc,
3851 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3852 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3853 def : ARMV5TEPat<(add GPR:$acc,
3854 (mul (sra GPR:$a, (i32 16)),
3855 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3856 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3857 def : ARMV5TEPat<(add GPR:$acc,
3858 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3859 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3860 def : ARMV5TEPat<(add GPR:$acc,
3861 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3863 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3864 def : ARMV5TEPat<(add GPR:$acc,
3865 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3866 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3869 // Pre-v7 uses MCR for synchronization barriers.
3870 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3871 Requires<[IsARM, HasV6]>;
3874 //===----------------------------------------------------------------------===//
3878 include "ARMInstrThumb.td"
3880 //===----------------------------------------------------------------------===//
3884 include "ARMInstrThumb2.td"
3886 //===----------------------------------------------------------------------===//
3887 // Floating Point Support
3890 include "ARMInstrVFP.td"
3892 //===----------------------------------------------------------------------===//
3893 // Advanced SIMD (NEON) Support
3896 include "ARMInstrNEON.td"