1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
50 def SDT_ARMMEMBARRIERV7 : SDTypeProfile<0, 0, []>;
51 def SDT_ARMSYNCBARRIERV7 : SDTypeProfile<0, 0, []>;
52 def SDT_ARMMEMBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
53 def SDT_ARMSYNCBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
56 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
57 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
59 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
60 [SDNPHasChain, SDNPOutFlag]>;
61 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
62 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
65 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
67 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
68 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
70 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
71 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
74 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
75 [SDNPHasChain, SDNPOptInFlag]>;
77 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
79 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
82 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
83 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
85 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
87 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
90 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
93 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
94 [SDNPOutFlag,SDNPCommutative]>;
96 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
98 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
99 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
100 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
102 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
103 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
105 def ARMMemBarrierV7 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV7,
107 def ARMSyncBarrierV7 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV7,
109 def ARMMemBarrierV6 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV6,
111 def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
114 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
116 //===----------------------------------------------------------------------===//
117 // ARM Instruction Predicate Definitions.
119 def HasV4T : Predicate<"Subtarget->hasV4TOps()">;
120 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
121 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
122 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
123 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
124 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
125 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
126 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
127 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
128 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
129 def HasNEON : Predicate<"Subtarget->hasNEON()">;
130 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
131 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
132 def IsThumb : Predicate<"Subtarget->isThumb()">;
133 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
134 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
135 def IsARM : Predicate<"!Subtarget->isThumb()">;
136 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
137 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
139 // FIXME: Eventually this will be just "hasV6T2Ops".
140 def UseMovt : Predicate<"Subtarget->useMovt()">;
141 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
143 //===----------------------------------------------------------------------===//
144 // ARM Flag Definitions.
146 class RegConstraint<string C> {
147 string Constraints = C;
150 //===----------------------------------------------------------------------===//
151 // ARM specific transformation functions and pattern fragments.
154 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
155 // so_imm_neg def below.
156 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
160 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
161 // so_imm_not def below.
162 def so_imm_not_XFORM : SDNodeXForm<imm, [{
163 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
166 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
167 def rot_imm : PatLeaf<(i32 imm), [{
168 int32_t v = (int32_t)N->getZExtValue();
169 return v == 8 || v == 16 || v == 24;
172 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
173 def imm1_15 : PatLeaf<(i32 imm), [{
174 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
177 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
178 def imm16_31 : PatLeaf<(i32 imm), [{
179 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
184 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
185 }], so_imm_neg_XFORM>;
189 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
190 }], so_imm_not_XFORM>;
192 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
193 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
194 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
197 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
199 def bf_inv_mask_imm : Operand<i32>,
201 uint32_t v = (uint32_t)N->getZExtValue();
204 // there can be 1's on either or both "outsides", all the "inside"
206 unsigned int lsb = 0, msb = 31;
207 while (v & (1 << msb)) --msb;
208 while (v & (1 << lsb)) ++lsb;
209 for (unsigned int i = lsb; i <= msb; ++i) {
215 let PrintMethod = "printBitfieldInvMaskImmOperand";
218 /// Split a 32-bit immediate into two 16 bit parts.
219 def lo16 : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
224 def hi16 : SDNodeXForm<imm, [{
225 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
228 def lo16AllZero : PatLeaf<(i32 imm), [{
229 // Returns true if all low 16-bits are 0.
230 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
233 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
235 def imm0_65535 : PatLeaf<(i32 imm), [{
236 return (uint32_t)N->getZExtValue() < 65536;
239 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
240 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
242 /// adde and sube predicates - True based on whether the carry flag output
243 /// will be needed or not.
244 def adde_dead_carry :
245 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
246 [{return !N->hasAnyUseOfValue(1);}]>;
247 def sube_dead_carry :
248 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
249 [{return !N->hasAnyUseOfValue(1);}]>;
250 def adde_live_carry :
251 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
252 [{return N->hasAnyUseOfValue(1);}]>;
253 def sube_live_carry :
254 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
255 [{return N->hasAnyUseOfValue(1);}]>;
257 //===----------------------------------------------------------------------===//
258 // Operand Definitions.
262 def brtarget : Operand<OtherVT>;
264 // A list of registers separated by comma. Used by load/store multiple.
265 def reglist : Operand<i32> {
266 let PrintMethod = "printRegisterList";
269 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
270 def cpinst_operand : Operand<i32> {
271 let PrintMethod = "printCPInstOperand";
274 def jtblock_operand : Operand<i32> {
275 let PrintMethod = "printJTBlockOperand";
277 def jt2block_operand : Operand<i32> {
278 let PrintMethod = "printJT2BlockOperand";
282 def pclabel : Operand<i32> {
283 let PrintMethod = "printPCLabel";
286 // shifter_operand operands: so_reg and so_imm.
287 def so_reg : Operand<i32>, // reg reg imm
288 ComplexPattern<i32, 3, "SelectShifterOperandReg",
289 [shl,srl,sra,rotr]> {
290 let PrintMethod = "printSORegOperand";
291 let MIOperandInfo = (ops GPR, GPR, i32imm);
294 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
295 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
296 // represented in the imm field in the same 12-bit form that they are encoded
297 // into so_imm instructions: the 8-bit immediate is the least significant bits
298 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
299 def so_imm : Operand<i32>,
301 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
303 let PrintMethod = "printSOImmOperand";
306 // Break so_imm's up into two pieces. This handles immediates with up to 16
307 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
308 // get the first/second pieces.
309 def so_imm2part : Operand<i32>,
311 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
313 let PrintMethod = "printSOImm2PartOperand";
316 def so_imm2part_1 : SDNodeXForm<imm, [{
317 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
318 return CurDAG->getTargetConstant(V, MVT::i32);
321 def so_imm2part_2 : SDNodeXForm<imm, [{
322 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
323 return CurDAG->getTargetConstant(V, MVT::i32);
326 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
327 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
329 let PrintMethod = "printSOImm2PartOperand";
332 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
333 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
334 return CurDAG->getTargetConstant(V, MVT::i32);
337 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
338 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
339 return CurDAG->getTargetConstant(V, MVT::i32);
342 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
343 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
344 return (int32_t)N->getZExtValue() < 32;
347 // Define ARM specific addressing modes.
349 // addrmode2 := reg +/- reg shop imm
350 // addrmode2 := reg +/- imm12
352 def addrmode2 : Operand<i32>,
353 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
354 let PrintMethod = "printAddrMode2Operand";
355 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
358 def am2offset : Operand<i32>,
359 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
360 let PrintMethod = "printAddrMode2OffsetOperand";
361 let MIOperandInfo = (ops GPR, i32imm);
364 // addrmode3 := reg +/- reg
365 // addrmode3 := reg +/- imm8
367 def addrmode3 : Operand<i32>,
368 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
369 let PrintMethod = "printAddrMode3Operand";
370 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
373 def am3offset : Operand<i32>,
374 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
375 let PrintMethod = "printAddrMode3OffsetOperand";
376 let MIOperandInfo = (ops GPR, i32imm);
379 // addrmode4 := reg, <mode|W>
381 def addrmode4 : Operand<i32>,
382 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
383 let PrintMethod = "printAddrMode4Operand";
384 let MIOperandInfo = (ops GPR:$addr, i32imm);
387 // addrmode5 := reg +/- imm8*4
389 def addrmode5 : Operand<i32>,
390 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
391 let PrintMethod = "printAddrMode5Operand";
392 let MIOperandInfo = (ops GPR:$base, i32imm);
395 // addrmode6 := reg with optional writeback
397 def addrmode6 : Operand<i32>,
398 ComplexPattern<i32, 2, "SelectAddrMode6", []> {
399 let PrintMethod = "printAddrMode6Operand";
400 let MIOperandInfo = (ops GPR:$addr, i32imm);
403 def am6offset : Operand<i32> {
404 let PrintMethod = "printAddrMode6OffsetOperand";
405 let MIOperandInfo = (ops GPR);
408 // addrmodepc := pc + reg
410 def addrmodepc : Operand<i32>,
411 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
412 let PrintMethod = "printAddrModePCOperand";
413 let MIOperandInfo = (ops GPR, i32imm);
416 def nohash_imm : Operand<i32> {
417 let PrintMethod = "printNoHashImmediate";
420 //===----------------------------------------------------------------------===//
422 include "ARMInstrFormats.td"
424 //===----------------------------------------------------------------------===//
425 // Multiclass helpers...
428 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
429 /// binop that produces a value.
430 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
431 bit Commutable = 0> {
432 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
433 IIC_iALUi, opc, "\t$dst, $a, $b",
434 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
437 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
438 IIC_iALUr, opc, "\t$dst, $a, $b",
439 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
440 let Inst{11-4} = 0b00000000;
442 let isCommutable = Commutable;
444 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
445 IIC_iALUsr, opc, "\t$dst, $a, $b",
446 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
451 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
452 /// instruction modifies the CPSR register.
453 let Defs = [CPSR] in {
454 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
455 bit Commutable = 0> {
456 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
457 IIC_iALUi, opc, "\t$dst, $a, $b",
458 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
462 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
463 IIC_iALUr, opc, "\t$dst, $a, $b",
464 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
465 let isCommutable = Commutable;
466 let Inst{11-4} = 0b00000000;
470 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
471 IIC_iALUsr, opc, "\t$dst, $a, $b",
472 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
479 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
480 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
481 /// a explicit result, only implicitly set CPSR.
482 let Defs = [CPSR] in {
483 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
484 bit Commutable = 0> {
485 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
487 [(opnode GPR:$a, so_imm:$b)]> {
491 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
493 [(opnode GPR:$a, GPR:$b)]> {
494 let Inst{11-4} = 0b00000000;
497 let isCommutable = Commutable;
499 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
501 [(opnode GPR:$a, so_reg:$b)]> {
508 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
509 /// register and one whose operand is a register rotated by 8/16/24.
510 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
511 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
512 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
513 IIC_iUNAr, opc, "\t$dst, $src",
514 [(set GPR:$dst, (opnode GPR:$src))]>,
515 Requires<[IsARM, HasV6]> {
516 let Inst{11-10} = 0b00;
517 let Inst{19-16} = 0b1111;
519 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
520 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
521 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
522 Requires<[IsARM, HasV6]> {
523 let Inst{19-16} = 0b1111;
527 multiclass AI_unary_rrot_np<bits<8> opcod, string opc> {
528 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
529 IIC_iUNAr, opc, "\t$dst, $src",
530 [/* For disassembly only; pattern left blank */]>,
531 Requires<[IsARM, HasV6]> {
532 let Inst{11-10} = 0b00;
533 let Inst{19-16} = 0b1111;
535 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
536 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
537 [/* For disassembly only; pattern left blank */]>,
538 Requires<[IsARM, HasV6]> {
539 let Inst{19-16} = 0b1111;
543 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
544 /// register and one whose operand is a register rotated by 8/16/24.
545 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
546 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
547 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
548 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
549 Requires<[IsARM, HasV6]> {
550 let Inst{11-10} = 0b00;
552 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
554 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
555 [(set GPR:$dst, (opnode GPR:$LHS,
556 (rotr GPR:$RHS, rot_imm:$rot)))]>,
557 Requires<[IsARM, HasV6]>;
560 // For disassembly only.
561 multiclass AI_bin_rrot_np<bits<8> opcod, string opc> {
562 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
563 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
564 [/* For disassembly only; pattern left blank */]>,
565 Requires<[IsARM, HasV6]> {
566 let Inst{11-10} = 0b00;
568 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
570 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
571 [/* For disassembly only; pattern left blank */]>,
572 Requires<[IsARM, HasV6]>;
575 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
576 let Uses = [CPSR] in {
577 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
578 bit Commutable = 0> {
579 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
580 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
581 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
585 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
586 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
587 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
589 let isCommutable = Commutable;
590 let Inst{11-4} = 0b00000000;
593 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
594 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
595 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
600 // Carry setting variants
601 let Defs = [CPSR] in {
602 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
603 bit Commutable = 0> {
604 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
605 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
606 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
611 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
612 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
613 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
615 let Inst{11-4} = 0b00000000;
619 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
620 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
621 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
630 //===----------------------------------------------------------------------===//
632 //===----------------------------------------------------------------------===//
634 //===----------------------------------------------------------------------===//
635 // Miscellaneous Instructions.
638 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
639 /// the function. The first operand is the ID# for this instruction, the second
640 /// is the index into the MachineConstantPool that this is, the third is the
641 /// size in bytes of this constant pool entry.
642 let neverHasSideEffects = 1, isNotDuplicable = 1 in
643 def CONSTPOOL_ENTRY :
644 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
645 i32imm:$size), NoItinerary,
646 "${instid:label} ${cpidx:cpentry}", []>;
648 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
649 // from removing one half of the matched pairs. That breaks PEI, which assumes
650 // these will always be in pairs, and asserts if it finds otherwise. Better way?
651 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
653 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
654 "@ ADJCALLSTACKUP $amt1",
655 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
657 def ADJCALLSTACKDOWN :
658 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
659 "@ ADJCALLSTACKDOWN $amt",
660 [(ARMcallseq_start timm:$amt)]>;
663 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
664 [/* For disassembly only; pattern left blank */]>,
665 Requires<[IsARM, HasV6T2]> {
666 let Inst{27-16} = 0b001100100000;
667 let Inst{7-0} = 0b00000000;
670 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
671 [/* For disassembly only; pattern left blank */]>,
672 Requires<[IsARM, HasV6T2]> {
673 let Inst{27-16} = 0b001100100000;
674 let Inst{7-0} = 0b00000001;
677 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
678 [/* For disassembly only; pattern left blank */]>,
679 Requires<[IsARM, HasV6T2]> {
680 let Inst{27-16} = 0b001100100000;
681 let Inst{7-0} = 0b00000010;
684 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
685 [/* For disassembly only; pattern left blank */]>,
686 Requires<[IsARM, HasV6T2]> {
687 let Inst{27-16} = 0b001100100000;
688 let Inst{7-0} = 0b00000011;
691 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
693 [/* For disassembly only; pattern left blank */]>,
694 Requires<[IsARM, HasV6]> {
695 let Inst{27-20} = 0b01101000;
696 let Inst{7-4} = 0b1011;
699 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
700 [/* For disassembly only; pattern left blank */]>,
701 Requires<[IsARM, HasV6T2]> {
702 let Inst{27-16} = 0b001100100000;
703 let Inst{7-0} = 0b00000100;
706 // The i32imm operand $val can be used by a debugger to store more information
707 // about the breakpoint.
708 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
709 [/* For disassembly only; pattern left blank */]>,
711 let Inst{27-20} = 0b00010010;
712 let Inst{7-4} = 0b0111;
715 // Change Processor State is a system instruction -- for disassembly only.
716 // The singleton $opt operand contains the following information:
717 // opt{4-0} = mode from Inst{4-0}
718 // opt{5} = changemode from Inst{17}
719 // opt{8-6} = AIF from Inst{8-6}
720 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
721 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
722 [/* For disassembly only; pattern left blank */]>,
724 let Inst{31-28} = 0b1111;
725 let Inst{27-20} = 0b00010000;
730 // Preload signals the memory system of possible future data/instruction access.
731 // These are for disassembly only.
733 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
734 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
735 multiclass APreLoad<bit data, bit read, string opc> {
737 def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary,
738 !strconcat(opc, "\t[$base, $imm]"), []> {
739 let Inst{31-26} = 0b111101;
740 let Inst{25} = 0; // 0 for immediate form
743 let Inst{21-20} = 0b01;
746 def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary,
747 !strconcat(opc, "\t$addr"), []> {
748 let Inst{31-26} = 0b111101;
749 let Inst{25} = 1; // 1 for register form
752 let Inst{21-20} = 0b01;
757 defm PLD : APreLoad<1, 1, "pld">;
758 defm PLDW : APreLoad<1, 0, "pldw">;
759 defm PLI : APreLoad<0, 1, "pli">;
761 def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
762 [/* For disassembly only; pattern left blank */]>,
764 let Inst{31-28} = 0b1111;
765 let Inst{27-20} = 0b00010000;
768 let Inst{7-4} = 0b0000;
771 def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
772 [/* For disassembly only; pattern left blank */]>,
774 let Inst{31-28} = 0b1111;
775 let Inst{27-20} = 0b00010000;
778 let Inst{7-4} = 0b0000;
781 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
782 [/* For disassembly only; pattern left blank */]>,
783 Requires<[IsARM, HasV7]> {
784 let Inst{27-16} = 0b001100100000;
785 let Inst{7-4} = 0b1111;
788 // A5.4 Permanently UNDEFINED instructions.
789 def TRAP : AI<(outs), (ins), MiscFrm, NoItinerary, "trap", "",
790 [/* For disassembly only; pattern left blank */]>,
792 let Inst{27-25} = 0b011;
793 let Inst{24-20} = 0b11111;
794 let Inst{7-5} = 0b111;
798 // Address computation and loads and stores in PIC mode.
799 let isNotDuplicable = 1 in {
800 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
801 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
802 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
804 let AddedComplexity = 10 in {
805 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
806 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
807 [(set GPR:$dst, (load addrmodepc:$addr))]>;
809 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
810 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr",
811 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
813 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
814 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr",
815 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
817 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
818 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr",
819 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
821 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
822 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr",
823 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
825 let AddedComplexity = 10 in {
826 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
827 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
828 [(store GPR:$src, addrmodepc:$addr)]>;
830 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
831 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
832 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
834 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
835 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
836 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
838 } // isNotDuplicable = 1
841 // LEApcrel - Load a pc-relative address into a register without offending the
843 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
845 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
846 "${:private}PCRELL${:uid}+8))\n"),
847 !strconcat("${:private}PCRELL${:uid}:\n\t",
848 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
851 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
852 (ins i32imm:$label, nohash_imm:$id, pred:$p),
854 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
856 "${:private}PCRELL${:uid}+8))\n"),
857 !strconcat("${:private}PCRELL${:uid}:\n\t",
858 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
863 //===----------------------------------------------------------------------===//
864 // Control Flow Instructions.
867 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
869 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
870 "bx", "\tlr", [(ARMretflag)]>,
871 Requires<[IsARM, HasV4T]> {
872 let Inst{3-0} = 0b1110;
873 let Inst{7-4} = 0b0001;
874 let Inst{19-8} = 0b111111111111;
875 let Inst{27-20} = 0b00010010;
879 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
880 "mov", "\tpc, lr", [(ARMretflag)]>,
881 Requires<[IsARM, NoV4T]> {
882 let Inst{11-0} = 0b000000001110;
883 let Inst{15-12} = 0b1111;
884 let Inst{19-16} = 0b0000;
885 let Inst{27-20} = 0b00011010;
890 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
892 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
894 Requires<[IsARM, HasV4T]> {
895 let Inst{7-4} = 0b0001;
896 let Inst{19-8} = 0b111111111111;
897 let Inst{27-20} = 0b00010010;
898 let Inst{31-28} = 0b1110;
902 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
904 Requires<[IsARM, NoV4T]> {
905 let Inst{11-4} = 0b00000000;
906 let Inst{15-12} = 0b1111;
907 let Inst{19-16} = 0b0000;
908 let Inst{27-20} = 0b00011010;
909 let Inst{31-28} = 0b1110;
913 // FIXME: remove when we have a way to marking a MI with these properties.
914 // FIXME: Should pc be an implicit operand like PICADD, etc?
915 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
916 hasExtraDefRegAllocReq = 1 in
917 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
918 reglist:$dsts, variable_ops),
919 IndexModeUpd, LdStMulFrm, IIC_Br,
920 "ldm${addr:submode}${p}\t$addr!, $dsts",
921 "$addr.addr = $wb", []>;
923 // On non-Darwin platforms R9 is callee-saved.
925 Defs = [R0, R1, R2, R3, R12, LR,
926 D0, D1, D2, D3, D4, D5, D6, D7,
927 D16, D17, D18, D19, D20, D21, D22, D23,
928 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
929 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
930 IIC_Br, "bl\t${func:call}",
931 [(ARMcall tglobaladdr:$func)]>,
932 Requires<[IsARM, IsNotDarwin]> {
933 let Inst{31-28} = 0b1110;
936 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
937 IIC_Br, "bl", "\t${func:call}",
938 [(ARMcall_pred tglobaladdr:$func)]>,
939 Requires<[IsARM, IsNotDarwin]>;
942 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
943 IIC_Br, "blx\t$func",
944 [(ARMcall GPR:$func)]>,
945 Requires<[IsARM, HasV5T, IsNotDarwin]> {
946 let Inst{7-4} = 0b0011;
947 let Inst{19-8} = 0b111111111111;
948 let Inst{27-20} = 0b00010010;
952 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
953 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
954 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
955 [(ARMcall_nolink tGPR:$func)]>,
956 Requires<[IsARM, HasV4T, IsNotDarwin]> {
957 let Inst{7-4} = 0b0001;
958 let Inst{19-8} = 0b111111111111;
959 let Inst{27-20} = 0b00010010;
963 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
964 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
965 [(ARMcall_nolink tGPR:$func)]>,
966 Requires<[IsARM, NoV4T, IsNotDarwin]> {
967 let Inst{11-4} = 0b00000000;
968 let Inst{15-12} = 0b1111;
969 let Inst{19-16} = 0b0000;
970 let Inst{27-20} = 0b00011010;
974 // On Darwin R9 is call-clobbered.
976 Defs = [R0, R1, R2, R3, R9, R12, LR,
977 D0, D1, D2, D3, D4, D5, D6, D7,
978 D16, D17, D18, D19, D20, D21, D22, D23,
979 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
980 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
981 IIC_Br, "bl\t${func:call}",
982 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
983 let Inst{31-28} = 0b1110;
986 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
987 IIC_Br, "bl", "\t${func:call}",
988 [(ARMcall_pred tglobaladdr:$func)]>,
989 Requires<[IsARM, IsDarwin]>;
992 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
993 IIC_Br, "blx\t$func",
994 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
995 let Inst{7-4} = 0b0011;
996 let Inst{19-8} = 0b111111111111;
997 let Inst{27-20} = 0b00010010;
1001 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1002 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1003 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1004 [(ARMcall_nolink tGPR:$func)]>,
1005 Requires<[IsARM, HasV4T, IsDarwin]> {
1006 let Inst{7-4} = 0b0001;
1007 let Inst{19-8} = 0b111111111111;
1008 let Inst{27-20} = 0b00010010;
1012 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1013 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1014 [(ARMcall_nolink tGPR:$func)]>,
1015 Requires<[IsARM, NoV4T, IsDarwin]> {
1016 let Inst{11-4} = 0b00000000;
1017 let Inst{15-12} = 0b1111;
1018 let Inst{19-16} = 0b0000;
1019 let Inst{27-20} = 0b00011010;
1023 let isBranch = 1, isTerminator = 1 in {
1024 // B is "predicable" since it can be xformed into a Bcc.
1025 let isBarrier = 1 in {
1026 let isPredicable = 1 in
1027 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1028 "b\t$target", [(br bb:$target)]>;
1030 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1031 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1032 IIC_Br, "mov\tpc, $target \n$jt",
1033 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1034 let Inst{11-4} = 0b00000000;
1035 let Inst{15-12} = 0b1111;
1036 let Inst{20} = 0; // S Bit
1037 let Inst{24-21} = 0b1101;
1038 let Inst{27-25} = 0b000;
1040 def BR_JTm : JTI<(outs),
1041 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1042 IIC_Br, "ldr\tpc, $target \n$jt",
1043 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1045 let Inst{15-12} = 0b1111;
1046 let Inst{20} = 1; // L bit
1047 let Inst{21} = 0; // W bit
1048 let Inst{22} = 0; // B bit
1049 let Inst{24} = 1; // P bit
1050 let Inst{27-25} = 0b011;
1052 def BR_JTadd : JTI<(outs),
1053 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1054 IIC_Br, "add\tpc, $target, $idx \n$jt",
1055 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1057 let Inst{15-12} = 0b1111;
1058 let Inst{20} = 0; // S bit
1059 let Inst{24-21} = 0b0100;
1060 let Inst{27-25} = 0b000;
1062 } // isNotDuplicable = 1, isIndirectBranch = 1
1065 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1066 // a two-value operand where a dag node expects two operands. :(
1067 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1068 IIC_Br, "b", "\t$target",
1069 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1072 // Branch and Exchange Jazelle -- for disassembly only
1073 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1074 [/* For disassembly only; pattern left blank */]> {
1075 let Inst{23-20} = 0b0010;
1076 //let Inst{19-8} = 0xfff;
1077 let Inst{7-4} = 0b0010;
1080 // Secure Monitor Call is a system instruction -- for disassembly only
1081 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1082 [/* For disassembly only; pattern left blank */]> {
1083 let Inst{23-20} = 0b0110;
1084 let Inst{7-4} = 0b0111;
1087 // Supervisor Call (Software Interrupt) -- for disassembly only
1089 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1090 [/* For disassembly only; pattern left blank */]>;
1093 // Store Return State is a system instruction -- for disassembly only
1094 def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1095 NoItinerary, "srs${addr:submode}\tsp!, $mode",
1096 [/* For disassembly only; pattern left blank */]> {
1097 let Inst{31-28} = 0b1111;
1098 let Inst{22-20} = 0b110; // W = 1
1101 def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1102 NoItinerary, "srs${addr:submode}\tsp, $mode",
1103 [/* For disassembly only; pattern left blank */]> {
1104 let Inst{31-28} = 0b1111;
1105 let Inst{22-20} = 0b100; // W = 0
1108 // Return From Exception is a system instruction -- for disassembly only
1109 def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1110 NoItinerary, "rfe${addr:submode}\t$base!",
1111 [/* For disassembly only; pattern left blank */]> {
1112 let Inst{31-28} = 0b1111;
1113 let Inst{22-20} = 0b011; // W = 1
1116 def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1117 NoItinerary, "rfe${addr:submode}\t$base",
1118 [/* For disassembly only; pattern left blank */]> {
1119 let Inst{31-28} = 0b1111;
1120 let Inst{22-20} = 0b001; // W = 0
1123 //===----------------------------------------------------------------------===//
1124 // Load / store Instructions.
1128 let canFoldAsLoad = 1, isReMaterializable = 1 in
1129 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1130 "ldr", "\t$dst, $addr",
1131 [(set GPR:$dst, (load addrmode2:$addr))]>;
1133 // Special LDR for loads from non-pc-relative constpools.
1134 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
1135 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1136 "ldr", "\t$dst, $addr", []>;
1138 // Loads with zero extension
1139 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1140 IIC_iLoadr, "ldrh", "\t$dst, $addr",
1141 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1143 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
1144 IIC_iLoadr, "ldrb", "\t$dst, $addr",
1145 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
1147 // Loads with sign extension
1148 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1149 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
1150 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1152 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1153 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
1154 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1156 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
1158 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1159 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
1160 []>, Requires<[IsARM, HasV5TE]>;
1163 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1164 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1165 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1167 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1168 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1169 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1171 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1172 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1173 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1175 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1176 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1177 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1179 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1180 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1181 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1183 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1184 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1185 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1187 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1188 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1189 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1191 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1192 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1193 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1195 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1196 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1197 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1199 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1200 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1201 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1203 // For disassembly only
1204 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1205 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadr,
1206 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1207 Requires<[IsARM, HasV5TE]>;
1209 // For disassembly only
1210 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1211 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadr,
1212 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1213 Requires<[IsARM, HasV5TE]>;
1217 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1219 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1220 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1221 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1222 let Inst{21} = 1; // overwrite
1225 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1226 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1227 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1228 let Inst{21} = 1; // overwrite
1231 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1232 (ins GPR:$base,am2offset:$offset), LdMiscFrm, IIC_iLoadru,
1233 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1234 let Inst{21} = 1; // overwrite
1237 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1238 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1239 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1240 let Inst{21} = 1; // overwrite
1243 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1244 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1245 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1246 let Inst{21} = 1; // overwrite
1250 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1251 "str", "\t$src, $addr",
1252 [(store GPR:$src, addrmode2:$addr)]>;
1254 // Stores with truncate
1255 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1256 IIC_iStorer, "strh", "\t$src, $addr",
1257 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1259 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1260 "strb", "\t$src, $addr",
1261 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
1264 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1265 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1266 StMiscFrm, IIC_iStorer,
1267 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1270 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1271 (ins GPR:$src, GPR:$base, am2offset:$offset),
1272 StFrm, IIC_iStoreru,
1273 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1275 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1277 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1278 (ins GPR:$src, GPR:$base,am2offset:$offset),
1279 StFrm, IIC_iStoreru,
1280 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1282 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1284 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1285 (ins GPR:$src, GPR:$base,am3offset:$offset),
1286 StMiscFrm, IIC_iStoreru,
1287 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1289 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1291 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1292 (ins GPR:$src, GPR:$base,am3offset:$offset),
1293 StMiscFrm, IIC_iStoreru,
1294 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1295 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1296 GPR:$base, am3offset:$offset))]>;
1298 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1299 (ins GPR:$src, GPR:$base,am2offset:$offset),
1300 StFrm, IIC_iStoreru,
1301 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1302 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1303 GPR:$base, am2offset:$offset))]>;
1305 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1306 (ins GPR:$src, GPR:$base,am2offset:$offset),
1307 StFrm, IIC_iStoreru,
1308 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1309 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1310 GPR:$base, am2offset:$offset))]>;
1312 // For disassembly only
1313 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1314 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1315 StMiscFrm, IIC_iStoreru,
1316 "strd", "\t$src1, $src2, [$base, $offset]!",
1317 "$base = $base_wb", []>;
1319 // For disassembly only
1320 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1321 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1322 StMiscFrm, IIC_iStoreru,
1323 "strd", "\t$src1, $src2, [$base], $offset",
1324 "$base = $base_wb", []>;
1326 // STRT, STRBT, and STRHT are for disassembly only.
1328 def STRT : AI2stwpo<(outs GPR:$base_wb),
1329 (ins GPR:$src, GPR:$base,am2offset:$offset),
1330 StFrm, IIC_iStoreru,
1331 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1332 [/* For disassembly only; pattern left blank */]> {
1333 let Inst{21} = 1; // overwrite
1336 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1337 (ins GPR:$src, GPR:$base,am2offset:$offset),
1338 StFrm, IIC_iStoreru,
1339 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1340 [/* For disassembly only; pattern left blank */]> {
1341 let Inst{21} = 1; // overwrite
1344 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1345 (ins GPR:$src, GPR:$base,am3offset:$offset),
1346 StMiscFrm, IIC_iStoreru,
1347 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1348 [/* For disassembly only; pattern left blank */]> {
1349 let Inst{21} = 1; // overwrite
1352 //===----------------------------------------------------------------------===//
1353 // Load / store multiple Instructions.
1356 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
1357 def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
1358 reglist:$dsts, variable_ops),
1359 IndexModeNone, LdStMulFrm, IIC_iLoadm,
1360 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
1362 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1363 reglist:$dsts, variable_ops),
1364 IndexModeUpd, LdStMulFrm, IIC_iLoadm,
1365 "ldm${addr:submode}${p}\t$addr!, $dsts",
1366 "$addr.addr = $wb", []>;
1367 } // mayLoad, hasExtraDefRegAllocReq
1369 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
1370 def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
1371 reglist:$srcs, variable_ops),
1372 IndexModeNone, LdStMulFrm, IIC_iStorem,
1373 "stm${addr:submode}${p}\t$addr, $srcs", "", []>;
1375 def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1376 reglist:$srcs, variable_ops),
1377 IndexModeUpd, LdStMulFrm, IIC_iStorem,
1378 "stm${addr:submode}${p}\t$addr!, $srcs",
1379 "$addr.addr = $wb", []>;
1380 } // mayStore, hasExtraSrcRegAllocReq
1382 //===----------------------------------------------------------------------===//
1383 // Move Instructions.
1386 let neverHasSideEffects = 1 in
1387 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1388 "mov", "\t$dst, $src", []>, UnaryDP {
1389 let Inst{11-4} = 0b00000000;
1393 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
1394 DPSoRegFrm, IIC_iMOVsr,
1395 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
1399 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1400 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
1401 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
1405 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1406 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
1408 "movw", "\t$dst, $src",
1409 [(set GPR:$dst, imm0_65535:$src)]>,
1410 Requires<[IsARM, HasV6T2]>, UnaryDP {
1415 let Constraints = "$src = $dst" in
1416 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
1418 "movt", "\t$dst, $imm",
1420 (or (and GPR:$src, 0xffff),
1421 lo16AllZero:$imm))]>, UnaryDP,
1422 Requires<[IsARM, HasV6T2]> {
1427 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1428 Requires<[IsARM, HasV6T2]>;
1430 let Uses = [CPSR] in
1431 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1432 "mov", "\t$dst, $src, rrx",
1433 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1435 // These aren't really mov instructions, but we have to define them this way
1436 // due to flag operands.
1438 let Defs = [CPSR] in {
1439 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1440 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1441 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1442 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1443 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1444 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1447 //===----------------------------------------------------------------------===//
1448 // Extend Instructions.
1453 defm SXTB : AI_unary_rrot<0b01101010,
1454 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1455 defm SXTH : AI_unary_rrot<0b01101011,
1456 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1458 defm SXTAB : AI_bin_rrot<0b01101010,
1459 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1460 defm SXTAH : AI_bin_rrot<0b01101011,
1461 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1463 // For disassembly only
1464 defm SXTB16 : AI_unary_rrot_np<0b01101000, "sxtb16">;
1466 // For disassembly only
1467 defm SXTAB16 : AI_bin_rrot_np<0b01101000, "sxtab16">;
1471 let AddedComplexity = 16 in {
1472 defm UXTB : AI_unary_rrot<0b01101110,
1473 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1474 defm UXTH : AI_unary_rrot<0b01101111,
1475 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1476 defm UXTB16 : AI_unary_rrot<0b01101100,
1477 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1479 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1480 (UXTB16r_rot GPR:$Src, 24)>;
1481 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1482 (UXTB16r_rot GPR:$Src, 8)>;
1484 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1485 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1486 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1487 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1490 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1491 // For disassembly only
1492 defm UXTAB16 : AI_bin_rrot_np<0b01101100, "uxtab16">;
1495 def SBFX : I<(outs GPR:$dst),
1496 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1497 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1498 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1499 Requires<[IsARM, HasV6T2]> {
1500 let Inst{27-21} = 0b0111101;
1501 let Inst{6-4} = 0b101;
1504 def UBFX : I<(outs GPR:$dst),
1505 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1506 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1507 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1508 Requires<[IsARM, HasV6T2]> {
1509 let Inst{27-21} = 0b0111111;
1510 let Inst{6-4} = 0b101;
1513 //===----------------------------------------------------------------------===//
1514 // Arithmetic Instructions.
1517 defm ADD : AsI1_bin_irs<0b0100, "add",
1518 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1519 defm SUB : AsI1_bin_irs<0b0010, "sub",
1520 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1522 // ADD and SUB with 's' bit set.
1523 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1524 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1525 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1526 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1528 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1529 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1530 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1531 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1532 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1533 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1534 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1535 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1537 // These don't define reg/reg forms, because they are handled above.
1538 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1539 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1540 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1544 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1545 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1546 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1550 // RSB with 's' bit set.
1551 let Defs = [CPSR] in {
1552 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1553 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1554 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1558 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1559 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1560 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1566 let Uses = [CPSR] in {
1567 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1568 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1569 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1573 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1574 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1575 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1581 // FIXME: Allow these to be predicated.
1582 let Defs = [CPSR], Uses = [CPSR] in {
1583 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1584 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1585 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1590 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1591 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1592 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1599 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1600 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1601 (SUBri GPR:$src, so_imm_neg:$imm)>;
1603 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1604 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1605 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1606 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1608 // Note: These are implemented in C++ code, because they have to generate
1609 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1611 // (mul X, 2^n+1) -> (add (X << n), X)
1612 // (mul X, 2^n-1) -> (rsb X, (X << n))
1614 // ARM Arithmetic Instruction -- for disassembly only
1615 // GPR:$dst = GPR:$a op GPR:$b
1616 class AAI<bits<8> op27_20, bits<4> op7_4, string opc>
1617 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
1618 opc, "\t$dst, $a, $b",
1619 [/* For disassembly only; pattern left blank */]> {
1620 let Inst{27-20} = op27_20;
1621 let Inst{7-4} = op7_4;
1624 // Saturating add/subtract -- for disassembly only
1626 def QADD : AAI<0b00010000, 0b0101, "qadd">;
1627 def QADD16 : AAI<0b01100010, 0b0001, "qadd16">;
1628 def QADD8 : AAI<0b01100010, 0b1001, "qadd8">;
1629 def QASX : AAI<0b01100010, 0b0011, "qasx">;
1630 def QDADD : AAI<0b00010100, 0b0101, "qdadd">;
1631 def QDSUB : AAI<0b00010110, 0b0101, "qdsub">;
1632 def QSAX : AAI<0b01100010, 0b0101, "qsax">;
1633 def QSUB : AAI<0b00010010, 0b0101, "qsub">;
1634 def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">;
1635 def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">;
1636 def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">;
1637 def UQADD8 : AAI<0b01100110, 0b1001, "uqadd8">;
1638 def UQASX : AAI<0b01100110, 0b0011, "uqasx">;
1639 def UQSAX : AAI<0b01100110, 0b0101, "uqsax">;
1640 def UQSUB16 : AAI<0b01100110, 0b0111, "uqsub16">;
1641 def UQSUB8 : AAI<0b01100110, 0b1111, "uqsub8">;
1643 // Signed/Unsigned add/subtract -- for disassembly only
1645 def SASX : AAI<0b01100001, 0b0011, "sasx">;
1646 def SADD16 : AAI<0b01100001, 0b0001, "sadd16">;
1647 def SADD8 : AAI<0b01100001, 0b1001, "sadd8">;
1648 def SSAX : AAI<0b01100001, 0b0101, "ssax">;
1649 def SSUB16 : AAI<0b01100001, 0b0111, "ssub16">;
1650 def SSUB8 : AAI<0b01100001, 0b1111, "ssub8">;
1651 def UASX : AAI<0b01100101, 0b0011, "uasx">;
1652 def UADD16 : AAI<0b01100101, 0b0001, "uadd16">;
1653 def UADD8 : AAI<0b01100101, 0b1001, "uadd8">;
1654 def USAX : AAI<0b01100101, 0b0101, "usax">;
1655 def USUB16 : AAI<0b01100101, 0b0111, "usub16">;
1656 def USUB8 : AAI<0b01100101, 0b1111, "usub8">;
1658 // Signed/Unsigned halving add/subtract -- for disassembly only
1660 def SHASX : AAI<0b01100011, 0b0011, "shasx">;
1661 def SHADD16 : AAI<0b01100011, 0b0001, "shadd16">;
1662 def SHADD8 : AAI<0b01100011, 0b1001, "shadd8">;
1663 def SHSAX : AAI<0b01100011, 0b0101, "shsax">;
1664 def SHSUB16 : AAI<0b01100011, 0b0111, "shsub16">;
1665 def SHSUB8 : AAI<0b01100011, 0b1111, "shsub8">;
1666 def UHASX : AAI<0b01100111, 0b0011, "uhasx">;
1667 def UHADD16 : AAI<0b01100111, 0b0001, "uhadd16">;
1668 def UHADD8 : AAI<0b01100111, 0b1001, "uhadd8">;
1669 def UHSAX : AAI<0b01100111, 0b0101, "uhsax">;
1670 def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">;
1671 def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">;
1673 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1675 def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1676 MulFrm /* for convenience */, NoItinerary, "usad8",
1677 "\t$dst, $a, $b", []>,
1678 Requires<[IsARM, HasV6]> {
1679 let Inst{27-20} = 0b01111000;
1680 let Inst{15-12} = 0b1111;
1681 let Inst{7-4} = 0b0001;
1683 def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1684 MulFrm /* for convenience */, NoItinerary, "usada8",
1685 "\t$dst, $a, $b, $acc", []>,
1686 Requires<[IsARM, HasV6]> {
1687 let Inst{27-20} = 0b01111000;
1688 let Inst{7-4} = 0b0001;
1691 // Signed/Unsigned saturate -- for disassembly only
1693 def SSATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1694 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1695 [/* For disassembly only; pattern left blank */]> {
1696 let Inst{27-21} = 0b0110101;
1697 let Inst{6-4} = 0b001;
1700 def SSATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1701 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1702 [/* For disassembly only; pattern left blank */]> {
1703 let Inst{27-21} = 0b0110101;
1704 let Inst{6-4} = 0b101;
1707 def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1708 NoItinerary, "ssat16", "\t$dst, $bit_pos, $a",
1709 [/* For disassembly only; pattern left blank */]> {
1710 let Inst{27-20} = 0b01101010;
1711 let Inst{7-4} = 0b0011;
1714 def USATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1715 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1716 [/* For disassembly only; pattern left blank */]> {
1717 let Inst{27-21} = 0b0110111;
1718 let Inst{6-4} = 0b001;
1721 def USATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1722 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1723 [/* For disassembly only; pattern left blank */]> {
1724 let Inst{27-21} = 0b0110111;
1725 let Inst{6-4} = 0b101;
1728 def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1729 NoItinerary, "usat16", "\t$dst, $bit_pos, $a",
1730 [/* For disassembly only; pattern left blank */]> {
1731 let Inst{27-20} = 0b01101110;
1732 let Inst{7-4} = 0b0011;
1735 //===----------------------------------------------------------------------===//
1736 // Bitwise Instructions.
1739 defm AND : AsI1_bin_irs<0b0000, "and",
1740 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1741 defm ORR : AsI1_bin_irs<0b1100, "orr",
1742 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1743 defm EOR : AsI1_bin_irs<0b0001, "eor",
1744 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1745 defm BIC : AsI1_bin_irs<0b1110, "bic",
1746 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1748 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1749 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1750 "bfc", "\t$dst, $imm", "$src = $dst",
1751 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1752 Requires<[IsARM, HasV6T2]> {
1753 let Inst{27-21} = 0b0111110;
1754 let Inst{6-0} = 0b0011111;
1757 // A8.6.18 BFI - Bitfield insert (Encoding A1)
1758 // Added for disassembler with the pattern field purposely left blank.
1759 def BFI : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1760 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1761 "bfi", "\t$dst, $src, $imm", "",
1762 [/* For disassembly only; pattern left blank */]>,
1763 Requires<[IsARM, HasV6T2]> {
1764 let Inst{27-21} = 0b0111110;
1765 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
1768 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1769 "mvn", "\t$dst, $src",
1770 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1772 let Inst{11-4} = 0b00000000;
1774 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1775 IIC_iMOVsr, "mvn", "\t$dst, $src",
1776 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1779 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1780 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1781 IIC_iMOVi, "mvn", "\t$dst, $imm",
1782 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1786 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1787 (BICri GPR:$src, so_imm_not:$imm)>;
1789 //===----------------------------------------------------------------------===//
1790 // Multiply Instructions.
1793 let isCommutable = 1 in
1794 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1795 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1796 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1798 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1799 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1800 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1802 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1803 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1804 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1805 Requires<[IsARM, HasV6T2]>;
1807 // Extra precision multiplies with low / high results
1808 let neverHasSideEffects = 1 in {
1809 let isCommutable = 1 in {
1810 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1811 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1812 "smull", "\t$ldst, $hdst, $a, $b", []>;
1814 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1815 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1816 "umull", "\t$ldst, $hdst, $a, $b", []>;
1819 // Multiply + accumulate
1820 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1821 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1822 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1824 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1825 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1826 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1828 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1829 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1830 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1831 Requires<[IsARM, HasV6]>;
1832 } // neverHasSideEffects
1834 // Most significant word multiply
1835 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1836 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1837 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1838 Requires<[IsARM, HasV6]> {
1839 let Inst{7-4} = 0b0001;
1840 let Inst{15-12} = 0b1111;
1843 def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1844 IIC_iMUL32, "smmulr", "\t$dst, $a, $b",
1845 [/* For disassembly only; pattern left blank */]>,
1846 Requires<[IsARM, HasV6]> {
1847 let Inst{7-4} = 0b0011; // R = 1
1848 let Inst{15-12} = 0b1111;
1851 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1852 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1853 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1854 Requires<[IsARM, HasV6]> {
1855 let Inst{7-4} = 0b0001;
1858 def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1859 IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c",
1860 [/* For disassembly only; pattern left blank */]>,
1861 Requires<[IsARM, HasV6]> {
1862 let Inst{7-4} = 0b0011; // R = 1
1865 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1866 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1867 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1868 Requires<[IsARM, HasV6]> {
1869 let Inst{7-4} = 0b1101;
1872 def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1873 IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c",
1874 [/* For disassembly only; pattern left blank */]>,
1875 Requires<[IsARM, HasV6]> {
1876 let Inst{7-4} = 0b1111; // R = 1
1879 multiclass AI_smul<string opc, PatFrag opnode> {
1880 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1881 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1882 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1883 (sext_inreg GPR:$b, i16)))]>,
1884 Requires<[IsARM, HasV5TE]> {
1889 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1890 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1891 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1892 (sra GPR:$b, (i32 16))))]>,
1893 Requires<[IsARM, HasV5TE]> {
1898 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1899 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1900 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1901 (sext_inreg GPR:$b, i16)))]>,
1902 Requires<[IsARM, HasV5TE]> {
1907 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1908 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1909 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1910 (sra GPR:$b, (i32 16))))]>,
1911 Requires<[IsARM, HasV5TE]> {
1916 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1917 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1918 [(set GPR:$dst, (sra (opnode GPR:$a,
1919 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1920 Requires<[IsARM, HasV5TE]> {
1925 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1926 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1927 [(set GPR:$dst, (sra (opnode GPR:$a,
1928 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1929 Requires<[IsARM, HasV5TE]> {
1936 multiclass AI_smla<string opc, PatFrag opnode> {
1937 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1938 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1939 [(set GPR:$dst, (add GPR:$acc,
1940 (opnode (sext_inreg GPR:$a, i16),
1941 (sext_inreg GPR:$b, i16))))]>,
1942 Requires<[IsARM, HasV5TE]> {
1947 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1948 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1949 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1950 (sra GPR:$b, (i32 16)))))]>,
1951 Requires<[IsARM, HasV5TE]> {
1956 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1957 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1958 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1959 (sext_inreg GPR:$b, i16))))]>,
1960 Requires<[IsARM, HasV5TE]> {
1965 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1966 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1967 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1968 (sra GPR:$b, (i32 16)))))]>,
1969 Requires<[IsARM, HasV5TE]> {
1974 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1975 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1976 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1977 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1978 Requires<[IsARM, HasV5TE]> {
1983 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1984 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1985 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1986 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1987 Requires<[IsARM, HasV5TE]> {
1993 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1994 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1996 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
1997 def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
1998 IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
1999 [/* For disassembly only; pattern left blank */]>,
2000 Requires<[IsARM, HasV5TE]> {
2005 def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2006 IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2007 [/* For disassembly only; pattern left blank */]>,
2008 Requires<[IsARM, HasV5TE]> {
2013 def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2014 IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2015 [/* For disassembly only; pattern left blank */]>,
2016 Requires<[IsARM, HasV5TE]> {
2021 def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2022 IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2023 [/* For disassembly only; pattern left blank */]>,
2024 Requires<[IsARM, HasV5TE]> {
2029 // Helper class for AI_smld -- for disassembly only
2030 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2031 InstrItinClass itin, string opc, string asm>
2032 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2037 let Inst{21-20} = 0b00;
2038 let Inst{22} = long;
2039 let Inst{27-23} = 0b01110;
2042 multiclass AI_smld<bit sub, string opc> {
2044 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2045 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b, $acc">;
2047 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2048 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b, $acc">;
2050 def LD : AMulDualI<1, sub, 0, (outs GPR:$ldst,GPR:$hdst), (ins GPR:$a,GPR:$b),
2051 NoItinerary, !strconcat(opc, "ld"), "\t$ldst, $hdst, $a, $b">;
2053 def LDX : AMulDualI<1, sub, 1, (outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2054 NoItinerary, !strconcat(opc, "ldx"),"\t$ldst, $hdst, $a, $b">;
2058 defm SMLA : AI_smld<0, "smla">;
2059 defm SMLS : AI_smld<1, "smls">;
2061 multiclass AI_sdml<bit sub, string opc> {
2063 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2064 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b"> {
2065 let Inst{15-12} = 0b1111;
2068 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2069 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b"> {
2070 let Inst{15-12} = 0b1111;
2075 defm SMUA : AI_sdml<0, "smua">;
2076 defm SMUS : AI_sdml<1, "smus">;
2078 //===----------------------------------------------------------------------===//
2079 // Misc. Arithmetic Instructions.
2082 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2083 "clz", "\t$dst, $src",
2084 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
2085 let Inst{7-4} = 0b0001;
2086 let Inst{11-8} = 0b1111;
2087 let Inst{19-16} = 0b1111;
2090 def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2091 "rbit", "\t$dst, $src",
2092 [(set GPR:$dst, (ARMrbit GPR:$src))]>,
2093 Requires<[IsARM, HasV6T2]> {
2094 let Inst{7-4} = 0b0011;
2095 let Inst{11-8} = 0b1111;
2096 let Inst{19-16} = 0b1111;
2099 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2100 "rev", "\t$dst, $src",
2101 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
2102 let Inst{7-4} = 0b0011;
2103 let Inst{11-8} = 0b1111;
2104 let Inst{19-16} = 0b1111;
2107 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2108 "rev16", "\t$dst, $src",
2110 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2111 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2112 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2113 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
2114 Requires<[IsARM, HasV6]> {
2115 let Inst{7-4} = 0b1011;
2116 let Inst{11-8} = 0b1111;
2117 let Inst{19-16} = 0b1111;
2120 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2121 "revsh", "\t$dst, $src",
2124 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2125 (shl GPR:$src, (i32 8))), i16))]>,
2126 Requires<[IsARM, HasV6]> {
2127 let Inst{7-4} = 0b1011;
2128 let Inst{11-8} = 0b1111;
2129 let Inst{19-16} = 0b1111;
2132 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
2133 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2134 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2135 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2136 (and (shl GPR:$src2, (i32 imm:$shamt)),
2138 Requires<[IsARM, HasV6]> {
2139 let Inst{6-4} = 0b001;
2142 // Alternate cases for PKHBT where identities eliminate some nodes.
2143 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2144 (PKHBT GPR:$src1, GPR:$src2, 0)>;
2145 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2146 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
2149 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
2150 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2151 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2152 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2153 (and (sra GPR:$src2, imm16_31:$shamt),
2154 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
2155 let Inst{6-4} = 0b101;
2158 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2159 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2160 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2161 (PKHTB GPR:$src1, GPR:$src2, 16)>;
2162 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2163 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2164 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
2166 //===----------------------------------------------------------------------===//
2167 // Comparison Instructions...
2170 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2171 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2172 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2173 // Compare-to-zero still works out, just not the relationals
2174 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2175 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2177 // Note that TST/TEQ don't set all the same flags that CMP does!
2178 defm TST : AI1_cmp_irs<0b1000, "tst",
2179 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2180 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2181 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2183 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2184 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2185 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2186 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2188 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2189 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2191 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2192 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2195 // Conditional moves
2196 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2197 // a two-value operand where a dag node expects two operands. :(
2198 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
2199 IIC_iCMOVr, "mov", "\t$dst, $true",
2200 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2201 RegConstraint<"$false = $dst">, UnaryDP {
2202 let Inst{11-4} = 0b00000000;
2206 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
2207 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
2208 "mov", "\t$dst, $true",
2209 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
2210 RegConstraint<"$false = $dst">, UnaryDP {
2214 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
2215 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
2216 "mov", "\t$dst, $true",
2217 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2218 RegConstraint<"$false = $dst">, UnaryDP {
2222 //===----------------------------------------------------------------------===//
2223 // Atomic operations intrinsics
2226 // memory barriers protect the atomic sequences
2227 let hasSideEffects = 1 in {
2228 def Int_MemBarrierV7 : AInoP<(outs), (ins),
2229 Pseudo, NoItinerary,
2231 [(ARMMemBarrierV7)]>,
2232 Requires<[IsARM, HasV7]> {
2233 let Inst{31-4} = 0xf57ff05;
2234 // FIXME: add support for options other than a full system DMB
2235 // See DMB disassembly-only variants below.
2236 let Inst{3-0} = 0b1111;
2239 def Int_SyncBarrierV7 : AInoP<(outs), (ins),
2240 Pseudo, NoItinerary,
2242 [(ARMSyncBarrierV7)]>,
2243 Requires<[IsARM, HasV7]> {
2244 let Inst{31-4} = 0xf57ff04;
2245 // FIXME: add support for options other than a full system DSB
2246 // See DSB disassembly-only variants below.
2247 let Inst{3-0} = 0b1111;
2250 def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero),
2251 Pseudo, NoItinerary,
2252 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2253 [(ARMMemBarrierV6 GPR:$zero)]>,
2254 Requires<[IsARM, HasV6]> {
2255 // FIXME: add support for options other than a full system DMB
2256 // FIXME: add encoding
2259 def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
2260 Pseudo, NoItinerary,
2261 "mcr", "\tp15, 0, $zero, c7, c10, 4",
2262 [(ARMSyncBarrierV6 GPR:$zero)]>,
2263 Requires<[IsARM, HasV6]> {
2264 // FIXME: add support for options other than a full system DSB
2265 // FIXME: add encoding
2269 // Helper class for multiclass MemB -- for disassembly only
2270 class AMBI<string opc, string asm>
2271 : AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm,
2272 [/* For disassembly only; pattern left blank */]>,
2273 Requires<[IsARM, HasV7]> {
2274 let Inst{31-20} = 0xf57;
2277 multiclass MemB<bits<4> op7_4, string opc> {
2279 def st : AMBI<opc, "\tst"> {
2280 let Inst{7-4} = op7_4;
2281 let Inst{3-0} = 0b1110;
2284 def ish : AMBI<opc, "\tish"> {
2285 let Inst{7-4} = op7_4;
2286 let Inst{3-0} = 0b1011;
2289 def ishst : AMBI<opc, "\tishst"> {
2290 let Inst{7-4} = op7_4;
2291 let Inst{3-0} = 0b1010;
2294 def nsh : AMBI<opc, "\tnsh"> {
2295 let Inst{7-4} = op7_4;
2296 let Inst{3-0} = 0b0111;
2299 def nshst : AMBI<opc, "\tnshst"> {
2300 let Inst{7-4} = op7_4;
2301 let Inst{3-0} = 0b0110;
2304 def osh : AMBI<opc, "\tosh"> {
2305 let Inst{7-4} = op7_4;
2306 let Inst{3-0} = 0b0011;
2309 def oshst : AMBI<opc, "\toshst"> {
2310 let Inst{7-4} = op7_4;
2311 let Inst{3-0} = 0b0010;
2315 // These DMB variants are for disassembly only.
2316 defm DMB : MemB<0b0101, "dmb">;
2318 // These DSB variants are for disassembly only.
2319 defm DSB : MemB<0b0100, "dsb">;
2321 // ISB has only full system option -- for disassembly only
2322 def ISBsy : AMBI<"isb", ""> {
2323 let Inst{7-4} = 0b0110;
2324 let Inst{3-0} = 0b1111;
2327 let usesCustomInserter = 1 in {
2328 let Uses = [CPSR] in {
2329 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2330 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2331 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
2332 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2333 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2334 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2335 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
2336 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2337 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2339 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
2340 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2341 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2342 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2343 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
2344 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2345 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2346 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2347 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
2348 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2349 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2350 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2351 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
2352 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2353 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2354 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2355 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
2356 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2357 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2358 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2359 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
2360 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2361 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2362 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2363 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
2364 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2365 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2366 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2367 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
2368 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2369 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2370 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2371 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
2372 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2373 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2374 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2375 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
2376 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2377 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2378 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2379 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
2380 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2381 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2382 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2383 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
2384 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2385 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2386 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2387 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
2388 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2389 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2390 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2391 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
2392 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2393 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2394 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2395 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
2396 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2397 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2398 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2399 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
2400 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2402 def ATOMIC_SWAP_I8 : PseudoInst<
2403 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2404 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
2405 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2406 def ATOMIC_SWAP_I16 : PseudoInst<
2407 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2408 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
2409 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2410 def ATOMIC_SWAP_I32 : PseudoInst<
2411 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2412 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
2413 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
2415 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
2416 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2417 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
2418 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
2419 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
2420 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2421 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
2422 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
2423 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
2424 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2425 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
2426 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
2430 let mayLoad = 1 in {
2431 def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2432 "ldrexb", "\t$dest, [$ptr]",
2434 def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2435 "ldrexh", "\t$dest, [$ptr]",
2437 def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2438 "ldrex", "\t$dest, [$ptr]",
2440 def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2442 "ldrexd", "\t$dest, $dest2, [$ptr]",
2446 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2447 def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2449 "strexb", "\t$success, $src, [$ptr]",
2451 def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2453 "strexh", "\t$success, $src, [$ptr]",
2455 def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2457 "strex", "\t$success, $src, [$ptr]",
2459 def STREXD : AIstrex<0b01, (outs GPR:$success),
2460 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2462 "strexd", "\t$success, $src, $src2, [$ptr]",
2466 // Clear-Exclusive is for disassembly only.
2467 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
2468 [/* For disassembly only; pattern left blank */]>,
2469 Requires<[IsARM, HasV7]> {
2470 let Inst{31-20} = 0xf57;
2471 let Inst{7-4} = 0b0001;
2474 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
2475 let mayLoad = 1 in {
2476 def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2477 "swp", "\t$dst, $src, [$ptr]",
2478 [/* For disassembly only; pattern left blank */]> {
2479 let Inst{27-23} = 0b00010;
2480 let Inst{22} = 0; // B = 0
2481 let Inst{21-20} = 0b00;
2482 let Inst{7-4} = 0b1001;
2485 def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2486 "swpb", "\t$dst, $src, [$ptr]",
2487 [/* For disassembly only; pattern left blank */]> {
2488 let Inst{27-23} = 0b00010;
2489 let Inst{22} = 1; // B = 1
2490 let Inst{21-20} = 0b00;
2491 let Inst{7-4} = 0b1001;
2495 //===----------------------------------------------------------------------===//
2499 // __aeabi_read_tp preserves the registers r1-r3.
2501 Defs = [R0, R12, LR, CPSR] in {
2502 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
2503 "bl\t__aeabi_read_tp",
2504 [(set R0, ARMthread_pointer)]>;
2507 //===----------------------------------------------------------------------===//
2508 // SJLJ Exception handling intrinsics
2509 // eh_sjlj_setjmp() is an instruction sequence to store the return
2510 // address and save #0 in R0 for the non-longjmp case.
2511 // Since by its nature we may be coming from some other function to get
2512 // here, and we're using the stack frame for the containing function to
2513 // save/restore registers, we can't keep anything live in regs across
2514 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2515 // when we get here from a longjmp(). We force everthing out of registers
2516 // except for our own input by listing the relevant registers in Defs. By
2517 // doing so, we also cause the prologue/epilogue code to actively preserve
2518 // all of the callee-saved resgisters, which is exactly what we want.
2519 // A constant value is passed in $val, and we use the location as a scratch.
2521 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2522 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2523 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2525 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
2526 AddrModeNone, SizeSpecial, IndexModeNone,
2527 Pseudo, NoItinerary,
2528 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
2529 "add\t$val, pc, #8\n\t"
2530 "str\t$val, [$src, #+4]\n\t"
2532 "add\tpc, pc, #0\n\t"
2533 "mov\tr0, #1 @ eh_setjmp end", "",
2534 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>;
2537 //===----------------------------------------------------------------------===//
2538 // Non-Instruction Patterns
2541 // Large immediate handling.
2543 // Two piece so_imms.
2544 let isReMaterializable = 1 in
2545 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
2547 "mov", "\t$dst, $src",
2548 [(set GPR:$dst, so_imm2part:$src)]>,
2549 Requires<[IsARM, NoV6T2]>;
2551 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
2552 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2553 (so_imm2part_2 imm:$RHS))>;
2554 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
2555 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2556 (so_imm2part_2 imm:$RHS))>;
2557 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
2558 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2559 (so_imm2part_2 imm:$RHS))>;
2560 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
2561 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
2562 (so_neg_imm2part_2 imm:$RHS))>;
2564 // 32-bit immediate using movw + movt.
2565 // This is a single pseudo instruction, the benefit is that it can be remat'd
2566 // as a single unit instead of having to handle reg inputs.
2567 // FIXME: Remove this when we can do generalized remat.
2568 let isReMaterializable = 1 in
2569 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
2570 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2571 [(set GPR:$dst, (i32 imm:$src))]>,
2572 Requires<[IsARM, HasV6T2]>;
2574 // ConstantPool, GlobalAddress, and JumpTable
2575 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
2576 Requires<[IsARM, DontUseMovt]>;
2577 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
2578 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
2579 Requires<[IsARM, UseMovt]>;
2580 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2581 (LEApcrelJT tjumptable:$dst, imm:$id)>;
2583 // TODO: add,sub,and, 3-instr forms?
2587 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
2588 Requires<[IsARM, IsNotDarwin]>;
2589 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
2590 Requires<[IsARM, IsDarwin]>;
2592 // zextload i1 -> zextload i8
2593 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2595 // extload -> zextload
2596 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2597 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2598 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
2600 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
2601 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
2604 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2605 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2606 (SMULBB GPR:$a, GPR:$b)>;
2607 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
2608 (SMULBB GPR:$a, GPR:$b)>;
2609 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2610 (sra GPR:$b, (i32 16))),
2611 (SMULBT GPR:$a, GPR:$b)>;
2612 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
2613 (SMULBT GPR:$a, GPR:$b)>;
2614 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
2615 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2616 (SMULTB GPR:$a, GPR:$b)>;
2617 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
2618 (SMULTB GPR:$a, GPR:$b)>;
2619 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2621 (SMULWB GPR:$a, GPR:$b)>;
2622 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
2623 (SMULWB GPR:$a, GPR:$b)>;
2625 def : ARMV5TEPat<(add GPR:$acc,
2626 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2627 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2628 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2629 def : ARMV5TEPat<(add GPR:$acc,
2630 (mul sext_16_node:$a, sext_16_node:$b)),
2631 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2632 def : ARMV5TEPat<(add GPR:$acc,
2633 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2634 (sra GPR:$b, (i32 16)))),
2635 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2636 def : ARMV5TEPat<(add GPR:$acc,
2637 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
2638 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2639 def : ARMV5TEPat<(add GPR:$acc,
2640 (mul (sra GPR:$a, (i32 16)),
2641 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2642 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2643 def : ARMV5TEPat<(add GPR:$acc,
2644 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
2645 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2646 def : ARMV5TEPat<(add GPR:$acc,
2647 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2649 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2650 def : ARMV5TEPat<(add GPR:$acc,
2651 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
2652 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2654 //===----------------------------------------------------------------------===//
2658 include "ARMInstrThumb.td"
2660 //===----------------------------------------------------------------------===//
2664 include "ARMInstrThumb2.td"
2666 //===----------------------------------------------------------------------===//
2667 // Floating Point Support
2670 include "ARMInstrVFP.td"
2672 //===----------------------------------------------------------------------===//
2673 // Advanced SIMD (NEON) Support
2676 include "ARMInstrNEON.td"
2678 //===----------------------------------------------------------------------===//
2679 // Coprocessor Instructions. For disassembly only.
2682 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2683 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2684 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2685 [/* For disassembly only; pattern left blank */]> {
2689 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2690 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2691 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2692 [/* For disassembly only; pattern left blank */]> {
2693 let Inst{31-28} = 0b1111;
2697 class ACI<dag oops, dag iops, string opc, string asm>
2698 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
2699 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
2700 let Inst{27-25} = 0b110;
2703 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
2705 def _OFFSET : ACI<(outs),
2706 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2707 opc, "\tp$cop, cr$CRd, $addr"> {
2708 let Inst{31-28} = op31_28;
2709 let Inst{24} = 1; // P = 1
2710 let Inst{21} = 0; // W = 0
2711 let Inst{22} = 0; // D = 0
2712 let Inst{20} = load;
2715 def _PRE : ACI<(outs),
2716 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2717 opc, "\tp$cop, cr$CRd, $addr!"> {
2718 let Inst{31-28} = op31_28;
2719 let Inst{24} = 1; // P = 1
2720 let Inst{21} = 1; // W = 1
2721 let Inst{22} = 0; // D = 0
2722 let Inst{20} = load;
2725 def _POST : ACI<(outs),
2726 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2727 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
2728 let Inst{31-28} = op31_28;
2729 let Inst{24} = 0; // P = 0
2730 let Inst{21} = 1; // W = 1
2731 let Inst{22} = 0; // D = 0
2732 let Inst{20} = load;
2735 def _OPTION : ACI<(outs),
2736 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
2737 opc, "\tp$cop, cr$CRd, [$base], $option"> {
2738 let Inst{31-28} = op31_28;
2739 let Inst{24} = 0; // P = 0
2740 let Inst{23} = 1; // U = 1
2741 let Inst{21} = 0; // W = 0
2742 let Inst{22} = 0; // D = 0
2743 let Inst{20} = load;
2746 def L_OFFSET : ACI<(outs),
2747 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2748 opc, "l\tp$cop, cr$CRd, $addr"> {
2749 let Inst{31-28} = op31_28;
2750 let Inst{24} = 1; // P = 1
2751 let Inst{21} = 0; // W = 0
2752 let Inst{22} = 1; // D = 1
2753 let Inst{20} = load;
2756 def L_PRE : ACI<(outs),
2757 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2758 opc, "l\tp$cop, cr$CRd, $addr!"> {
2759 let Inst{31-28} = op31_28;
2760 let Inst{24} = 1; // P = 1
2761 let Inst{21} = 1; // W = 1
2762 let Inst{22} = 1; // D = 1
2763 let Inst{20} = load;
2766 def L_POST : ACI<(outs),
2767 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2768 opc, "l\tp$cop, cr$CRd, [$base], $offset"> {
2769 let Inst{31-28} = op31_28;
2770 let Inst{24} = 0; // P = 0
2771 let Inst{21} = 1; // W = 1
2772 let Inst{22} = 1; // D = 1
2773 let Inst{20} = load;
2776 def L_OPTION : ACI<(outs),
2777 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
2778 opc, "l\tp$cop, cr$CRd, [$base], $option"> {
2779 let Inst{31-28} = op31_28;
2780 let Inst{24} = 0; // P = 0
2781 let Inst{23} = 1; // U = 1
2782 let Inst{21} = 0; // W = 0
2783 let Inst{22} = 1; // D = 1
2784 let Inst{20} = load;
2788 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
2789 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
2790 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
2791 defm STC2 : LdStCop<0b1111, 0, "stc2">;
2793 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2794 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2795 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2796 [/* For disassembly only; pattern left blank */]> {
2801 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2802 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2803 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2804 [/* For disassembly only; pattern left blank */]> {
2805 let Inst{31-28} = 0b1111;
2810 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2811 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2812 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2813 [/* For disassembly only; pattern left blank */]> {
2818 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2819 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2820 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2821 [/* For disassembly only; pattern left blank */]> {
2822 let Inst{31-28} = 0b1111;
2827 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2828 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2829 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2830 [/* For disassembly only; pattern left blank */]> {
2831 let Inst{23-20} = 0b0100;
2834 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2835 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2836 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2837 [/* For disassembly only; pattern left blank */]> {
2838 let Inst{31-28} = 0b1111;
2839 let Inst{23-20} = 0b0100;
2842 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2843 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2844 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2845 [/* For disassembly only; pattern left blank */]> {
2846 let Inst{23-20} = 0b0101;
2849 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2850 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2851 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2852 [/* For disassembly only; pattern left blank */]> {
2853 let Inst{31-28} = 0b1111;
2854 let Inst{23-20} = 0b0101;
2857 //===----------------------------------------------------------------------===//
2858 // Move between special register and ARM core register -- for disassembly only
2861 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
2862 [/* For disassembly only; pattern left blank */]> {
2863 let Inst{23-20} = 0b0000;
2864 let Inst{7-4} = 0b0000;
2867 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
2868 [/* For disassembly only; pattern left blank */]> {
2869 let Inst{23-20} = 0b0100;
2870 let Inst{7-4} = 0b0000;
2873 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
2874 "msr", "\tcpsr$mask, $src",
2875 [/* For disassembly only; pattern left blank */]> {
2876 let Inst{23-20} = 0b0010;
2877 let Inst{7-4} = 0b0000;
2880 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
2881 "msr", "\tcpsr$mask, $a",
2882 [/* For disassembly only; pattern left blank */]> {
2883 let Inst{23-20} = 0b0010;
2884 let Inst{7-4} = 0b0000;
2887 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
2888 "msr", "\tspsr$mask, $src",
2889 [/* For disassembly only; pattern left blank */]> {
2890 let Inst{23-20} = 0b0110;
2891 let Inst{7-4} = 0b0000;
2894 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
2895 "msr", "\tspsr$mask, $a",
2896 [/* For disassembly only; pattern left blank */]> {
2897 let Inst{23-20} = 0b0110;
2898 let Inst{7-4} = 0b0000;