1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
51 def SDT_ARMMEMBARRIERV7 : SDTypeProfile<0, 0, []>;
52 def SDT_ARMSYNCBARRIERV7 : SDTypeProfile<0, 0, []>;
53 def SDT_ARMMEMBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
54 def SDT_ARMSYNCBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
57 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
58 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
60 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
61 [SDNPHasChain, SDNPOutFlag]>;
62 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
66 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
68 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
69 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
71 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
72 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
75 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
76 [SDNPHasChain, SDNPOptInFlag]>;
78 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
80 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
83 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
84 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
86 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
88 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
91 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
94 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
95 [SDNPOutFlag,SDNPCommutative]>;
97 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
99 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
100 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
101 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
103 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
104 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
105 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
106 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
107 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
109 def ARMMemBarrierV7 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV7,
111 def ARMSyncBarrierV7 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV7,
113 def ARMMemBarrierV6 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV6,
115 def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6,
118 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
120 //===----------------------------------------------------------------------===//
121 // ARM Instruction Predicate Definitions.
123 def HasV4T : Predicate<"Subtarget->hasV4TOps()">;
124 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
125 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
126 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
127 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
128 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
129 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
130 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
131 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
132 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
133 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
134 def HasNEON : Predicate<"Subtarget->hasNEON()">;
135 def HasDivide : Predicate<"Subtarget->hasDivide()">;
136 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">;
137 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
138 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
139 def IsThumb : Predicate<"Subtarget->isThumb()">;
140 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
141 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
142 def IsARM : Predicate<"!Subtarget->isThumb()">;
143 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
144 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
146 // FIXME: Eventually this will be just "hasV6T2Ops".
147 def UseMovt : Predicate<"Subtarget->useMovt()">;
148 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
150 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
152 //===----------------------------------------------------------------------===//
153 // ARM Flag Definitions.
155 class RegConstraint<string C> {
156 string Constraints = C;
159 //===----------------------------------------------------------------------===//
160 // ARM specific transformation functions and pattern fragments.
163 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
164 // so_imm_neg def below.
165 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
166 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
169 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
170 // so_imm_not def below.
171 def so_imm_not_XFORM : SDNodeXForm<imm, [{
172 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
175 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
176 def rot_imm : PatLeaf<(i32 imm), [{
177 int32_t v = (int32_t)N->getZExtValue();
178 return v == 8 || v == 16 || v == 24;
181 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
182 def imm1_15 : PatLeaf<(i32 imm), [{
183 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
186 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
187 def imm16_31 : PatLeaf<(i32 imm), [{
188 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
193 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
194 }], so_imm_neg_XFORM>;
198 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
199 }], so_imm_not_XFORM>;
201 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
202 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
203 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
206 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
208 def bf_inv_mask_imm : Operand<i32>,
210 uint32_t v = (uint32_t)N->getZExtValue();
213 // there can be 1's on either or both "outsides", all the "inside"
215 unsigned int lsb = 0, msb = 31;
216 while (v & (1 << msb)) --msb;
217 while (v & (1 << lsb)) ++lsb;
218 for (unsigned int i = lsb; i <= msb; ++i) {
224 let PrintMethod = "printBitfieldInvMaskImmOperand";
227 /// Split a 32-bit immediate into two 16 bit parts.
228 def lo16 : SDNodeXForm<imm, [{
229 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
233 def hi16 : SDNodeXForm<imm, [{
234 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
237 def lo16AllZero : PatLeaf<(i32 imm), [{
238 // Returns true if all low 16-bits are 0.
239 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
242 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
244 def imm0_65535 : PatLeaf<(i32 imm), [{
245 return (uint32_t)N->getZExtValue() < 65536;
248 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
249 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
251 /// adde and sube predicates - True based on whether the carry flag output
252 /// will be needed or not.
253 def adde_dead_carry :
254 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
255 [{return !N->hasAnyUseOfValue(1);}]>;
256 def sube_dead_carry :
257 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
258 [{return !N->hasAnyUseOfValue(1);}]>;
259 def adde_live_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return N->hasAnyUseOfValue(1);}]>;
262 def sube_live_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return N->hasAnyUseOfValue(1);}]>;
266 //===----------------------------------------------------------------------===//
267 // Operand Definitions.
271 def brtarget : Operand<OtherVT>;
273 // A list of registers separated by comma. Used by load/store multiple.
274 def reglist : Operand<i32> {
275 let PrintMethod = "printRegisterList";
278 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
279 def cpinst_operand : Operand<i32> {
280 let PrintMethod = "printCPInstOperand";
283 def jtblock_operand : Operand<i32> {
284 let PrintMethod = "printJTBlockOperand";
286 def jt2block_operand : Operand<i32> {
287 let PrintMethod = "printJT2BlockOperand";
291 def pclabel : Operand<i32> {
292 let PrintMethod = "printPCLabel";
295 // shifter_operand operands: so_reg and so_imm.
296 def so_reg : Operand<i32>, // reg reg imm
297 ComplexPattern<i32, 3, "SelectShifterOperandReg",
298 [shl,srl,sra,rotr]> {
299 let PrintMethod = "printSORegOperand";
300 let MIOperandInfo = (ops GPR, GPR, i32imm);
303 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
304 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
305 // represented in the imm field in the same 12-bit form that they are encoded
306 // into so_imm instructions: the 8-bit immediate is the least significant bits
307 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
308 def so_imm : Operand<i32>,
310 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
312 let PrintMethod = "printSOImmOperand";
315 // Break so_imm's up into two pieces. This handles immediates with up to 16
316 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
317 // get the first/second pieces.
318 def so_imm2part : Operand<i32>,
320 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
322 let PrintMethod = "printSOImm2PartOperand";
325 def so_imm2part_1 : SDNodeXForm<imm, [{
326 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
327 return CurDAG->getTargetConstant(V, MVT::i32);
330 def so_imm2part_2 : SDNodeXForm<imm, [{
331 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
332 return CurDAG->getTargetConstant(V, MVT::i32);
335 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
336 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
338 let PrintMethod = "printSOImm2PartOperand";
341 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
342 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
343 return CurDAG->getTargetConstant(V, MVT::i32);
346 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
347 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
348 return CurDAG->getTargetConstant(V, MVT::i32);
351 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
352 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
353 return (int32_t)N->getZExtValue() < 32;
356 // Define ARM specific addressing modes.
358 // addrmode2 := reg +/- reg shop imm
359 // addrmode2 := reg +/- imm12
361 def addrmode2 : Operand<i32>,
362 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
363 let PrintMethod = "printAddrMode2Operand";
364 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
367 def am2offset : Operand<i32>,
368 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
369 let PrintMethod = "printAddrMode2OffsetOperand";
370 let MIOperandInfo = (ops GPR, i32imm);
373 // addrmode3 := reg +/- reg
374 // addrmode3 := reg +/- imm8
376 def addrmode3 : Operand<i32>,
377 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
378 let PrintMethod = "printAddrMode3Operand";
379 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
382 def am3offset : Operand<i32>,
383 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
384 let PrintMethod = "printAddrMode3OffsetOperand";
385 let MIOperandInfo = (ops GPR, i32imm);
388 // addrmode4 := reg, <mode|W>
390 def addrmode4 : Operand<i32>,
391 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
392 let PrintMethod = "printAddrMode4Operand";
393 let MIOperandInfo = (ops GPR:$addr, i32imm);
396 // addrmode5 := reg +/- imm8*4
398 def addrmode5 : Operand<i32>,
399 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
400 let PrintMethod = "printAddrMode5Operand";
401 let MIOperandInfo = (ops GPR:$base, i32imm);
404 // addrmode6 := reg with optional writeback
406 def addrmode6 : Operand<i32>,
407 ComplexPattern<i32, 2, "SelectAddrMode6", []> {
408 let PrintMethod = "printAddrMode6Operand";
409 let MIOperandInfo = (ops GPR:$addr, i32imm);
412 def am6offset : Operand<i32> {
413 let PrintMethod = "printAddrMode6OffsetOperand";
414 let MIOperandInfo = (ops GPR);
417 // addrmodepc := pc + reg
419 def addrmodepc : Operand<i32>,
420 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
421 let PrintMethod = "printAddrModePCOperand";
422 let MIOperandInfo = (ops GPR, i32imm);
425 def nohash_imm : Operand<i32> {
426 let PrintMethod = "printNoHashImmediate";
429 //===----------------------------------------------------------------------===//
431 include "ARMInstrFormats.td"
433 //===----------------------------------------------------------------------===//
434 // Multiclass helpers...
437 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
438 /// binop that produces a value.
439 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
440 bit Commutable = 0> {
441 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
442 IIC_iALUi, opc, "\t$dst, $a, $b",
443 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
446 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
447 IIC_iALUr, opc, "\t$dst, $a, $b",
448 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
449 let Inst{11-4} = 0b00000000;
451 let isCommutable = Commutable;
453 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
454 IIC_iALUsr, opc, "\t$dst, $a, $b",
455 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
460 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
461 /// instruction modifies the CPSR register.
462 let Defs = [CPSR] in {
463 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
464 bit Commutable = 0> {
465 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
466 IIC_iALUi, opc, "\t$dst, $a, $b",
467 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
471 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
472 IIC_iALUr, opc, "\t$dst, $a, $b",
473 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
474 let isCommutable = Commutable;
475 let Inst{11-4} = 0b00000000;
479 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
480 IIC_iALUsr, opc, "\t$dst, $a, $b",
481 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
488 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
489 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
490 /// a explicit result, only implicitly set CPSR.
491 let Defs = [CPSR] in {
492 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
493 bit Commutable = 0> {
494 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
496 [(opnode GPR:$a, so_imm:$b)]> {
500 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
502 [(opnode GPR:$a, GPR:$b)]> {
503 let Inst{11-4} = 0b00000000;
506 let isCommutable = Commutable;
508 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
510 [(opnode GPR:$a, so_reg:$b)]> {
517 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
518 /// register and one whose operand is a register rotated by 8/16/24.
519 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
520 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
521 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
522 IIC_iUNAr, opc, "\t$dst, $src",
523 [(set GPR:$dst, (opnode GPR:$src))]>,
524 Requires<[IsARM, HasV6]> {
525 let Inst{11-10} = 0b00;
526 let Inst{19-16} = 0b1111;
528 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
529 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
530 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
531 Requires<[IsARM, HasV6]> {
532 let Inst{19-16} = 0b1111;
536 multiclass AI_unary_rrot_np<bits<8> opcod, string opc> {
537 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
538 IIC_iUNAr, opc, "\t$dst, $src",
539 [/* For disassembly only; pattern left blank */]>,
540 Requires<[IsARM, HasV6]> {
541 let Inst{11-10} = 0b00;
542 let Inst{19-16} = 0b1111;
544 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
545 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
546 [/* For disassembly only; pattern left blank */]>,
547 Requires<[IsARM, HasV6]> {
548 let Inst{19-16} = 0b1111;
552 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
553 /// register and one whose operand is a register rotated by 8/16/24.
554 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
555 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
556 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
557 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
558 Requires<[IsARM, HasV6]> {
559 let Inst{11-10} = 0b00;
561 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
563 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
564 [(set GPR:$dst, (opnode GPR:$LHS,
565 (rotr GPR:$RHS, rot_imm:$rot)))]>,
566 Requires<[IsARM, HasV6]>;
569 // For disassembly only.
570 multiclass AI_bin_rrot_np<bits<8> opcod, string opc> {
571 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
572 IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
573 [/* For disassembly only; pattern left blank */]>,
574 Requires<[IsARM, HasV6]> {
575 let Inst{11-10} = 0b00;
577 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS,
579 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
580 [/* For disassembly only; pattern left blank */]>,
581 Requires<[IsARM, HasV6]>;
584 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
585 let Uses = [CPSR] in {
586 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
587 bit Commutable = 0> {
588 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
589 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
590 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
594 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
595 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
596 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
598 let isCommutable = Commutable;
599 let Inst{11-4} = 0b00000000;
602 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
603 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
604 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
609 // Carry setting variants
610 let Defs = [CPSR] in {
611 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
612 bit Commutable = 0> {
613 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
614 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"),
615 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
620 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
621 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"),
622 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
624 let Inst{11-4} = 0b00000000;
628 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
629 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"),
630 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
639 //===----------------------------------------------------------------------===//
641 //===----------------------------------------------------------------------===//
643 //===----------------------------------------------------------------------===//
644 // Miscellaneous Instructions.
647 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
648 /// the function. The first operand is the ID# for this instruction, the second
649 /// is the index into the MachineConstantPool that this is, the third is the
650 /// size in bytes of this constant pool entry.
651 let neverHasSideEffects = 1, isNotDuplicable = 1 in
652 def CONSTPOOL_ENTRY :
653 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
654 i32imm:$size), NoItinerary,
655 "${instid:label} ${cpidx:cpentry}", []>;
657 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
658 // from removing one half of the matched pairs. That breaks PEI, which assumes
659 // these will always be in pairs, and asserts if it finds otherwise. Better way?
660 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
662 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
663 "${:comment} ADJCALLSTACKUP $amt1",
664 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
666 def ADJCALLSTACKDOWN :
667 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
668 "${:comment} ADJCALLSTACKDOWN $amt",
669 [(ARMcallseq_start timm:$amt)]>;
672 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
673 [/* For disassembly only; pattern left blank */]>,
674 Requires<[IsARM, HasV6T2]> {
675 let Inst{27-16} = 0b001100100000;
676 let Inst{7-0} = 0b00000000;
679 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
680 [/* For disassembly only; pattern left blank */]>,
681 Requires<[IsARM, HasV6T2]> {
682 let Inst{27-16} = 0b001100100000;
683 let Inst{7-0} = 0b00000001;
686 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
687 [/* For disassembly only; pattern left blank */]>,
688 Requires<[IsARM, HasV6T2]> {
689 let Inst{27-16} = 0b001100100000;
690 let Inst{7-0} = 0b00000010;
693 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
694 [/* For disassembly only; pattern left blank */]>,
695 Requires<[IsARM, HasV6T2]> {
696 let Inst{27-16} = 0b001100100000;
697 let Inst{7-0} = 0b00000011;
700 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
702 [/* For disassembly only; pattern left blank */]>,
703 Requires<[IsARM, HasV6]> {
704 let Inst{27-20} = 0b01101000;
705 let Inst{7-4} = 0b1011;
708 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
709 [/* For disassembly only; pattern left blank */]>,
710 Requires<[IsARM, HasV6T2]> {
711 let Inst{27-16} = 0b001100100000;
712 let Inst{7-0} = 0b00000100;
715 // The i32imm operand $val can be used by a debugger to store more information
716 // about the breakpoint.
717 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
718 [/* For disassembly only; pattern left blank */]>,
720 let Inst{27-20} = 0b00010010;
721 let Inst{7-4} = 0b0111;
724 // Change Processor State is a system instruction -- for disassembly only.
725 // The singleton $opt operand contains the following information:
726 // opt{4-0} = mode from Inst{4-0}
727 // opt{5} = changemode from Inst{17}
728 // opt{8-6} = AIF from Inst{8-6}
729 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
730 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
731 [/* For disassembly only; pattern left blank */]>,
733 let Inst{31-28} = 0b1111;
734 let Inst{27-20} = 0b00010000;
739 // Preload signals the memory system of possible future data/instruction access.
740 // These are for disassembly only.
742 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
743 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
744 multiclass APreLoad<bit data, bit read, string opc> {
746 def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary,
747 !strconcat(opc, "\t[$base, $imm]"), []> {
748 let Inst{31-26} = 0b111101;
749 let Inst{25} = 0; // 0 for immediate form
752 let Inst{21-20} = 0b01;
755 def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary,
756 !strconcat(opc, "\t$addr"), []> {
757 let Inst{31-26} = 0b111101;
758 let Inst{25} = 1; // 1 for register form
761 let Inst{21-20} = 0b01;
766 defm PLD : APreLoad<1, 1, "pld">;
767 defm PLDW : APreLoad<1, 0, "pldw">;
768 defm PLI : APreLoad<0, 1, "pli">;
770 def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
771 [/* For disassembly only; pattern left blank */]>,
773 let Inst{31-28} = 0b1111;
774 let Inst{27-20} = 0b00010000;
777 let Inst{7-4} = 0b0000;
780 def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
781 [/* For disassembly only; pattern left blank */]>,
783 let Inst{31-28} = 0b1111;
784 let Inst{27-20} = 0b00010000;
787 let Inst{7-4} = 0b0000;
790 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
791 [/* For disassembly only; pattern left blank */]>,
792 Requires<[IsARM, HasV7]> {
793 let Inst{27-16} = 0b001100100000;
794 let Inst{7-4} = 0b1111;
797 // A5.4 Permanently UNDEFINED instructions.
798 // FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
800 let isBarrier = 1, isTerminator = 1 in
801 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
802 ".long 0xe7ffdefe ${:comment} trap", [(trap)]>,
804 let Inst{27-25} = 0b011;
805 let Inst{24-20} = 0b11111;
806 let Inst{7-5} = 0b111;
810 // Address computation and loads and stores in PIC mode.
811 let isNotDuplicable = 1 in {
812 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
813 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
814 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
816 let AddedComplexity = 10 in {
817 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
818 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
819 [(set GPR:$dst, (load addrmodepc:$addr))]>;
821 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
822 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr",
823 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
825 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
826 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr",
827 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
829 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
830 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr",
831 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
833 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
834 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr",
835 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
837 let AddedComplexity = 10 in {
838 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
839 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
840 [(store GPR:$src, addrmodepc:$addr)]>;
842 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
843 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr",
844 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
846 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
847 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr",
848 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
850 } // isNotDuplicable = 1
853 // LEApcrel - Load a pc-relative address into a register without offending the
855 let neverHasSideEffects = 1 in {
856 let isReMaterializable = 1 in
857 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
859 "adr$p\t$dst, #$label", []>;
861 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
862 (ins i32imm:$label, nohash_imm:$id, pred:$p),
864 "adr$p\t$dst, #${label}_${id}", []> {
867 } // neverHasSideEffects
869 //===----------------------------------------------------------------------===//
870 // Control Flow Instructions.
873 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
875 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
876 "bx", "\tlr", [(ARMretflag)]>,
877 Requires<[IsARM, HasV4T]> {
878 let Inst{3-0} = 0b1110;
879 let Inst{7-4} = 0b0001;
880 let Inst{19-8} = 0b111111111111;
881 let Inst{27-20} = 0b00010010;
885 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
886 "mov", "\tpc, lr", [(ARMretflag)]>,
887 Requires<[IsARM, NoV4T]> {
888 let Inst{11-0} = 0b000000001110;
889 let Inst{15-12} = 0b1111;
890 let Inst{19-16} = 0b0000;
891 let Inst{27-20} = 0b00011010;
896 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
898 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
900 Requires<[IsARM, HasV4T]> {
901 let Inst{7-4} = 0b0001;
902 let Inst{19-8} = 0b111111111111;
903 let Inst{27-20} = 0b00010010;
904 let Inst{31-28} = 0b1110;
908 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
910 Requires<[IsARM, NoV4T]> {
911 let Inst{11-4} = 0b00000000;
912 let Inst{15-12} = 0b1111;
913 let Inst{19-16} = 0b0000;
914 let Inst{27-20} = 0b00011010;
915 let Inst{31-28} = 0b1110;
919 // FIXME: remove when we have a way to marking a MI with these properties.
920 // FIXME: Should pc be an implicit operand like PICADD, etc?
921 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
922 hasExtraDefRegAllocReq = 1 in
923 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
924 reglist:$dsts, variable_ops),
925 IndexModeUpd, LdStMulFrm, IIC_Br,
926 "ldm${addr:submode}${p}\t$addr!, $dsts",
927 "$addr.addr = $wb", []>;
929 // On non-Darwin platforms R9 is callee-saved.
931 Defs = [R0, R1, R2, R3, R12, LR,
932 D0, D1, D2, D3, D4, D5, D6, D7,
933 D16, D17, D18, D19, D20, D21, D22, D23,
934 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
935 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
936 IIC_Br, "bl\t${func:call}",
937 [(ARMcall tglobaladdr:$func)]>,
938 Requires<[IsARM, IsNotDarwin]> {
939 let Inst{31-28} = 0b1110;
942 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
943 IIC_Br, "bl", "\t${func:call}",
944 [(ARMcall_pred tglobaladdr:$func)]>,
945 Requires<[IsARM, IsNotDarwin]>;
948 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
949 IIC_Br, "blx\t$func",
950 [(ARMcall GPR:$func)]>,
951 Requires<[IsARM, HasV5T, IsNotDarwin]> {
952 let Inst{7-4} = 0b0011;
953 let Inst{19-8} = 0b111111111111;
954 let Inst{27-20} = 0b00010010;
958 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
959 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
960 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
961 [(ARMcall_nolink tGPR:$func)]>,
962 Requires<[IsARM, HasV4T, IsNotDarwin]> {
963 let Inst{7-4} = 0b0001;
964 let Inst{19-8} = 0b111111111111;
965 let Inst{27-20} = 0b00010010;
969 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
970 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
971 [(ARMcall_nolink tGPR:$func)]>,
972 Requires<[IsARM, NoV4T, IsNotDarwin]> {
973 let Inst{11-4} = 0b00000000;
974 let Inst{15-12} = 0b1111;
975 let Inst{19-16} = 0b0000;
976 let Inst{27-20} = 0b00011010;
980 // On Darwin R9 is call-clobbered.
982 Defs = [R0, R1, R2, R3, R9, R12, LR,
983 D0, D1, D2, D3, D4, D5, D6, D7,
984 D16, D17, D18, D19, D20, D21, D22, D23,
985 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
986 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
987 IIC_Br, "bl\t${func:call}",
988 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
989 let Inst{31-28} = 0b1110;
992 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
993 IIC_Br, "bl", "\t${func:call}",
994 [(ARMcall_pred tglobaladdr:$func)]>,
995 Requires<[IsARM, IsDarwin]>;
998 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
999 IIC_Br, "blx\t$func",
1000 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1001 let Inst{7-4} = 0b0011;
1002 let Inst{19-8} = 0b111111111111;
1003 let Inst{27-20} = 0b00010010;
1007 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1008 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1009 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1010 [(ARMcall_nolink tGPR:$func)]>,
1011 Requires<[IsARM, HasV4T, IsDarwin]> {
1012 let Inst{7-4} = 0b0001;
1013 let Inst{19-8} = 0b111111111111;
1014 let Inst{27-20} = 0b00010010;
1018 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1019 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1020 [(ARMcall_nolink tGPR:$func)]>,
1021 Requires<[IsARM, NoV4T, IsDarwin]> {
1022 let Inst{11-4} = 0b00000000;
1023 let Inst{15-12} = 0b1111;
1024 let Inst{19-16} = 0b0000;
1025 let Inst{27-20} = 0b00011010;
1029 let isBranch = 1, isTerminator = 1 in {
1030 // B is "predicable" since it can be xformed into a Bcc.
1031 let isBarrier = 1 in {
1032 let isPredicable = 1 in
1033 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1034 "b\t$target", [(br bb:$target)]>;
1036 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1037 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1038 IIC_Br, "mov\tpc, $target \n$jt",
1039 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1040 let Inst{11-4} = 0b00000000;
1041 let Inst{15-12} = 0b1111;
1042 let Inst{20} = 0; // S Bit
1043 let Inst{24-21} = 0b1101;
1044 let Inst{27-25} = 0b000;
1046 def BR_JTm : JTI<(outs),
1047 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1048 IIC_Br, "ldr\tpc, $target \n$jt",
1049 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1051 let Inst{15-12} = 0b1111;
1052 let Inst{20} = 1; // L bit
1053 let Inst{21} = 0; // W bit
1054 let Inst{22} = 0; // B bit
1055 let Inst{24} = 1; // P bit
1056 let Inst{27-25} = 0b011;
1058 def BR_JTadd : JTI<(outs),
1059 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1060 IIC_Br, "add\tpc, $target, $idx \n$jt",
1061 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1063 let Inst{15-12} = 0b1111;
1064 let Inst{20} = 0; // S bit
1065 let Inst{24-21} = 0b0100;
1066 let Inst{27-25} = 0b000;
1068 } // isNotDuplicable = 1, isIndirectBranch = 1
1071 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1072 // a two-value operand where a dag node expects two operands. :(
1073 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1074 IIC_Br, "b", "\t$target",
1075 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1078 // Branch and Exchange Jazelle -- for disassembly only
1079 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1080 [/* For disassembly only; pattern left blank */]> {
1081 let Inst{23-20} = 0b0010;
1082 //let Inst{19-8} = 0xfff;
1083 let Inst{7-4} = 0b0010;
1086 // Secure Monitor Call is a system instruction -- for disassembly only
1087 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1088 [/* For disassembly only; pattern left blank */]> {
1089 let Inst{23-20} = 0b0110;
1090 let Inst{7-4} = 0b0111;
1093 // Supervisor Call (Software Interrupt) -- for disassembly only
1095 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1096 [/* For disassembly only; pattern left blank */]>;
1099 // Store Return State is a system instruction -- for disassembly only
1100 def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1101 NoItinerary, "srs${addr:submode}\tsp!, $mode",
1102 [/* For disassembly only; pattern left blank */]> {
1103 let Inst{31-28} = 0b1111;
1104 let Inst{22-20} = 0b110; // W = 1
1107 def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1108 NoItinerary, "srs${addr:submode}\tsp, $mode",
1109 [/* For disassembly only; pattern left blank */]> {
1110 let Inst{31-28} = 0b1111;
1111 let Inst{22-20} = 0b100; // W = 0
1114 // Return From Exception is a system instruction -- for disassembly only
1115 def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1116 NoItinerary, "rfe${addr:submode}\t$base!",
1117 [/* For disassembly only; pattern left blank */]> {
1118 let Inst{31-28} = 0b1111;
1119 let Inst{22-20} = 0b011; // W = 1
1122 def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1123 NoItinerary, "rfe${addr:submode}\t$base",
1124 [/* For disassembly only; pattern left blank */]> {
1125 let Inst{31-28} = 0b1111;
1126 let Inst{22-20} = 0b001; // W = 0
1129 //===----------------------------------------------------------------------===//
1130 // Load / store Instructions.
1134 let canFoldAsLoad = 1, isReMaterializable = 1 in
1135 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1136 "ldr", "\t$dst, $addr",
1137 [(set GPR:$dst, (load addrmode2:$addr))]>;
1139 // Special LDR for loads from non-pc-relative constpools.
1140 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1141 isReMaterializable = 1 in
1142 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
1143 "ldr", "\t$dst, $addr", []>;
1145 // Loads with zero extension
1146 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1147 IIC_iLoadr, "ldrh", "\t$dst, $addr",
1148 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1150 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
1151 IIC_iLoadr, "ldrb", "\t$dst, $addr",
1152 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
1154 // Loads with sign extension
1155 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1156 IIC_iLoadr, "ldrsh", "\t$dst, $addr",
1157 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1159 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1160 IIC_iLoadr, "ldrsb", "\t$dst, $addr",
1161 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1163 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1165 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1166 IIC_iLoadr, "ldrd", "\t$dst1, $addr",
1167 []>, Requires<[IsARM, HasV5TE]>;
1170 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1171 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1172 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1174 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1175 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1176 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1178 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1179 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1180 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1182 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1183 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1184 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1186 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1187 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
1188 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1190 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1191 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1192 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1194 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1195 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1196 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1198 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1199 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1200 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1202 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1203 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
1204 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1206 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1207 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1208 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1210 // For disassembly only
1211 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1212 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadr,
1213 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1214 Requires<[IsARM, HasV5TE]>;
1216 // For disassembly only
1217 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1218 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadr,
1219 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1220 Requires<[IsARM, HasV5TE]>;
1222 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1224 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1226 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1227 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
1228 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1229 let Inst{21} = 1; // overwrite
1232 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1233 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
1234 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1235 let Inst{21} = 1; // overwrite
1238 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1239 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1240 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1241 let Inst{21} = 1; // overwrite
1244 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1245 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1246 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1247 let Inst{21} = 1; // overwrite
1250 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1251 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
1252 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1253 let Inst{21} = 1; // overwrite
1257 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1258 "str", "\t$src, $addr",
1259 [(store GPR:$src, addrmode2:$addr)]>;
1261 // Stores with truncate
1262 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1263 IIC_iStorer, "strh", "\t$src, $addr",
1264 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1266 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
1267 "strb", "\t$src, $addr",
1268 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
1271 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1272 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1273 StMiscFrm, IIC_iStorer,
1274 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1277 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1278 (ins GPR:$src, GPR:$base, am2offset:$offset),
1279 StFrm, IIC_iStoreru,
1280 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1282 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1284 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1285 (ins GPR:$src, GPR:$base,am2offset:$offset),
1286 StFrm, IIC_iStoreru,
1287 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1289 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1291 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1292 (ins GPR:$src, GPR:$base,am3offset:$offset),
1293 StMiscFrm, IIC_iStoreru,
1294 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1296 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1298 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1299 (ins GPR:$src, GPR:$base,am3offset:$offset),
1300 StMiscFrm, IIC_iStoreru,
1301 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1302 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1303 GPR:$base, am3offset:$offset))]>;
1305 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1306 (ins GPR:$src, GPR:$base,am2offset:$offset),
1307 StFrm, IIC_iStoreru,
1308 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1309 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1310 GPR:$base, am2offset:$offset))]>;
1312 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1313 (ins GPR:$src, GPR:$base,am2offset:$offset),
1314 StFrm, IIC_iStoreru,
1315 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1316 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1317 GPR:$base, am2offset:$offset))]>;
1319 // For disassembly only
1320 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1321 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1322 StMiscFrm, IIC_iStoreru,
1323 "strd", "\t$src1, $src2, [$base, $offset]!",
1324 "$base = $base_wb", []>;
1326 // For disassembly only
1327 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1328 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1329 StMiscFrm, IIC_iStoreru,
1330 "strd", "\t$src1, $src2, [$base], $offset",
1331 "$base = $base_wb", []>;
1333 // STRT, STRBT, and STRHT are for disassembly only.
1335 def STRT : AI2stwpo<(outs GPR:$base_wb),
1336 (ins GPR:$src, GPR:$base,am2offset:$offset),
1337 StFrm, IIC_iStoreru,
1338 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1339 [/* For disassembly only; pattern left blank */]> {
1340 let Inst{21} = 1; // overwrite
1343 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1344 (ins GPR:$src, GPR:$base,am2offset:$offset),
1345 StFrm, IIC_iStoreru,
1346 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1347 [/* For disassembly only; pattern left blank */]> {
1348 let Inst{21} = 1; // overwrite
1351 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1352 (ins GPR:$src, GPR:$base,am3offset:$offset),
1353 StMiscFrm, IIC_iStoreru,
1354 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1355 [/* For disassembly only; pattern left blank */]> {
1356 let Inst{21} = 1; // overwrite
1359 //===----------------------------------------------------------------------===//
1360 // Load / store multiple Instructions.
1363 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1364 def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
1365 reglist:$dsts, variable_ops),
1366 IndexModeNone, LdStMulFrm, IIC_iLoadm,
1367 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
1369 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1370 reglist:$dsts, variable_ops),
1371 IndexModeUpd, LdStMulFrm, IIC_iLoadm,
1372 "ldm${addr:submode}${p}\t$addr!, $dsts",
1373 "$addr.addr = $wb", []>;
1374 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1376 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1377 def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
1378 reglist:$srcs, variable_ops),
1379 IndexModeNone, LdStMulFrm, IIC_iStorem,
1380 "stm${addr:submode}${p}\t$addr, $srcs", "", []>;
1382 def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1383 reglist:$srcs, variable_ops),
1384 IndexModeUpd, LdStMulFrm, IIC_iStorem,
1385 "stm${addr:submode}${p}\t$addr!, $srcs",
1386 "$addr.addr = $wb", []>;
1387 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1389 //===----------------------------------------------------------------------===//
1390 // Move Instructions.
1393 let neverHasSideEffects = 1 in
1394 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1395 "mov", "\t$dst, $src", []>, UnaryDP {
1396 let Inst{11-4} = 0b00000000;
1400 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
1401 DPSoRegFrm, IIC_iMOVsr,
1402 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
1406 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1407 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
1408 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
1412 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1413 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
1415 "movw", "\t$dst, $src",
1416 [(set GPR:$dst, imm0_65535:$src)]>,
1417 Requires<[IsARM, HasV6T2]>, UnaryDP {
1422 let Constraints = "$src = $dst" in
1423 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
1425 "movt", "\t$dst, $imm",
1427 (or (and GPR:$src, 0xffff),
1428 lo16AllZero:$imm))]>, UnaryDP,
1429 Requires<[IsARM, HasV6T2]> {
1434 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1435 Requires<[IsARM, HasV6T2]>;
1437 let Uses = [CPSR] in
1438 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
1439 "mov", "\t$dst, $src, rrx",
1440 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
1442 // These aren't really mov instructions, but we have to define them this way
1443 // due to flag operands.
1445 let Defs = [CPSR] in {
1446 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1447 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1",
1448 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
1449 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
1450 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1",
1451 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
1454 //===----------------------------------------------------------------------===//
1455 // Extend Instructions.
1460 defm SXTB : AI_unary_rrot<0b01101010,
1461 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1462 defm SXTH : AI_unary_rrot<0b01101011,
1463 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1465 defm SXTAB : AI_bin_rrot<0b01101010,
1466 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1467 defm SXTAH : AI_bin_rrot<0b01101011,
1468 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1470 // For disassembly only
1471 defm SXTB16 : AI_unary_rrot_np<0b01101000, "sxtb16">;
1473 // For disassembly only
1474 defm SXTAB16 : AI_bin_rrot_np<0b01101000, "sxtab16">;
1478 let AddedComplexity = 16 in {
1479 defm UXTB : AI_unary_rrot<0b01101110,
1480 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1481 defm UXTH : AI_unary_rrot<0b01101111,
1482 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1483 defm UXTB16 : AI_unary_rrot<0b01101100,
1484 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1486 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1487 (UXTB16r_rot GPR:$Src, 24)>;
1488 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1489 (UXTB16r_rot GPR:$Src, 8)>;
1491 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1492 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1493 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1494 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1497 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1498 // For disassembly only
1499 defm UXTAB16 : AI_bin_rrot_np<0b01101100, "uxtab16">;
1502 def SBFX : I<(outs GPR:$dst),
1503 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1504 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1505 "sbfx", "\t$dst, $src, $lsb, $width", "", []>,
1506 Requires<[IsARM, HasV6T2]> {
1507 let Inst{27-21} = 0b0111101;
1508 let Inst{6-4} = 0b101;
1511 def UBFX : I<(outs GPR:$dst),
1512 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
1513 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1514 "ubfx", "\t$dst, $src, $lsb, $width", "", []>,
1515 Requires<[IsARM, HasV6T2]> {
1516 let Inst{27-21} = 0b0111111;
1517 let Inst{6-4} = 0b101;
1520 //===----------------------------------------------------------------------===//
1521 // Arithmetic Instructions.
1524 defm ADD : AsI1_bin_irs<0b0100, "add",
1525 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1526 defm SUB : AsI1_bin_irs<0b0010, "sub",
1527 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1529 // ADD and SUB with 's' bit set.
1530 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1531 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1532 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1533 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1535 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1536 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1537 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1538 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1539 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1540 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1541 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1542 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1544 // These don't define reg/reg forms, because they are handled above.
1545 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1546 IIC_iALUi, "rsb", "\t$dst, $a, $b",
1547 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1551 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1552 IIC_iALUsr, "rsb", "\t$dst, $a, $b",
1553 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
1557 // RSB with 's' bit set.
1558 let Defs = [CPSR] in {
1559 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1560 IIC_iALUi, "rsbs", "\t$dst, $a, $b",
1561 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1565 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1566 IIC_iALUsr, "rsbs", "\t$dst, $a, $b",
1567 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
1573 let Uses = [CPSR] in {
1574 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1575 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
1576 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1580 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1581 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
1582 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1588 // FIXME: Allow these to be predicated.
1589 let Defs = [CPSR], Uses = [CPSR] in {
1590 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1591 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
1592 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>,
1597 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1598 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
1599 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,
1606 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1607 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1608 (SUBri GPR:$src, so_imm_neg:$imm)>;
1610 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1611 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1612 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1613 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1615 // Note: These are implemented in C++ code, because they have to generate
1616 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1618 // (mul X, 2^n+1) -> (add (X << n), X)
1619 // (mul X, 2^n-1) -> (rsb X, (X << n))
1621 // ARM Arithmetic Instruction -- for disassembly only
1622 // GPR:$dst = GPR:$a op GPR:$b
1623 class AAI<bits<8> op27_20, bits<4> op7_4, string opc>
1624 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
1625 opc, "\t$dst, $a, $b",
1626 [/* For disassembly only; pattern left blank */]> {
1627 let Inst{27-20} = op27_20;
1628 let Inst{7-4} = op7_4;
1631 // Saturating add/subtract -- for disassembly only
1633 def QADD : AAI<0b00010000, 0b0101, "qadd">;
1634 def QADD16 : AAI<0b01100010, 0b0001, "qadd16">;
1635 def QADD8 : AAI<0b01100010, 0b1001, "qadd8">;
1636 def QASX : AAI<0b01100010, 0b0011, "qasx">;
1637 def QDADD : AAI<0b00010100, 0b0101, "qdadd">;
1638 def QDSUB : AAI<0b00010110, 0b0101, "qdsub">;
1639 def QSAX : AAI<0b01100010, 0b0101, "qsax">;
1640 def QSUB : AAI<0b00010010, 0b0101, "qsub">;
1641 def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">;
1642 def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">;
1643 def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">;
1644 def UQADD8 : AAI<0b01100110, 0b1001, "uqadd8">;
1645 def UQASX : AAI<0b01100110, 0b0011, "uqasx">;
1646 def UQSAX : AAI<0b01100110, 0b0101, "uqsax">;
1647 def UQSUB16 : AAI<0b01100110, 0b0111, "uqsub16">;
1648 def UQSUB8 : AAI<0b01100110, 0b1111, "uqsub8">;
1650 // Signed/Unsigned add/subtract -- for disassembly only
1652 def SASX : AAI<0b01100001, 0b0011, "sasx">;
1653 def SADD16 : AAI<0b01100001, 0b0001, "sadd16">;
1654 def SADD8 : AAI<0b01100001, 0b1001, "sadd8">;
1655 def SSAX : AAI<0b01100001, 0b0101, "ssax">;
1656 def SSUB16 : AAI<0b01100001, 0b0111, "ssub16">;
1657 def SSUB8 : AAI<0b01100001, 0b1111, "ssub8">;
1658 def UASX : AAI<0b01100101, 0b0011, "uasx">;
1659 def UADD16 : AAI<0b01100101, 0b0001, "uadd16">;
1660 def UADD8 : AAI<0b01100101, 0b1001, "uadd8">;
1661 def USAX : AAI<0b01100101, 0b0101, "usax">;
1662 def USUB16 : AAI<0b01100101, 0b0111, "usub16">;
1663 def USUB8 : AAI<0b01100101, 0b1111, "usub8">;
1665 // Signed/Unsigned halving add/subtract -- for disassembly only
1667 def SHASX : AAI<0b01100011, 0b0011, "shasx">;
1668 def SHADD16 : AAI<0b01100011, 0b0001, "shadd16">;
1669 def SHADD8 : AAI<0b01100011, 0b1001, "shadd8">;
1670 def SHSAX : AAI<0b01100011, 0b0101, "shsax">;
1671 def SHSUB16 : AAI<0b01100011, 0b0111, "shsub16">;
1672 def SHSUB8 : AAI<0b01100011, 0b1111, "shsub8">;
1673 def UHASX : AAI<0b01100111, 0b0011, "uhasx">;
1674 def UHADD16 : AAI<0b01100111, 0b0001, "uhadd16">;
1675 def UHADD8 : AAI<0b01100111, 0b1001, "uhadd8">;
1676 def UHSAX : AAI<0b01100111, 0b0101, "uhsax">;
1677 def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">;
1678 def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">;
1680 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1682 def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
1683 MulFrm /* for convenience */, NoItinerary, "usad8",
1684 "\t$dst, $a, $b", []>,
1685 Requires<[IsARM, HasV6]> {
1686 let Inst{27-20} = 0b01111000;
1687 let Inst{15-12} = 0b1111;
1688 let Inst{7-4} = 0b0001;
1690 def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1691 MulFrm /* for convenience */, NoItinerary, "usada8",
1692 "\t$dst, $a, $b, $acc", []>,
1693 Requires<[IsARM, HasV6]> {
1694 let Inst{27-20} = 0b01111000;
1695 let Inst{7-4} = 0b0001;
1698 // Signed/Unsigned saturate -- for disassembly only
1700 def SSATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1701 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1702 [/* For disassembly only; pattern left blank */]> {
1703 let Inst{27-21} = 0b0110101;
1704 let Inst{6-4} = 0b001;
1707 def SSATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1708 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1709 [/* For disassembly only; pattern left blank */]> {
1710 let Inst{27-21} = 0b0110101;
1711 let Inst{6-4} = 0b101;
1714 def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1715 NoItinerary, "ssat16", "\t$dst, $bit_pos, $a",
1716 [/* For disassembly only; pattern left blank */]> {
1717 let Inst{27-20} = 0b01101010;
1718 let Inst{7-4} = 0b0011;
1721 def USATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1722 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1723 [/* For disassembly only; pattern left blank */]> {
1724 let Inst{27-21} = 0b0110111;
1725 let Inst{6-4} = 0b001;
1728 def USATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1729 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1730 [/* For disassembly only; pattern left blank */]> {
1731 let Inst{27-21} = 0b0110111;
1732 let Inst{6-4} = 0b101;
1735 def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1736 NoItinerary, "usat16", "\t$dst, $bit_pos, $a",
1737 [/* For disassembly only; pattern left blank */]> {
1738 let Inst{27-20} = 0b01101110;
1739 let Inst{7-4} = 0b0011;
1742 //===----------------------------------------------------------------------===//
1743 // Bitwise Instructions.
1746 defm AND : AsI1_bin_irs<0b0000, "and",
1747 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1748 defm ORR : AsI1_bin_irs<0b1100, "orr",
1749 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1750 defm EOR : AsI1_bin_irs<0b0001, "eor",
1751 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1752 defm BIC : AsI1_bin_irs<0b1110, "bic",
1753 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1755 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1756 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1757 "bfc", "\t$dst, $imm", "$src = $dst",
1758 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1759 Requires<[IsARM, HasV6T2]> {
1760 let Inst{27-21} = 0b0111110;
1761 let Inst{6-0} = 0b0011111;
1764 // A8.6.18 BFI - Bitfield insert (Encoding A1)
1765 // Added for disassembler with the pattern field purposely left blank.
1766 def BFI : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1767 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1768 "bfi", "\t$dst, $src, $imm", "",
1769 [/* For disassembly only; pattern left blank */]>,
1770 Requires<[IsARM, HasV6T2]> {
1771 let Inst{27-21} = 0b0111110;
1772 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
1775 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1776 "mvn", "\t$dst, $src",
1777 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
1779 let Inst{11-4} = 0b00000000;
1781 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1782 IIC_iMOVsr, "mvn", "\t$dst, $src",
1783 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
1786 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1787 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1788 IIC_iMOVi, "mvn", "\t$dst, $imm",
1789 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1793 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1794 (BICri GPR:$src, so_imm_not:$imm)>;
1796 //===----------------------------------------------------------------------===//
1797 // Multiply Instructions.
1800 let isCommutable = 1 in
1801 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1802 IIC_iMUL32, "mul", "\t$dst, $a, $b",
1803 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1805 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1806 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
1807 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1809 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1810 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
1811 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1812 Requires<[IsARM, HasV6T2]>;
1814 // Extra precision multiplies with low / high results
1815 let neverHasSideEffects = 1 in {
1816 let isCommutable = 1 in {
1817 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1818 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1819 "smull", "\t$ldst, $hdst, $a, $b", []>;
1821 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1822 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1823 "umull", "\t$ldst, $hdst, $a, $b", []>;
1826 // Multiply + accumulate
1827 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1828 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1829 "smlal", "\t$ldst, $hdst, $a, $b", []>;
1831 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1832 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1833 "umlal", "\t$ldst, $hdst, $a, $b", []>;
1835 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1836 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1837 "umaal", "\t$ldst, $hdst, $a, $b", []>,
1838 Requires<[IsARM, HasV6]>;
1839 } // neverHasSideEffects
1841 // Most significant word multiply
1842 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1843 IIC_iMUL32, "smmul", "\t$dst, $a, $b",
1844 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1845 Requires<[IsARM, HasV6]> {
1846 let Inst{7-4} = 0b0001;
1847 let Inst{15-12} = 0b1111;
1850 def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1851 IIC_iMUL32, "smmulr", "\t$dst, $a, $b",
1852 [/* For disassembly only; pattern left blank */]>,
1853 Requires<[IsARM, HasV6]> {
1854 let Inst{7-4} = 0b0011; // R = 1
1855 let Inst{15-12} = 0b1111;
1858 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1859 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
1860 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1861 Requires<[IsARM, HasV6]> {
1862 let Inst{7-4} = 0b0001;
1865 def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1866 IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c",
1867 [/* For disassembly only; pattern left blank */]>,
1868 Requires<[IsARM, HasV6]> {
1869 let Inst{7-4} = 0b0011; // R = 1
1872 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1873 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
1874 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1875 Requires<[IsARM, HasV6]> {
1876 let Inst{7-4} = 0b1101;
1879 def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1880 IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c",
1881 [/* For disassembly only; pattern left blank */]>,
1882 Requires<[IsARM, HasV6]> {
1883 let Inst{7-4} = 0b1111; // R = 1
1886 multiclass AI_smul<string opc, PatFrag opnode> {
1887 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1888 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
1889 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1890 (sext_inreg GPR:$b, i16)))]>,
1891 Requires<[IsARM, HasV5TE]> {
1896 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1897 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
1898 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1899 (sra GPR:$b, (i32 16))))]>,
1900 Requires<[IsARM, HasV5TE]> {
1905 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1906 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
1907 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1908 (sext_inreg GPR:$b, i16)))]>,
1909 Requires<[IsARM, HasV5TE]> {
1914 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1915 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
1916 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1917 (sra GPR:$b, (i32 16))))]>,
1918 Requires<[IsARM, HasV5TE]> {
1923 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1924 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
1925 [(set GPR:$dst, (sra (opnode GPR:$a,
1926 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1927 Requires<[IsARM, HasV5TE]> {
1932 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1933 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
1934 [(set GPR:$dst, (sra (opnode GPR:$a,
1935 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1936 Requires<[IsARM, HasV5TE]> {
1943 multiclass AI_smla<string opc, PatFrag opnode> {
1944 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1945 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
1946 [(set GPR:$dst, (add GPR:$acc,
1947 (opnode (sext_inreg GPR:$a, i16),
1948 (sext_inreg GPR:$b, i16))))]>,
1949 Requires<[IsARM, HasV5TE]> {
1954 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1955 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
1956 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1957 (sra GPR:$b, (i32 16)))))]>,
1958 Requires<[IsARM, HasV5TE]> {
1963 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1964 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
1965 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1966 (sext_inreg GPR:$b, i16))))]>,
1967 Requires<[IsARM, HasV5TE]> {
1972 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1973 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
1974 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1975 (sra GPR:$b, (i32 16)))))]>,
1976 Requires<[IsARM, HasV5TE]> {
1981 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1982 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
1983 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1984 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1985 Requires<[IsARM, HasV5TE]> {
1990 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1991 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
1992 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1993 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1994 Requires<[IsARM, HasV5TE]> {
2000 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2001 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2003 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2004 def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2005 IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
2006 [/* For disassembly only; pattern left blank */]>,
2007 Requires<[IsARM, HasV5TE]> {
2012 def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2013 IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
2014 [/* For disassembly only; pattern left blank */]>,
2015 Requires<[IsARM, HasV5TE]> {
2020 def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2021 IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
2022 [/* For disassembly only; pattern left blank */]>,
2023 Requires<[IsARM, HasV5TE]> {
2028 def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2029 IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
2030 [/* For disassembly only; pattern left blank */]>,
2031 Requires<[IsARM, HasV5TE]> {
2036 // Helper class for AI_smld -- for disassembly only
2037 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2038 InstrItinClass itin, string opc, string asm>
2039 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2044 let Inst{21-20} = 0b00;
2045 let Inst{22} = long;
2046 let Inst{27-23} = 0b01110;
2049 multiclass AI_smld<bit sub, string opc> {
2051 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2052 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b, $acc">;
2054 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
2055 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b, $acc">;
2057 def LD : AMulDualI<1, sub, 0, (outs GPR:$ldst,GPR:$hdst), (ins GPR:$a,GPR:$b),
2058 NoItinerary, !strconcat(opc, "ld"), "\t$ldst, $hdst, $a, $b">;
2060 def LDX : AMulDualI<1, sub, 1, (outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b),
2061 NoItinerary, !strconcat(opc, "ldx"),"\t$ldst, $hdst, $a, $b">;
2065 defm SMLA : AI_smld<0, "smla">;
2066 defm SMLS : AI_smld<1, "smls">;
2068 multiclass AI_sdml<bit sub, string opc> {
2070 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2071 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b"> {
2072 let Inst{15-12} = 0b1111;
2075 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
2076 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b"> {
2077 let Inst{15-12} = 0b1111;
2082 defm SMUA : AI_sdml<0, "smua">;
2083 defm SMUS : AI_sdml<1, "smus">;
2085 //===----------------------------------------------------------------------===//
2086 // Misc. Arithmetic Instructions.
2089 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2090 "clz", "\t$dst, $src",
2091 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
2092 let Inst{7-4} = 0b0001;
2093 let Inst{11-8} = 0b1111;
2094 let Inst{19-16} = 0b1111;
2097 def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2098 "rbit", "\t$dst, $src",
2099 [(set GPR:$dst, (ARMrbit GPR:$src))]>,
2100 Requires<[IsARM, HasV6T2]> {
2101 let Inst{7-4} = 0b0011;
2102 let Inst{11-8} = 0b1111;
2103 let Inst{19-16} = 0b1111;
2106 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2107 "rev", "\t$dst, $src",
2108 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
2109 let Inst{7-4} = 0b0011;
2110 let Inst{11-8} = 0b1111;
2111 let Inst{19-16} = 0b1111;
2114 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2115 "rev16", "\t$dst, $src",
2117 (or (and (srl GPR:$src, (i32 8)), 0xFF),
2118 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
2119 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
2120 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
2121 Requires<[IsARM, HasV6]> {
2122 let Inst{7-4} = 0b1011;
2123 let Inst{11-8} = 0b1111;
2124 let Inst{19-16} = 0b1111;
2127 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
2128 "revsh", "\t$dst, $src",
2131 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
2132 (shl GPR:$src, (i32 8))), i16))]>,
2133 Requires<[IsARM, HasV6]> {
2134 let Inst{7-4} = 0b1011;
2135 let Inst{11-8} = 0b1111;
2136 let Inst{19-16} = 0b1111;
2139 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
2140 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2141 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2142 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2143 (and (shl GPR:$src2, (i32 imm:$shamt)),
2145 Requires<[IsARM, HasV6]> {
2146 let Inst{6-4} = 0b001;
2149 // Alternate cases for PKHBT where identities eliminate some nodes.
2150 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
2151 (PKHBT GPR:$src1, GPR:$src2, 0)>;
2152 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2153 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
2156 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
2157 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2158 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2159 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2160 (and (sra GPR:$src2, imm16_31:$shamt),
2161 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
2162 let Inst{6-4} = 0b101;
2165 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2166 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2167 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2168 (PKHTB GPR:$src1, GPR:$src2, 16)>;
2169 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2170 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2171 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
2173 //===----------------------------------------------------------------------===//
2174 // Comparison Instructions...
2177 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2178 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2179 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2180 // Compare-to-zero still works out, just not the relationals
2181 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2182 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2184 // Note that TST/TEQ don't set all the same flags that CMP does!
2185 defm TST : AI1_cmp_irs<0b1000, "tst",
2186 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2187 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2188 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2190 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2191 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2192 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2193 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2195 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2196 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2198 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2199 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2202 // Conditional moves
2203 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2204 // a two-value operand where a dag node expects two operands. :(
2205 let neverHasSideEffects = 1 in {
2206 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
2207 IIC_iCMOVr, "mov", "\t$dst, $true",
2208 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
2209 RegConstraint<"$false = $dst">, UnaryDP {
2210 let Inst{11-4} = 0b00000000;
2214 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
2215 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
2216 "mov", "\t$dst, $true",
2217 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
2218 RegConstraint<"$false = $dst">, UnaryDP {
2222 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
2223 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
2224 "mov", "\t$dst, $true",
2225 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
2226 RegConstraint<"$false = $dst">, UnaryDP {
2229 } // neverHasSideEffects
2231 //===----------------------------------------------------------------------===//
2232 // Atomic operations intrinsics
2235 // memory barriers protect the atomic sequences
2236 let hasSideEffects = 1 in {
2237 def Int_MemBarrierV7 : AInoP<(outs), (ins),
2238 Pseudo, NoItinerary,
2240 [(ARMMemBarrierV7)]>,
2241 Requires<[IsARM, HasV7]> {
2242 let Inst{31-4} = 0xf57ff05;
2243 // FIXME: add support for options other than a full system DMB
2244 // See DMB disassembly-only variants below.
2245 let Inst{3-0} = 0b1111;
2248 def Int_SyncBarrierV7 : AInoP<(outs), (ins),
2249 Pseudo, NoItinerary,
2251 [(ARMSyncBarrierV7)]>,
2252 Requires<[IsARM, HasV7]> {
2253 let Inst{31-4} = 0xf57ff04;
2254 // FIXME: add support for options other than a full system DSB
2255 // See DSB disassembly-only variants below.
2256 let Inst{3-0} = 0b1111;
2259 def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero),
2260 Pseudo, NoItinerary,
2261 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2262 [(ARMMemBarrierV6 GPR:$zero)]>,
2263 Requires<[IsARM, HasV6]> {
2264 // FIXME: add support for options other than a full system DMB
2265 // FIXME: add encoding
2268 def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero),
2269 Pseudo, NoItinerary,
2270 "mcr", "\tp15, 0, $zero, c7, c10, 4",
2271 [(ARMSyncBarrierV6 GPR:$zero)]>,
2272 Requires<[IsARM, HasV6]> {
2273 // FIXME: add support for options other than a full system DSB
2274 // FIXME: add encoding
2278 // Helper class for multiclass MemB -- for disassembly only
2279 class AMBI<string opc, string asm>
2280 : AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm,
2281 [/* For disassembly only; pattern left blank */]>,
2282 Requires<[IsARM, HasV7]> {
2283 let Inst{31-20} = 0xf57;
2286 multiclass MemB<bits<4> op7_4, string opc> {
2288 def st : AMBI<opc, "\tst"> {
2289 let Inst{7-4} = op7_4;
2290 let Inst{3-0} = 0b1110;
2293 def ish : AMBI<opc, "\tish"> {
2294 let Inst{7-4} = op7_4;
2295 let Inst{3-0} = 0b1011;
2298 def ishst : AMBI<opc, "\tishst"> {
2299 let Inst{7-4} = op7_4;
2300 let Inst{3-0} = 0b1010;
2303 def nsh : AMBI<opc, "\tnsh"> {
2304 let Inst{7-4} = op7_4;
2305 let Inst{3-0} = 0b0111;
2308 def nshst : AMBI<opc, "\tnshst"> {
2309 let Inst{7-4} = op7_4;
2310 let Inst{3-0} = 0b0110;
2313 def osh : AMBI<opc, "\tosh"> {
2314 let Inst{7-4} = op7_4;
2315 let Inst{3-0} = 0b0011;
2318 def oshst : AMBI<opc, "\toshst"> {
2319 let Inst{7-4} = op7_4;
2320 let Inst{3-0} = 0b0010;
2324 // These DMB variants are for disassembly only.
2325 defm DMB : MemB<0b0101, "dmb">;
2327 // These DSB variants are for disassembly only.
2328 defm DSB : MemB<0b0100, "dsb">;
2330 // ISB has only full system option -- for disassembly only
2331 def ISBsy : AMBI<"isb", ""> {
2332 let Inst{7-4} = 0b0110;
2333 let Inst{3-0} = 0b1111;
2336 let usesCustomInserter = 1 in {
2337 let Uses = [CPSR] in {
2338 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2339 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2340 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
2341 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2342 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2343 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2344 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
2345 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2346 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2348 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
2349 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2350 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2351 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2352 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
2353 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2354 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2355 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2356 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
2357 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2358 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2359 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2360 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
2361 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2362 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2363 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2364 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
2365 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2366 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2367 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2368 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
2369 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2370 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2371 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2372 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
2373 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2374 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2375 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2376 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
2377 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2378 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2379 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2380 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
2381 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2382 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2383 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2384 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
2385 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2386 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2387 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2388 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
2389 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2390 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2391 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2392 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
2393 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2394 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2395 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2396 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
2397 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2398 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2399 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2400 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
2401 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2402 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2403 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2404 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
2405 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2406 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2407 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
2408 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
2409 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2411 def ATOMIC_SWAP_I8 : PseudoInst<
2412 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2413 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
2414 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2415 def ATOMIC_SWAP_I16 : PseudoInst<
2416 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2417 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
2418 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2419 def ATOMIC_SWAP_I32 : PseudoInst<
2420 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
2421 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
2422 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
2424 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
2425 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2426 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
2427 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
2428 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
2429 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2430 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
2431 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
2432 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
2433 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
2434 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
2435 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
2439 let mayLoad = 1 in {
2440 def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2441 "ldrexb", "\t$dest, [$ptr]",
2443 def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2444 "ldrexh", "\t$dest, [$ptr]",
2446 def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary,
2447 "ldrex", "\t$dest, [$ptr]",
2449 def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
2451 "ldrexd", "\t$dest, $dest2, [$ptr]",
2455 let mayStore = 1, Constraints = "@earlyclobber $success" in {
2456 def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2458 "strexb", "\t$success, $src, [$ptr]",
2460 def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2462 "strexh", "\t$success, $src, [$ptr]",
2464 def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
2466 "strex", "\t$success, $src, [$ptr]",
2468 def STREXD : AIstrex<0b01, (outs GPR:$success),
2469 (ins GPR:$src, GPR:$src2, GPR:$ptr),
2471 "strexd", "\t$success, $src, $src2, [$ptr]",
2475 // Clear-Exclusive is for disassembly only.
2476 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
2477 [/* For disassembly only; pattern left blank */]>,
2478 Requires<[IsARM, HasV7]> {
2479 let Inst{31-20} = 0xf57;
2480 let Inst{7-4} = 0b0001;
2483 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
2484 let mayLoad = 1 in {
2485 def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2486 "swp", "\t$dst, $src, [$ptr]",
2487 [/* For disassembly only; pattern left blank */]> {
2488 let Inst{27-23} = 0b00010;
2489 let Inst{22} = 0; // B = 0
2490 let Inst{21-20} = 0b00;
2491 let Inst{7-4} = 0b1001;
2494 def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary,
2495 "swpb", "\t$dst, $src, [$ptr]",
2496 [/* For disassembly only; pattern left blank */]> {
2497 let Inst{27-23} = 0b00010;
2498 let Inst{22} = 1; // B = 1
2499 let Inst{21-20} = 0b00;
2500 let Inst{7-4} = 0b1001;
2504 //===----------------------------------------------------------------------===//
2508 // __aeabi_read_tp preserves the registers r1-r3.
2510 Defs = [R0, R12, LR, CPSR] in {
2511 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
2512 "bl\t__aeabi_read_tp",
2513 [(set R0, ARMthread_pointer)]>;
2516 //===----------------------------------------------------------------------===//
2517 // SJLJ Exception handling intrinsics
2518 // eh_sjlj_setjmp() is an instruction sequence to store the return
2519 // address and save #0 in R0 for the non-longjmp case.
2520 // Since by its nature we may be coming from some other function to get
2521 // here, and we're using the stack frame for the containing function to
2522 // save/restore registers, we can't keep anything live in regs across
2523 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2524 // when we get here from a longjmp(). We force everthing out of registers
2525 // except for our own input by listing the relevant registers in Defs. By
2526 // doing so, we also cause the prologue/epilogue code to actively preserve
2527 // all of the callee-saved resgisters, which is exactly what we want.
2528 // A constant value is passed in $val, and we use the location as a scratch.
2530 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
2531 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
2532 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2533 D31 ], hasSideEffects = 1, isBarrier = 1 in {
2534 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
2535 AddrModeNone, SizeSpecial, IndexModeNone,
2536 Pseudo, NoItinerary,
2537 "add\t$val, pc, #8\t${:comment} eh_setjmp begin\n\t"
2538 "str\t$val, [$src, #+4]\n\t"
2540 "add\tpc, pc, #0\n\t"
2541 "mov\tr0, #1 ${:comment} eh_setjmp end", "",
2542 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
2543 Requires<[IsARM, HasVFP2]>;
2547 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
2548 hasSideEffects = 1, isBarrier = 1 in {
2549 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
2550 AddrModeNone, SizeSpecial, IndexModeNone,
2551 Pseudo, NoItinerary,
2552 "add\t$val, pc, #8\n ${:comment} eh_setjmp begin\n\t"
2553 "str\t$val, [$src, #+4]\n\t"
2555 "add\tpc, pc, #0\n\t"
2556 "mov\tr0, #1 ${:comment} eh_setjmp end", "",
2557 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
2558 Requires<[IsARM, NoVFP]>;
2561 // FIXME: Non-Darwin version(s)
2562 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
2563 Defs = [ R7, LR, SP ] in {
2564 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
2565 AddrModeNone, SizeSpecial, IndexModeNone,
2566 Pseudo, NoItinerary,
2567 "ldr\tsp, [$src, #8]\n\t"
2568 "ldr\t$scratch, [$src, #4]\n\t"
2569 "ldr\tr7, [$src]\n\t"
2571 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
2572 Requires<[IsARM, IsDarwin]>;
2575 //===----------------------------------------------------------------------===//
2576 // Non-Instruction Patterns
2579 // Large immediate handling.
2581 // Two piece so_imms.
2582 let isReMaterializable = 1 in
2583 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
2585 "mov", "\t$dst, $src",
2586 [(set GPR:$dst, so_imm2part:$src)]>,
2587 Requires<[IsARM, NoV6T2]>;
2589 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
2590 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2591 (so_imm2part_2 imm:$RHS))>;
2592 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
2593 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2594 (so_imm2part_2 imm:$RHS))>;
2595 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
2596 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
2597 (so_imm2part_2 imm:$RHS))>;
2598 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
2599 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
2600 (so_neg_imm2part_2 imm:$RHS))>;
2602 // 32-bit immediate using movw + movt.
2603 // This is a single pseudo instruction, the benefit is that it can be remat'd
2604 // as a single unit instead of having to handle reg inputs.
2605 // FIXME: Remove this when we can do generalized remat.
2606 let isReMaterializable = 1 in
2607 def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
2608 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
2609 [(set GPR:$dst, (i32 imm:$src))]>,
2610 Requires<[IsARM, HasV6T2]>;
2612 // ConstantPool, GlobalAddress, and JumpTable
2613 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
2614 Requires<[IsARM, DontUseMovt]>;
2615 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
2616 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
2617 Requires<[IsARM, UseMovt]>;
2618 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
2619 (LEApcrelJT tjumptable:$dst, imm:$id)>;
2621 // TODO: add,sub,and, 3-instr forms?
2625 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
2626 Requires<[IsARM, IsNotDarwin]>;
2627 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
2628 Requires<[IsARM, IsDarwin]>;
2630 // zextload i1 -> zextload i8
2631 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2633 // extload -> zextload
2634 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2635 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
2636 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
2638 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
2639 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
2642 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2643 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2644 (SMULBB GPR:$a, GPR:$b)>;
2645 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
2646 (SMULBB GPR:$a, GPR:$b)>;
2647 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2648 (sra GPR:$b, (i32 16))),
2649 (SMULBT GPR:$a, GPR:$b)>;
2650 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
2651 (SMULBT GPR:$a, GPR:$b)>;
2652 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
2653 (sra (shl GPR:$b, (i32 16)), (i32 16))),
2654 (SMULTB GPR:$a, GPR:$b)>;
2655 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
2656 (SMULTB GPR:$a, GPR:$b)>;
2657 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2659 (SMULWB GPR:$a, GPR:$b)>;
2660 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
2661 (SMULWB GPR:$a, GPR:$b)>;
2663 def : ARMV5TEPat<(add GPR:$acc,
2664 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2665 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2666 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2667 def : ARMV5TEPat<(add GPR:$acc,
2668 (mul sext_16_node:$a, sext_16_node:$b)),
2669 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2670 def : ARMV5TEPat<(add GPR:$acc,
2671 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
2672 (sra GPR:$b, (i32 16)))),
2673 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2674 def : ARMV5TEPat<(add GPR:$acc,
2675 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
2676 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2677 def : ARMV5TEPat<(add GPR:$acc,
2678 (mul (sra GPR:$a, (i32 16)),
2679 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
2680 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2681 def : ARMV5TEPat<(add GPR:$acc,
2682 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
2683 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2684 def : ARMV5TEPat<(add GPR:$acc,
2685 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
2687 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2688 def : ARMV5TEPat<(add GPR:$acc,
2689 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
2690 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2692 //===----------------------------------------------------------------------===//
2696 include "ARMInstrThumb.td"
2698 //===----------------------------------------------------------------------===//
2702 include "ARMInstrThumb2.td"
2704 //===----------------------------------------------------------------------===//
2705 // Floating Point Support
2708 include "ARMInstrVFP.td"
2710 //===----------------------------------------------------------------------===//
2711 // Advanced SIMD (NEON) Support
2714 include "ARMInstrNEON.td"
2716 //===----------------------------------------------------------------------===//
2717 // Coprocessor Instructions. For disassembly only.
2720 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2721 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2722 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2723 [/* For disassembly only; pattern left blank */]> {
2727 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2728 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2729 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
2730 [/* For disassembly only; pattern left blank */]> {
2731 let Inst{31-28} = 0b1111;
2735 class ACI<dag oops, dag iops, string opc, string asm>
2736 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
2737 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
2738 let Inst{27-25} = 0b110;
2741 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
2743 def _OFFSET : ACI<(outs),
2744 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2745 opc, "\tp$cop, cr$CRd, $addr"> {
2746 let Inst{31-28} = op31_28;
2747 let Inst{24} = 1; // P = 1
2748 let Inst{21} = 0; // W = 0
2749 let Inst{22} = 0; // D = 0
2750 let Inst{20} = load;
2753 def _PRE : ACI<(outs),
2754 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2755 opc, "\tp$cop, cr$CRd, $addr!"> {
2756 let Inst{31-28} = op31_28;
2757 let Inst{24} = 1; // P = 1
2758 let Inst{21} = 1; // W = 1
2759 let Inst{22} = 0; // D = 0
2760 let Inst{20} = load;
2763 def _POST : ACI<(outs),
2764 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2765 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
2766 let Inst{31-28} = op31_28;
2767 let Inst{24} = 0; // P = 0
2768 let Inst{21} = 1; // W = 1
2769 let Inst{22} = 0; // D = 0
2770 let Inst{20} = load;
2773 def _OPTION : ACI<(outs),
2774 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
2775 opc, "\tp$cop, cr$CRd, [$base], $option"> {
2776 let Inst{31-28} = op31_28;
2777 let Inst{24} = 0; // P = 0
2778 let Inst{23} = 1; // U = 1
2779 let Inst{21} = 0; // W = 0
2780 let Inst{22} = 0; // D = 0
2781 let Inst{20} = load;
2784 def L_OFFSET : ACI<(outs),
2785 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2786 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
2787 let Inst{31-28} = op31_28;
2788 let Inst{24} = 1; // P = 1
2789 let Inst{21} = 0; // W = 0
2790 let Inst{22} = 1; // D = 1
2791 let Inst{20} = load;
2794 def L_PRE : ACI<(outs),
2795 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
2796 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
2797 let Inst{31-28} = op31_28;
2798 let Inst{24} = 1; // P = 1
2799 let Inst{21} = 1; // W = 1
2800 let Inst{22} = 1; // D = 1
2801 let Inst{20} = load;
2804 def L_POST : ACI<(outs),
2805 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
2806 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
2807 let Inst{31-28} = op31_28;
2808 let Inst{24} = 0; // P = 0
2809 let Inst{21} = 1; // W = 1
2810 let Inst{22} = 1; // D = 1
2811 let Inst{20} = load;
2814 def L_OPTION : ACI<(outs),
2815 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
2816 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
2817 let Inst{31-28} = op31_28;
2818 let Inst{24} = 0; // P = 0
2819 let Inst{23} = 1; // U = 1
2820 let Inst{21} = 0; // W = 0
2821 let Inst{22} = 1; // D = 1
2822 let Inst{20} = load;
2826 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
2827 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
2828 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
2829 defm STC2 : LdStCop<0b1111, 0, "stc2">;
2831 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2832 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2833 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2834 [/* For disassembly only; pattern left blank */]> {
2839 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2840 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2841 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2842 [/* For disassembly only; pattern left blank */]> {
2843 let Inst{31-28} = 0b1111;
2848 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2849 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2850 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2851 [/* For disassembly only; pattern left blank */]> {
2856 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
2857 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
2858 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
2859 [/* For disassembly only; pattern left blank */]> {
2860 let Inst{31-28} = 0b1111;
2865 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2866 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2867 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2868 [/* For disassembly only; pattern left blank */]> {
2869 let Inst{23-20} = 0b0100;
2872 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2873 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2874 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2875 [/* For disassembly only; pattern left blank */]> {
2876 let Inst{31-28} = 0b1111;
2877 let Inst{23-20} = 0b0100;
2880 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2881 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2882 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2883 [/* For disassembly only; pattern left blank */]> {
2884 let Inst{23-20} = 0b0101;
2887 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
2888 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
2889 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
2890 [/* For disassembly only; pattern left blank */]> {
2891 let Inst{31-28} = 0b1111;
2892 let Inst{23-20} = 0b0101;
2895 //===----------------------------------------------------------------------===//
2896 // Move between special register and ARM core register -- for disassembly only
2899 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
2900 [/* For disassembly only; pattern left blank */]> {
2901 let Inst{23-20} = 0b0000;
2902 let Inst{7-4} = 0b0000;
2905 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
2906 [/* For disassembly only; pattern left blank */]> {
2907 let Inst{23-20} = 0b0100;
2908 let Inst{7-4} = 0b0000;
2911 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
2912 "msr", "\tcpsr$mask, $src",
2913 [/* For disassembly only; pattern left blank */]> {
2914 let Inst{23-20} = 0b0010;
2915 let Inst{7-4} = 0b0000;
2918 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
2919 "msr", "\tcpsr$mask, $a",
2920 [/* For disassembly only; pattern left blank */]> {
2921 let Inst{23-20} = 0b0010;
2922 let Inst{7-4} = 0b0000;
2925 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
2926 "msr", "\tspsr$mask, $src",
2927 [/* For disassembly only; pattern left blank */]> {
2928 let Inst{23-20} = 0b0110;
2929 let Inst{7-4} = 0b0000;
2932 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
2933 "msr", "\tspsr$mask, $a",
2934 [/* For disassembly only; pattern left blank */]> {
2935 let Inst{23-20} = 0b0110;
2936 let Inst{7-4} = 0b0000;