1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
62 def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
76 def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
77 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
80 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
83 SDTCisInt<0>, SDTCisVT<1, i32>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
86 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
93 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
94 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
96 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
97 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
100 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
101 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
102 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
104 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
106 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
107 [SDNPHasChain, SDNPSideEffect,
108 SDNPOptInGlue, SDNPOutGlue]>;
109 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
112 SDNPMayStore, SDNPMayLoad]>;
114 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
124 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
128 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
131 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
134 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
136 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
139 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
142 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
145 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
148 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
149 [SDNPOutGlue, SDNPCommutative]>;
151 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
153 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
154 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
155 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
157 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
159 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
160 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
161 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
163 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
164 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
165 SDT_ARMEH_SJLJ_Setjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
168 SDT_ARMEH_SJLJ_Longjmp,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH",
171 SDT_ARMEH_SJLJ_SetupDispatch,
172 [SDNPHasChain, SDNPSideEffect]>;
174 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
175 [SDNPHasChain, SDNPSideEffect]>;
176 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
177 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
179 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
184 def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY,
185 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
186 SDNPMayStore, SDNPMayLoad]>;
188 //===----------------------------------------------------------------------===//
189 // ARM Instruction Predicate Definitions.
191 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
192 AssemblerPredicate<"HasV4TOps", "armv4t">;
193 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
194 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
195 AssemblerPredicate<"HasV5TOps", "armv5t">;
196 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
197 AssemblerPredicate<"HasV5TEOps", "armv5te">;
198 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
199 AssemblerPredicate<"HasV6Ops", "armv6">;
200 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
201 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
202 AssemblerPredicate<"HasV6MOps",
203 "armv6m or armv6t2">;
204 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
205 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
206 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
207 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
208 AssemblerPredicate<"HasV6KOps", "armv6k">;
209 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
210 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
211 AssemblerPredicate<"HasV7Ops", "armv7">;
212 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
213 AssemblerPredicate<"HasV8Ops", "armv8">;
214 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
215 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
216 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
217 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
218 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
219 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
220 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
221 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
222 AssemblerPredicate<"FeatureVFP2", "VFP2">;
223 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
224 AssemblerPredicate<"FeatureVFP3", "VFP3">;
225 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
226 AssemblerPredicate<"FeatureVFP4", "VFP4">;
227 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
228 AssemblerPredicate<"!FeatureVFPOnlySP",
229 "double precision VFP">;
230 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
231 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
232 def HasNEON : Predicate<"Subtarget->hasNEON()">,
233 AssemblerPredicate<"FeatureNEON", "NEON">;
234 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
235 AssemblerPredicate<"FeatureCrypto", "crypto">;
236 def HasCRC : Predicate<"Subtarget->hasCRC()">,
237 AssemblerPredicate<"FeatureCRC", "crc">;
238 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
239 AssemblerPredicate<"FeatureFP16","half-float conversions">;
240 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
241 AssemblerPredicate<"FeatureFullFP16","full half-float">;
242 def HasDivide : Predicate<"Subtarget->hasDivide()">,
243 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
244 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
245 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
246 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
247 AssemblerPredicate<"FeatureT2XtPk",
249 def HasDSP : Predicate<"Subtarget->hasDSP()">,
250 AssemblerPredicate<"FeatureDSP", "dsp">;
251 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
252 AssemblerPredicate<"FeatureDB",
254 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
255 AssemblerPredicate<"FeatureMP",
257 def HasVirtualization: Predicate<"false">,
258 AssemblerPredicate<"FeatureVirtualization",
259 "virtualization-extensions">;
260 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
261 AssemblerPredicate<"FeatureTrustZone",
263 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
264 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
265 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
266 def IsThumb : Predicate<"Subtarget->isThumb()">,
267 AssemblerPredicate<"ModeThumb", "thumb">;
268 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
269 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
270 AssemblerPredicate<"ModeThumb,FeatureThumb2",
272 def IsMClass : Predicate<"Subtarget->isMClass()">,
273 AssemblerPredicate<"FeatureMClass", "armv*m">;
274 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
275 AssemblerPredicate<"!FeatureMClass",
277 def IsARM : Predicate<"!Subtarget->isThumb()">,
278 AssemblerPredicate<"!ModeThumb", "arm-mode">;
279 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
280 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
281 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
282 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
283 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
284 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
286 // FIXME: Eventually this will be just "hasV6T2Ops".
287 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
288 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
289 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
290 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
292 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
293 // But only select them if more precision in FP computation is allowed.
294 // Do not use them for Darwin platforms.
295 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
296 " FPOpFusion::Fast && "
297 " Subtarget->hasVFP4()) && "
298 "!Subtarget->isTargetDarwin()">;
299 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
300 " FPOpFusion::Fast &&"
301 " Subtarget->hasVFP4()) || "
302 "Subtarget->isTargetDarwin()">;
304 // VGETLNi32 is microcoded on Swift - prefer VMOV.
305 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
306 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
308 // VDUP.32 is microcoded on Swift - prefer VMOV.
309 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
310 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
312 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
313 // this allows more effective execution domain optimization. See
314 // setExecutionDomain().
315 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
316 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
318 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
319 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
321 //===----------------------------------------------------------------------===//
322 // ARM Flag Definitions.
324 class RegConstraint<string C> {
325 string Constraints = C;
328 //===----------------------------------------------------------------------===//
329 // ARM specific transformation functions and pattern fragments.
332 // imm_neg_XFORM - Return the negation of an i32 immediate value.
333 def imm_neg_XFORM : SDNodeXForm<imm, [{
334 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
337 // imm_not_XFORM - Return the complement of a i32 immediate value.
338 def imm_not_XFORM : SDNodeXForm<imm, [{
339 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
342 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
343 def imm16_31 : ImmLeaf<i32, [{
344 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
347 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
348 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
349 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
352 /// Split a 32-bit immediate into two 16 bit parts.
353 def hi16 : SDNodeXForm<imm, [{
354 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
358 def lo16AllZero : PatLeaf<(i32 imm), [{
359 // Returns true if all low 16-bits are 0.
360 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
363 class BinOpWithFlagFrag<dag res> :
364 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
365 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
366 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
368 // An 'and' node with a single use.
369 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
370 return N->hasOneUse();
373 // An 'xor' node with a single use.
374 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
375 return N->hasOneUse();
378 // An 'fmul' node with a single use.
379 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
380 return N->hasOneUse();
383 // An 'fadd' node which checks for single non-hazardous use.
384 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
385 return hasNoVMLxHazardUse(N);
388 // An 'fsub' node which checks for single non-hazardous use.
389 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
390 return hasNoVMLxHazardUse(N);
393 //===----------------------------------------------------------------------===//
394 // Operand Definitions.
397 // Immediate operands with a shared generic asm render method.
398 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
400 // Operands that are part of a memory addressing mode.
401 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
404 // FIXME: rename brtarget to t2_brtarget
405 def brtarget : Operand<OtherVT> {
406 let EncoderMethod = "getBranchTargetOpValue";
407 let OperandType = "OPERAND_PCREL";
408 let DecoderMethod = "DecodeT2BROperand";
411 // FIXME: get rid of this one?
412 def uncondbrtarget : Operand<OtherVT> {
413 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // Branch target for ARM. Handles conditional/unconditional
418 def br_target : Operand<OtherVT> {
419 let EncoderMethod = "getARMBranchTargetOpValue";
420 let OperandType = "OPERAND_PCREL";
424 // FIXME: rename bltarget to t2_bl_target?
425 def bltarget : Operand<i32> {
426 // Encoded the same as branch targets.
427 let EncoderMethod = "getBranchTargetOpValue";
428 let OperandType = "OPERAND_PCREL";
431 // Call target for ARM. Handles conditional/unconditional
432 // FIXME: rename bl_target to t2_bltarget?
433 def bl_target : Operand<i32> {
434 let EncoderMethod = "getARMBLTargetOpValue";
435 let OperandType = "OPERAND_PCREL";
438 def blx_target : Operand<i32> {
439 let EncoderMethod = "getARMBLXTargetOpValue";
440 let OperandType = "OPERAND_PCREL";
443 // A list of registers separated by comma. Used by load/store multiple.
444 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
445 def reglist : Operand<i32> {
446 let EncoderMethod = "getRegisterListOpValue";
447 let ParserMatchClass = RegListAsmOperand;
448 let PrintMethod = "printRegisterList";
449 let DecoderMethod = "DecodeRegListOperand";
452 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
454 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
455 def dpr_reglist : Operand<i32> {
456 let EncoderMethod = "getRegisterListOpValue";
457 let ParserMatchClass = DPRRegListAsmOperand;
458 let PrintMethod = "printRegisterList";
459 let DecoderMethod = "DecodeDPRRegListOperand";
462 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
463 def spr_reglist : Operand<i32> {
464 let EncoderMethod = "getRegisterListOpValue";
465 let ParserMatchClass = SPRRegListAsmOperand;
466 let PrintMethod = "printRegisterList";
467 let DecoderMethod = "DecodeSPRRegListOperand";
470 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
471 def cpinst_operand : Operand<i32> {
472 let PrintMethod = "printCPInstOperand";
476 def pclabel : Operand<i32> {
477 let PrintMethod = "printPCLabel";
480 // ADR instruction labels.
481 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
482 def adrlabel : Operand<i32> {
483 let EncoderMethod = "getAdrLabelOpValue";
484 let ParserMatchClass = AdrLabelAsmOperand;
485 let PrintMethod = "printAdrLabelOperand<0>";
488 def neon_vcvt_imm32 : Operand<i32> {
489 let EncoderMethod = "getNEONVcvtImm32OpValue";
490 let DecoderMethod = "DecodeVCVTImmOperand";
493 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
494 def rot_imm_XFORM: SDNodeXForm<imm, [{
495 switch (N->getZExtValue()){
496 default: llvm_unreachable(nullptr);
497 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
498 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
499 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
500 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
503 def RotImmAsmOperand : AsmOperandClass {
505 let ParserMethod = "parseRotImm";
507 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
508 int32_t v = N->getZExtValue();
509 return v == 8 || v == 16 || v == 24; }],
511 let PrintMethod = "printRotImmOperand";
512 let ParserMatchClass = RotImmAsmOperand;
515 // shift_imm: An integer that encodes a shift amount and the type of shift
516 // (asr or lsl). The 6-bit immediate encodes as:
519 // {4-0} imm5 shift amount.
520 // asr #32 encoded as imm5 == 0.
521 def ShifterImmAsmOperand : AsmOperandClass {
522 let Name = "ShifterImm";
523 let ParserMethod = "parseShifterImm";
525 def shift_imm : Operand<i32> {
526 let PrintMethod = "printShiftImmOperand";
527 let ParserMatchClass = ShifterImmAsmOperand;
530 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
531 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
532 def so_reg_reg : Operand<i32>, // reg reg imm
533 ComplexPattern<i32, 3, "SelectRegShifterOperand",
534 [shl, srl, sra, rotr]> {
535 let EncoderMethod = "getSORegRegOpValue";
536 let PrintMethod = "printSORegRegOperand";
537 let DecoderMethod = "DecodeSORegRegOperand";
538 let ParserMatchClass = ShiftedRegAsmOperand;
539 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
542 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
543 def so_reg_imm : Operand<i32>, // reg imm
544 ComplexPattern<i32, 2, "SelectImmShifterOperand",
545 [shl, srl, sra, rotr]> {
546 let EncoderMethod = "getSORegImmOpValue";
547 let PrintMethod = "printSORegImmOperand";
548 let DecoderMethod = "DecodeSORegImmOperand";
549 let ParserMatchClass = ShiftedImmAsmOperand;
550 let MIOperandInfo = (ops GPR, i32imm);
553 // FIXME: Does this need to be distinct from so_reg?
554 def shift_so_reg_reg : Operand<i32>, // reg reg imm
555 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
556 [shl,srl,sra,rotr]> {
557 let EncoderMethod = "getSORegRegOpValue";
558 let PrintMethod = "printSORegRegOperand";
559 let DecoderMethod = "DecodeSORegRegOperand";
560 let ParserMatchClass = ShiftedRegAsmOperand;
561 let MIOperandInfo = (ops GPR, GPR, i32imm);
564 // FIXME: Does this need to be distinct from so_reg?
565 def shift_so_reg_imm : Operand<i32>, // reg reg imm
566 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
567 [shl,srl,sra,rotr]> {
568 let EncoderMethod = "getSORegImmOpValue";
569 let PrintMethod = "printSORegImmOperand";
570 let DecoderMethod = "DecodeSORegImmOperand";
571 let ParserMatchClass = ShiftedImmAsmOperand;
572 let MIOperandInfo = (ops GPR, i32imm);
575 // mod_imm: match a 32-bit immediate operand, which can be encoded into
576 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
577 // - "Modified Immediate Constants"). Within the MC layer we keep this
578 // immediate in its encoded form.
579 def ModImmAsmOperand: AsmOperandClass {
581 let ParserMethod = "parseModImm";
583 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
584 return ARM_AM::getSOImmVal(Imm) != -1;
586 let EncoderMethod = "getModImmOpValue";
587 let PrintMethod = "printModImmOperand";
588 let ParserMatchClass = ModImmAsmOperand;
591 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
592 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
593 // The actual parsing, encoding, decoding are handled by the destination
594 // instructions, which use mod_imm.
596 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
597 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
598 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
600 let ParserMatchClass = ModImmNotAsmOperand;
603 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
604 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
605 unsigned Value = -(unsigned)N->getZExtValue();
606 return Value && ARM_AM::getSOImmVal(Value) != -1;
608 let ParserMatchClass = ModImmNegAsmOperand;
611 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
612 def arm_i32imm : PatLeaf<(imm), [{
613 if (Subtarget->useMovt(*MF))
615 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
618 /// imm0_1 predicate - Immediate in the range [0,1].
619 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
620 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
622 /// imm0_3 predicate - Immediate in the range [0,3].
623 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
624 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
626 /// imm0_7 predicate - Immediate in the range [0,7].
627 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
628 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
629 return Imm >= 0 && Imm < 8;
631 let ParserMatchClass = Imm0_7AsmOperand;
634 /// imm8 predicate - Immediate is exactly 8.
635 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
636 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
637 let ParserMatchClass = Imm8AsmOperand;
640 /// imm16 predicate - Immediate is exactly 16.
641 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
642 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
643 let ParserMatchClass = Imm16AsmOperand;
646 /// imm32 predicate - Immediate is exactly 32.
647 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
648 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
649 let ParserMatchClass = Imm32AsmOperand;
652 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
654 /// imm1_7 predicate - Immediate in the range [1,7].
655 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
656 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
657 let ParserMatchClass = Imm1_7AsmOperand;
660 /// imm1_15 predicate - Immediate in the range [1,15].
661 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
662 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
663 let ParserMatchClass = Imm1_15AsmOperand;
666 /// imm1_31 predicate - Immediate in the range [1,31].
667 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
668 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
669 let ParserMatchClass = Imm1_31AsmOperand;
672 /// imm0_15 predicate - Immediate in the range [0,15].
673 def Imm0_15AsmOperand: ImmAsmOperand {
674 let Name = "Imm0_15";
675 let DiagnosticType = "ImmRange0_15";
677 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
678 return Imm >= 0 && Imm < 16;
680 let ParserMatchClass = Imm0_15AsmOperand;
683 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
684 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
685 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
686 return Imm >= 0 && Imm < 32;
688 let ParserMatchClass = Imm0_31AsmOperand;
691 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
692 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
693 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
694 return Imm >= 0 && Imm < 32;
696 let ParserMatchClass = Imm0_32AsmOperand;
699 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
700 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
701 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
702 return Imm >= 0 && Imm < 64;
704 let ParserMatchClass = Imm0_63AsmOperand;
707 /// imm0_239 predicate - Immediate in the range [0,239].
708 def Imm0_239AsmOperand : ImmAsmOperand {
709 let Name = "Imm0_239";
710 let DiagnosticType = "ImmRange0_239";
712 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
713 let ParserMatchClass = Imm0_239AsmOperand;
716 /// imm0_255 predicate - Immediate in the range [0,255].
717 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
718 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
719 let ParserMatchClass = Imm0_255AsmOperand;
722 /// imm0_65535 - An immediate is in the range [0.65535].
723 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
724 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
725 return Imm >= 0 && Imm < 65536;
727 let ParserMatchClass = Imm0_65535AsmOperand;
730 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
731 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
732 return -Imm >= 0 && -Imm < 65536;
735 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
736 // a relocatable expression.
738 // FIXME: This really needs a Thumb version separate from the ARM version.
739 // While the range is the same, and can thus use the same match class,
740 // the encoding is different so it should have a different encoder method.
741 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
742 def imm0_65535_expr : Operand<i32> {
743 let EncoderMethod = "getHiLo16ImmOpValue";
744 let ParserMatchClass = Imm0_65535ExprAsmOperand;
747 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
748 def imm256_65535_expr : Operand<i32> {
749 let ParserMatchClass = Imm256_65535ExprAsmOperand;
752 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
753 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
754 def imm24b : Operand<i32>, ImmLeaf<i32, [{
755 return Imm >= 0 && Imm <= 0xffffff;
757 let ParserMatchClass = Imm24bitAsmOperand;
761 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
763 def BitfieldAsmOperand : AsmOperandClass {
764 let Name = "Bitfield";
765 let ParserMethod = "parseBitfield";
768 def bf_inv_mask_imm : Operand<i32>,
770 return ARM::isBitFieldInvertedMask(N->getZExtValue());
772 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
773 let PrintMethod = "printBitfieldInvMaskImmOperand";
774 let DecoderMethod = "DecodeBitfieldMaskOperand";
775 let ParserMatchClass = BitfieldAsmOperand;
778 def imm1_32_XFORM: SDNodeXForm<imm, [{
779 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
782 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
783 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
784 uint64_t Imm = N->getZExtValue();
785 return Imm > 0 && Imm <= 32;
788 let PrintMethod = "printImmPlusOneOperand";
789 let ParserMatchClass = Imm1_32AsmOperand;
792 def imm1_16_XFORM: SDNodeXForm<imm, [{
793 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
796 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
797 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
799 let PrintMethod = "printImmPlusOneOperand";
800 let ParserMatchClass = Imm1_16AsmOperand;
803 // Define ARM specific addressing modes.
804 // addrmode_imm12 := reg +/- imm12
806 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
807 class AddrMode_Imm12 : MemOperand,
808 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
809 // 12-bit immediate operand. Note that instructions using this encode
810 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
811 // immediate values are as normal.
813 let EncoderMethod = "getAddrModeImm12OpValue";
814 let DecoderMethod = "DecodeAddrModeImm12Operand";
815 let ParserMatchClass = MemImm12OffsetAsmOperand;
816 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
819 def addrmode_imm12 : AddrMode_Imm12 {
820 let PrintMethod = "printAddrModeImm12Operand<false>";
823 def addrmode_imm12_pre : AddrMode_Imm12 {
824 let PrintMethod = "printAddrModeImm12Operand<true>";
827 // ldst_so_reg := reg +/- reg shop imm
829 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
830 def ldst_so_reg : MemOperand,
831 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
832 let EncoderMethod = "getLdStSORegOpValue";
833 // FIXME: Simplify the printer
834 let PrintMethod = "printAddrMode2Operand";
835 let DecoderMethod = "DecodeSORegMemOperand";
836 let ParserMatchClass = MemRegOffsetAsmOperand;
837 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
840 // postidx_imm8 := +/- [0,255]
843 // {8} 1 is imm8 is non-negative. 0 otherwise.
844 // {7-0} [0,255] imm8 value.
845 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
846 def postidx_imm8 : MemOperand {
847 let PrintMethod = "printPostIdxImm8Operand";
848 let ParserMatchClass = PostIdxImm8AsmOperand;
849 let MIOperandInfo = (ops i32imm);
852 // postidx_imm8s4 := +/- [0,1020]
855 // {8} 1 is imm8 is non-negative. 0 otherwise.
856 // {7-0} [0,255] imm8 value, scaled by 4.
857 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
858 def postidx_imm8s4 : MemOperand {
859 let PrintMethod = "printPostIdxImm8s4Operand";
860 let ParserMatchClass = PostIdxImm8s4AsmOperand;
861 let MIOperandInfo = (ops i32imm);
865 // postidx_reg := +/- reg
867 def PostIdxRegAsmOperand : AsmOperandClass {
868 let Name = "PostIdxReg";
869 let ParserMethod = "parsePostIdxReg";
871 def postidx_reg : MemOperand {
872 let EncoderMethod = "getPostIdxRegOpValue";
873 let DecoderMethod = "DecodePostIdxReg";
874 let PrintMethod = "printPostIdxRegOperand";
875 let ParserMatchClass = PostIdxRegAsmOperand;
876 let MIOperandInfo = (ops GPRnopc, i32imm);
880 // addrmode2 := reg +/- imm12
881 // := reg +/- reg shop imm
883 // FIXME: addrmode2 should be refactored the rest of the way to always
884 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
885 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
886 def addrmode2 : MemOperand,
887 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
888 let EncoderMethod = "getAddrMode2OpValue";
889 let PrintMethod = "printAddrMode2Operand";
890 let ParserMatchClass = AddrMode2AsmOperand;
891 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
894 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
895 let Name = "PostIdxRegShifted";
896 let ParserMethod = "parsePostIdxReg";
898 def am2offset_reg : MemOperand,
899 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
900 [], [SDNPWantRoot]> {
901 let EncoderMethod = "getAddrMode2OffsetOpValue";
902 let PrintMethod = "printAddrMode2OffsetOperand";
903 // When using this for assembly, it's always as a post-index offset.
904 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
905 let MIOperandInfo = (ops GPRnopc, i32imm);
908 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
909 // the GPR is purely vestigal at this point.
910 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
911 def am2offset_imm : MemOperand,
912 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
913 [], [SDNPWantRoot]> {
914 let EncoderMethod = "getAddrMode2OffsetOpValue";
915 let PrintMethod = "printAddrMode2OffsetOperand";
916 let ParserMatchClass = AM2OffsetImmAsmOperand;
917 let MIOperandInfo = (ops GPRnopc, i32imm);
921 // addrmode3 := reg +/- reg
922 // addrmode3 := reg +/- imm8
924 // FIXME: split into imm vs. reg versions.
925 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
926 class AddrMode3 : MemOperand,
927 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
928 let EncoderMethod = "getAddrMode3OpValue";
929 let ParserMatchClass = AddrMode3AsmOperand;
930 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
933 def addrmode3 : AddrMode3
935 let PrintMethod = "printAddrMode3Operand<false>";
938 def addrmode3_pre : AddrMode3
940 let PrintMethod = "printAddrMode3Operand<true>";
943 // FIXME: split into imm vs. reg versions.
944 // FIXME: parser method to handle +/- register.
945 def AM3OffsetAsmOperand : AsmOperandClass {
946 let Name = "AM3Offset";
947 let ParserMethod = "parseAM3Offset";
949 def am3offset : MemOperand,
950 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
951 [], [SDNPWantRoot]> {
952 let EncoderMethod = "getAddrMode3OffsetOpValue";
953 let PrintMethod = "printAddrMode3OffsetOperand";
954 let ParserMatchClass = AM3OffsetAsmOperand;
955 let MIOperandInfo = (ops GPR, i32imm);
958 // ldstm_mode := {ia, ib, da, db}
960 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
961 let EncoderMethod = "getLdStmModeOpValue";
962 let PrintMethod = "printLdStmModeOperand";
965 // addrmode5 := reg +/- imm8*4
967 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
968 class AddrMode5 : MemOperand,
969 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
970 let EncoderMethod = "getAddrMode5OpValue";
971 let DecoderMethod = "DecodeAddrMode5Operand";
972 let ParserMatchClass = AddrMode5AsmOperand;
973 let MIOperandInfo = (ops GPR:$base, i32imm);
976 def addrmode5 : AddrMode5 {
977 let PrintMethod = "printAddrMode5Operand<false>";
980 def addrmode5_pre : AddrMode5 {
981 let PrintMethod = "printAddrMode5Operand<true>";
984 // addrmode5fp16 := reg +/- imm8*2
986 def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; }
987 class AddrMode5FP16 : Operand<i32>,
988 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> {
989 let EncoderMethod = "getAddrMode5FP16OpValue";
990 let DecoderMethod = "DecodeAddrMode5FP16Operand";
991 let ParserMatchClass = AddrMode5FP16AsmOperand;
992 let MIOperandInfo = (ops GPR:$base, i32imm);
995 def addrmode5fp16 : AddrMode5FP16 {
996 let PrintMethod = "printAddrMode5FP16Operand<false>";
999 // addrmode6 := reg with optional alignment
1001 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
1002 def addrmode6 : MemOperand,
1003 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1004 let PrintMethod = "printAddrMode6Operand";
1005 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1006 let EncoderMethod = "getAddrMode6AddressOpValue";
1007 let DecoderMethod = "DecodeAddrMode6Operand";
1008 let ParserMatchClass = AddrMode6AsmOperand;
1011 def am6offset : MemOperand,
1012 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
1013 [], [SDNPWantRoot]> {
1014 let PrintMethod = "printAddrMode6OffsetOperand";
1015 let MIOperandInfo = (ops GPR);
1016 let EncoderMethod = "getAddrMode6OffsetOpValue";
1017 let DecoderMethod = "DecodeGPRRegisterClass";
1020 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
1021 // (single element from one lane) for size 32.
1022 def addrmode6oneL32 : MemOperand,
1023 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1024 let PrintMethod = "printAddrMode6Operand";
1025 let MIOperandInfo = (ops GPR:$addr, i32imm);
1026 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1029 // Base class for addrmode6 with specific alignment restrictions.
1030 class AddrMode6Align : MemOperand,
1031 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1032 let PrintMethod = "printAddrMode6Operand";
1033 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1034 let EncoderMethod = "getAddrMode6AddressOpValue";
1035 let DecoderMethod = "DecodeAddrMode6Operand";
1038 // Special version of addrmode6 to handle no allowed alignment encoding for
1039 // VLD/VST instructions and checking the alignment is not specified.
1040 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1041 let Name = "AlignedMemoryNone";
1042 let DiagnosticType = "AlignedMemoryRequiresNone";
1044 def addrmode6alignNone : AddrMode6Align {
1045 // The alignment specifier can only be omitted.
1046 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1049 // Special version of addrmode6 to handle 16-bit alignment encoding for
1050 // VLD/VST instructions and checking the alignment value.
1051 def AddrMode6Align16AsmOperand : AsmOperandClass {
1052 let Name = "AlignedMemory16";
1053 let DiagnosticType = "AlignedMemoryRequires16";
1055 def addrmode6align16 : AddrMode6Align {
1056 // The alignment specifier can only be 16 or omitted.
1057 let ParserMatchClass = AddrMode6Align16AsmOperand;
1060 // Special version of addrmode6 to handle 32-bit alignment encoding for
1061 // VLD/VST instructions and checking the alignment value.
1062 def AddrMode6Align32AsmOperand : AsmOperandClass {
1063 let Name = "AlignedMemory32";
1064 let DiagnosticType = "AlignedMemoryRequires32";
1066 def addrmode6align32 : AddrMode6Align {
1067 // The alignment specifier can only be 32 or omitted.
1068 let ParserMatchClass = AddrMode6Align32AsmOperand;
1071 // Special version of addrmode6 to handle 64-bit alignment encoding for
1072 // VLD/VST instructions and checking the alignment value.
1073 def AddrMode6Align64AsmOperand : AsmOperandClass {
1074 let Name = "AlignedMemory64";
1075 let DiagnosticType = "AlignedMemoryRequires64";
1077 def addrmode6align64 : AddrMode6Align {
1078 // The alignment specifier can only be 64 or omitted.
1079 let ParserMatchClass = AddrMode6Align64AsmOperand;
1082 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1083 // for VLD/VST instructions and checking the alignment value.
1084 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1085 let Name = "AlignedMemory64or128";
1086 let DiagnosticType = "AlignedMemoryRequires64or128";
1088 def addrmode6align64or128 : AddrMode6Align {
1089 // The alignment specifier can only be 64, 128 or omitted.
1090 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1093 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1094 // encoding for VLD/VST instructions and checking the alignment value.
1095 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1096 let Name = "AlignedMemory64or128or256";
1097 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1099 def addrmode6align64or128or256 : AddrMode6Align {
1100 // The alignment specifier can only be 64, 128, 256 or omitted.
1101 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1104 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1105 // instructions, specifically VLD4-dup.
1106 def addrmode6dup : MemOperand,
1107 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1108 let PrintMethod = "printAddrMode6Operand";
1109 let MIOperandInfo = (ops GPR:$addr, i32imm);
1110 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1111 // FIXME: This is close, but not quite right. The alignment specifier is
1113 let ParserMatchClass = AddrMode6AsmOperand;
1116 // Base class for addrmode6dup with specific alignment restrictions.
1117 class AddrMode6DupAlign : MemOperand,
1118 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1119 let PrintMethod = "printAddrMode6Operand";
1120 let MIOperandInfo = (ops GPR:$addr, i32imm);
1121 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1124 // Special version of addrmode6 to handle no allowed alignment encoding for
1125 // VLD-dup instruction and checking the alignment is not specified.
1126 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1127 let Name = "DupAlignedMemoryNone";
1128 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1130 def addrmode6dupalignNone : AddrMode6DupAlign {
1131 // The alignment specifier can only be omitted.
1132 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1135 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1136 // instruction and checking the alignment value.
1137 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1138 let Name = "DupAlignedMemory16";
1139 let DiagnosticType = "DupAlignedMemoryRequires16";
1141 def addrmode6dupalign16 : AddrMode6DupAlign {
1142 // The alignment specifier can only be 16 or omitted.
1143 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1146 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1147 // instruction and checking the alignment value.
1148 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1149 let Name = "DupAlignedMemory32";
1150 let DiagnosticType = "DupAlignedMemoryRequires32";
1152 def addrmode6dupalign32 : AddrMode6DupAlign {
1153 // The alignment specifier can only be 32 or omitted.
1154 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1157 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1158 // instructions and checking the alignment value.
1159 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1160 let Name = "DupAlignedMemory64";
1161 let DiagnosticType = "DupAlignedMemoryRequires64";
1163 def addrmode6dupalign64 : AddrMode6DupAlign {
1164 // The alignment specifier can only be 64 or omitted.
1165 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1168 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1169 // for VLD instructions and checking the alignment value.
1170 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1171 let Name = "DupAlignedMemory64or128";
1172 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1174 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1175 // The alignment specifier can only be 64, 128 or omitted.
1176 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1179 // addrmodepc := pc + reg
1181 def addrmodepc : MemOperand,
1182 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1183 let PrintMethod = "printAddrModePCOperand";
1184 let MIOperandInfo = (ops GPR, i32imm);
1187 // addr_offset_none := reg
1189 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1190 def addr_offset_none : MemOperand,
1191 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1192 let PrintMethod = "printAddrMode7Operand";
1193 let DecoderMethod = "DecodeAddrMode7Operand";
1194 let ParserMatchClass = MemNoOffsetAsmOperand;
1195 let MIOperandInfo = (ops GPR:$base);
1198 def nohash_imm : Operand<i32> {
1199 let PrintMethod = "printNoHashImmediate";
1202 def CoprocNumAsmOperand : AsmOperandClass {
1203 let Name = "CoprocNum";
1204 let ParserMethod = "parseCoprocNumOperand";
1206 def p_imm : Operand<i32> {
1207 let PrintMethod = "printPImmediate";
1208 let ParserMatchClass = CoprocNumAsmOperand;
1209 let DecoderMethod = "DecodeCoprocessor";
1212 def CoprocRegAsmOperand : AsmOperandClass {
1213 let Name = "CoprocReg";
1214 let ParserMethod = "parseCoprocRegOperand";
1216 def c_imm : Operand<i32> {
1217 let PrintMethod = "printCImmediate";
1218 let ParserMatchClass = CoprocRegAsmOperand;
1220 def CoprocOptionAsmOperand : AsmOperandClass {
1221 let Name = "CoprocOption";
1222 let ParserMethod = "parseCoprocOptionOperand";
1224 def coproc_option_imm : Operand<i32> {
1225 let PrintMethod = "printCoprocOptionImm";
1226 let ParserMatchClass = CoprocOptionAsmOperand;
1229 //===----------------------------------------------------------------------===//
1231 include "ARMInstrFormats.td"
1233 //===----------------------------------------------------------------------===//
1234 // Multiclass helpers...
1237 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1238 /// binop that produces a value.
1239 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1240 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1241 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1242 PatFrag opnode, bit Commutable = 0> {
1243 // The register-immediate version is re-materializable. This is useful
1244 // in particular for taking the address of a local.
1245 let isReMaterializable = 1 in {
1246 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1247 iii, opc, "\t$Rd, $Rn, $imm",
1248 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1249 Sched<[WriteALU, ReadALU]> {
1254 let Inst{19-16} = Rn;
1255 let Inst{15-12} = Rd;
1256 let Inst{11-0} = imm;
1259 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1260 iir, opc, "\t$Rd, $Rn, $Rm",
1261 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1262 Sched<[WriteALU, ReadALU, ReadALU]> {
1267 let isCommutable = Commutable;
1268 let Inst{19-16} = Rn;
1269 let Inst{15-12} = Rd;
1270 let Inst{11-4} = 0b00000000;
1274 def rsi : AsI1<opcod, (outs GPR:$Rd),
1275 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1276 iis, opc, "\t$Rd, $Rn, $shift",
1277 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1278 Sched<[WriteALUsi, ReadALU]> {
1283 let Inst{19-16} = Rn;
1284 let Inst{15-12} = Rd;
1285 let Inst{11-5} = shift{11-5};
1287 let Inst{3-0} = shift{3-0};
1290 def rsr : AsI1<opcod, (outs GPR:$Rd),
1291 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1292 iis, opc, "\t$Rd, $Rn, $shift",
1293 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1294 Sched<[WriteALUsr, ReadALUsr]> {
1299 let Inst{19-16} = Rn;
1300 let Inst{15-12} = Rd;
1301 let Inst{11-8} = shift{11-8};
1303 let Inst{6-5} = shift{6-5};
1305 let Inst{3-0} = shift{3-0};
1309 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1310 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1311 /// it is equivalent to the AsI1_bin_irs counterpart.
1312 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1313 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1314 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1315 PatFrag opnode, bit Commutable = 0> {
1316 // The register-immediate version is re-materializable. This is useful
1317 // in particular for taking the address of a local.
1318 let isReMaterializable = 1 in {
1319 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1320 iii, opc, "\t$Rd, $Rn, $imm",
1321 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1322 Sched<[WriteALU, ReadALU]> {
1327 let Inst{19-16} = Rn;
1328 let Inst{15-12} = Rd;
1329 let Inst{11-0} = imm;
1332 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1333 iir, opc, "\t$Rd, $Rn, $Rm",
1334 [/* pattern left blank */]>,
1335 Sched<[WriteALU, ReadALU, ReadALU]> {
1339 let Inst{11-4} = 0b00000000;
1342 let Inst{15-12} = Rd;
1343 let Inst{19-16} = Rn;
1346 def rsi : AsI1<opcod, (outs GPR:$Rd),
1347 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1348 iis, opc, "\t$Rd, $Rn, $shift",
1349 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1350 Sched<[WriteALUsi, ReadALU]> {
1355 let Inst{19-16} = Rn;
1356 let Inst{15-12} = Rd;
1357 let Inst{11-5} = shift{11-5};
1359 let Inst{3-0} = shift{3-0};
1362 def rsr : AsI1<opcod, (outs GPR:$Rd),
1363 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1364 iis, opc, "\t$Rd, $Rn, $shift",
1365 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1366 Sched<[WriteALUsr, ReadALUsr]> {
1371 let Inst{19-16} = Rn;
1372 let Inst{15-12} = Rd;
1373 let Inst{11-8} = shift{11-8};
1375 let Inst{6-5} = shift{6-5};
1377 let Inst{3-0} = shift{3-0};
1381 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1383 /// These opcodes will be converted to the real non-S opcodes by
1384 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1385 let hasPostISelHook = 1, Defs = [CPSR] in {
1386 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1387 InstrItinClass iis, PatFrag opnode,
1388 bit Commutable = 0> {
1389 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1391 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1392 Sched<[WriteALU, ReadALU]>;
1394 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1396 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1397 Sched<[WriteALU, ReadALU, ReadALU]> {
1398 let isCommutable = Commutable;
1400 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1401 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1403 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1404 so_reg_imm:$shift))]>,
1405 Sched<[WriteALUsi, ReadALU]>;
1407 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1408 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1410 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1411 so_reg_reg:$shift))]>,
1412 Sched<[WriteALUSsr, ReadALUsr]>;
1416 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1417 /// operands are reversed.
1418 let hasPostISelHook = 1, Defs = [CPSR] in {
1419 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1420 InstrItinClass iis, PatFrag opnode,
1421 bit Commutable = 0> {
1422 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1424 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1425 Sched<[WriteALU, ReadALU]>;
1427 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1428 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1430 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1432 Sched<[WriteALUsi, ReadALU]>;
1434 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1435 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1437 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1439 Sched<[WriteALUSsr, ReadALUsr]>;
1443 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1444 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1445 /// a explicit result, only implicitly set CPSR.
1446 let isCompare = 1, Defs = [CPSR] in {
1447 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1448 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1449 PatFrag opnode, bit Commutable = 0,
1450 string rrDecoderMethod = ""> {
1451 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1453 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1454 Sched<[WriteCMP, ReadALU]> {
1459 let Inst{19-16} = Rn;
1460 let Inst{15-12} = 0b0000;
1461 let Inst{11-0} = imm;
1463 let Unpredictable{15-12} = 0b1111;
1465 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1467 [(opnode GPR:$Rn, GPR:$Rm)]>,
1468 Sched<[WriteCMP, ReadALU, ReadALU]> {
1471 let isCommutable = Commutable;
1474 let Inst{19-16} = Rn;
1475 let Inst{15-12} = 0b0000;
1476 let Inst{11-4} = 0b00000000;
1478 let DecoderMethod = rrDecoderMethod;
1480 let Unpredictable{15-12} = 0b1111;
1482 def rsi : AI1<opcod, (outs),
1483 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1484 opc, "\t$Rn, $shift",
1485 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1486 Sched<[WriteCMPsi, ReadALU]> {
1491 let Inst{19-16} = Rn;
1492 let Inst{15-12} = 0b0000;
1493 let Inst{11-5} = shift{11-5};
1495 let Inst{3-0} = shift{3-0};
1497 let Unpredictable{15-12} = 0b1111;
1499 def rsr : AI1<opcod, (outs),
1500 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1501 opc, "\t$Rn, $shift",
1502 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1503 Sched<[WriteCMPsr, ReadALU]> {
1508 let Inst{19-16} = Rn;
1509 let Inst{15-12} = 0b0000;
1510 let Inst{11-8} = shift{11-8};
1512 let Inst{6-5} = shift{6-5};
1514 let Inst{3-0} = shift{3-0};
1516 let Unpredictable{15-12} = 0b1111;
1522 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1523 /// register and one whose operand is a register rotated by 8/16/24.
1524 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1525 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1526 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1527 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1528 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1529 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1533 let Inst{19-16} = 0b1111;
1534 let Inst{15-12} = Rd;
1535 let Inst{11-10} = rot;
1539 class AI_ext_rrot_np<bits<8> opcod, string opc>
1540 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1541 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1542 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1544 let Inst{19-16} = 0b1111;
1545 let Inst{11-10} = rot;
1548 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1549 /// register and one whose operand is a register rotated by 8/16/24.
1550 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1551 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1552 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1553 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1554 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1555 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1560 let Inst{19-16} = Rn;
1561 let Inst{15-12} = Rd;
1562 let Inst{11-10} = rot;
1563 let Inst{9-4} = 0b000111;
1567 class AI_exta_rrot_np<bits<8> opcod, string opc>
1568 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1569 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1570 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1573 let Inst{19-16} = Rn;
1574 let Inst{11-10} = rot;
1577 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1578 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1579 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1580 bit Commutable = 0> {
1581 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1582 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1583 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1584 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1586 Sched<[WriteALU, ReadALU]> {
1591 let Inst{15-12} = Rd;
1592 let Inst{19-16} = Rn;
1593 let Inst{11-0} = imm;
1595 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1596 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1597 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1599 Sched<[WriteALU, ReadALU, ReadALU]> {
1603 let Inst{11-4} = 0b00000000;
1605 let isCommutable = Commutable;
1607 let Inst{15-12} = Rd;
1608 let Inst{19-16} = Rn;
1610 def rsi : AsI1<opcod, (outs GPR:$Rd),
1611 (ins GPR:$Rn, so_reg_imm:$shift),
1612 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1613 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1615 Sched<[WriteALUsi, ReadALU]> {
1620 let Inst{19-16} = Rn;
1621 let Inst{15-12} = Rd;
1622 let Inst{11-5} = shift{11-5};
1624 let Inst{3-0} = shift{3-0};
1626 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1627 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1628 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1629 [(set GPRnopc:$Rd, CPSR,
1630 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1632 Sched<[WriteALUsr, ReadALUsr]> {
1637 let Inst{19-16} = Rn;
1638 let Inst{15-12} = Rd;
1639 let Inst{11-8} = shift{11-8};
1641 let Inst{6-5} = shift{6-5};
1643 let Inst{3-0} = shift{3-0};
1648 /// AI1_rsc_irs - Define instructions and patterns for rsc
1649 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1650 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1651 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1652 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1653 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1654 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1656 Sched<[WriteALU, ReadALU]> {
1661 let Inst{15-12} = Rd;
1662 let Inst{19-16} = Rn;
1663 let Inst{11-0} = imm;
1665 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1666 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1667 [/* pattern left blank */]>,
1668 Sched<[WriteALU, ReadALU, ReadALU]> {
1672 let Inst{11-4} = 0b00000000;
1675 let Inst{15-12} = Rd;
1676 let Inst{19-16} = Rn;
1678 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1679 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1680 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1682 Sched<[WriteALUsi, ReadALU]> {
1687 let Inst{19-16} = Rn;
1688 let Inst{15-12} = Rd;
1689 let Inst{11-5} = shift{11-5};
1691 let Inst{3-0} = shift{3-0};
1693 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1694 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1695 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1697 Sched<[WriteALUsr, ReadALUsr]> {
1702 let Inst{19-16} = Rn;
1703 let Inst{15-12} = Rd;
1704 let Inst{11-8} = shift{11-8};
1706 let Inst{6-5} = shift{6-5};
1708 let Inst{3-0} = shift{3-0};
1713 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1714 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1715 InstrItinClass iir, PatFrag opnode> {
1716 // Note: We use the complex addrmode_imm12 rather than just an input
1717 // GPR and a constrained immediate so that we can use this to match
1718 // frame index references and avoid matching constant pool references.
1719 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1720 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1721 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1724 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1725 let Inst{19-16} = addr{16-13}; // Rn
1726 let Inst{15-12} = Rt;
1727 let Inst{11-0} = addr{11-0}; // imm12
1729 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1730 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1731 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1734 let shift{4} = 0; // Inst{4} = 0
1735 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1736 let Inst{19-16} = shift{16-13}; // Rn
1737 let Inst{15-12} = Rt;
1738 let Inst{11-0} = shift{11-0};
1743 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1744 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1745 InstrItinClass iir, PatFrag opnode> {
1746 // Note: We use the complex addrmode_imm12 rather than just an input
1747 // GPR and a constrained immediate so that we can use this to match
1748 // frame index references and avoid matching constant pool references.
1749 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1750 (ins addrmode_imm12:$addr),
1751 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1752 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1755 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1756 let Inst{19-16} = addr{16-13}; // Rn
1757 let Inst{15-12} = Rt;
1758 let Inst{11-0} = addr{11-0}; // imm12
1760 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1761 (ins ldst_so_reg:$shift),
1762 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1763 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1766 let shift{4} = 0; // Inst{4} = 0
1767 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1768 let Inst{19-16} = shift{16-13}; // Rn
1769 let Inst{15-12} = Rt;
1770 let Inst{11-0} = shift{11-0};
1776 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1777 InstrItinClass iir, PatFrag opnode> {
1778 // Note: We use the complex addrmode_imm12 rather than just an input
1779 // GPR and a constrained immediate so that we can use this to match
1780 // frame index references and avoid matching constant pool references.
1781 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1782 (ins GPR:$Rt, addrmode_imm12:$addr),
1783 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1784 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1787 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1788 let Inst{19-16} = addr{16-13}; // Rn
1789 let Inst{15-12} = Rt;
1790 let Inst{11-0} = addr{11-0}; // imm12
1792 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1793 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1794 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1797 let shift{4} = 0; // Inst{4} = 0
1798 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1799 let Inst{19-16} = shift{16-13}; // Rn
1800 let Inst{15-12} = Rt;
1801 let Inst{11-0} = shift{11-0};
1805 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1806 InstrItinClass iir, PatFrag opnode> {
1807 // Note: We use the complex addrmode_imm12 rather than just an input
1808 // GPR and a constrained immediate so that we can use this to match
1809 // frame index references and avoid matching constant pool references.
1810 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1811 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1812 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1813 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1816 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1817 let Inst{19-16} = addr{16-13}; // Rn
1818 let Inst{15-12} = Rt;
1819 let Inst{11-0} = addr{11-0}; // imm12
1821 def rs : AI2ldst<0b011, 0, isByte, (outs),
1822 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1823 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1824 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1827 let shift{4} = 0; // Inst{4} = 0
1828 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1829 let Inst{19-16} = shift{16-13}; // Rn
1830 let Inst{15-12} = Rt;
1831 let Inst{11-0} = shift{11-0};
1836 //===----------------------------------------------------------------------===//
1838 //===----------------------------------------------------------------------===//
1840 //===----------------------------------------------------------------------===//
1841 // Miscellaneous Instructions.
1844 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1845 /// the function. The first operand is the ID# for this instruction, the second
1846 /// is the index into the MachineConstantPool that this is, the third is the
1847 /// size in bytes of this constant pool entry.
1848 let hasSideEffects = 0, isNotDuplicable = 1 in
1849 def CONSTPOOL_ENTRY :
1850 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1851 i32imm:$size), NoItinerary, []>;
1853 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1854 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1855 /// mode). Used mostly in ARM and Thumb-1 modes.
1856 def JUMPTABLE_ADDRS :
1857 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1858 i32imm:$size), NoItinerary, []>;
1860 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1861 /// that cannot be optimised to use TBB or TBH.
1862 def JUMPTABLE_INSTS :
1863 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1864 i32imm:$size), NoItinerary, []>;
1866 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1867 /// a TBB instruction.
1869 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1870 i32imm:$size), NoItinerary, []>;
1872 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1873 /// a TBH instruction.
1875 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1876 i32imm:$size), NoItinerary, []>;
1879 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1880 // from removing one half of the matched pairs. That breaks PEI, which assumes
1881 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1882 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1883 def ADJCALLSTACKUP :
1884 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1885 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1887 def ADJCALLSTACKDOWN :
1888 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1889 [(ARMcallseq_start timm:$amt)]>;
1892 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1893 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1894 Requires<[IsARM, HasV6]> {
1896 let Inst{27-8} = 0b00110010000011110000;
1897 let Inst{7-0} = imm;
1900 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1901 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1902 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1903 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1904 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1905 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1907 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1908 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1913 let Inst{15-12} = Rd;
1914 let Inst{19-16} = Rn;
1915 let Inst{27-20} = 0b01101000;
1916 let Inst{7-4} = 0b1011;
1917 let Inst{11-8} = 0b1111;
1918 let Unpredictable{11-8} = 0b1111;
1921 // The 16-bit operand $val can be used by a debugger to store more information
1922 // about the breakpoint.
1923 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1924 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1926 let Inst{3-0} = val{3-0};
1927 let Inst{19-8} = val{15-4};
1928 let Inst{27-20} = 0b00010010;
1929 let Inst{31-28} = 0xe; // AL
1930 let Inst{7-4} = 0b0111;
1932 // default immediate for breakpoint mnemonic
1933 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1935 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1936 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1938 let Inst{3-0} = val{3-0};
1939 let Inst{19-8} = val{15-4};
1940 let Inst{27-20} = 0b00010000;
1941 let Inst{31-28} = 0xe; // AL
1942 let Inst{7-4} = 0b0111;
1945 // Change Processor State
1946 // FIXME: We should use InstAlias to handle the optional operands.
1947 class CPS<dag iops, string asm_ops>
1948 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1949 []>, Requires<[IsARM]> {
1955 let Inst{31-28} = 0b1111;
1956 let Inst{27-20} = 0b00010000;
1957 let Inst{19-18} = imod;
1958 let Inst{17} = M; // Enabled if mode is set;
1959 let Inst{16-9} = 0b00000000;
1960 let Inst{8-6} = iflags;
1962 let Inst{4-0} = mode;
1965 let DecoderMethod = "DecodeCPSInstruction" in {
1967 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1968 "$imod\t$iflags, $mode">;
1969 let mode = 0, M = 0 in
1970 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1972 let imod = 0, iflags = 0, M = 1 in
1973 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1976 // Preload signals the memory system of possible future data/instruction access.
1977 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1979 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1980 IIC_Preload, !strconcat(opc, "\t$addr"),
1981 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1982 Sched<[WritePreLd]> {
1985 let Inst{31-26} = 0b111101;
1986 let Inst{25} = 0; // 0 for immediate form
1987 let Inst{24} = data;
1988 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1989 let Inst{22} = read;
1990 let Inst{21-20} = 0b01;
1991 let Inst{19-16} = addr{16-13}; // Rn
1992 let Inst{15-12} = 0b1111;
1993 let Inst{11-0} = addr{11-0}; // imm12
1996 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1997 !strconcat(opc, "\t$shift"),
1998 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1999 Sched<[WritePreLd]> {
2001 let Inst{31-26} = 0b111101;
2002 let Inst{25} = 1; // 1 for register form
2003 let Inst{24} = data;
2004 let Inst{23} = shift{12}; // U (add = ('U' == 1))
2005 let Inst{22} = read;
2006 let Inst{21-20} = 0b01;
2007 let Inst{19-16} = shift{16-13}; // Rn
2008 let Inst{15-12} = 0b1111;
2009 let Inst{11-0} = shift{11-0};
2014 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
2015 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
2016 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
2018 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
2019 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2021 let Inst{31-10} = 0b1111000100000001000000;
2026 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2027 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2029 let Inst{27-4} = 0b001100100000111100001111;
2030 let Inst{3-0} = opt;
2033 // A8.8.247 UDF - Undefined (Encoding A1)
2034 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2035 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2037 let Inst{31-28} = 0b1110; // AL
2038 let Inst{27-25} = 0b011;
2039 let Inst{24-20} = 0b11111;
2040 let Inst{19-8} = imm16{15-4};
2041 let Inst{7-4} = 0b1111;
2042 let Inst{3-0} = imm16{3-0};
2046 * A5.4 Permanently UNDEFINED instructions.
2048 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2049 * Other UDF encodings generate SIGILL.
2051 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2053 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2055 * 1101 1110 iiii iiii
2056 * It uses the following encoding:
2057 * 1110 0111 1111 1110 1101 1110 1111 0000
2058 * - In ARM: UDF #60896;
2059 * - In Thumb: UDF #254 followed by a branch-to-self.
2061 let isBarrier = 1, isTerminator = 1 in
2062 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2064 Requires<[IsARM,UseNaClTrap]> {
2065 let Inst = 0xe7fedef0;
2067 let isBarrier = 1, isTerminator = 1 in
2068 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2070 Requires<[IsARM,DontUseNaClTrap]> {
2071 let Inst = 0xe7ffdefe;
2074 // Address computation and loads and stores in PIC mode.
2075 let isNotDuplicable = 1 in {
2076 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2078 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2079 Sched<[WriteALU, ReadALU]>;
2081 let AddedComplexity = 10 in {
2082 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2084 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2086 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2088 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2090 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2092 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2094 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2096 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2098 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2100 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2102 let AddedComplexity = 10 in {
2103 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2104 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2106 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2107 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2108 addrmodepc:$addr)]>;
2110 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2111 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2113 } // isNotDuplicable = 1
2116 // LEApcrel - Load a pc-relative address into a register without offending the
2118 let hasSideEffects = 0, isReMaterializable = 1 in
2119 // The 'adr' mnemonic encodes differently if the label is before or after
2120 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2121 // know until then which form of the instruction will be used.
2122 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2123 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2124 Sched<[WriteALU, ReadALU]> {
2127 let Inst{27-25} = 0b001;
2129 let Inst{23-22} = label{13-12};
2132 let Inst{19-16} = 0b1111;
2133 let Inst{15-12} = Rd;
2134 let Inst{11-0} = label{11-0};
2137 let hasSideEffects = 1 in {
2138 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2139 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2141 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2142 (ins i32imm:$label, pred:$p),
2143 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2146 //===----------------------------------------------------------------------===//
2147 // Control Flow Instructions.
2150 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2152 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2153 "bx", "\tlr", [(ARMretflag)]>,
2154 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2155 let Inst{27-0} = 0b0001001011111111111100011110;
2159 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2160 "mov", "\tpc, lr", [(ARMretflag)]>,
2161 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2162 let Inst{27-0} = 0b0001101000001111000000001110;
2165 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2166 // the user-space one).
2167 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2169 [(ARMintretflag imm:$offset)]>;
2172 // Indirect branches
2173 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2175 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2176 [(brind GPR:$dst)]>,
2177 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2179 let Inst{31-4} = 0b1110000100101111111111110001;
2180 let Inst{3-0} = dst;
2183 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2184 "bx", "\t$dst", [/* pattern left blank */]>,
2185 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2187 let Inst{27-4} = 0b000100101111111111110001;
2188 let Inst{3-0} = dst;
2192 // SP is marked as a use to prevent stack-pointer assignments that appear
2193 // immediately before calls from potentially appearing dead.
2195 // FIXME: Do we really need a non-predicated version? If so, it should
2196 // at least be a pseudo instruction expanding to the predicated version
2197 // at MC lowering time.
2198 Defs = [LR], Uses = [SP] in {
2199 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2200 IIC_Br, "bl\t$func",
2201 [(ARMcall tglobaladdr:$func)]>,
2202 Requires<[IsARM]>, Sched<[WriteBrL]> {
2203 let Inst{31-28} = 0b1110;
2205 let Inst{23-0} = func;
2206 let DecoderMethod = "DecodeBranchImmInstruction";
2209 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2210 IIC_Br, "bl", "\t$func",
2211 [(ARMcall_pred tglobaladdr:$func)]>,
2212 Requires<[IsARM]>, Sched<[WriteBrL]> {
2214 let Inst{23-0} = func;
2215 let DecoderMethod = "DecodeBranchImmInstruction";
2219 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2220 IIC_Br, "blx\t$func",
2221 [(ARMcall GPR:$func)]>,
2222 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2224 let Inst{31-4} = 0b1110000100101111111111110011;
2225 let Inst{3-0} = func;
2228 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2229 IIC_Br, "blx", "\t$func",
2230 [(ARMcall_pred GPR:$func)]>,
2231 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2233 let Inst{27-4} = 0b000100101111111111110011;
2234 let Inst{3-0} = func;
2238 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2239 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2240 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2241 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2244 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2245 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2246 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2248 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2249 // return stack predictor.
2250 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2251 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2252 Requires<[IsARM]>, Sched<[WriteBr]>;
2255 let isBranch = 1, isTerminator = 1 in {
2256 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2257 // a two-value operand where a dag node expects two operands. :(
2258 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2259 IIC_Br, "b", "\t$target",
2260 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2263 let Inst{23-0} = target;
2264 let DecoderMethod = "DecodeBranchImmInstruction";
2267 let isBarrier = 1 in {
2268 // B is "predicable" since it's just a Bcc with an 'always' condition.
2269 let isPredicable = 1 in
2270 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2271 // should be sufficient.
2272 // FIXME: Is B really a Barrier? That doesn't seem right.
2273 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2274 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2277 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2278 def BR_JTr : ARMPseudoInst<(outs),
2279 (ins GPR:$target, i32imm:$jt),
2281 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2283 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2284 // into i12 and rs suffixed versions.
2285 def BR_JTm : ARMPseudoInst<(outs),
2286 (ins addrmode2:$target, i32imm:$jt),
2288 [(ARMbrjt (i32 (load addrmode2:$target)),
2289 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2290 def BR_JTadd : ARMPseudoInst<(outs),
2291 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2293 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2294 Sched<[WriteBrTbl]>;
2295 } // isNotDuplicable = 1, isIndirectBranch = 1
2301 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2302 "blx\t$target", []>,
2303 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2304 let Inst{31-25} = 0b1111101;
2306 let Inst{23-0} = target{24-1};
2307 let Inst{24} = target{0};
2311 // Branch and Exchange Jazelle
2312 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2313 [/* pattern left blank */]>, Sched<[WriteBr]> {
2315 let Inst{23-20} = 0b0010;
2316 let Inst{19-8} = 0xfff;
2317 let Inst{7-4} = 0b0010;
2318 let Inst{3-0} = func;
2324 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2325 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2328 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2331 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2333 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2334 Requires<[IsARM]>, Sched<[WriteBr]>;
2336 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2338 (BX GPR:$dst)>, Sched<[WriteBr]>,
2342 // Secure Monitor Call is a system instruction.
2343 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2344 []>, Requires<[IsARM, HasTrustZone]> {
2346 let Inst{23-4} = 0b01100000000000000111;
2347 let Inst{3-0} = opt;
2349 def : MnemonicAlias<"smi", "smc">;
2351 // Supervisor Call (Software Interrupt)
2352 let isCall = 1, Uses = [SP] in {
2353 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2356 let Inst{23-0} = svc;
2360 // Store Return State
2361 class SRSI<bit wb, string asm>
2362 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2363 NoItinerary, asm, "", []> {
2365 let Inst{31-28} = 0b1111;
2366 let Inst{27-25} = 0b100;
2370 let Inst{19-16} = 0b1101; // SP
2371 let Inst{15-5} = 0b00000101000;
2372 let Inst{4-0} = mode;
2375 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2376 let Inst{24-23} = 0;
2378 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2379 let Inst{24-23} = 0;
2381 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2382 let Inst{24-23} = 0b10;
2384 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2385 let Inst{24-23} = 0b10;
2387 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2388 let Inst{24-23} = 0b01;
2390 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2391 let Inst{24-23} = 0b01;
2393 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2394 let Inst{24-23} = 0b11;
2396 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2397 let Inst{24-23} = 0b11;
2400 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2401 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2403 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2404 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2406 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2407 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2409 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2410 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2412 // Return From Exception
2413 class RFEI<bit wb, string asm>
2414 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2415 NoItinerary, asm, "", []> {
2417 let Inst{31-28} = 0b1111;
2418 let Inst{27-25} = 0b100;
2422 let Inst{19-16} = Rn;
2423 let Inst{15-0} = 0xa00;
2426 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2427 let Inst{24-23} = 0;
2429 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2430 let Inst{24-23} = 0;
2432 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2433 let Inst{24-23} = 0b10;
2435 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2436 let Inst{24-23} = 0b10;
2438 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2439 let Inst{24-23} = 0b01;
2441 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2442 let Inst{24-23} = 0b01;
2444 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2445 let Inst{24-23} = 0b11;
2447 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2448 let Inst{24-23} = 0b11;
2451 // Hypervisor Call is a system instruction
2453 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2454 "hvc", "\t$imm", []>,
2455 Requires<[IsARM, HasVirtualization]> {
2458 // Even though HVC isn't predicable, it's encoding includes a condition field.
2459 // The instruction is undefined if the condition field is 0xf otherwise it is
2460 // unpredictable if it isn't condition AL (0xe).
2461 let Inst{31-28} = 0b1110;
2462 let Unpredictable{31-28} = 0b1111;
2463 let Inst{27-24} = 0b0001;
2464 let Inst{23-20} = 0b0100;
2465 let Inst{19-8} = imm{15-4};
2466 let Inst{7-4} = 0b0111;
2467 let Inst{3-0} = imm{3-0};
2471 // Return from exception in Hypervisor mode.
2472 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2473 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2474 Requires<[IsARM, HasVirtualization]> {
2475 let Inst{23-0} = 0b011000000000000001101110;
2478 //===----------------------------------------------------------------------===//
2479 // Load / Store Instructions.
2485 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2486 UnOpFrag<(load node:$Src)>>;
2487 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2488 UnOpFrag<(zextloadi8 node:$Src)>>;
2489 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2490 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2491 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2492 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2494 // Special LDR for loads from non-pc-relative constpools.
2495 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2496 isReMaterializable = 1, isCodeGenOnly = 1 in
2497 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2498 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2502 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2503 let Inst{19-16} = 0b1111;
2504 let Inst{15-12} = Rt;
2505 let Inst{11-0} = addr{11-0}; // imm12
2508 // Loads with zero extension
2509 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2510 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2511 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2513 // Loads with sign extension
2514 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2515 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2516 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2518 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2519 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2520 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2522 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2524 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2525 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2526 Requires<[IsARM, HasV5TE]>;
2529 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2530 NoItinerary, "lda", "\t$Rt, $addr", []>;
2531 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2532 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2533 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2534 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2537 multiclass AI2_ldridx<bit isByte, string opc,
2538 InstrItinClass iii, InstrItinClass iir> {
2539 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2540 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2541 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2544 let Inst{23} = addr{12};
2545 let Inst{19-16} = addr{16-13};
2546 let Inst{11-0} = addr{11-0};
2547 let DecoderMethod = "DecodeLDRPreImm";
2550 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2551 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2552 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2555 let Inst{23} = addr{12};
2556 let Inst{19-16} = addr{16-13};
2557 let Inst{11-0} = addr{11-0};
2559 let DecoderMethod = "DecodeLDRPreReg";
2562 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2563 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2564 IndexModePost, LdFrm, iir,
2565 opc, "\t$Rt, $addr, $offset",
2566 "$addr.base = $Rn_wb", []> {
2572 let Inst{23} = offset{12};
2573 let Inst{19-16} = addr;
2574 let Inst{11-0} = offset{11-0};
2577 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2580 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2581 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2582 IndexModePost, LdFrm, iii,
2583 opc, "\t$Rt, $addr, $offset",
2584 "$addr.base = $Rn_wb", []> {
2590 let Inst{23} = offset{12};
2591 let Inst{19-16} = addr;
2592 let Inst{11-0} = offset{11-0};
2594 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2599 let mayLoad = 1, hasSideEffects = 0 in {
2600 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2601 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2602 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2603 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2606 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2607 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2608 (ins addrmode3_pre:$addr), IndexModePre,
2610 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2612 let Inst{23} = addr{8}; // U bit
2613 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2614 let Inst{19-16} = addr{12-9}; // Rn
2615 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2616 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2617 let DecoderMethod = "DecodeAddrMode3Instruction";
2619 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2620 (ins addr_offset_none:$addr, am3offset:$offset),
2621 IndexModePost, LdMiscFrm, itin,
2622 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2626 let Inst{23} = offset{8}; // U bit
2627 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2628 let Inst{19-16} = addr;
2629 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2630 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2631 let DecoderMethod = "DecodeAddrMode3Instruction";
2635 let mayLoad = 1, hasSideEffects = 0 in {
2636 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2637 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2638 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2639 let hasExtraDefRegAllocReq = 1 in {
2640 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2641 (ins addrmode3_pre:$addr), IndexModePre,
2642 LdMiscFrm, IIC_iLoad_d_ru,
2643 "ldrd", "\t$Rt, $Rt2, $addr!",
2644 "$addr.base = $Rn_wb", []> {
2646 let Inst{23} = addr{8}; // U bit
2647 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2648 let Inst{19-16} = addr{12-9}; // Rn
2649 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2650 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2651 let DecoderMethod = "DecodeAddrMode3Instruction";
2653 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2654 (ins addr_offset_none:$addr, am3offset:$offset),
2655 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2656 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2657 "$addr.base = $Rn_wb", []> {
2660 let Inst{23} = offset{8}; // U bit
2661 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2662 let Inst{19-16} = addr;
2663 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2664 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2665 let DecoderMethod = "DecodeAddrMode3Instruction";
2667 } // hasExtraDefRegAllocReq = 1
2668 } // mayLoad = 1, hasSideEffects = 0
2670 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2671 let mayLoad = 1, hasSideEffects = 0 in {
2672 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2673 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2674 IndexModePost, LdFrm, IIC_iLoad_ru,
2675 "ldrt", "\t$Rt, $addr, $offset",
2676 "$addr.base = $Rn_wb", []> {
2682 let Inst{23} = offset{12};
2683 let Inst{21} = 1; // overwrite
2684 let Inst{19-16} = addr;
2685 let Inst{11-5} = offset{11-5};
2687 let Inst{3-0} = offset{3-0};
2688 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2692 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2693 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2694 IndexModePost, LdFrm, IIC_iLoad_ru,
2695 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2701 let Inst{23} = offset{12};
2702 let Inst{21} = 1; // overwrite
2703 let Inst{19-16} = addr;
2704 let Inst{11-0} = offset{11-0};
2705 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2708 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2709 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2710 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2711 "ldrbt", "\t$Rt, $addr, $offset",
2712 "$addr.base = $Rn_wb", []> {
2718 let Inst{23} = offset{12};
2719 let Inst{21} = 1; // overwrite
2720 let Inst{19-16} = addr;
2721 let Inst{11-5} = offset{11-5};
2723 let Inst{3-0} = offset{3-0};
2724 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2728 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2729 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2730 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2731 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2737 let Inst{23} = offset{12};
2738 let Inst{21} = 1; // overwrite
2739 let Inst{19-16} = addr;
2740 let Inst{11-0} = offset{11-0};
2741 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2744 multiclass AI3ldrT<bits<4> op, string opc> {
2745 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2746 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2747 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2748 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2750 let Inst{23} = offset{8};
2752 let Inst{11-8} = offset{7-4};
2753 let Inst{3-0} = offset{3-0};
2755 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2756 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2757 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2758 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2760 let Inst{23} = Rm{4};
2763 let Unpredictable{11-8} = 0b1111;
2764 let Inst{3-0} = Rm{3-0};
2765 let DecoderMethod = "DecodeLDR";
2769 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2770 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2771 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2775 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2779 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2784 // Stores with truncate
2785 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2786 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2787 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2790 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2791 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2792 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2793 Requires<[IsARM, HasV5TE]> {
2799 multiclass AI2_stridx<bit isByte, string opc,
2800 InstrItinClass iii, InstrItinClass iir> {
2801 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2802 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2804 opc, "\t$Rt, $addr!",
2805 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2808 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2809 let Inst{19-16} = addr{16-13}; // Rn
2810 let Inst{11-0} = addr{11-0}; // imm12
2811 let DecoderMethod = "DecodeSTRPreImm";
2814 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2815 (ins GPR:$Rt, ldst_so_reg:$addr),
2816 IndexModePre, StFrm, iir,
2817 opc, "\t$Rt, $addr!",
2818 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2821 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2822 let Inst{19-16} = addr{16-13}; // Rn
2823 let Inst{11-0} = addr{11-0};
2824 let Inst{4} = 0; // Inst{4} = 0
2825 let DecoderMethod = "DecodeSTRPreReg";
2827 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2828 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2829 IndexModePost, StFrm, iir,
2830 opc, "\t$Rt, $addr, $offset",
2831 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2837 let Inst{23} = offset{12};
2838 let Inst{19-16} = addr;
2839 let Inst{11-0} = offset{11-0};
2842 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2845 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2846 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2847 IndexModePost, StFrm, iii,
2848 opc, "\t$Rt, $addr, $offset",
2849 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2855 let Inst{23} = offset{12};
2856 let Inst{19-16} = addr;
2857 let Inst{11-0} = offset{11-0};
2859 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2863 let mayStore = 1, hasSideEffects = 0 in {
2864 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2865 // IIC_iStore_siu depending on whether it the offset register is shifted.
2866 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2867 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2870 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2871 am2offset_reg:$offset),
2872 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2873 am2offset_reg:$offset)>;
2874 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2875 am2offset_imm:$offset),
2876 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2877 am2offset_imm:$offset)>;
2878 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2879 am2offset_reg:$offset),
2880 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2881 am2offset_reg:$offset)>;
2882 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2883 am2offset_imm:$offset),
2884 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2885 am2offset_imm:$offset)>;
2887 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2888 // put the patterns on the instruction definitions directly as ISel wants
2889 // the address base and offset to be separate operands, not a single
2890 // complex operand like we represent the instructions themselves. The
2891 // pseudos map between the two.
2892 let usesCustomInserter = 1,
2893 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2894 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2895 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2898 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2899 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2900 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2903 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2904 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2905 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2908 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2909 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2910 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2913 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2914 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2915 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2918 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2923 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2924 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2925 StMiscFrm, IIC_iStore_bh_ru,
2926 "strh", "\t$Rt, $addr!",
2927 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2929 let Inst{23} = addr{8}; // U bit
2930 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2931 let Inst{19-16} = addr{12-9}; // Rn
2932 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2933 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2934 let DecoderMethod = "DecodeAddrMode3Instruction";
2937 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2938 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2939 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2940 "strh", "\t$Rt, $addr, $offset",
2941 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2942 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2943 addr_offset_none:$addr,
2944 am3offset:$offset))]> {
2947 let Inst{23} = offset{8}; // U bit
2948 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2949 let Inst{19-16} = addr;
2950 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2951 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2952 let DecoderMethod = "DecodeAddrMode3Instruction";
2955 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2956 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2957 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2958 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2959 "strd", "\t$Rt, $Rt2, $addr!",
2960 "$addr.base = $Rn_wb", []> {
2962 let Inst{23} = addr{8}; // U bit
2963 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2964 let Inst{19-16} = addr{12-9}; // Rn
2965 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2966 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2967 let DecoderMethod = "DecodeAddrMode3Instruction";
2970 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2971 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2973 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2974 "strd", "\t$Rt, $Rt2, $addr, $offset",
2975 "$addr.base = $Rn_wb", []> {
2978 let Inst{23} = offset{8}; // U bit
2979 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2980 let Inst{19-16} = addr;
2981 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2982 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2983 let DecoderMethod = "DecodeAddrMode3Instruction";
2985 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2987 // STRT, STRBT, and STRHT
2989 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2990 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2991 IndexModePost, StFrm, IIC_iStore_bh_ru,
2992 "strbt", "\t$Rt, $addr, $offset",
2993 "$addr.base = $Rn_wb", []> {
2999 let Inst{23} = offset{12};
3000 let Inst{21} = 1; // overwrite
3001 let Inst{19-16} = addr;
3002 let Inst{11-5} = offset{11-5};
3004 let Inst{3-0} = offset{3-0};
3005 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3009 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3010 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3011 IndexModePost, StFrm, IIC_iStore_bh_ru,
3012 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3018 let Inst{23} = offset{12};
3019 let Inst{21} = 1; // overwrite
3020 let Inst{19-16} = addr;
3021 let Inst{11-0} = offset{11-0};
3022 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3026 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3027 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3029 let mayStore = 1, hasSideEffects = 0 in {
3030 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3031 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3032 IndexModePost, StFrm, IIC_iStore_ru,
3033 "strt", "\t$Rt, $addr, $offset",
3034 "$addr.base = $Rn_wb", []> {
3040 let Inst{23} = offset{12};
3041 let Inst{21} = 1; // overwrite
3042 let Inst{19-16} = addr;
3043 let Inst{11-5} = offset{11-5};
3045 let Inst{3-0} = offset{3-0};
3046 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3050 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3051 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3052 IndexModePost, StFrm, IIC_iStore_ru,
3053 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3059 let Inst{23} = offset{12};
3060 let Inst{21} = 1; // overwrite
3061 let Inst{19-16} = addr;
3062 let Inst{11-0} = offset{11-0};
3063 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3068 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3069 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3071 multiclass AI3strT<bits<4> op, string opc> {
3072 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3073 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3074 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3075 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3077 let Inst{23} = offset{8};
3079 let Inst{11-8} = offset{7-4};
3080 let Inst{3-0} = offset{3-0};
3082 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3083 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3084 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3085 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3087 let Inst{23} = Rm{4};
3090 let Inst{3-0} = Rm{3-0};
3095 defm STRHT : AI3strT<0b1011, "strht">;
3097 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3098 NoItinerary, "stl", "\t$Rt, $addr", []>;
3099 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3100 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3101 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3102 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3104 //===----------------------------------------------------------------------===//
3105 // Load / store multiple Instructions.
3108 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3109 InstrItinClass itin, InstrItinClass itin_upd> {
3110 // IA is the default, so no need for an explicit suffix on the
3111 // mnemonic here. Without it is the canonical spelling.
3113 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3114 IndexModeNone, f, itin,
3115 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3116 let Inst{24-23} = 0b01; // Increment After
3117 let Inst{22} = P_bit;
3118 let Inst{21} = 0; // No writeback
3119 let Inst{20} = L_bit;
3122 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3123 IndexModeUpd, f, itin_upd,
3124 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3125 let Inst{24-23} = 0b01; // Increment After
3126 let Inst{22} = P_bit;
3127 let Inst{21} = 1; // Writeback
3128 let Inst{20} = L_bit;
3130 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3133 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3134 IndexModeNone, f, itin,
3135 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3136 let Inst{24-23} = 0b00; // Decrement After
3137 let Inst{22} = P_bit;
3138 let Inst{21} = 0; // No writeback
3139 let Inst{20} = L_bit;
3142 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3143 IndexModeUpd, f, itin_upd,
3144 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3145 let Inst{24-23} = 0b00; // Decrement After
3146 let Inst{22} = P_bit;
3147 let Inst{21} = 1; // Writeback
3148 let Inst{20} = L_bit;
3150 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3153 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3154 IndexModeNone, f, itin,
3155 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3156 let Inst{24-23} = 0b10; // Decrement Before
3157 let Inst{22} = P_bit;
3158 let Inst{21} = 0; // No writeback
3159 let Inst{20} = L_bit;
3162 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3163 IndexModeUpd, f, itin_upd,
3164 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3165 let Inst{24-23} = 0b10; // Decrement Before
3166 let Inst{22} = P_bit;
3167 let Inst{21} = 1; // Writeback
3168 let Inst{20} = L_bit;
3170 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3173 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3174 IndexModeNone, f, itin,
3175 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3176 let Inst{24-23} = 0b11; // Increment Before
3177 let Inst{22} = P_bit;
3178 let Inst{21} = 0; // No writeback
3179 let Inst{20} = L_bit;
3182 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3183 IndexModeUpd, f, itin_upd,
3184 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3185 let Inst{24-23} = 0b11; // Increment Before
3186 let Inst{22} = P_bit;
3187 let Inst{21} = 1; // Writeback
3188 let Inst{20} = L_bit;
3190 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3194 let hasSideEffects = 0 in {
3196 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3197 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3198 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3200 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3201 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3203 ComplexDeprecationPredicate<"ARMStore">;
3207 // FIXME: remove when we have a way to marking a MI with these properties.
3208 // FIXME: Should pc be an implicit operand like PICADD, etc?
3209 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3210 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3211 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3212 reglist:$regs, variable_ops),
3213 4, IIC_iLoad_mBr, [],
3214 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3215 RegConstraint<"$Rn = $wb">;
3217 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3218 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3221 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3222 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3227 //===----------------------------------------------------------------------===//
3228 // Move Instructions.
3231 let hasSideEffects = 0 in
3232 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3233 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3237 let Inst{19-16} = 0b0000;
3238 let Inst{11-4} = 0b00000000;
3241 let Inst{15-12} = Rd;
3244 // A version for the smaller set of tail call registers.
3245 let hasSideEffects = 0 in
3246 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3247 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3251 let Inst{11-4} = 0b00000000;
3254 let Inst{15-12} = Rd;
3257 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3258 DPSoRegRegFrm, IIC_iMOVsr,
3259 "mov", "\t$Rd, $src",
3260 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3264 let Inst{15-12} = Rd;
3265 let Inst{19-16} = 0b0000;
3266 let Inst{11-8} = src{11-8};
3268 let Inst{6-5} = src{6-5};
3270 let Inst{3-0} = src{3-0};
3274 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3275 DPSoRegImmFrm, IIC_iMOVsr,
3276 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3277 UnaryDP, Sched<[WriteALU]> {
3280 let Inst{15-12} = Rd;
3281 let Inst{19-16} = 0b0000;
3282 let Inst{11-5} = src{11-5};
3284 let Inst{3-0} = src{3-0};
3288 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3289 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3290 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3295 let Inst{15-12} = Rd;
3296 let Inst{19-16} = 0b0000;
3297 let Inst{11-0} = imm;
3300 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3301 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3303 "movw", "\t$Rd, $imm",
3304 [(set GPR:$Rd, imm0_65535:$imm)]>,
3305 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3308 let Inst{15-12} = Rd;
3309 let Inst{11-0} = imm{11-0};
3310 let Inst{19-16} = imm{15-12};
3313 let DecoderMethod = "DecodeArmMOVTWInstruction";
3316 def : InstAlias<"mov${p} $Rd, $imm",
3317 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3320 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3321 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3324 let Constraints = "$src = $Rd" in {
3325 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3326 (ins GPR:$src, imm0_65535_expr:$imm),
3328 "movt", "\t$Rd, $imm",
3330 (or (and GPR:$src, 0xffff),
3331 lo16AllZero:$imm))]>, UnaryDP,
3332 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3335 let Inst{15-12} = Rd;
3336 let Inst{11-0} = imm{11-0};
3337 let Inst{19-16} = imm{15-12};
3340 let DecoderMethod = "DecodeArmMOVTWInstruction";
3343 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3344 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3349 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3350 Requires<[IsARM, HasV6T2]>;
3352 let Uses = [CPSR] in
3353 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3354 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3355 Requires<[IsARM]>, Sched<[WriteALU]>;
3357 // These aren't really mov instructions, but we have to define them this way
3358 // due to flag operands.
3360 let Defs = [CPSR] in {
3361 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3362 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3363 Sched<[WriteALU]>, Requires<[IsARM]>;
3364 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3365 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3366 Sched<[WriteALU]>, Requires<[IsARM]>;
3369 //===----------------------------------------------------------------------===//
3370 // Extend Instructions.
3375 def SXTB : AI_ext_rrot<0b01101010,
3376 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3377 def SXTH : AI_ext_rrot<0b01101011,
3378 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3380 def SXTAB : AI_exta_rrot<0b01101010,
3381 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3382 def SXTAH : AI_exta_rrot<0b01101011,
3383 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3385 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3387 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3391 let AddedComplexity = 16 in {
3392 def UXTB : AI_ext_rrot<0b01101110,
3393 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3394 def UXTH : AI_ext_rrot<0b01101111,
3395 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3396 def UXTB16 : AI_ext_rrot<0b01101100,
3397 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3399 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3400 // The transformation should probably be done as a combiner action
3401 // instead so we can include a check for masking back in the upper
3402 // eight bits of the source into the lower eight bits of the result.
3403 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3404 // (UXTB16r_rot GPR:$Src, 3)>;
3405 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3406 (UXTB16 GPR:$Src, 1)>;
3408 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3409 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3410 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3411 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3414 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3415 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3418 def SBFX : I<(outs GPRnopc:$Rd),
3419 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3420 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3421 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3422 Requires<[IsARM, HasV6T2]> {
3427 let Inst{27-21} = 0b0111101;
3428 let Inst{6-4} = 0b101;
3429 let Inst{20-16} = width;
3430 let Inst{15-12} = Rd;
3431 let Inst{11-7} = lsb;
3435 def UBFX : I<(outs GPRnopc:$Rd),
3436 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3437 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3438 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3439 Requires<[IsARM, HasV6T2]> {
3444 let Inst{27-21} = 0b0111111;
3445 let Inst{6-4} = 0b101;
3446 let Inst{20-16} = width;
3447 let Inst{15-12} = Rd;
3448 let Inst{11-7} = lsb;
3452 //===----------------------------------------------------------------------===//
3453 // Arithmetic Instructions.
3456 defm ADD : AsI1_bin_irs<0b0100, "add",
3457 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3458 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3459 defm SUB : AsI1_bin_irs<0b0010, "sub",
3460 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3461 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3463 // ADD and SUB with 's' bit set.
3465 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3466 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3467 // AdjustInstrPostInstrSelection where we determine whether or not to
3468 // set the "s" bit based on CPSR liveness.
3470 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3471 // support for an optional CPSR definition that corresponds to the DAG
3472 // node's second value. We can then eliminate the implicit def of CPSR.
3473 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3474 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3475 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3476 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3478 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3479 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3480 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3481 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3483 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3484 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3485 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3487 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3488 // CPSR and the implicit def of CPSR is not needed.
3489 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3490 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3492 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3493 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3495 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3496 // The assume-no-carry-in form uses the negation of the input since add/sub
3497 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3498 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3500 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3501 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3502 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3503 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3505 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3506 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3507 Requires<[IsARM, HasV6T2]>;
3508 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3509 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3510 Requires<[IsARM, HasV6T2]>;
3512 // The with-carry-in form matches bitwise not instead of the negation.
3513 // Effectively, the inverse interpretation of the carry flag already accounts
3514 // for part of the negation.
3515 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3516 (SBCri GPR:$src, mod_imm_not:$imm)>;
3517 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3518 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3519 Requires<[IsARM, HasV6T2]>;
3521 // Note: These are implemented in C++ code, because they have to generate
3522 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3524 // (mul X, 2^n+1) -> (add (X << n), X)
3525 // (mul X, 2^n-1) -> (rsb X, (X << n))
3527 // ARM Arithmetic Instruction
3528 // GPR:$dst = GPR:$a op GPR:$b
3529 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3530 list<dag> pattern = [],
3531 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3532 string asm = "\t$Rd, $Rn, $Rm">
3533 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3534 Sched<[WriteALU, ReadALU, ReadALU]> {
3538 let Inst{27-20} = op27_20;
3539 let Inst{11-4} = op11_4;
3540 let Inst{19-16} = Rn;
3541 let Inst{15-12} = Rd;
3544 let Unpredictable{11-8} = 0b1111;
3547 // Saturating add/subtract
3549 let DecoderMethod = "DecodeQADDInstruction" in
3550 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3551 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3552 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3554 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3555 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3556 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3557 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3558 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3560 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3561 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3564 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3565 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3566 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3567 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3568 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3569 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3570 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3571 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3572 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3573 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3574 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3575 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3577 // Signed/Unsigned add/subtract
3579 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3580 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3581 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3582 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3583 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3584 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3585 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3586 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3587 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3588 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3589 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3590 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3592 // Signed/Unsigned halving add/subtract
3594 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3595 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3596 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3597 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3598 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3599 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3600 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3601 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3602 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3603 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3604 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3605 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3607 // Unsigned Sum of Absolute Differences [and Accumulate].
3609 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3610 MulFrm /* for convenience */, NoItinerary, "usad8",
3611 "\t$Rd, $Rn, $Rm", []>,
3612 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3616 let Inst{27-20} = 0b01111000;
3617 let Inst{15-12} = 0b1111;
3618 let Inst{7-4} = 0b0001;
3619 let Inst{19-16} = Rd;
3620 let Inst{11-8} = Rm;
3623 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3624 MulFrm /* for convenience */, NoItinerary, "usada8",
3625 "\t$Rd, $Rn, $Rm, $Ra", []>,
3626 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3631 let Inst{27-20} = 0b01111000;
3632 let Inst{7-4} = 0b0001;
3633 let Inst{19-16} = Rd;
3634 let Inst{15-12} = Ra;
3635 let Inst{11-8} = Rm;
3639 // Signed/Unsigned saturate
3641 def SSAT : AI<(outs GPRnopc:$Rd),
3642 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3643 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3648 let Inst{27-21} = 0b0110101;
3649 let Inst{5-4} = 0b01;
3650 let Inst{20-16} = sat_imm;
3651 let Inst{15-12} = Rd;
3652 let Inst{11-7} = sh{4-0};
3653 let Inst{6} = sh{5};
3657 def SSAT16 : AI<(outs GPRnopc:$Rd),
3658 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3659 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3663 let Inst{27-20} = 0b01101010;
3664 let Inst{11-4} = 0b11110011;
3665 let Inst{15-12} = Rd;
3666 let Inst{19-16} = sat_imm;
3670 def USAT : AI<(outs GPRnopc:$Rd),
3671 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3672 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3677 let Inst{27-21} = 0b0110111;
3678 let Inst{5-4} = 0b01;
3679 let Inst{15-12} = Rd;
3680 let Inst{11-7} = sh{4-0};
3681 let Inst{6} = sh{5};
3682 let Inst{20-16} = sat_imm;
3686 def USAT16 : AI<(outs GPRnopc:$Rd),
3687 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3688 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3692 let Inst{27-20} = 0b01101110;
3693 let Inst{11-4} = 0b11110011;
3694 let Inst{15-12} = Rd;
3695 let Inst{19-16} = sat_imm;
3699 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
3700 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
3701 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
3702 (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
3704 //===----------------------------------------------------------------------===//
3705 // Bitwise Instructions.
3708 defm AND : AsI1_bin_irs<0b0000, "and",
3709 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3710 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3711 defm ORR : AsI1_bin_irs<0b1100, "orr",
3712 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3713 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3714 defm EOR : AsI1_bin_irs<0b0001, "eor",
3715 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3716 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3717 defm BIC : AsI1_bin_irs<0b1110, "bic",
3718 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3719 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3721 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3722 // like in the actual instruction encoding. The complexity of mapping the mask
3723 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3724 // instruction description.
3725 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3726 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3727 "bfc", "\t$Rd, $imm", "$src = $Rd",
3728 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3729 Requires<[IsARM, HasV6T2]> {
3732 let Inst{27-21} = 0b0111110;
3733 let Inst{6-0} = 0b0011111;
3734 let Inst{15-12} = Rd;
3735 let Inst{11-7} = imm{4-0}; // lsb
3736 let Inst{20-16} = imm{9-5}; // msb
3739 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3740 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3741 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3742 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3743 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3744 bf_inv_mask_imm:$imm))]>,
3745 Requires<[IsARM, HasV6T2]> {
3749 let Inst{27-21} = 0b0111110;
3750 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3751 let Inst{15-12} = Rd;
3752 let Inst{11-7} = imm{4-0}; // lsb
3753 let Inst{20-16} = imm{9-5}; // width
3757 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3758 "mvn", "\t$Rd, $Rm",
3759 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3763 let Inst{19-16} = 0b0000;
3764 let Inst{11-4} = 0b00000000;
3765 let Inst{15-12} = Rd;
3768 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3769 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3770 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3775 let Inst{19-16} = 0b0000;
3776 let Inst{15-12} = Rd;
3777 let Inst{11-5} = shift{11-5};
3779 let Inst{3-0} = shift{3-0};
3781 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3782 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3783 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3788 let Inst{19-16} = 0b0000;
3789 let Inst{15-12} = Rd;
3790 let Inst{11-8} = shift{11-8};
3792 let Inst{6-5} = shift{6-5};
3794 let Inst{3-0} = shift{3-0};
3796 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3797 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3798 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3799 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3803 let Inst{19-16} = 0b0000;
3804 let Inst{15-12} = Rd;
3805 let Inst{11-0} = imm;
3808 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3809 (BICri GPR:$src, mod_imm_not:$imm)>;
3811 //===----------------------------------------------------------------------===//
3812 // Multiply Instructions.
3814 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3815 string opc, string asm, list<dag> pattern>
3816 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3820 let Inst{19-16} = Rd;
3821 let Inst{11-8} = Rm;
3824 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3825 string opc, string asm, list<dag> pattern>
3826 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3831 let Inst{19-16} = RdHi;
3832 let Inst{15-12} = RdLo;
3833 let Inst{11-8} = Rm;
3836 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3837 string opc, string asm, list<dag> pattern>
3838 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3843 let Inst{19-16} = RdHi;
3844 let Inst{15-12} = RdLo;
3845 let Inst{11-8} = Rm;
3849 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3850 // property. Remove them when it's possible to add those properties
3851 // on an individual MachineInstr, not just an instruction description.
3852 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3853 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3854 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3855 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3856 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3857 Requires<[IsARM, HasV6]> {
3858 let Inst{15-12} = 0b0000;
3859 let Unpredictable{15-12} = 0b1111;
3862 let Constraints = "@earlyclobber $Rd" in
3863 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3864 pred:$p, cc_out:$s),
3866 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3867 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3868 Requires<[IsARM, NoV6, UseMulOps]>;
3871 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3872 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3873 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3874 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3875 Requires<[IsARM, HasV6, UseMulOps]> {
3877 let Inst{15-12} = Ra;
3880 let Constraints = "@earlyclobber $Rd" in
3881 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3882 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3883 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3884 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3885 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3886 Requires<[IsARM, NoV6]>;
3888 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3889 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3890 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3891 Requires<[IsARM, HasV6T2, UseMulOps]> {
3896 let Inst{19-16} = Rd;
3897 let Inst{15-12} = Ra;
3898 let Inst{11-8} = Rm;
3902 // Extra precision multiplies with low / high results
3903 let hasSideEffects = 0 in {
3904 let isCommutable = 1 in {
3905 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3906 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3907 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3908 Requires<[IsARM, HasV6]>;
3910 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3911 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3912 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3913 Requires<[IsARM, HasV6]>;
3915 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3916 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3917 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3919 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3920 Requires<[IsARM, NoV6]>;
3922 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3923 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3925 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3926 Requires<[IsARM, NoV6]>;
3930 // Multiply + accumulate
3931 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3932 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3933 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3934 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3935 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3936 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3937 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3938 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3940 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3941 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3942 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3943 Requires<[IsARM, HasV6]> {
3948 let Inst{19-16} = RdHi;
3949 let Inst{15-12} = RdLo;
3950 let Inst{11-8} = Rm;
3955 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3956 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3957 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3959 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3960 pred:$p, cc_out:$s)>,
3961 Requires<[IsARM, NoV6]>;
3962 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3963 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3965 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3966 pred:$p, cc_out:$s)>,
3967 Requires<[IsARM, NoV6]>;
3972 // Most significant word multiply
3973 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3974 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3975 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3976 Requires<[IsARM, HasV6]> {
3977 let Inst{15-12} = 0b1111;
3980 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3981 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3982 Requires<[IsARM, HasV6]> {
3983 let Inst{15-12} = 0b1111;
3986 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3987 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3988 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3989 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3990 Requires<[IsARM, HasV6, UseMulOps]>;
3992 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3993 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3994 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3995 Requires<[IsARM, HasV6]>;
3997 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3998 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3999 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4000 Requires<[IsARM, HasV6, UseMulOps]>;
4002 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
4003 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4004 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
4005 Requires<[IsARM, HasV6]>;
4007 multiclass AI_smul<string opc, PatFrag opnode> {
4008 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4009 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4010 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
4011 (sext_inreg GPR:$Rm, i16)))]>,
4012 Requires<[IsARM, HasV5TE]>;
4014 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4015 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4016 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
4017 (sra GPR:$Rm, (i32 16))))]>,
4018 Requires<[IsARM, HasV5TE]>;
4020 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4021 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4022 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4023 (sext_inreg GPR:$Rm, i16)))]>,
4024 Requires<[IsARM, HasV5TE]>;
4026 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4027 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4028 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4029 (sra GPR:$Rm, (i32 16))))]>,
4030 Requires<[IsARM, HasV5TE]>;
4032 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4033 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4035 Requires<[IsARM, HasV5TE]>;
4037 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4038 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4040 Requires<[IsARM, HasV5TE]>;
4044 multiclass AI_smla<string opc, PatFrag opnode> {
4045 let DecoderMethod = "DecodeSMLAInstruction" in {
4046 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4047 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4048 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4049 [(set GPRnopc:$Rd, (add GPR:$Ra,
4050 (opnode (sext_inreg GPRnopc:$Rn, i16),
4051 (sext_inreg GPRnopc:$Rm, i16))))]>,
4052 Requires<[IsARM, HasV5TE, UseMulOps]>;
4054 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4055 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4056 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4058 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4059 (sra GPRnopc:$Rm, (i32 16)))))]>,
4060 Requires<[IsARM, HasV5TE, UseMulOps]>;
4062 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4063 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4064 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4066 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4067 (sext_inreg GPRnopc:$Rm, i16))))]>,
4068 Requires<[IsARM, HasV5TE, UseMulOps]>;
4070 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4071 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4072 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4074 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4075 (sra GPRnopc:$Rm, (i32 16)))))]>,
4076 Requires<[IsARM, HasV5TE, UseMulOps]>;
4078 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4079 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4080 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4082 Requires<[IsARM, HasV5TE, UseMulOps]>;
4084 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4085 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4086 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4088 Requires<[IsARM, HasV5TE, UseMulOps]>;
4092 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4093 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4095 // Halfword multiply accumulate long: SMLAL<x><y>.
4096 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4097 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4098 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4099 Requires<[IsARM, HasV5TE]>;
4101 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4102 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4103 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4104 Requires<[IsARM, HasV5TE]>;
4106 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4107 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4108 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4109 Requires<[IsARM, HasV5TE]>;
4111 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4112 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4113 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4114 Requires<[IsARM, HasV5TE]>;
4116 // Helper class for AI_smld.
4117 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4118 InstrItinClass itin, string opc, string asm>
4119 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4122 let Inst{27-23} = 0b01110;
4123 let Inst{22} = long;
4124 let Inst{21-20} = 0b00;
4125 let Inst{11-8} = Rm;
4132 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4133 InstrItinClass itin, string opc, string asm>
4134 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4136 let Inst{15-12} = 0b1111;
4137 let Inst{19-16} = Rd;
4139 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4140 InstrItinClass itin, string opc, string asm>
4141 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4144 let Inst{19-16} = Rd;
4145 let Inst{15-12} = Ra;
4147 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4148 InstrItinClass itin, string opc, string asm>
4149 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4152 let Inst{19-16} = RdHi;
4153 let Inst{15-12} = RdLo;
4156 multiclass AI_smld<bit sub, string opc> {
4158 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4159 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4160 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4162 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4163 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4164 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4166 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4167 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4168 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4170 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4171 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4172 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4176 defm SMLA : AI_smld<0, "smla">;
4177 defm SMLS : AI_smld<1, "smls">;
4179 multiclass AI_sdml<bit sub, string opc> {
4181 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4182 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4183 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4184 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4187 defm SMUA : AI_sdml<0, "smua">;
4188 defm SMUS : AI_sdml<1, "smus">;
4190 //===----------------------------------------------------------------------===//
4191 // Division Instructions (ARMv7-A with virtualization extension)
4193 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4194 "sdiv", "\t$Rd, $Rn, $Rm",
4195 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4196 Requires<[IsARM, HasDivideInARM]>;
4198 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4199 "udiv", "\t$Rd, $Rn, $Rm",
4200 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4201 Requires<[IsARM, HasDivideInARM]>;
4203 //===----------------------------------------------------------------------===//
4204 // Misc. Arithmetic Instructions.
4207 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4208 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4209 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4212 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4213 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4214 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4215 Requires<[IsARM, HasV6T2]>,
4218 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4219 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4220 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4223 let AddedComplexity = 5 in
4224 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4225 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4226 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4227 Requires<[IsARM, HasV6]>,
4230 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4231 (REV16 (LDRH addrmode3:$addr))>;
4232 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4233 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4235 let AddedComplexity = 5 in
4236 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4237 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4238 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4239 Requires<[IsARM, HasV6]>,
4242 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4243 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4246 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4247 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4248 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4249 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4250 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4252 Requires<[IsARM, HasV6]>,
4253 Sched<[WriteALUsi, ReadALU]>;
4255 // Alternate cases for PKHBT where identities eliminate some nodes.
4256 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4257 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4258 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4259 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4261 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4262 // will match the pattern below.
4263 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4264 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4265 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4266 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4267 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4269 Requires<[IsARM, HasV6]>,
4270 Sched<[WriteALUsi, ReadALU]>;
4272 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4273 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4274 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4275 // pkhtb src1, src2, asr (17..31).
4276 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4277 (srl GPRnopc:$src2, imm16:$sh)),
4278 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4279 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4280 (sra GPRnopc:$src2, imm16_31:$sh)),
4281 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4282 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4283 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4284 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4286 //===----------------------------------------------------------------------===//
4290 // + CRC32{B,H,W} 0x04C11DB7
4291 // + CRC32C{B,H,W} 0x1EDC6F41
4294 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4295 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4296 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4297 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4298 Requires<[IsARM, HasV8, HasCRC]> {
4303 let Inst{31-28} = 0b1110;
4304 let Inst{27-23} = 0b00010;
4305 let Inst{22-21} = sz;
4307 let Inst{19-16} = Rn;
4308 let Inst{15-12} = Rd;
4309 let Inst{11-10} = 0b00;
4312 let Inst{7-4} = 0b0100;
4315 let Unpredictable{11-8} = 0b1101;
4318 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4319 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4320 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4321 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4322 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4323 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4325 //===----------------------------------------------------------------------===//
4326 // ARMv8.1a Privilege Access Never extension
4330 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4331 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4334 let Inst{31-28} = 0b1111;
4335 let Inst{27-20} = 0b00010001;
4336 let Inst{19-16} = 0b0000;
4337 let Inst{15-10} = 0b000000;
4340 let Inst{7-4} = 0b0000;
4341 let Inst{3-0} = 0b0000;
4343 let Unpredictable{19-16} = 0b1111;
4344 let Unpredictable{15-10} = 0b111111;
4345 let Unpredictable{8} = 0b1;
4346 let Unpredictable{3-0} = 0b1111;
4349 //===----------------------------------------------------------------------===//
4350 // Comparison Instructions...
4353 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4354 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4355 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4357 // ARMcmpZ can re-use the above instruction definitions.
4358 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4359 (CMPri GPR:$src, mod_imm:$imm)>;
4360 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4361 (CMPrr GPR:$src, GPR:$rhs)>;
4362 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4363 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4364 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4365 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4367 // CMN register-integer
4368 let isCompare = 1, Defs = [CPSR] in {
4369 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4370 "cmn", "\t$Rn, $imm",
4371 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4372 Sched<[WriteCMP, ReadALU]> {
4377 let Inst{19-16} = Rn;
4378 let Inst{15-12} = 0b0000;
4379 let Inst{11-0} = imm;
4381 let Unpredictable{15-12} = 0b1111;
4384 // CMN register-register/shift
4385 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4386 "cmn", "\t$Rn, $Rm",
4387 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4388 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4391 let isCommutable = 1;
4394 let Inst{19-16} = Rn;
4395 let Inst{15-12} = 0b0000;
4396 let Inst{11-4} = 0b00000000;
4399 let Unpredictable{15-12} = 0b1111;
4402 def CMNzrsi : AI1<0b1011, (outs),
4403 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4404 "cmn", "\t$Rn, $shift",
4405 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4406 GPR:$Rn, so_reg_imm:$shift)]>,
4407 Sched<[WriteCMPsi, ReadALU]> {
4412 let Inst{19-16} = Rn;
4413 let Inst{15-12} = 0b0000;
4414 let Inst{11-5} = shift{11-5};
4416 let Inst{3-0} = shift{3-0};
4418 let Unpredictable{15-12} = 0b1111;
4421 def CMNzrsr : AI1<0b1011, (outs),
4422 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4423 "cmn", "\t$Rn, $shift",
4424 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4425 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4426 Sched<[WriteCMPsr, ReadALU]> {
4431 let Inst{19-16} = Rn;
4432 let Inst{15-12} = 0b0000;
4433 let Inst{11-8} = shift{11-8};
4435 let Inst{6-5} = shift{6-5};
4437 let Inst{3-0} = shift{3-0};
4439 let Unpredictable{15-12} = 0b1111;
4444 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4445 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4447 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4448 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4450 // Note that TST/TEQ don't set all the same flags that CMP does!
4451 defm TST : AI1_cmp_irs<0b1000, "tst",
4452 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4453 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4454 "DecodeTSTInstruction">;
4455 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4456 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4457 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4459 // Pseudo i64 compares for some floating point compares.
4460 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4462 def BCCi64 : PseudoInst<(outs),
4463 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4465 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4468 def BCCZi64 : PseudoInst<(outs),
4469 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4470 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4472 } // usesCustomInserter
4475 // Conditional moves
4476 let hasSideEffects = 0 in {
4478 let isCommutable = 1, isSelect = 1 in
4479 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4480 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4482 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4484 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4486 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4487 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4490 (ARMcmov GPR:$false, so_reg_imm:$shift,
4492 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4493 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4494 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4496 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4498 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4501 let isMoveImm = 1 in
4503 : ARMPseudoInst<(outs GPR:$Rd),
4504 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4506 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4508 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4511 let isMoveImm = 1 in
4512 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4513 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4515 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4517 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4519 // Two instruction predicate mov immediate.
4520 let isMoveImm = 1 in
4522 : ARMPseudoInst<(outs GPR:$Rd),
4523 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4525 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4527 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4529 let isMoveImm = 1 in
4530 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4531 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4533 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4535 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4540 //===----------------------------------------------------------------------===//
4541 // Atomic operations intrinsics
4544 def MemBarrierOptOperand : AsmOperandClass {
4545 let Name = "MemBarrierOpt";
4546 let ParserMethod = "parseMemBarrierOptOperand";
4548 def memb_opt : Operand<i32> {
4549 let PrintMethod = "printMemBOption";
4550 let ParserMatchClass = MemBarrierOptOperand;
4551 let DecoderMethod = "DecodeMemBarrierOption";
4554 def InstSyncBarrierOptOperand : AsmOperandClass {
4555 let Name = "InstSyncBarrierOpt";
4556 let ParserMethod = "parseInstSyncBarrierOptOperand";
4558 def instsyncb_opt : Operand<i32> {
4559 let PrintMethod = "printInstSyncBOption";
4560 let ParserMatchClass = InstSyncBarrierOptOperand;
4561 let DecoderMethod = "DecodeInstSyncBarrierOption";
4564 // Memory barriers protect the atomic sequences
4565 let hasSideEffects = 1 in {
4566 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4567 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4568 Requires<[IsARM, HasDB]> {
4570 let Inst{31-4} = 0xf57ff05;
4571 let Inst{3-0} = opt;
4574 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4575 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4576 Requires<[IsARM, HasDB]> {
4578 let Inst{31-4} = 0xf57ff04;
4579 let Inst{3-0} = opt;
4582 // ISB has only full system option
4583 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4584 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4585 Requires<[IsARM, HasDB]> {
4587 let Inst{31-4} = 0xf57ff06;
4588 let Inst{3-0} = opt;
4592 let usesCustomInserter = 1, Defs = [CPSR] in {
4594 // Pseudo instruction that combines movs + predicated rsbmi
4595 // to implement integer ABS
4596 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4599 let usesCustomInserter = 1 in {
4600 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4601 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4603 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4606 let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in {
4607 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs...
4608 // Copies N registers worth of memory from address %src to address %dst
4609 // and returns the incremented addresses. N scratch register will
4610 // be attached for the copy to use.
4611 def MEMCPY : PseudoInst<
4612 (outs GPR:$newdst, GPR:$newsrc),
4613 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
4615 [(set GPR:$newdst, GPR:$newsrc,
4616 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4619 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4620 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4623 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4624 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4627 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4628 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4631 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4632 (int_arm_strex node:$val, node:$ptr), [{
4633 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4636 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4637 (int_arm_strex node:$val, node:$ptr), [{
4638 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4641 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4642 (int_arm_strex node:$val, node:$ptr), [{
4643 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4646 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4647 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4650 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4651 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4654 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4655 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4658 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4659 (int_arm_stlex node:$val, node:$ptr), [{
4660 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4663 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4664 (int_arm_stlex node:$val, node:$ptr), [{
4665 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4668 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4669 (int_arm_stlex node:$val, node:$ptr), [{
4670 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4673 let mayLoad = 1 in {
4674 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4675 NoItinerary, "ldrexb", "\t$Rt, $addr",
4676 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4677 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4678 NoItinerary, "ldrexh", "\t$Rt, $addr",
4679 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4680 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4681 NoItinerary, "ldrex", "\t$Rt, $addr",
4682 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4683 let hasExtraDefRegAllocReq = 1 in
4684 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4685 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4686 let DecoderMethod = "DecodeDoubleRegLoad";
4689 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4690 NoItinerary, "ldaexb", "\t$Rt, $addr",
4691 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4692 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4693 NoItinerary, "ldaexh", "\t$Rt, $addr",
4694 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4695 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4696 NoItinerary, "ldaex", "\t$Rt, $addr",
4697 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4698 let hasExtraDefRegAllocReq = 1 in
4699 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4700 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4701 let DecoderMethod = "DecodeDoubleRegLoad";
4705 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4706 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4707 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4708 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4709 addr_offset_none:$addr))]>;
4710 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4711 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4712 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4713 addr_offset_none:$addr))]>;
4714 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4715 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4716 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4717 addr_offset_none:$addr))]>;
4718 let hasExtraSrcRegAllocReq = 1 in
4719 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4720 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4721 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4722 let DecoderMethod = "DecodeDoubleRegStore";
4724 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4725 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4727 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4728 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4729 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4731 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4732 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4733 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4735 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4736 let hasExtraSrcRegAllocReq = 1 in
4737 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4738 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4739 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4740 let DecoderMethod = "DecodeDoubleRegStore";
4744 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4746 Requires<[IsARM, HasV7]> {
4747 let Inst{31-0} = 0b11110101011111111111000000011111;
4750 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4751 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4752 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4753 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4755 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4756 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4757 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4758 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4760 class acquiring_load<PatFrag base>
4761 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4762 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4763 return isAtLeastAcquire(Ordering);
4766 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4767 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4768 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4770 class releasing_store<PatFrag base>
4771 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4772 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4773 return isAtLeastRelease(Ordering);
4776 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4777 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4778 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4780 let AddedComplexity = 8 in {
4781 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4782 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4783 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4784 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4785 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4786 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4789 // SWP/SWPB are deprecated in V6/V7.
4790 let mayLoad = 1, mayStore = 1 in {
4791 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4792 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4794 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4795 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4799 //===----------------------------------------------------------------------===//
4800 // Coprocessor Instructions.
4803 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4804 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4805 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4806 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4807 imm:$CRm, imm:$opc2)]>,
4816 let Inst{3-0} = CRm;
4818 let Inst{7-5} = opc2;
4819 let Inst{11-8} = cop;
4820 let Inst{15-12} = CRd;
4821 let Inst{19-16} = CRn;
4822 let Inst{23-20} = opc1;
4825 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4826 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4827 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4828 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4829 imm:$CRm, imm:$opc2)]>,
4831 let Inst{31-28} = 0b1111;
4839 let Inst{3-0} = CRm;
4841 let Inst{7-5} = opc2;
4842 let Inst{11-8} = cop;
4843 let Inst{15-12} = CRd;
4844 let Inst{19-16} = CRn;
4845 let Inst{23-20} = opc1;
4848 class ACI<dag oops, dag iops, string opc, string asm,
4849 IndexMode im = IndexModeNone>
4850 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4852 let Inst{27-25} = 0b110;
4854 class ACInoP<dag oops, dag iops, string opc, string asm,
4855 IndexMode im = IndexModeNone>
4856 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4858 let Inst{31-28} = 0b1111;
4859 let Inst{27-25} = 0b110;
4861 multiclass LdStCop<bit load, bit Dbit, string asm> {
4862 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4863 asm, "\t$cop, $CRd, $addr"> {
4867 let Inst{24} = 1; // P = 1
4868 let Inst{23} = addr{8};
4869 let Inst{22} = Dbit;
4870 let Inst{21} = 0; // W = 0
4871 let Inst{20} = load;
4872 let Inst{19-16} = addr{12-9};
4873 let Inst{15-12} = CRd;
4874 let Inst{11-8} = cop;
4875 let Inst{7-0} = addr{7-0};
4876 let DecoderMethod = "DecodeCopMemInstruction";
4878 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4879 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4883 let Inst{24} = 1; // P = 1
4884 let Inst{23} = addr{8};
4885 let Inst{22} = Dbit;
4886 let Inst{21} = 1; // W = 1
4887 let Inst{20} = load;
4888 let Inst{19-16} = addr{12-9};
4889 let Inst{15-12} = CRd;
4890 let Inst{11-8} = cop;
4891 let Inst{7-0} = addr{7-0};
4892 let DecoderMethod = "DecodeCopMemInstruction";
4894 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4895 postidx_imm8s4:$offset),
4896 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4901 let Inst{24} = 0; // P = 0
4902 let Inst{23} = offset{8};
4903 let Inst{22} = Dbit;
4904 let Inst{21} = 1; // W = 1
4905 let Inst{20} = load;
4906 let Inst{19-16} = addr;
4907 let Inst{15-12} = CRd;
4908 let Inst{11-8} = cop;
4909 let Inst{7-0} = offset{7-0};
4910 let DecoderMethod = "DecodeCopMemInstruction";
4912 def _OPTION : ACI<(outs),
4913 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4914 coproc_option_imm:$option),
4915 asm, "\t$cop, $CRd, $addr, $option"> {
4920 let Inst{24} = 0; // P = 0
4921 let Inst{23} = 1; // U = 1
4922 let Inst{22} = Dbit;
4923 let Inst{21} = 0; // W = 0
4924 let Inst{20} = load;
4925 let Inst{19-16} = addr;
4926 let Inst{15-12} = CRd;
4927 let Inst{11-8} = cop;
4928 let Inst{7-0} = option;
4929 let DecoderMethod = "DecodeCopMemInstruction";
4932 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4933 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4934 asm, "\t$cop, $CRd, $addr"> {
4938 let Inst{24} = 1; // P = 1
4939 let Inst{23} = addr{8};
4940 let Inst{22} = Dbit;
4941 let Inst{21} = 0; // W = 0
4942 let Inst{20} = load;
4943 let Inst{19-16} = addr{12-9};
4944 let Inst{15-12} = CRd;
4945 let Inst{11-8} = cop;
4946 let Inst{7-0} = addr{7-0};
4947 let DecoderMethod = "DecodeCopMemInstruction";
4949 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4950 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4954 let Inst{24} = 1; // P = 1
4955 let Inst{23} = addr{8};
4956 let Inst{22} = Dbit;
4957 let Inst{21} = 1; // W = 1
4958 let Inst{20} = load;
4959 let Inst{19-16} = addr{12-9};
4960 let Inst{15-12} = CRd;
4961 let Inst{11-8} = cop;
4962 let Inst{7-0} = addr{7-0};
4963 let DecoderMethod = "DecodeCopMemInstruction";
4965 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4966 postidx_imm8s4:$offset),
4967 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4972 let Inst{24} = 0; // P = 0
4973 let Inst{23} = offset{8};
4974 let Inst{22} = Dbit;
4975 let Inst{21} = 1; // W = 1
4976 let Inst{20} = load;
4977 let Inst{19-16} = addr;
4978 let Inst{15-12} = CRd;
4979 let Inst{11-8} = cop;
4980 let Inst{7-0} = offset{7-0};
4981 let DecoderMethod = "DecodeCopMemInstruction";
4983 def _OPTION : ACInoP<(outs),
4984 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4985 coproc_option_imm:$option),
4986 asm, "\t$cop, $CRd, $addr, $option"> {
4991 let Inst{24} = 0; // P = 0
4992 let Inst{23} = 1; // U = 1
4993 let Inst{22} = Dbit;
4994 let Inst{21} = 0; // W = 0
4995 let Inst{20} = load;
4996 let Inst{19-16} = addr;
4997 let Inst{15-12} = CRd;
4998 let Inst{11-8} = cop;
4999 let Inst{7-0} = option;
5000 let DecoderMethod = "DecodeCopMemInstruction";
5004 defm LDC : LdStCop <1, 0, "ldc">;
5005 defm LDCL : LdStCop <1, 1, "ldcl">;
5006 defm STC : LdStCop <0, 0, "stc">;
5007 defm STCL : LdStCop <0, 1, "stcl">;
5008 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
5009 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
5010 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
5011 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
5013 //===----------------------------------------------------------------------===//
5014 // Move between coprocessor and ARM core register.
5017 class MovRCopro<string opc, bit direction, dag oops, dag iops,
5019 : ABI<0b1110, oops, iops, NoItinerary, opc,
5020 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
5021 let Inst{20} = direction;
5031 let Inst{15-12} = Rt;
5032 let Inst{11-8} = cop;
5033 let Inst{23-21} = opc1;
5034 let Inst{7-5} = opc2;
5035 let Inst{3-0} = CRm;
5036 let Inst{19-16} = CRn;
5039 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5041 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5042 c_imm:$CRm, imm0_7:$opc2),
5043 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5044 imm:$CRm, imm:$opc2)]>,
5045 ComplexDeprecationPredicate<"MCR">;
5046 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5047 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5048 c_imm:$CRm, 0, pred:$p)>;
5049 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5050 (outs GPRwithAPSR:$Rt),
5051 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5053 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5054 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5055 c_imm:$CRm, 0, pred:$p)>;
5057 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5058 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5060 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5062 : ABXI<0b1110, oops, iops, NoItinerary,
5063 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5064 let Inst{31-24} = 0b11111110;
5065 let Inst{20} = direction;
5075 let Inst{15-12} = Rt;
5076 let Inst{11-8} = cop;
5077 let Inst{23-21} = opc1;
5078 let Inst{7-5} = opc2;
5079 let Inst{3-0} = CRm;
5080 let Inst{19-16} = CRn;
5083 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5085 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5086 c_imm:$CRm, imm0_7:$opc2),
5087 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5088 imm:$CRm, imm:$opc2)]>,
5090 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5091 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5093 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5094 (outs GPRwithAPSR:$Rt),
5095 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5098 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5099 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5102 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5103 imm:$CRm, imm:$opc2),
5104 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5106 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5108 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5111 let Inst{23-21} = 0b010;
5112 let Inst{20} = direction;
5120 let Inst{15-12} = Rt;
5121 let Inst{19-16} = Rt2;
5122 let Inst{11-8} = cop;
5123 let Inst{7-4} = opc1;
5124 let Inst{3-0} = CRm;
5127 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5128 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5129 GPRnopc:$Rt2, c_imm:$CRm),
5130 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5131 GPRnopc:$Rt2, imm:$CRm)]>;
5132 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5133 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5134 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5136 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5137 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5138 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5139 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5141 let Inst{31-28} = 0b1111;
5142 let Inst{23-21} = 0b010;
5143 let Inst{20} = direction;
5151 let Inst{15-12} = Rt;
5152 let Inst{19-16} = Rt2;
5153 let Inst{11-8} = cop;
5154 let Inst{7-4} = opc1;
5155 let Inst{3-0} = CRm;
5157 let DecoderMethod = "DecodeMRRC2";
5160 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5161 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5162 GPRnopc:$Rt2, imm:$CRm)]>;
5163 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5165 //===----------------------------------------------------------------------===//
5166 // Move between special register and ARM core register
5169 // Move to ARM core register from Special Register
5170 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5171 "mrs", "\t$Rd, apsr", []> {
5173 let Inst{23-16} = 0b00001111;
5174 let Unpredictable{19-17} = 0b111;
5176 let Inst{15-12} = Rd;
5178 let Inst{11-0} = 0b000000000000;
5179 let Unpredictable{11-0} = 0b110100001111;
5182 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5185 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5186 // section B9.3.9, with the R bit set to 1.
5187 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5188 "mrs", "\t$Rd, spsr", []> {
5190 let Inst{23-16} = 0b01001111;
5191 let Unpredictable{19-16} = 0b1111;
5193 let Inst{15-12} = Rd;
5195 let Inst{11-0} = 0b000000000000;
5196 let Unpredictable{11-0} = 0b110100001111;
5199 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5200 // separate encoding (distinguished by bit 5.
5201 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5202 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5203 Requires<[IsARM, HasVirtualization]> {
5208 let Inst{22} = banked{5}; // R bit
5209 let Inst{21-20} = 0b00;
5210 let Inst{19-16} = banked{3-0};
5211 let Inst{15-12} = Rd;
5212 let Inst{11-9} = 0b001;
5213 let Inst{8} = banked{4};
5214 let Inst{7-0} = 0b00000000;
5217 // Move from ARM core register to Special Register
5219 // No need to have both system and application versions of MSR (immediate) or
5220 // MSR (register), the encodings are the same and the assembly parser has no way
5221 // to distinguish between them. The mask operand contains the special register
5222 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5223 // accessed in the special register.
5224 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5225 "msr", "\t$mask, $Rn", []> {
5230 let Inst{22} = mask{4}; // R bit
5231 let Inst{21-20} = 0b10;
5232 let Inst{19-16} = mask{3-0};
5233 let Inst{15-12} = 0b1111;
5234 let Inst{11-4} = 0b00000000;
5238 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5239 "msr", "\t$mask, $imm", []> {
5244 let Inst{22} = mask{4}; // R bit
5245 let Inst{21-20} = 0b10;
5246 let Inst{19-16} = mask{3-0};
5247 let Inst{15-12} = 0b1111;
5248 let Inst{11-0} = imm;
5251 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5252 // separate encoding (distinguished by bit 5.
5253 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5254 NoItinerary, "msr", "\t$banked, $Rn", []>,
5255 Requires<[IsARM, HasVirtualization]> {
5260 let Inst{22} = banked{5}; // R bit
5261 let Inst{21-20} = 0b10;
5262 let Inst{19-16} = banked{3-0};
5263 let Inst{15-12} = 0b1111;
5264 let Inst{11-9} = 0b001;
5265 let Inst{8} = banked{4};
5266 let Inst{7-4} = 0b0000;
5270 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5271 // are needed to probe the stack when allocating more than
5272 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5273 // ensure that the guard pages used by the OS virtual memory manager are
5274 // allocated in correct sequence.
5275 // The main point of having separate instruction are extra unmodelled effects
5276 // (compared to ordinary calls) like stack pointer change.
5278 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5279 [SDNPHasChain, SDNPSideEffect]>;
5280 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5281 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5283 def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK,
5284 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
5285 let usesCustomInserter = 1, Defs = [CPSR] in
5286 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary,
5287 [(win__dbzchk GPR:$divisor)]>;
5289 //===----------------------------------------------------------------------===//
5293 // __aeabi_read_tp preserves the registers r1-r3.
5294 // This is a pseudo inst so that we can get the encoding right,
5295 // complete with fixup for the aeabi_read_tp function.
5296 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5297 // is defined in "ARMInstrThumb.td".
5299 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5300 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5301 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5304 //===----------------------------------------------------------------------===//
5305 // SJLJ Exception handling intrinsics
5306 // eh_sjlj_setjmp() is an instruction sequence to store the return
5307 // address and save #0 in R0 for the non-longjmp case.
5308 // Since by its nature we may be coming from some other function to get
5309 // here, and we're using the stack frame for the containing function to
5310 // save/restore registers, we can't keep anything live in regs across
5311 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5312 // when we get here from a longjmp(). We force everything out of registers
5313 // except for our own input by listing the relevant registers in Defs. By
5314 // doing so, we also cause the prologue/epilogue code to actively preserve
5315 // all of the callee-saved resgisters, which is exactly what we want.
5316 // A constant value is passed in $val, and we use the location as a scratch.
5318 // These are pseudo-instructions and are lowered to individual MC-insts, so
5319 // no encoding information is necessary.
5321 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5322 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5323 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5324 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5326 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5327 Requires<[IsARM, HasVFP2]>;
5331 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5332 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5333 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5335 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5336 Requires<[IsARM, NoVFP]>;
5339 // FIXME: Non-IOS version(s)
5340 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5341 Defs = [ R7, LR, SP ] in {
5342 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5344 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5348 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
5349 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
5350 [(ARMeh_sjlj_setup_dispatch)]>;
5352 // eh.sjlj.dispatchsetup pseudo-instruction.
5353 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5354 // the pseudo is expanded (which happens before any passes that need the
5355 // instruction size).
5356 let isBarrier = 1 in
5357 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5360 //===----------------------------------------------------------------------===//
5361 // Non-Instruction Patterns
5364 // ARMv4 indirect branch using (MOVr PC, dst)
5365 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5366 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5367 4, IIC_Br, [(brind GPR:$dst)],
5368 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5369 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5371 // Large immediate handling.
5373 // 32-bit immediate using two piece mod_imms or movw + movt.
5374 // This is a single pseudo instruction, the benefit is that it can be remat'd
5375 // as a single unit instead of having to handle reg inputs.
5376 // FIXME: Remove this when we can do generalized remat.
5377 let isReMaterializable = 1, isMoveImm = 1 in
5378 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5379 [(set GPR:$dst, (arm_i32imm:$src))]>,
5382 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5383 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5384 Requires<[IsARM, DontUseMovt]>;
5386 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5387 // It also makes it possible to rematerialize the instructions.
5388 // FIXME: Remove this when we can do generalized remat and when machine licm
5389 // can properly the instructions.
5390 let isReMaterializable = 1 in {
5391 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5393 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5394 Requires<[IsARM, UseMovt]>;
5396 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5399 (ARMWrapperPIC tglobaladdr:$addr))]>,
5400 Requires<[IsARM, DontUseMovt]>;
5402 let AddedComplexity = 10 in
5403 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5406 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5407 Requires<[IsARM, DontUseMovt]>;
5409 let AddedComplexity = 10 in
5410 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5412 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5413 Requires<[IsARM, UseMovt]>;
5414 } // isReMaterializable
5416 // ConstantPool, GlobalAddress, and JumpTable
5417 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5418 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5419 Requires<[IsARM, UseMovt]>;
5420 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5421 (LEApcrelJT tjumptable:$dst)>;
5423 // TODO: add,sub,and, 3-instr forms?
5425 // Tail calls. These patterns also apply to Thumb mode.
5426 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5427 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5428 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5431 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5432 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5433 (BMOVPCB_CALL texternalsym:$func)>;
5435 // zextload i1 -> zextload i8
5436 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5437 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5439 // extload -> zextload
5440 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5441 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5442 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5443 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5445 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5447 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5448 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5451 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5452 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5453 (SMULBB GPR:$a, GPR:$b)>;
5454 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5455 (SMULBB GPR:$a, GPR:$b)>;
5456 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5457 (sra GPR:$b, (i32 16))),
5458 (SMULBT GPR:$a, GPR:$b)>;
5459 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5460 (SMULBT GPR:$a, GPR:$b)>;
5461 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5462 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5463 (SMULTB GPR:$a, GPR:$b)>;
5464 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5465 (SMULTB GPR:$a, GPR:$b)>;
5467 def : ARMV5MOPat<(add GPR:$acc,
5468 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5469 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5470 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5471 def : ARMV5MOPat<(add GPR:$acc,
5472 (mul sext_16_node:$a, sext_16_node:$b)),
5473 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5474 def : ARMV5MOPat<(add GPR:$acc,
5475 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5476 (sra GPR:$b, (i32 16)))),
5477 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5478 def : ARMV5MOPat<(add GPR:$acc,
5479 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5480 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5481 def : ARMV5MOPat<(add GPR:$acc,
5482 (mul (sra GPR:$a, (i32 16)),
5483 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5484 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5485 def : ARMV5MOPat<(add GPR:$acc,
5486 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5487 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5490 // Pre-v7 uses MCR for synchronization barriers.
5491 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5492 Requires<[IsARM, HasV6]>;
5494 // SXT/UXT with no rotate
5495 let AddedComplexity = 16 in {
5496 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5497 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5498 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5499 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5500 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5501 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5502 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5505 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5506 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5508 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5509 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5510 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5511 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5513 // Atomic load/store patterns
5514 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5515 (LDRBrs ldst_so_reg:$src)>;
5516 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5517 (LDRBi12 addrmode_imm12:$src)>;
5518 def : ARMPat<(atomic_load_16 addrmode3:$src),
5519 (LDRH addrmode3:$src)>;
5520 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5521 (LDRrs ldst_so_reg:$src)>;
5522 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5523 (LDRi12 addrmode_imm12:$src)>;
5524 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5525 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5526 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5527 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5528 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5529 (STRH GPR:$val, addrmode3:$ptr)>;
5530 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5531 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5532 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5533 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5536 //===----------------------------------------------------------------------===//
5540 include "ARMInstrThumb.td"
5542 //===----------------------------------------------------------------------===//
5546 include "ARMInstrThumb2.td"
5548 //===----------------------------------------------------------------------===//
5549 // Floating Point Support
5552 include "ARMInstrVFP.td"
5554 //===----------------------------------------------------------------------===//
5555 // Advanced SIMD (NEON) Support
5558 include "ARMInstrNEON.td"
5560 //===----------------------------------------------------------------------===//
5561 // Assembler aliases
5565 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5566 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5567 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5569 // System instructions
5570 def : MnemonicAlias<"swi", "svc">;
5572 // Load / Store Multiple
5573 def : MnemonicAlias<"ldmfd", "ldm">;
5574 def : MnemonicAlias<"ldmia", "ldm">;
5575 def : MnemonicAlias<"ldmea", "ldmdb">;
5576 def : MnemonicAlias<"stmfd", "stmdb">;
5577 def : MnemonicAlias<"stmia", "stm">;
5578 def : MnemonicAlias<"stmea", "stm">;
5580 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5581 // shift amount is zero (i.e., unspecified).
5582 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5583 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5584 Requires<[IsARM, HasV6]>;
5585 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5586 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5587 Requires<[IsARM, HasV6]>;
5589 // PUSH/POP aliases for STM/LDM
5590 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5591 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5593 // SSAT/USAT optional shift operand.
5594 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5595 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5596 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5597 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5600 // Extend instruction optional rotate operand.
5601 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5602 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5603 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5604 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5605 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5606 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5607 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5608 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5609 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5610 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5611 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5612 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5614 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5615 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5616 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5617 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5618 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5619 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5620 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5621 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5622 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5623 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5624 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5625 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5629 def : MnemonicAlias<"rfefa", "rfeda">;
5630 def : MnemonicAlias<"rfeea", "rfedb">;
5631 def : MnemonicAlias<"rfefd", "rfeia">;
5632 def : MnemonicAlias<"rfeed", "rfeib">;
5633 def : MnemonicAlias<"rfe", "rfeia">;
5636 def : MnemonicAlias<"srsfa", "srsib">;
5637 def : MnemonicAlias<"srsea", "srsia">;
5638 def : MnemonicAlias<"srsfd", "srsdb">;
5639 def : MnemonicAlias<"srsed", "srsda">;
5640 def : MnemonicAlias<"srs", "srsia">;
5643 def : MnemonicAlias<"qsubaddx", "qsax">;
5645 def : MnemonicAlias<"saddsubx", "sasx">;
5646 // SHASX == SHADDSUBX
5647 def : MnemonicAlias<"shaddsubx", "shasx">;
5648 // SHSAX == SHSUBADDX
5649 def : MnemonicAlias<"shsubaddx", "shsax">;
5651 def : MnemonicAlias<"ssubaddx", "ssax">;
5653 def : MnemonicAlias<"uaddsubx", "uasx">;
5654 // UHASX == UHADDSUBX
5655 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5656 // UHSAX == UHSUBADDX
5657 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5658 // UQASX == UQADDSUBX
5659 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5660 // UQSAX == UQSUBADDX
5661 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5663 def : MnemonicAlias<"usubaddx", "usax">;
5665 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5667 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5668 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5669 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5670 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5671 // Same for AND <--> BIC
5672 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5673 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5674 pred:$p, cc_out:$s)>;
5675 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5676 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5677 pred:$p, cc_out:$s)>;
5678 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5679 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5680 pred:$p, cc_out:$s)>;
5681 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5682 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5683 pred:$p, cc_out:$s)>;
5685 // Likewise, "add Rd, mod_imm_neg" -> sub
5686 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5687 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5688 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5689 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5690 // Same for CMP <--> CMN via mod_imm_neg
5691 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5692 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5693 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5694 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5696 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5697 // LSR, ROR, and RRX instructions.
5698 // FIXME: We need C++ parser hooks to map the alias to the MOV
5699 // encoding. It seems we should be able to do that sort of thing
5700 // in tblgen, but it could get ugly.
5701 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5702 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5703 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5705 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5706 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5708 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5709 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5711 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5712 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5715 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5716 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5717 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5718 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5719 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5721 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5722 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5724 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5725 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5727 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5728 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5732 // "neg" is and alias for "rsb rd, rn, #0"
5733 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5734 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5736 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5737 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5738 Requires<[IsARM, NoV6]>;
5740 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5741 // the instruction definitions need difference constraints pre-v6.
5742 // Use these aliases for the assembly parsing on pre-v6.
5743 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5744 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5745 Requires<[IsARM, NoV6]>;
5746 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5747 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5748 pred:$p, cc_out:$s)>,
5749 Requires<[IsARM, NoV6]>;
5750 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5751 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5752 Requires<[IsARM, NoV6]>;
5753 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5754 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5755 Requires<[IsARM, NoV6]>;
5756 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5757 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5758 Requires<[IsARM, NoV6]>;
5759 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5760 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5761 Requires<[IsARM, NoV6]>;
5763 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5765 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5766 ComplexDeprecationPredicate<"IT">;
5768 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5769 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5771 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;