1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // ARM specific DAG Nodes.
20 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
43 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
44 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
46 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
47 [SDNPHasChain, SDNPOutFlag]>;
48 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
49 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
51 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
53 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
57 [SDNPHasChain, SDNPOptInFlag]>;
59 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
61 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
64 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
65 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
67 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
70 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
73 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
75 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
76 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
77 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
79 //===----------------------------------------------------------------------===//
80 // ARM Instruction Predicate Definitions.
82 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
83 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
84 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
85 def IsThumb : Predicate<"Subtarget->isThumb()">;
86 def IsARM : Predicate<"!Subtarget->isThumb()">;
88 //===----------------------------------------------------------------------===//
89 // ARM Flag Definitions.
91 class RegConstraint<string C> {
92 string Constraints = C;
95 //===----------------------------------------------------------------------===//
96 // ARM specific transformation functions and pattern fragments.
99 // so_imm_XFORM - Return a so_imm value packed into the format described for
101 def so_imm_XFORM : SDNodeXForm<imm, [{
102 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
106 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
107 // so_imm_neg def below.
108 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
109 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
113 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
114 // so_imm_not def below.
115 def so_imm_not_XFORM : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
120 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
121 def rot_imm : PatLeaf<(i32 imm), [{
122 int32_t v = (int32_t)N->getValue();
123 return v == 8 || v == 16 || v == 24;
126 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
127 def imm1_15 : PatLeaf<(i32 imm), [{
128 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
131 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
132 def imm16_31 : PatLeaf<(i32 imm), [{
133 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
137 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
141 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
144 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
145 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
146 return TLI.ComputeNumSignBits(SDOperand(N,0)) >= 17;
151 //===----------------------------------------------------------------------===//
152 // Operand Definitions.
156 def brtarget : Operand<OtherVT>;
158 // Operand for printing out a condition code.
159 def CCOp : Operand<i32> {
160 let PrintMethod = "printCCOperand";
163 // A list of registers separated by comma. Used by load/store multiple.
164 def reglist : Operand<i32> {
165 let PrintMethod = "printRegisterList";
168 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
169 def cpinst_operand : Operand<i32> {
170 let PrintMethod = "printCPInstOperand";
173 def jtblock_operand : Operand<i32> {
174 let PrintMethod = "printJTBlockOperand";
178 def pclabel : Operand<i32> {
179 let PrintMethod = "printPCLabel";
182 // shifter_operand operands: so_reg and so_imm.
183 def so_reg : Operand<i32>, // reg reg imm
184 ComplexPattern<i32, 3, "SelectShifterOperandReg",
185 [shl,srl,sra,rotr]> {
186 let PrintMethod = "printSORegOperand";
187 let MIOperandInfo = (ops GPR, GPR, i32imm);
190 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
191 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
192 // represented in the imm field in the same 12-bit form that they are encoded
193 // into so_imm instructions: the 8-bit immediate is the least significant bits
194 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
195 def so_imm : Operand<i32>,
197 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
199 let PrintMethod = "printSOImmOperand";
202 // Break so_imm's up into two pieces. This handles immediates with up to 16
203 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
204 // get the first/second pieces.
205 def so_imm2part : Operand<i32>,
207 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
208 let PrintMethod = "printSOImm2PartOperand";
211 def so_imm2part_1 : SDNodeXForm<imm, [{
212 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
213 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
216 def so_imm2part_2 : SDNodeXForm<imm, [{
217 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
218 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
222 // Define ARM specific addressing modes.
224 // addrmode2 := reg +/- reg shop imm
225 // addrmode2 := reg +/- imm12
227 def addrmode2 : Operand<i32>,
228 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
229 let PrintMethod = "printAddrMode2Operand";
230 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
233 def am2offset : Operand<i32>,
234 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
235 let PrintMethod = "printAddrMode2OffsetOperand";
236 let MIOperandInfo = (ops GPR, i32imm);
239 // addrmode3 := reg +/- reg
240 // addrmode3 := reg +/- imm8
242 def addrmode3 : Operand<i32>,
243 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
244 let PrintMethod = "printAddrMode3Operand";
245 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
248 def am3offset : Operand<i32>,
249 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
250 let PrintMethod = "printAddrMode3OffsetOperand";
251 let MIOperandInfo = (ops GPR, i32imm);
254 // addrmode4 := reg, <mode|W>
256 def addrmode4 : Operand<i32>,
257 ComplexPattern<i32, 2, "", []> {
258 let PrintMethod = "printAddrMode4Operand";
259 let MIOperandInfo = (ops GPR, i32imm);
262 // addrmode5 := reg +/- imm8*4
264 def addrmode5 : Operand<i32>,
265 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
266 let PrintMethod = "printAddrMode5Operand";
267 let MIOperandInfo = (ops GPR, i32imm);
270 // addrmodepc := pc + reg
272 def addrmodepc : Operand<i32>,
273 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
274 let PrintMethod = "printAddrModePCOperand";
275 let MIOperandInfo = (ops GPR, i32imm);
278 //===----------------------------------------------------------------------===//
279 // ARM Instruction flags. These need to match ARMInstrInfo.h.
283 class AddrMode<bits<4> val> {
286 def AddrModeNone : AddrMode<0>;
287 def AddrMode1 : AddrMode<1>;
288 def AddrMode2 : AddrMode<2>;
289 def AddrMode3 : AddrMode<3>;
290 def AddrMode4 : AddrMode<4>;
291 def AddrMode5 : AddrMode<5>;
292 def AddrModeT1 : AddrMode<6>;
293 def AddrModeT2 : AddrMode<7>;
294 def AddrModeT4 : AddrMode<8>;
295 def AddrModeTs : AddrMode<9>;
298 class SizeFlagVal<bits<3> val> {
301 def SizeInvalid : SizeFlagVal<0>; // Unset.
302 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
303 def Size8Bytes : SizeFlagVal<2>;
304 def Size4Bytes : SizeFlagVal<3>;
305 def Size2Bytes : SizeFlagVal<4>;
307 // Load / store index mode.
308 class IndexMode<bits<2> val> {
311 def IndexModeNone : IndexMode<0>;
312 def IndexModePre : IndexMode<1>;
313 def IndexModePost : IndexMode<2>;
315 //===----------------------------------------------------------------------===//
316 // ARM Instruction templates.
319 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
320 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
321 list<Predicate> Predicates = [IsARM];
323 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
324 list<Predicate> Predicates = [IsARM, HasV5TE];
326 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
327 list<Predicate> Predicates = [IsARM, HasV6];
330 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
331 dag ops, string asmstr, string cstr>
333 let Namespace = "ARM";
335 bits<4> Opcode = opcod;
337 bits<4> AddrModeBits = AM.Value;
340 bits<3> SizeFlag = SZ.Value;
343 bits<2> IndexModeBits = IM.Value;
345 dag OperandList = ops;
346 let AsmString = asmstr;
347 let Constraints = cstr;
350 class PseudoInst<dag ops, string asm, list<dag> pattern>
351 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ops, asm, ""> {
352 let Pattern = pattern;
355 class I<dag ops, AddrMode am, SizeFlagVal sz, IndexMode im,
356 string asm, string cstr, list<dag> pattern>
357 // FIXME: Set all opcodes to 0 for now.
358 : InstARM<0, am, sz, im, ops, asm, cstr> {
359 let Pattern = pattern;
360 list<Predicate> Predicates = [IsARM];
363 class AI<dag ops, string asm, list<dag> pattern>
364 : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
365 class AI1<dag ops, string asm, list<dag> pattern>
366 : I<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
367 class AI2<dag ops, string asm, list<dag> pattern>
368 : I<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
369 class AI3<dag ops, string asm, list<dag> pattern>
370 : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
371 class AI4<dag ops, string asm, list<dag> pattern>
372 : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
373 class AIx2<dag ops, string asm, list<dag> pattern>
374 : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
375 class AI1x2<dag ops, string asm, list<dag> pattern>
376 : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
379 class AI2pr<dag ops, string asm, string cstr, list<dag> pattern>
380 : I<ops, AddrMode2, Size4Bytes, IndexModePre, asm, cstr, pattern>;
381 class AI3pr<dag ops, string asm, string cstr, list<dag> pattern>
382 : I<ops, AddrMode3, Size4Bytes, IndexModePre, asm, cstr, pattern>;
385 class AI2po<dag ops, string asm, string cstr, list<dag> pattern>
386 : I<ops, AddrMode2, Size4Bytes, IndexModePost, asm, cstr, pattern>;
387 class AI3po<dag ops, string asm, string cstr, list<dag> pattern>
388 : I<ops, AddrMode3, Size4Bytes, IndexModePost, asm, cstr, pattern>;
390 // BR_JT instructions
391 class JTI<dag ops, string asm, list<dag> pattern>
392 : I<ops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
393 class JTI1<dag ops, string asm, list<dag> pattern>
394 : I<ops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
395 class JTI2<dag ops, string asm, list<dag> pattern>
396 : I<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
399 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
400 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
403 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
404 /// binop that produces a value.
405 multiclass AI1_bin_irs<string opc, PatFrag opnode> {
406 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
407 !strconcat(opc, " $dst, $a, $b"),
408 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
409 def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
410 !strconcat(opc, " $dst, $a, $b"),
411 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
412 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
413 !strconcat(opc, " $dst, $a, $b"),
414 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
417 /// AI1_bin0_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns.
418 /// Similar to AI1_bin_irs except the instruction does not produce a result.
419 multiclass AI1_bin0_irs<string opc, PatFrag opnode> {
420 def ri : AI1<(ops GPR:$a, so_imm:$b),
421 !strconcat(opc, " $a, $b"),
422 [(opnode GPR:$a, so_imm:$b)]>;
423 def rr : AI1<(ops GPR:$a, GPR:$b),
424 !strconcat(opc, " $a, $b"),
425 [(opnode GPR:$a, GPR:$b)]>;
426 def rs : AI1<(ops GPR:$a, so_reg:$b),
427 !strconcat(opc, " $a, $b"),
428 [(opnode GPR:$a, so_reg:$b)]>;
431 /// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop.
432 multiclass AI1_bin_is<string opc, PatFrag opnode> {
433 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
434 !strconcat(opc, " $dst, $a, $b"),
435 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
436 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
437 !strconcat(opc, " $dst, $a, $b"),
438 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
441 /// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary
443 multiclass AI1_unary_irs<string opc, PatFrag opnode> {
444 def i : AI1<(ops GPR:$dst, so_imm:$a),
445 !strconcat(opc, " $dst, $a"),
446 [(set GPR:$dst, (opnode so_imm:$a))]>;
447 def r : AI1<(ops GPR:$dst, GPR:$a),
448 !strconcat(opc, " $dst, $a"),
449 [(set GPR:$dst, (opnode GPR:$a))]>;
450 def s : AI1<(ops GPR:$dst, so_reg:$a),
451 !strconcat(opc, " $dst, $a"),
452 [(set GPR:$dst, (opnode so_reg:$a))]>;
455 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
456 /// register and one whose operand is a register rotated by 8/16/24.
457 multiclass AI_unary_rrot<string opc, PatFrag opnode> {
458 def r : AI<(ops GPR:$dst, GPR:$Src),
459 !strconcat(opc, " $dst, $Src"),
460 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
461 def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot),
462 !strconcat(opc, " $dst, $Src, ror $rot"),
463 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
464 Requires<[IsARM, HasV6]>;
467 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
468 /// register and one whose operand is a register rotated by 8/16/24.
469 multiclass AI_bin_rrot<string opc, PatFrag opnode> {
470 def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS),
471 !strconcat(opc, " $dst, $LHS, $RHS"),
472 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
473 Requires<[IsARM, HasV6]>;
474 def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot),
475 !strconcat(opc, " $dst, $LHS, $RHS, ror $rot"),
476 [(set GPR:$dst, (opnode GPR:$LHS,
477 (rotr GPR:$RHS, rot_imm:$rot)))]>,
478 Requires<[IsARM, HasV6]>;
482 //===----------------------------------------------------------------------===//
484 //===----------------------------------------------------------------------===//
486 //===----------------------------------------------------------------------===//
487 // Miscellaneous Instructions.
489 def IMPLICIT_DEF_GPR :
490 PseudoInst<(ops GPR:$rD),
491 "@ IMPLICIT_DEF_GPR $rD",
492 [(set GPR:$rD, (undef))]>;
495 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
496 /// the function. The first operand is the ID# for this instruction, the second
497 /// is the index into the MachineConstantPool that this is, the third is the
498 /// size in bytes of this constant pool entry.
499 def CONSTPOOL_ENTRY :
500 PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
501 "${instid:label} ${cpidx:cpentry}", []>;
504 PseudoInst<(ops i32imm:$amt),
505 "@ ADJCALLSTACKUP $amt",
506 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
508 def ADJCALLSTACKDOWN :
509 PseudoInst<(ops i32imm:$amt),
510 "@ ADJCALLSTACKDOWN $amt",
511 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
514 PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
515 ".loc $file, $line, $col",
516 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
518 def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp),
519 "$cp:\n\tadd $dst, pc, $a",
520 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
521 let AddedComplexity = 10 in
522 def PICLD : AI2<(ops GPR:$dst, addrmodepc:$addr),
523 "${addr:label}:\n\tldr $dst, $addr",
524 [(set GPR:$dst, (load addrmodepc:$addr))]>;
526 //===----------------------------------------------------------------------===//
527 // Control Flow Instructions.
530 let isReturn = 1, isTerminator = 1 in
531 def BX_RET : AI<(ops), "bx lr", [(ARMretflag)]>;
533 // FIXME: remove when we have a way to marking a MI with these properties.
534 let isLoad = 1, isReturn = 1, isTerminator = 1 in
535 def LDM_RET : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops),
536 "ldm${addr:submode} $addr, $dst1",
539 let isCall = 1, noResults = 1,
540 Defs = [R0, R1, R2, R3, R12, LR,
541 D0, D1, D2, D3, D4, D5, D6, D7] in {
542 def BL : AI<(ops i32imm:$func, variable_ops),
544 [(ARMcall tglobaladdr:$func)]>;
546 def BLX : AI<(ops GPR:$dst, variable_ops),
548 [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
551 def BX : AIx2<(ops GPR:$dst, variable_ops),
552 "mov lr, pc\n\tbx $dst",
553 [(ARMcall_nolink GPR:$dst)]>;
557 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
558 def B : AI<(ops brtarget:$dst), "b $dst",
561 def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
562 "mov pc, $dst \n$jt",
563 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
564 def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id),
565 "ldr pc, $dst \n$jt",
566 [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt,
568 def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
569 "add pc, $dst, $idx \n$jt",
570 [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
574 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
575 def Bcc : AI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
576 [(ARMbrcond bb:$dst, imm:$cc)]>;
578 //===----------------------------------------------------------------------===//
579 // Load / store Instructions.
584 def LDR : AI2<(ops GPR:$dst, addrmode2:$addr),
586 [(set GPR:$dst, (load addrmode2:$addr))]>;
588 // Special LDR for loads from non-pc-relative constpools.
589 let isReMaterializable = 1 in
590 def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
591 "ldr $dst, $addr", []>;
593 // Loads with zero extension
594 def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr),
596 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
598 def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr),
600 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
602 // Loads with sign extension
603 def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr),
605 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
607 def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr),
609 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
612 def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr),
614 []>, Requires<[IsARM, HasV5T]>;
617 def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
618 "ldr $dst, $addr!", "$addr.base = $base_wb", []>;
620 def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset),
621 "ldr $dst, [$base], $offset", "$base = $base_wb", []>;
623 def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
624 "ldrh $dst, $addr!", "$addr.base = $base_wb", []>;
626 def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
627 "ldrh $dst, [$base], $offset", "$base = $base_wb", []>;
629 def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
630 "ldrb $dst, $addr!", "$addr.base = $base_wb", []>;
632 def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset),
633 "ldrb $dst, [$base], $offset", "$base = $base_wb", []>;
635 def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
636 "ldrsh $dst, $addr!", "$addr.base = $base_wb", []>;
638 def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
639 "ldrsh $dst, [$base], $offset", "$base = $base_wb", []>;
641 def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
642 "ldrsb $dst, $addr!", "$addr.base = $base_wb", []>;
644 def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
645 "ldrsb $dst, [$base], $offset", "$base = $base_wb", []>;
650 def STR : AI2<(ops GPR:$src, addrmode2:$addr),
652 [(store GPR:$src, addrmode2:$addr)]>;
654 // Stores with truncate
655 def STRH : AI3<(ops GPR:$src, addrmode3:$addr),
657 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
659 def STRB : AI2<(ops GPR:$src, addrmode2:$addr),
661 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
664 def STRD : AI3<(ops GPR:$src, addrmode3:$addr),
666 []>, Requires<[IsARM, HasV5T]>;
669 def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset),
670 "str $src, [$base, $offset]!", "$base = $base_wb",
672 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
674 def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
675 "str $src, [$base], $offset", "$base = $base_wb",
677 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
679 def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
680 "strh $src, [$base, $offset]!", "$base = $base_wb",
682 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
684 def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
685 "strh $src, [$base], $offset", "$base = $base_wb",
686 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
687 GPR:$base, am3offset:$offset))]>;
689 def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
690 "strb $src, [$base, $offset]!", "$base = $base_wb",
691 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
692 GPR:$base, am2offset:$offset))]>;
694 def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
695 "strb $src, [$base], $offset", "$base = $base_wb",
696 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
697 GPR:$base, am2offset:$offset))]>;
700 //===----------------------------------------------------------------------===//
701 // Load / store multiple Instructions.
705 def LDM : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops),
706 "ldm${addr:submode} $addr, $dst1",
710 def STM : AI4<(ops addrmode4:$addr, reglist:$src1, variable_ops),
711 "stm${addr:submode} $addr, $src1",
714 //===----------------------------------------------------------------------===//
715 // Move Instructions.
718 def MOVr : AI1<(ops GPR:$dst, GPR:$src),
719 "mov $dst, $src", []>;
720 def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
721 "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
723 let isReMaterializable = 1 in
724 def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
725 "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
727 // These aren't really mov instructions, but we have to define them this way
728 // due to flag operands.
730 def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
731 "movs $dst, $src, lsr #1",
732 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
733 def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
734 "movs $dst, $src, asr #1",
735 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
736 def MOVrx : AI1<(ops GPR:$dst, GPR:$src),
737 "mov $dst, $src, rrx",
738 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
741 //===----------------------------------------------------------------------===//
742 // Extend Instructions.
747 defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
748 defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
750 defm SXTAB : AI_bin_rrot<"sxtab",
751 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
752 defm SXTAH : AI_bin_rrot<"sxtah",
753 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
755 // TODO: SXT(A){B|H}16
759 let AddedComplexity = 16 in {
760 defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
761 defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
762 defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
764 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
765 (UXTB16r_rot GPR:$Src, 24)>;
766 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
767 (UXTB16r_rot GPR:$Src, 8)>;
769 defm UXTAB : AI_bin_rrot<"uxtab",
770 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
771 defm UXTAH : AI_bin_rrot<"uxtah",
772 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
775 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
776 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
778 // TODO: UXT(A){B|H}16
780 //===----------------------------------------------------------------------===//
781 // Arithmetic Instructions.
784 defm ADD : AI1_bin_irs<"add" , BinOpFrag<(add node:$LHS, node:$RHS)>>;
785 defm ADDS : AI1_bin_irs<"adds", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
786 defm ADC : AI1_bin_irs<"adc" , BinOpFrag<(adde node:$LHS, node:$RHS)>>;
787 defm SUB : AI1_bin_irs<"sub" , BinOpFrag<(sub node:$LHS, node:$RHS)>>;
788 defm SUBS : AI1_bin_irs<"subs", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
789 defm SBC : AI1_bin_irs<"sbc" , BinOpFrag<(sube node:$LHS, node:$RHS)>>;
791 // These don't define reg/reg forms, because they are handled above.
792 defm RSB : AI1_bin_is <"rsb" , BinOpFrag<(sub node:$RHS, node:$LHS)>>;
793 defm RSBS : AI1_bin_is <"rsbs", BinOpFrag<(subc node:$RHS, node:$LHS)>>;
794 defm RSC : AI1_bin_is <"rsc" , BinOpFrag<(sube node:$RHS, node:$LHS)>>;
796 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
797 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
798 (SUBri GPR:$src, so_imm_neg:$imm)>;
800 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
801 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
802 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
803 // (SBCri GPR:$src, so_imm_neg:$imm)>;
805 // Note: These are implemented in C++ code, because they have to generate
806 // ADD/SUBrs instructions, which use a complex pattern that a xform function
808 // (mul X, 2^n+1) -> (add (X << n), X)
809 // (mul X, 2^n-1) -> (rsb X, (X << n))
812 //===----------------------------------------------------------------------===//
813 // Bitwise Instructions.
816 defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
817 defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
818 defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
819 defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
821 def MVNr : AI<(ops GPR:$dst, GPR:$src),
822 "mvn $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
823 def MVNs : AI<(ops GPR:$dst, so_reg:$src),
824 "mvn $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
825 let isReMaterializable = 1 in
826 def MVNi : AI<(ops GPR:$dst, so_imm:$imm),
827 "mvn $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
829 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
830 (BICri GPR:$src, so_imm_not:$imm)>;
832 //===----------------------------------------------------------------------===//
833 // Multiply Instructions.
836 // AI_orr - Defines a (op r, r) pattern.
837 class AI_orr<string opc, SDNode opnode>
838 : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
839 !strconcat(opc, " $dst, $a, $b"),
840 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
842 // AI_oorr - Defines a (op (op r, r), r) pattern.
843 class AI_oorr<string opc, SDNode opnode1, SDNode opnode2>
844 : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
845 !strconcat(opc, " $dst, $a, $b, $c"),
846 [(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>;
848 def MUL : AI_orr<"mul", mul>;
849 def MLA : AI_oorr<"mla", add, mul>;
851 // Extra precision multiplies with low / high results
852 def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
853 "smull $ldst, $hdst, $a, $b",
856 def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
857 "umull $ldst, $hdst, $a, $b",
860 // Multiply + accumulate
861 def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
862 "smlal $ldst, $hdst, $a, $b",
865 def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
866 "umlal $ldst, $hdst, $a, $b",
869 def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
870 "umaal $ldst, $hdst, $a, $b",
871 []>, Requires<[IsARM, HasV6]>;
873 // Most significant word multiply
874 def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>;
875 def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>;
878 def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
879 "smmls $dst, $a, $b, $c",
880 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
881 Requires<[IsARM, HasV6]>;
883 multiclass AI_smul<string opc, PatFrag opnode> {
884 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
885 !strconcat(opc, "bb $dst, $a, $b"),
886 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
887 (sext_inreg GPR:$b, i16)))]>,
888 Requires<[IsARM, HasV5TE]>;
889 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
890 !strconcat(opc, "bt $dst, $a, $b"),
891 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
892 (sra GPR:$b, 16)))]>,
893 Requires<[IsARM, HasV5TE]>;
894 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
895 !strconcat(opc, "tb $dst, $a, $b"),
896 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
897 (sext_inreg GPR:$b, i16)))]>,
898 Requires<[IsARM, HasV5TE]>;
899 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
900 !strconcat(opc, "tt $dst, $a, $b"),
901 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
902 (sra GPR:$b, 16)))]>,
903 Requires<[IsARM, HasV5TE]>;
904 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
905 !strconcat(opc, "wb $dst, $a, $b"),
906 [(set GPR:$dst, (sra (opnode GPR:$a,
907 (sext_inreg GPR:$b, i16)), 16))]>,
908 Requires<[IsARM, HasV5TE]>;
909 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
910 !strconcat(opc, "wt $dst, $a, $b"),
911 [(set GPR:$dst, (sra (opnode GPR:$a,
912 (sra GPR:$b, 16)), 16))]>,
913 Requires<[IsARM, HasV5TE]>;
916 multiclass AI_smla<string opc, PatFrag opnode> {
917 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
918 !strconcat(opc, "bb $dst, $a, $b, $acc"),
919 [(set GPR:$dst, (add GPR:$acc,
920 (opnode (sext_inreg GPR:$a, i16),
921 (sext_inreg GPR:$b, i16))))]>,
922 Requires<[IsARM, HasV5TE]>;
923 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
924 !strconcat(opc, "bt $dst, $a, $b, $acc"),
925 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
926 (sra GPR:$b, 16))))]>,
927 Requires<[IsARM, HasV5TE]>;
928 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
929 !strconcat(opc, "tb $dst, $a, $b, $acc"),
930 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
931 (sext_inreg GPR:$b, i16))))]>,
932 Requires<[IsARM, HasV5TE]>;
933 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
934 !strconcat(opc, "tt $dst, $a, $b, $acc"),
935 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
936 (sra GPR:$b, 16))))]>,
937 Requires<[IsARM, HasV5TE]>;
939 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
940 !strconcat(opc, "wb $dst, $a, $b, $acc"),
941 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
942 (sext_inreg GPR:$b, i16)), 16)))]>,
943 Requires<[IsARM, HasV5TE]>;
944 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
945 !strconcat(opc, "wt $dst, $a, $b, $acc"),
946 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
947 (sra GPR:$b, 16)), 16)))]>,
948 Requires<[IsARM, HasV5TE]>;
951 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
952 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
954 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
955 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
957 //===----------------------------------------------------------------------===//
958 // Misc. Arithmetic Instructions.
961 def CLZ : AI<(ops GPR:$dst, GPR:$src),
963 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
965 def REV : AI<(ops GPR:$dst, GPR:$src),
967 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
969 def REV16 : AI<(ops GPR:$dst, GPR:$src),
972 (or (and (srl GPR:$src, 8), 0xFF),
973 (or (and (shl GPR:$src, 8), 0xFF00),
974 (or (and (srl GPR:$src, 8), 0xFF0000),
975 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
976 Requires<[IsARM, HasV6]>;
978 def REVSH : AI<(ops GPR:$dst, GPR:$src),
982 (or (srl (and GPR:$src, 0xFFFF), 8),
983 (shl GPR:$src, 8)), i16))]>,
984 Requires<[IsARM, HasV6]>;
986 def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
987 "pkhbt $dst, $src1, $src2, LSL $shamt",
988 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
989 (and (shl GPR:$src2, (i32 imm:$shamt)),
991 Requires<[IsARM, HasV6]>;
993 // Alternate cases for PKHBT where identities eliminate some nodes.
994 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
995 (PKHBT GPR:$src1, GPR:$src2, 0)>;
996 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
997 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1000 def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
1001 "pkhtb $dst, $src1, $src2, ASR $shamt",
1002 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1003 (and (sra GPR:$src2, imm16_31:$shamt),
1004 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1006 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1007 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1008 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1009 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1010 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1011 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1012 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1015 //===----------------------------------------------------------------------===//
1016 // Comparison Instructions...
1019 defm CMP : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1020 defm CMN : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1022 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1023 (CMNri GPR:$src, so_imm_neg:$imm)>;
1025 // Note that TST/TEQ don't set all the same flags that CMP does!
1026 def TSTrr : AI1<(ops GPR:$a, so_reg:$b), "tst $a, $b", []>;
1027 def TSTri : AI1<(ops GPR:$a, so_imm:$b), "tst $a, $b", []>;
1028 def TEQrr : AI1<(ops GPR:$a, so_reg:$b), "teq $a, $b", []>;
1029 def TEQri : AI1<(ops GPR:$a, so_imm:$b), "teq $a, $b", []>;
1031 // Conditional moves
1032 def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
1033 "mov$cc $dst, $true",
1034 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>,
1035 RegConstraint<"$false = $dst">;
1037 def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, CCOp:$cc),
1038 "mov$cc $dst, $true",
1039 [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>,
1040 RegConstraint<"$false = $dst">;
1042 def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, CCOp:$cc),
1043 "mov$cc $dst, $true",
1044 [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>,
1045 RegConstraint<"$false = $dst">;
1048 // LEApcrel - Load a pc-relative address into a register without offending the
1050 def LEApcrel : AI1<(ops GPR:$dst, i32imm:$label),
1051 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1052 "${:private}PCRELL${:uid}+8))\n"),
1053 !strconcat("${:private}PCRELL${:uid}:\n\t",
1054 "add $dst, pc, #PCRELV${:uid}")),
1057 def LEApcrelJT : AI1<(ops GPR:$dst, i32imm:$label, i32imm:$id),
1058 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1059 "${:private}PCRELL${:uid}+8))\n"),
1060 !strconcat("${:private}PCRELL${:uid}:\n\t",
1061 "add $dst, pc, #PCRELV${:uid}")),
1064 //===----------------------------------------------------------------------===//
1065 // Non-Instruction Patterns
1068 // ConstantPool, GlobalAddress, and JumpTable
1069 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1070 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1071 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1072 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1074 // Large immediate handling.
1076 // Two piece so_imms.
1077 let isReMaterializable = 1 in
1078 def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
1080 [(set GPR:$dst, so_imm2part:$src)]>;
1082 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1083 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1084 (so_imm2part_2 imm:$RHS))>;
1085 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1086 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1087 (so_imm2part_2 imm:$RHS))>;
1089 // TODO: add,sub,and, 3-instr forms?
1093 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1095 // zextload i1 -> zextload i8
1096 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1098 // extload -> zextload
1099 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1100 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1101 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1103 // truncstore i1 -> truncstore i8
1104 def : Pat<(truncstorei1 GPR:$src, addrmode2:$dst),
1105 (STRB GPR:$src, addrmode2:$dst)>;
1106 def : Pat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1107 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1108 def : Pat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1109 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1112 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1113 (SMULBB GPR:$a, GPR:$b)>;
1114 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1115 (SMULBB GPR:$a, GPR:$b)>;
1116 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1117 (SMULBT GPR:$a, GPR:$b)>;
1118 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1119 (SMULBT GPR:$a, GPR:$b)>;
1120 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1121 (SMULTB GPR:$a, GPR:$b)>;
1122 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1123 (SMULTB GPR:$a, GPR:$b)>;
1124 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1125 (SMULWB GPR:$a, GPR:$b)>;
1126 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1127 (SMULWB GPR:$a, GPR:$b)>;
1129 def : ARMV5TEPat<(add GPR:$acc,
1130 (mul (sra (shl GPR:$a, 16), 16),
1131 (sra (shl GPR:$b, 16), 16))),
1132 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1133 def : ARMV5TEPat<(add GPR:$acc,
1134 (mul sext_16_node:$a, sext_16_node:$b)),
1135 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1136 def : ARMV5TEPat<(add GPR:$acc,
1137 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1138 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1139 def : ARMV5TEPat<(add GPR:$acc,
1140 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1141 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1142 def : ARMV5TEPat<(add GPR:$acc,
1143 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1144 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1145 def : ARMV5TEPat<(add GPR:$acc,
1146 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1147 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1148 def : ARMV5TEPat<(add GPR:$acc,
1149 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1150 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1151 def : ARMV5TEPat<(add GPR:$acc,
1152 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1153 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1155 //===----------------------------------------------------------------------===//
1159 include "ARMInstrThumb.td"
1161 //===----------------------------------------------------------------------===//
1162 // Floating Point Support
1165 include "ARMInstrVFP.td"