1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
66 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
68 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
74 SDTCisInt<0>, SDTCisVT<1, i32>]>;
76 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
77 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
84 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
85 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
86 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
87 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
89 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
97 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
100 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
105 [SDNPHasChain, SDNPOptInGlue]>;
107 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
110 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
113 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
115 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
118 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
121 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
124 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
125 [SDNPOutGlue, SDNPCommutative]>;
127 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
129 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
130 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
131 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
133 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
135 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
136 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
137 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
139 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
140 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
142 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
145 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
147 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
149 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
152 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
154 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
158 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
160 //===----------------------------------------------------------------------===//
161 // ARM Instruction Predicate Definitions.
163 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
164 AssemblerPredicate<"HasV4TOps">;
165 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
166 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
167 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
168 AssemblerPredicate<"HasV5TEOps">;
169 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
170 AssemblerPredicate<"HasV6Ops">;
171 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
172 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
173 AssemblerPredicate<"HasV6T2Ops">;
174 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
175 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
176 AssemblerPredicate<"HasV7Ops">;
177 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
178 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
179 AssemblerPredicate<"FeatureVFP2">;
180 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
181 AssemblerPredicate<"FeatureVFP3">;
182 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
183 AssemblerPredicate<"FeatureVFP4">;
184 def NoVFP4 : Predicate<"!Subtarget->hasVFP4()">;
185 def HasNEON : Predicate<"Subtarget->hasNEON()">,
186 AssemblerPredicate<"FeatureNEON">;
187 def HasNEON2 : Predicate<"Subtarget->hasNEON2()">,
188 AssemblerPredicate<"FeatureNEON2">;
189 def NoNEON2 : Predicate<"!Subtarget->hasNEON2()">;
190 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
191 AssemblerPredicate<"FeatureFP16">;
192 def HasDivide : Predicate<"Subtarget->hasDivide()">,
193 AssemblerPredicate<"FeatureHWDiv">;
194 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
195 AssemblerPredicate<"FeatureT2XtPk">;
196 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
197 AssemblerPredicate<"FeatureDSPThumb2">;
198 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
199 AssemblerPredicate<"FeatureDB">;
200 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
201 AssemblerPredicate<"FeatureMP">;
202 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
203 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
204 def IsThumb : Predicate<"Subtarget->isThumb()">,
205 AssemblerPredicate<"ModeThumb">;
206 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
207 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
208 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
209 def IsMClass : Predicate<"Subtarget->isMClass()">,
210 AssemblerPredicate<"FeatureMClass">;
211 def IsARClass : Predicate<"!Subtarget->isMClass()">,
212 AssemblerPredicate<"!FeatureMClass">;
213 def IsARM : Predicate<"!Subtarget->isThumb()">,
214 AssemblerPredicate<"!ModeThumb">;
215 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
216 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
217 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
219 // FIXME: Eventually this will be just "hasV6T2Ops".
220 def UseMovt : Predicate<"Subtarget->useMovt()">;
221 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
222 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
224 //===----------------------------------------------------------------------===//
225 // ARM Flag Definitions.
227 class RegConstraint<string C> {
228 string Constraints = C;
231 //===----------------------------------------------------------------------===//
232 // ARM specific transformation functions and pattern fragments.
235 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
236 // so_imm_neg def below.
237 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
238 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
241 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
242 // so_imm_not def below.
243 def so_imm_not_XFORM : SDNodeXForm<imm, [{
244 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
247 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
248 def imm16_31 : ImmLeaf<i32, [{
249 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
252 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
253 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
254 int64_t Value = -(int)N->getZExtValue();
255 return Value && ARM_AM::getSOImmVal(Value) != -1;
256 }], so_imm_neg_XFORM> {
257 let ParserMatchClass = so_imm_neg_asmoperand;
260 // Note: this pattern doesn't require an encoder method and such, as it's
261 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
262 // is handled by the destination instructions, which use so_imm.
263 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
264 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
265 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
266 }], so_imm_not_XFORM> {
267 let ParserMatchClass = so_imm_not_asmoperand;
270 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
271 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
272 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
275 /// Split a 32-bit immediate into two 16 bit parts.
276 def hi16 : SDNodeXForm<imm, [{
277 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
280 def lo16AllZero : PatLeaf<(i32 imm), [{
281 // Returns true if all low 16-bits are 0.
282 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
285 class BinOpWithFlagFrag<dag res> :
286 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
287 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
288 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
290 // An 'and' node with a single use.
291 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
292 return N->hasOneUse();
295 // An 'xor' node with a single use.
296 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
297 return N->hasOneUse();
300 // An 'fmul' node with a single use.
301 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
302 return N->hasOneUse();
305 // An 'fadd' node which checks for single non-hazardous use.
306 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
307 return hasNoVMLxHazardUse(N);
310 // An 'fsub' node which checks for single non-hazardous use.
311 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
312 return hasNoVMLxHazardUse(N);
315 //===----------------------------------------------------------------------===//
316 // Operand Definitions.
319 // Immediate operands with a shared generic asm render method.
320 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
323 // FIXME: rename brtarget to t2_brtarget
324 def brtarget : Operand<OtherVT> {
325 let EncoderMethod = "getBranchTargetOpValue";
326 let OperandType = "OPERAND_PCREL";
327 let DecoderMethod = "DecodeT2BROperand";
330 // FIXME: get rid of this one?
331 def uncondbrtarget : Operand<OtherVT> {
332 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
333 let OperandType = "OPERAND_PCREL";
336 // Branch target for ARM. Handles conditional/unconditional
337 def br_target : Operand<OtherVT> {
338 let EncoderMethod = "getARMBranchTargetOpValue";
339 let OperandType = "OPERAND_PCREL";
343 // FIXME: rename bltarget to t2_bl_target?
344 def bltarget : Operand<i32> {
345 // Encoded the same as branch targets.
346 let EncoderMethod = "getBranchTargetOpValue";
347 let OperandType = "OPERAND_PCREL";
350 // Call target for ARM. Handles conditional/unconditional
351 // FIXME: rename bl_target to t2_bltarget?
352 def bl_target : Operand<i32> {
353 let EncoderMethod = "getARMBLTargetOpValue";
354 let OperandType = "OPERAND_PCREL";
357 def blx_target : Operand<i32> {
358 let EncoderMethod = "getARMBLXTargetOpValue";
359 let OperandType = "OPERAND_PCREL";
362 // A list of registers separated by comma. Used by load/store multiple.
363 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
364 def reglist : Operand<i32> {
365 let EncoderMethod = "getRegisterListOpValue";
366 let ParserMatchClass = RegListAsmOperand;
367 let PrintMethod = "printRegisterList";
368 let DecoderMethod = "DecodeRegListOperand";
371 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
372 def dpr_reglist : Operand<i32> {
373 let EncoderMethod = "getRegisterListOpValue";
374 let ParserMatchClass = DPRRegListAsmOperand;
375 let PrintMethod = "printRegisterList";
376 let DecoderMethod = "DecodeDPRRegListOperand";
379 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
380 def spr_reglist : Operand<i32> {
381 let EncoderMethod = "getRegisterListOpValue";
382 let ParserMatchClass = SPRRegListAsmOperand;
383 let PrintMethod = "printRegisterList";
384 let DecoderMethod = "DecodeSPRRegListOperand";
387 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
388 def cpinst_operand : Operand<i32> {
389 let PrintMethod = "printCPInstOperand";
393 def pclabel : Operand<i32> {
394 let PrintMethod = "printPCLabel";
397 // ADR instruction labels.
398 def adrlabel : Operand<i32> {
399 let EncoderMethod = "getAdrLabelOpValue";
402 def neon_vcvt_imm32 : Operand<i32> {
403 let EncoderMethod = "getNEONVcvtImm32OpValue";
404 let DecoderMethod = "DecodeVCVTImmOperand";
407 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
408 def rot_imm_XFORM: SDNodeXForm<imm, [{
409 switch (N->getZExtValue()){
411 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
412 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
413 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
414 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
417 def RotImmAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseRotImm";
421 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
422 int32_t v = N->getZExtValue();
423 return v == 8 || v == 16 || v == 24; }],
425 let PrintMethod = "printRotImmOperand";
426 let ParserMatchClass = RotImmAsmOperand;
429 // shift_imm: An integer that encodes a shift amount and the type of shift
430 // (asr or lsl). The 6-bit immediate encodes as:
433 // {4-0} imm5 shift amount.
434 // asr #32 encoded as imm5 == 0.
435 def ShifterImmAsmOperand : AsmOperandClass {
436 let Name = "ShifterImm";
437 let ParserMethod = "parseShifterImm";
439 def shift_imm : Operand<i32> {
440 let PrintMethod = "printShiftImmOperand";
441 let ParserMatchClass = ShifterImmAsmOperand;
444 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
445 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
446 def so_reg_reg : Operand<i32>, // reg reg imm
447 ComplexPattern<i32, 3, "SelectRegShifterOperand",
448 [shl, srl, sra, rotr]> {
449 let EncoderMethod = "getSORegRegOpValue";
450 let PrintMethod = "printSORegRegOperand";
451 let DecoderMethod = "DecodeSORegRegOperand";
452 let ParserMatchClass = ShiftedRegAsmOperand;
453 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
456 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
457 def so_reg_imm : Operand<i32>, // reg imm
458 ComplexPattern<i32, 2, "SelectImmShifterOperand",
459 [shl, srl, sra, rotr]> {
460 let EncoderMethod = "getSORegImmOpValue";
461 let PrintMethod = "printSORegImmOperand";
462 let DecoderMethod = "DecodeSORegImmOperand";
463 let ParserMatchClass = ShiftedImmAsmOperand;
464 let MIOperandInfo = (ops GPR, i32imm);
467 // FIXME: Does this need to be distinct from so_reg?
468 def shift_so_reg_reg : Operand<i32>, // reg reg imm
469 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
470 [shl,srl,sra,rotr]> {
471 let EncoderMethod = "getSORegRegOpValue";
472 let PrintMethod = "printSORegRegOperand";
473 let DecoderMethod = "DecodeSORegRegOperand";
474 let ParserMatchClass = ShiftedRegAsmOperand;
475 let MIOperandInfo = (ops GPR, GPR, i32imm);
478 // FIXME: Does this need to be distinct from so_reg?
479 def shift_so_reg_imm : Operand<i32>, // reg reg imm
480 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
481 [shl,srl,sra,rotr]> {
482 let EncoderMethod = "getSORegImmOpValue";
483 let PrintMethod = "printSORegImmOperand";
484 let DecoderMethod = "DecodeSORegImmOperand";
485 let ParserMatchClass = ShiftedImmAsmOperand;
486 let MIOperandInfo = (ops GPR, i32imm);
490 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
491 // 8-bit immediate rotated by an arbitrary number of bits.
492 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
493 def so_imm : Operand<i32>, ImmLeaf<i32, [{
494 return ARM_AM::getSOImmVal(Imm) != -1;
496 let EncoderMethod = "getSOImmOpValue";
497 let ParserMatchClass = SOImmAsmOperand;
498 let DecoderMethod = "DecodeSOImmOperand";
501 // Break so_imm's up into two pieces. This handles immediates with up to 16
502 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
503 // get the first/second pieces.
504 def so_imm2part : PatLeaf<(imm), [{
505 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
508 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
510 def arm_i32imm : PatLeaf<(imm), [{
511 if (Subtarget->hasV6T2Ops())
513 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
516 /// imm0_1 predicate - Immediate in the range [0,1].
517 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
518 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
520 /// imm0_3 predicate - Immediate in the range [0,3].
521 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
522 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
524 /// imm0_7 predicate - Immediate in the range [0,7].
525 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
526 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
527 return Imm >= 0 && Imm < 8;
529 let ParserMatchClass = Imm0_7AsmOperand;
532 /// imm8 predicate - Immediate is exactly 8.
533 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
534 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
535 let ParserMatchClass = Imm8AsmOperand;
538 /// imm16 predicate - Immediate is exactly 16.
539 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
540 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
541 let ParserMatchClass = Imm16AsmOperand;
544 /// imm32 predicate - Immediate is exactly 32.
545 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
546 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
547 let ParserMatchClass = Imm32AsmOperand;
550 /// imm1_7 predicate - Immediate in the range [1,7].
551 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
552 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
553 let ParserMatchClass = Imm1_7AsmOperand;
556 /// imm1_15 predicate - Immediate in the range [1,15].
557 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
558 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
559 let ParserMatchClass = Imm1_15AsmOperand;
562 /// imm1_31 predicate - Immediate in the range [1,31].
563 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
564 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
565 let ParserMatchClass = Imm1_31AsmOperand;
568 /// imm0_15 predicate - Immediate in the range [0,15].
569 def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; }
570 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
571 return Imm >= 0 && Imm < 16;
573 let ParserMatchClass = Imm0_15AsmOperand;
576 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
577 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
578 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
579 return Imm >= 0 && Imm < 32;
581 let ParserMatchClass = Imm0_31AsmOperand;
584 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
585 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
586 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
587 return Imm >= 0 && Imm < 32;
589 let ParserMatchClass = Imm0_32AsmOperand;
592 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
593 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
594 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
595 return Imm >= 0 && Imm < 64;
597 let ParserMatchClass = Imm0_63AsmOperand;
600 /// imm0_255 predicate - Immediate in the range [0,255].
601 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
602 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
603 let ParserMatchClass = Imm0_255AsmOperand;
606 /// imm0_65535 - An immediate is in the range [0.65535].
607 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
608 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
609 return Imm >= 0 && Imm < 65536;
611 let ParserMatchClass = Imm0_65535AsmOperand;
614 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
615 // a relocatable expression.
617 // FIXME: This really needs a Thumb version separate from the ARM version.
618 // While the range is the same, and can thus use the same match class,
619 // the encoding is different so it should have a different encoder method.
620 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
621 def imm0_65535_expr : Operand<i32> {
622 let EncoderMethod = "getHiLo16ImmOpValue";
623 let ParserMatchClass = Imm0_65535ExprAsmOperand;
626 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
627 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
628 def imm24b : Operand<i32>, ImmLeaf<i32, [{
629 return Imm >= 0 && Imm <= 0xffffff;
631 let ParserMatchClass = Imm24bitAsmOperand;
635 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
637 def BitfieldAsmOperand : AsmOperandClass {
638 let Name = "Bitfield";
639 let ParserMethod = "parseBitfield";
642 def bf_inv_mask_imm : Operand<i32>,
644 return ARM::isBitFieldInvertedMask(N->getZExtValue());
646 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
647 let PrintMethod = "printBitfieldInvMaskImmOperand";
648 let DecoderMethod = "DecodeBitfieldMaskOperand";
649 let ParserMatchClass = BitfieldAsmOperand;
652 def imm1_32_XFORM: SDNodeXForm<imm, [{
653 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
655 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
656 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
657 uint64_t Imm = N->getZExtValue();
658 return Imm > 0 && Imm <= 32;
661 let PrintMethod = "printImmPlusOneOperand";
662 let ParserMatchClass = Imm1_32AsmOperand;
665 def imm1_16_XFORM: SDNodeXForm<imm, [{
666 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
668 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
669 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
671 let PrintMethod = "printImmPlusOneOperand";
672 let ParserMatchClass = Imm1_16AsmOperand;
675 // Define ARM specific addressing modes.
676 // addrmode_imm12 := reg +/- imm12
678 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
679 def addrmode_imm12 : Operand<i32>,
680 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
681 // 12-bit immediate operand. Note that instructions using this encode
682 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
683 // immediate values are as normal.
685 let EncoderMethod = "getAddrModeImm12OpValue";
686 let PrintMethod = "printAddrModeImm12Operand";
687 let DecoderMethod = "DecodeAddrModeImm12Operand";
688 let ParserMatchClass = MemImm12OffsetAsmOperand;
689 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
691 // ldst_so_reg := reg +/- reg shop imm
693 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
694 def ldst_so_reg : Operand<i32>,
695 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
696 let EncoderMethod = "getLdStSORegOpValue";
697 // FIXME: Simplify the printer
698 let PrintMethod = "printAddrMode2Operand";
699 let DecoderMethod = "DecodeSORegMemOperand";
700 let ParserMatchClass = MemRegOffsetAsmOperand;
701 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
704 // postidx_imm8 := +/- [0,255]
707 // {8} 1 is imm8 is non-negative. 0 otherwise.
708 // {7-0} [0,255] imm8 value.
709 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
710 def postidx_imm8 : Operand<i32> {
711 let PrintMethod = "printPostIdxImm8Operand";
712 let ParserMatchClass = PostIdxImm8AsmOperand;
713 let MIOperandInfo = (ops i32imm);
716 // postidx_imm8s4 := +/- [0,1020]
719 // {8} 1 is imm8 is non-negative. 0 otherwise.
720 // {7-0} [0,255] imm8 value, scaled by 4.
721 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
722 def postidx_imm8s4 : Operand<i32> {
723 let PrintMethod = "printPostIdxImm8s4Operand";
724 let ParserMatchClass = PostIdxImm8s4AsmOperand;
725 let MIOperandInfo = (ops i32imm);
729 // postidx_reg := +/- reg
731 def PostIdxRegAsmOperand : AsmOperandClass {
732 let Name = "PostIdxReg";
733 let ParserMethod = "parsePostIdxReg";
735 def postidx_reg : Operand<i32> {
736 let EncoderMethod = "getPostIdxRegOpValue";
737 let DecoderMethod = "DecodePostIdxReg";
738 let PrintMethod = "printPostIdxRegOperand";
739 let ParserMatchClass = PostIdxRegAsmOperand;
740 let MIOperandInfo = (ops GPRnopc, i32imm);
744 // addrmode2 := reg +/- imm12
745 // := reg +/- reg shop imm
747 // FIXME: addrmode2 should be refactored the rest of the way to always
748 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
749 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
750 def addrmode2 : Operand<i32>,
751 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
752 let EncoderMethod = "getAddrMode2OpValue";
753 let PrintMethod = "printAddrMode2Operand";
754 let ParserMatchClass = AddrMode2AsmOperand;
755 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
758 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
759 let Name = "PostIdxRegShifted";
760 let ParserMethod = "parsePostIdxReg";
762 def am2offset_reg : Operand<i32>,
763 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
764 [], [SDNPWantRoot]> {
765 let EncoderMethod = "getAddrMode2OffsetOpValue";
766 let PrintMethod = "printAddrMode2OffsetOperand";
767 // When using this for assembly, it's always as a post-index offset.
768 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
769 let MIOperandInfo = (ops GPRnopc, i32imm);
772 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
773 // the GPR is purely vestigal at this point.
774 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
775 def am2offset_imm : Operand<i32>,
776 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
777 [], [SDNPWantRoot]> {
778 let EncoderMethod = "getAddrMode2OffsetOpValue";
779 let PrintMethod = "printAddrMode2OffsetOperand";
780 let ParserMatchClass = AM2OffsetImmAsmOperand;
781 let MIOperandInfo = (ops GPRnopc, i32imm);
785 // addrmode3 := reg +/- reg
786 // addrmode3 := reg +/- imm8
788 // FIXME: split into imm vs. reg versions.
789 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
790 def addrmode3 : Operand<i32>,
791 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
792 let EncoderMethod = "getAddrMode3OpValue";
793 let PrintMethod = "printAddrMode3Operand";
794 let ParserMatchClass = AddrMode3AsmOperand;
795 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
798 // FIXME: split into imm vs. reg versions.
799 // FIXME: parser method to handle +/- register.
800 def AM3OffsetAsmOperand : AsmOperandClass {
801 let Name = "AM3Offset";
802 let ParserMethod = "parseAM3Offset";
804 def am3offset : Operand<i32>,
805 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
806 [], [SDNPWantRoot]> {
807 let EncoderMethod = "getAddrMode3OffsetOpValue";
808 let PrintMethod = "printAddrMode3OffsetOperand";
809 let ParserMatchClass = AM3OffsetAsmOperand;
810 let MIOperandInfo = (ops GPR, i32imm);
813 // ldstm_mode := {ia, ib, da, db}
815 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
816 let EncoderMethod = "getLdStmModeOpValue";
817 let PrintMethod = "printLdStmModeOperand";
820 // addrmode5 := reg +/- imm8*4
822 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
823 def addrmode5 : Operand<i32>,
824 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
825 let PrintMethod = "printAddrMode5Operand";
826 let EncoderMethod = "getAddrMode5OpValue";
827 let DecoderMethod = "DecodeAddrMode5Operand";
828 let ParserMatchClass = AddrMode5AsmOperand;
829 let MIOperandInfo = (ops GPR:$base, i32imm);
832 // addrmode6 := reg with optional alignment
834 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
835 def addrmode6 : Operand<i32>,
836 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
837 let PrintMethod = "printAddrMode6Operand";
838 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
839 let EncoderMethod = "getAddrMode6AddressOpValue";
840 let DecoderMethod = "DecodeAddrMode6Operand";
841 let ParserMatchClass = AddrMode6AsmOperand;
844 def am6offset : Operand<i32>,
845 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
846 [], [SDNPWantRoot]> {
847 let PrintMethod = "printAddrMode6OffsetOperand";
848 let MIOperandInfo = (ops GPR);
849 let EncoderMethod = "getAddrMode6OffsetOpValue";
850 let DecoderMethod = "DecodeGPRRegisterClass";
853 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
854 // (single element from one lane) for size 32.
855 def addrmode6oneL32 : Operand<i32>,
856 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
857 let PrintMethod = "printAddrMode6Operand";
858 let MIOperandInfo = (ops GPR:$addr, i32imm);
859 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
862 // Special version of addrmode6 to handle alignment encoding for VLD-dup
863 // instructions, specifically VLD4-dup.
864 def addrmode6dup : Operand<i32>,
865 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
866 let PrintMethod = "printAddrMode6Operand";
867 let MIOperandInfo = (ops GPR:$addr, i32imm);
868 let EncoderMethod = "getAddrMode6DupAddressOpValue";
869 // FIXME: This is close, but not quite right. The alignment specifier is
871 let ParserMatchClass = AddrMode6AsmOperand;
874 // addrmodepc := pc + reg
876 def addrmodepc : Operand<i32>,
877 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
878 let PrintMethod = "printAddrModePCOperand";
879 let MIOperandInfo = (ops GPR, i32imm);
882 // addr_offset_none := reg
884 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
885 def addr_offset_none : Operand<i32>,
886 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
887 let PrintMethod = "printAddrMode7Operand";
888 let DecoderMethod = "DecodeAddrMode7Operand";
889 let ParserMatchClass = MemNoOffsetAsmOperand;
890 let MIOperandInfo = (ops GPR:$base);
893 def nohash_imm : Operand<i32> {
894 let PrintMethod = "printNoHashImmediate";
897 def CoprocNumAsmOperand : AsmOperandClass {
898 let Name = "CoprocNum";
899 let ParserMethod = "parseCoprocNumOperand";
901 def p_imm : Operand<i32> {
902 let PrintMethod = "printPImmediate";
903 let ParserMatchClass = CoprocNumAsmOperand;
904 let DecoderMethod = "DecodeCoprocessor";
907 def CoprocRegAsmOperand : AsmOperandClass {
908 let Name = "CoprocReg";
909 let ParserMethod = "parseCoprocRegOperand";
911 def c_imm : Operand<i32> {
912 let PrintMethod = "printCImmediate";
913 let ParserMatchClass = CoprocRegAsmOperand;
915 def CoprocOptionAsmOperand : AsmOperandClass {
916 let Name = "CoprocOption";
917 let ParserMethod = "parseCoprocOptionOperand";
919 def coproc_option_imm : Operand<i32> {
920 let PrintMethod = "printCoprocOptionImm";
921 let ParserMatchClass = CoprocOptionAsmOperand;
924 //===----------------------------------------------------------------------===//
926 include "ARMInstrFormats.td"
928 //===----------------------------------------------------------------------===//
929 // Multiclass helpers...
932 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
933 /// binop that produces a value.
934 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
935 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
936 PatFrag opnode, string baseOpc, bit Commutable = 0> {
937 // The register-immediate version is re-materializable. This is useful
938 // in particular for taking the address of a local.
939 let isReMaterializable = 1 in {
940 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
941 iii, opc, "\t$Rd, $Rn, $imm",
942 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
947 let Inst{19-16} = Rn;
948 let Inst{15-12} = Rd;
949 let Inst{11-0} = imm;
952 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
953 iir, opc, "\t$Rd, $Rn, $Rm",
954 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
959 let isCommutable = Commutable;
960 let Inst{19-16} = Rn;
961 let Inst{15-12} = Rd;
962 let Inst{11-4} = 0b00000000;
966 def rsi : AsI1<opcod, (outs GPR:$Rd),
967 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
968 iis, opc, "\t$Rd, $Rn, $shift",
969 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
974 let Inst{19-16} = Rn;
975 let Inst{15-12} = Rd;
976 let Inst{11-5} = shift{11-5};
978 let Inst{3-0} = shift{3-0};
981 def rsr : AsI1<opcod, (outs GPR:$Rd),
982 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
983 iis, opc, "\t$Rd, $Rn, $shift",
984 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
989 let Inst{19-16} = Rn;
990 let Inst{15-12} = Rd;
991 let Inst{11-8} = shift{11-8};
993 let Inst{6-5} = shift{6-5};
995 let Inst{3-0} = shift{3-0};
998 // Assembly aliases for optional destination operand when it's the same
999 // as the source operand.
1000 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1001 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1002 so_imm:$imm, pred:$p,
1005 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1006 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1010 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1011 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1012 so_reg_imm:$shift, pred:$p,
1015 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1016 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1017 so_reg_reg:$shift, pred:$p,
1023 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1024 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1025 /// it is equivalent to the AsI1_bin_irs counterpart.
1026 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1027 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1028 PatFrag opnode, string baseOpc, bit Commutable = 0> {
1029 // The register-immediate version is re-materializable. This is useful
1030 // in particular for taking the address of a local.
1031 let isReMaterializable = 1 in {
1032 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1033 iii, opc, "\t$Rd, $Rn, $imm",
1034 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1039 let Inst{19-16} = Rn;
1040 let Inst{15-12} = Rd;
1041 let Inst{11-0} = imm;
1044 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1045 iir, opc, "\t$Rd, $Rn, $Rm",
1046 [/* pattern left blank */]> {
1050 let Inst{11-4} = 0b00000000;
1053 let Inst{15-12} = Rd;
1054 let Inst{19-16} = Rn;
1057 def rsi : AsI1<opcod, (outs GPR:$Rd),
1058 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1059 iis, opc, "\t$Rd, $Rn, $shift",
1060 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1065 let Inst{19-16} = Rn;
1066 let Inst{15-12} = Rd;
1067 let Inst{11-5} = shift{11-5};
1069 let Inst{3-0} = shift{3-0};
1072 def rsr : AsI1<opcod, (outs GPR:$Rd),
1073 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1074 iis, opc, "\t$Rd, $Rn, $shift",
1075 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1080 let Inst{19-16} = Rn;
1081 let Inst{15-12} = Rd;
1082 let Inst{11-8} = shift{11-8};
1084 let Inst{6-5} = shift{6-5};
1086 let Inst{3-0} = shift{3-0};
1089 // Assembly aliases for optional destination operand when it's the same
1090 // as the source operand.
1091 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1092 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1093 so_imm:$imm, pred:$p,
1096 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1097 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1101 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1102 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1103 so_reg_imm:$shift, pred:$p,
1106 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1107 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1108 so_reg_reg:$shift, pred:$p,
1114 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1116 /// These opcodes will be converted to the real non-S opcodes by
1117 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1118 let hasPostISelHook = 1, Defs = [CPSR] in {
1119 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1120 InstrItinClass iis, PatFrag opnode,
1121 bit Commutable = 0> {
1122 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1124 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1126 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1128 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1129 let isCommutable = Commutable;
1131 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1132 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1134 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1135 so_reg_imm:$shift))]>;
1137 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1138 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1140 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1141 so_reg_reg:$shift))]>;
1145 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1146 /// operands are reversed.
1147 let hasPostISelHook = 1, Defs = [CPSR] in {
1148 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1149 InstrItinClass iis, PatFrag opnode,
1150 bit Commutable = 0> {
1151 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1153 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1155 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1156 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1158 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1161 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1162 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1164 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1169 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1170 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1171 /// a explicit result, only implicitly set CPSR.
1172 let isCompare = 1, Defs = [CPSR] in {
1173 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1174 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1175 PatFrag opnode, bit Commutable = 0> {
1176 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1178 [(opnode GPR:$Rn, so_imm:$imm)]> {
1183 let Inst{19-16} = Rn;
1184 let Inst{15-12} = 0b0000;
1185 let Inst{11-0} = imm;
1187 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1189 [(opnode GPR:$Rn, GPR:$Rm)]> {
1192 let isCommutable = Commutable;
1195 let Inst{19-16} = Rn;
1196 let Inst{15-12} = 0b0000;
1197 let Inst{11-4} = 0b00000000;
1200 def rsi : AI1<opcod, (outs),
1201 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1202 opc, "\t$Rn, $shift",
1203 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1208 let Inst{19-16} = Rn;
1209 let Inst{15-12} = 0b0000;
1210 let Inst{11-5} = shift{11-5};
1212 let Inst{3-0} = shift{3-0};
1214 def rsr : AI1<opcod, (outs),
1215 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1216 opc, "\t$Rn, $shift",
1217 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1222 let Inst{19-16} = Rn;
1223 let Inst{15-12} = 0b0000;
1224 let Inst{11-8} = shift{11-8};
1226 let Inst{6-5} = shift{6-5};
1228 let Inst{3-0} = shift{3-0};
1234 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1235 /// register and one whose operand is a register rotated by 8/16/24.
1236 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1237 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1238 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1239 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1240 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1241 Requires<[IsARM, HasV6]> {
1245 let Inst{19-16} = 0b1111;
1246 let Inst{15-12} = Rd;
1247 let Inst{11-10} = rot;
1251 class AI_ext_rrot_np<bits<8> opcod, string opc>
1252 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1253 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1254 Requires<[IsARM, HasV6]> {
1256 let Inst{19-16} = 0b1111;
1257 let Inst{11-10} = rot;
1260 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1261 /// register and one whose operand is a register rotated by 8/16/24.
1262 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1263 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1264 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1265 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1266 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1267 Requires<[IsARM, HasV6]> {
1272 let Inst{19-16} = Rn;
1273 let Inst{15-12} = Rd;
1274 let Inst{11-10} = rot;
1275 let Inst{9-4} = 0b000111;
1279 class AI_exta_rrot_np<bits<8> opcod, string opc>
1280 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1281 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1282 Requires<[IsARM, HasV6]> {
1285 let Inst{19-16} = Rn;
1286 let Inst{11-10} = rot;
1289 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1290 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1291 string baseOpc, bit Commutable = 0> {
1292 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1293 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1294 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1295 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1301 let Inst{15-12} = Rd;
1302 let Inst{19-16} = Rn;
1303 let Inst{11-0} = imm;
1305 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1306 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1307 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1312 let Inst{11-4} = 0b00000000;
1314 let isCommutable = Commutable;
1316 let Inst{15-12} = Rd;
1317 let Inst{19-16} = Rn;
1319 def rsi : AsI1<opcod, (outs GPR:$Rd),
1320 (ins GPR:$Rn, so_reg_imm:$shift),
1321 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1322 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1328 let Inst{19-16} = Rn;
1329 let Inst{15-12} = Rd;
1330 let Inst{11-5} = shift{11-5};
1332 let Inst{3-0} = shift{3-0};
1334 def rsr : AsI1<opcod, (outs GPR:$Rd),
1335 (ins GPR:$Rn, so_reg_reg:$shift),
1336 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1337 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1343 let Inst{19-16} = Rn;
1344 let Inst{15-12} = Rd;
1345 let Inst{11-8} = shift{11-8};
1347 let Inst{6-5} = shift{6-5};
1349 let Inst{3-0} = shift{3-0};
1353 // Assembly aliases for optional destination operand when it's the same
1354 // as the source operand.
1355 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1356 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1357 so_imm:$imm, pred:$p,
1360 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1361 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1365 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1366 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1367 so_reg_imm:$shift, pred:$p,
1370 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1371 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1372 so_reg_reg:$shift, pred:$p,
1377 /// AI1_rsc_irs - Define instructions and patterns for rsc
1378 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1380 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1381 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1382 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1383 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1389 let Inst{15-12} = Rd;
1390 let Inst{19-16} = Rn;
1391 let Inst{11-0} = imm;
1393 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1394 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1395 [/* pattern left blank */]> {
1399 let Inst{11-4} = 0b00000000;
1402 let Inst{15-12} = Rd;
1403 let Inst{19-16} = Rn;
1405 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1406 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1407 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1413 let Inst{19-16} = Rn;
1414 let Inst{15-12} = Rd;
1415 let Inst{11-5} = shift{11-5};
1417 let Inst{3-0} = shift{3-0};
1419 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1420 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1421 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1427 let Inst{19-16} = Rn;
1428 let Inst{15-12} = Rd;
1429 let Inst{11-8} = shift{11-8};
1431 let Inst{6-5} = shift{6-5};
1433 let Inst{3-0} = shift{3-0};
1437 // Assembly aliases for optional destination operand when it's the same
1438 // as the source operand.
1439 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1440 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1441 so_imm:$imm, pred:$p,
1444 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1445 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1449 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1450 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1451 so_reg_imm:$shift, pred:$p,
1454 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1455 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1456 so_reg_reg:$shift, pred:$p,
1461 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1462 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1463 InstrItinClass iir, PatFrag opnode> {
1464 // Note: We use the complex addrmode_imm12 rather than just an input
1465 // GPR and a constrained immediate so that we can use this to match
1466 // frame index references and avoid matching constant pool references.
1467 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1468 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1469 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1472 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1473 let Inst{19-16} = addr{16-13}; // Rn
1474 let Inst{15-12} = Rt;
1475 let Inst{11-0} = addr{11-0}; // imm12
1477 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1478 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1479 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1482 let shift{4} = 0; // Inst{4} = 0
1483 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1484 let Inst{19-16} = shift{16-13}; // Rn
1485 let Inst{15-12} = Rt;
1486 let Inst{11-0} = shift{11-0};
1491 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1492 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1493 InstrItinClass iir, PatFrag opnode> {
1494 // Note: We use the complex addrmode_imm12 rather than just an input
1495 // GPR and a constrained immediate so that we can use this to match
1496 // frame index references and avoid matching constant pool references.
1497 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1498 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1499 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1502 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1503 let Inst{19-16} = addr{16-13}; // Rn
1504 let Inst{15-12} = Rt;
1505 let Inst{11-0} = addr{11-0}; // imm12
1507 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1508 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1509 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1512 let shift{4} = 0; // Inst{4} = 0
1513 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1514 let Inst{19-16} = shift{16-13}; // Rn
1515 let Inst{15-12} = Rt;
1516 let Inst{11-0} = shift{11-0};
1522 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1523 InstrItinClass iir, PatFrag opnode> {
1524 // Note: We use the complex addrmode_imm12 rather than just an input
1525 // GPR and a constrained immediate so that we can use this to match
1526 // frame index references and avoid matching constant pool references.
1527 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1528 (ins GPR:$Rt, addrmode_imm12:$addr),
1529 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1530 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1533 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1534 let Inst{19-16} = addr{16-13}; // Rn
1535 let Inst{15-12} = Rt;
1536 let Inst{11-0} = addr{11-0}; // imm12
1538 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1539 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1540 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1543 let shift{4} = 0; // Inst{4} = 0
1544 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1545 let Inst{19-16} = shift{16-13}; // Rn
1546 let Inst{15-12} = Rt;
1547 let Inst{11-0} = shift{11-0};
1551 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1552 InstrItinClass iir, PatFrag opnode> {
1553 // Note: We use the complex addrmode_imm12 rather than just an input
1554 // GPR and a constrained immediate so that we can use this to match
1555 // frame index references and avoid matching constant pool references.
1556 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1557 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1558 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1559 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1562 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1563 let Inst{19-16} = addr{16-13}; // Rn
1564 let Inst{15-12} = Rt;
1565 let Inst{11-0} = addr{11-0}; // imm12
1567 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1568 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1569 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1572 let shift{4} = 0; // Inst{4} = 0
1573 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1574 let Inst{19-16} = shift{16-13}; // Rn
1575 let Inst{15-12} = Rt;
1576 let Inst{11-0} = shift{11-0};
1581 //===----------------------------------------------------------------------===//
1583 //===----------------------------------------------------------------------===//
1585 //===----------------------------------------------------------------------===//
1586 // Miscellaneous Instructions.
1589 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1590 /// the function. The first operand is the ID# for this instruction, the second
1591 /// is the index into the MachineConstantPool that this is, the third is the
1592 /// size in bytes of this constant pool entry.
1593 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1594 def CONSTPOOL_ENTRY :
1595 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1596 i32imm:$size), NoItinerary, []>;
1598 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1599 // from removing one half of the matched pairs. That breaks PEI, which assumes
1600 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1601 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1602 def ADJCALLSTACKUP :
1603 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1604 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1606 def ADJCALLSTACKDOWN :
1607 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1608 [(ARMcallseq_start timm:$amt)]>;
1611 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1612 // (These pseudos use a hand-written selection code).
1613 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1614 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1615 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1617 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1618 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1620 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1621 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1623 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1624 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1626 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1627 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1629 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1630 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1632 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1633 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1635 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1636 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1637 GPR:$set1, GPR:$set2),
1641 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1642 Requires<[IsARM, HasV6T2]> {
1643 let Inst{27-16} = 0b001100100000;
1644 let Inst{15-8} = 0b11110000;
1645 let Inst{7-0} = 0b00000000;
1648 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1649 Requires<[IsARM, HasV6T2]> {
1650 let Inst{27-16} = 0b001100100000;
1651 let Inst{15-8} = 0b11110000;
1652 let Inst{7-0} = 0b00000001;
1655 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1656 Requires<[IsARM, HasV6T2]> {
1657 let Inst{27-16} = 0b001100100000;
1658 let Inst{15-8} = 0b11110000;
1659 let Inst{7-0} = 0b00000010;
1662 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1663 Requires<[IsARM, HasV6T2]> {
1664 let Inst{27-16} = 0b001100100000;
1665 let Inst{15-8} = 0b11110000;
1666 let Inst{7-0} = 0b00000011;
1669 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1670 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1675 let Inst{15-12} = Rd;
1676 let Inst{19-16} = Rn;
1677 let Inst{27-20} = 0b01101000;
1678 let Inst{7-4} = 0b1011;
1679 let Inst{11-8} = 0b1111;
1682 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1683 []>, Requires<[IsARM, HasV6T2]> {
1684 let Inst{27-16} = 0b001100100000;
1685 let Inst{15-8} = 0b11110000;
1686 let Inst{7-0} = 0b00000100;
1689 // The i32imm operand $val can be used by a debugger to store more information
1690 // about the breakpoint.
1691 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1692 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1694 let Inst{3-0} = val{3-0};
1695 let Inst{19-8} = val{15-4};
1696 let Inst{27-20} = 0b00010010;
1697 let Inst{7-4} = 0b0111;
1700 // Change Processor State
1701 // FIXME: We should use InstAlias to handle the optional operands.
1702 class CPS<dag iops, string asm_ops>
1703 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1704 []>, Requires<[IsARM]> {
1710 let Inst{31-28} = 0b1111;
1711 let Inst{27-20} = 0b00010000;
1712 let Inst{19-18} = imod;
1713 let Inst{17} = M; // Enabled if mode is set;
1714 let Inst{16-9} = 0b00000000;
1715 let Inst{8-6} = iflags;
1717 let Inst{4-0} = mode;
1720 let DecoderMethod = "DecodeCPSInstruction" in {
1722 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1723 "$imod\t$iflags, $mode">;
1724 let mode = 0, M = 0 in
1725 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1727 let imod = 0, iflags = 0, M = 1 in
1728 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1731 // Preload signals the memory system of possible future data/instruction access.
1732 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1734 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1735 !strconcat(opc, "\t$addr"),
1736 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1739 let Inst{31-26} = 0b111101;
1740 let Inst{25} = 0; // 0 for immediate form
1741 let Inst{24} = data;
1742 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1743 let Inst{22} = read;
1744 let Inst{21-20} = 0b01;
1745 let Inst{19-16} = addr{16-13}; // Rn
1746 let Inst{15-12} = 0b1111;
1747 let Inst{11-0} = addr{11-0}; // imm12
1750 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1751 !strconcat(opc, "\t$shift"),
1752 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1754 let Inst{31-26} = 0b111101;
1755 let Inst{25} = 1; // 1 for register form
1756 let Inst{24} = data;
1757 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1758 let Inst{22} = read;
1759 let Inst{21-20} = 0b01;
1760 let Inst{19-16} = shift{16-13}; // Rn
1761 let Inst{15-12} = 0b1111;
1762 let Inst{11-0} = shift{11-0};
1767 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1768 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1769 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1771 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1772 "setend\t$end", []>, Requires<[IsARM]> {
1774 let Inst{31-10} = 0b1111000100000001000000;
1779 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1780 []>, Requires<[IsARM, HasV7]> {
1782 let Inst{27-4} = 0b001100100000111100001111;
1783 let Inst{3-0} = opt;
1786 // A5.4 Permanently UNDEFINED instructions.
1787 let isBarrier = 1, isTerminator = 1 in
1788 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1791 let Inst = 0xe7ffdefe;
1794 // Address computation and loads and stores in PIC mode.
1795 let isNotDuplicable = 1 in {
1796 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1798 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1800 let AddedComplexity = 10 in {
1801 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1803 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1805 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1807 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1809 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1811 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1813 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1815 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1817 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1819 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1821 let AddedComplexity = 10 in {
1822 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1823 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1825 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1826 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1827 addrmodepc:$addr)]>;
1829 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1830 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1832 } // isNotDuplicable = 1
1835 // LEApcrel - Load a pc-relative address into a register without offending the
1837 let neverHasSideEffects = 1, isReMaterializable = 1 in
1838 // The 'adr' mnemonic encodes differently if the label is before or after
1839 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1840 // know until then which form of the instruction will be used.
1841 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1842 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1845 let Inst{27-25} = 0b001;
1847 let Inst{23-22} = label{13-12};
1850 let Inst{19-16} = 0b1111;
1851 let Inst{15-12} = Rd;
1852 let Inst{11-0} = label{11-0};
1854 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1857 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1858 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1861 //===----------------------------------------------------------------------===//
1862 // Control Flow Instructions.
1865 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1867 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1868 "bx", "\tlr", [(ARMretflag)]>,
1869 Requires<[IsARM, HasV4T]> {
1870 let Inst{27-0} = 0b0001001011111111111100011110;
1874 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1875 "mov", "\tpc, lr", [(ARMretflag)]>,
1876 Requires<[IsARM, NoV4T]> {
1877 let Inst{27-0} = 0b0001101000001111000000001110;
1881 // Indirect branches
1882 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1884 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1885 [(brind GPR:$dst)]>,
1886 Requires<[IsARM, HasV4T]> {
1888 let Inst{31-4} = 0b1110000100101111111111110001;
1889 let Inst{3-0} = dst;
1892 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1893 "bx", "\t$dst", [/* pattern left blank */]>,
1894 Requires<[IsARM, HasV4T]> {
1896 let Inst{27-4} = 0b000100101111111111110001;
1897 let Inst{3-0} = dst;
1901 // SP is marked as a use to prevent stack-pointer assignments that appear
1902 // immediately before calls from potentially appearing dead.
1904 // FIXME: Do we really need a non-predicated version? If so, it should
1905 // at least be a pseudo instruction expanding to the predicated version
1906 // at MC lowering time.
1907 Defs = [LR], Uses = [SP] in {
1908 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1909 IIC_Br, "bl\t$func",
1910 [(ARMcall tglobaladdr:$func)]>,
1911 Requires<[IsARM, IsNotIOS]> {
1912 let Inst{31-28} = 0b1110;
1914 let Inst{23-0} = func;
1915 let DecoderMethod = "DecodeBranchImmInstruction";
1918 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1919 IIC_Br, "bl", "\t$func",
1920 [(ARMcall_pred tglobaladdr:$func)]>,
1921 Requires<[IsARM, IsNotIOS]> {
1923 let Inst{23-0} = func;
1924 let DecoderMethod = "DecodeBranchImmInstruction";
1928 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1929 IIC_Br, "blx\t$func",
1930 [(ARMcall GPR:$func)]>,
1931 Requires<[IsARM, HasV5T, IsNotIOS]> {
1933 let Inst{31-4} = 0b1110000100101111111111110011;
1934 let Inst{3-0} = func;
1937 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1938 IIC_Br, "blx", "\t$func",
1939 [(ARMcall_pred GPR:$func)]>,
1940 Requires<[IsARM, HasV5T, IsNotIOS]> {
1942 let Inst{27-4} = 0b000100101111111111110011;
1943 let Inst{3-0} = func;
1947 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1948 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1949 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1950 Requires<[IsARM, HasV4T, IsNotIOS]>;
1953 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1954 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1955 Requires<[IsARM, NoV4T, IsNotIOS]>;
1957 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1958 // return stack predictor.
1959 def BMOVPCB_CALL : ARMPseudoInst<(outs),
1960 (ins bl_target:$func, variable_ops),
1961 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1962 Requires<[IsARM, IsNotIOS]>;
1966 // On IOS R9 is call-clobbered.
1967 // R7 is marked as a use to prevent frame-pointer assignments from being
1968 // moved above / below calls.
1969 Defs = [LR], Uses = [R7, SP] in {
1970 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1972 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1973 Requires<[IsARM, IsIOS]>;
1975 def BLr9_pred : ARMPseudoExpand<(outs),
1976 (ins bl_target:$func, pred:$p, variable_ops),
1978 [(ARMcall_pred tglobaladdr:$func)],
1979 (BL_pred bl_target:$func, pred:$p)>,
1980 Requires<[IsARM, IsIOS]>;
1983 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1985 [(ARMcall GPR:$func)],
1987 Requires<[IsARM, HasV5T, IsIOS]>;
1989 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1991 [(ARMcall_pred GPR:$func)],
1992 (BLX_pred GPR:$func, pred:$p)>,
1993 Requires<[IsARM, HasV5T, IsIOS]>;
1996 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1997 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1998 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1999 Requires<[IsARM, HasV4T, IsIOS]>;
2002 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
2003 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2004 Requires<[IsARM, NoV4T, IsIOS]>;
2006 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2007 // return stack predictor.
2008 def BMOVPCBr9_CALL : ARMPseudoInst<(outs),(ins bl_target:$func, variable_ops),
2009 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2010 Requires<[IsARM, IsIOS]>;
2013 let isBranch = 1, isTerminator = 1 in {
2014 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2015 // a two-value operand where a dag node expects two operands. :(
2016 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2017 IIC_Br, "b", "\t$target",
2018 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2020 let Inst{23-0} = target;
2021 let DecoderMethod = "DecodeBranchImmInstruction";
2024 let isBarrier = 1 in {
2025 // B is "predicable" since it's just a Bcc with an 'always' condition.
2026 let isPredicable = 1 in
2027 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2028 // should be sufficient.
2029 // FIXME: Is B really a Barrier? That doesn't seem right.
2030 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2031 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2033 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2034 def BR_JTr : ARMPseudoInst<(outs),
2035 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2037 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2038 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2039 // into i12 and rs suffixed versions.
2040 def BR_JTm : ARMPseudoInst<(outs),
2041 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2043 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2045 def BR_JTadd : ARMPseudoInst<(outs),
2046 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2048 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2050 } // isNotDuplicable = 1, isIndirectBranch = 1
2056 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2057 "blx\t$target", []>,
2058 Requires<[IsARM, HasV5T]> {
2059 let Inst{31-25} = 0b1111101;
2061 let Inst{23-0} = target{24-1};
2062 let Inst{24} = target{0};
2065 // Branch and Exchange Jazelle
2066 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2067 [/* pattern left blank */]> {
2069 let Inst{23-20} = 0b0010;
2070 let Inst{19-8} = 0xfff;
2071 let Inst{7-4} = 0b0010;
2072 let Inst{3-0} = func;
2077 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2079 let Uses = [SP] in {
2080 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2081 IIC_Br, []>, Requires<[IsIOS]>;
2083 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2084 IIC_Br, []>, Requires<[IsIOS]>;
2086 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2088 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2089 Requires<[IsARM, IsIOS]>;
2091 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2094 Requires<[IsARM, IsIOS]>;
2098 // Non-IOS versions (the difference is R9).
2099 let Uses = [SP] in {
2100 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2101 IIC_Br, []>, Requires<[IsNotIOS]>;
2103 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2104 IIC_Br, []>, Requires<[IsNotIOS]>;
2106 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2108 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2109 Requires<[IsARM, IsNotIOS]>;
2111 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2114 Requires<[IsARM, IsNotIOS]>;
2118 // Secure Monitor Call is a system instruction.
2119 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2122 let Inst{23-4} = 0b01100000000000000111;
2123 let Inst{3-0} = opt;
2126 // Supervisor Call (Software Interrupt)
2127 let isCall = 1, Uses = [SP] in {
2128 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2130 let Inst{23-0} = svc;
2134 // Store Return State
2135 class SRSI<bit wb, string asm>
2136 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2137 NoItinerary, asm, "", []> {
2139 let Inst{31-28} = 0b1111;
2140 let Inst{27-25} = 0b100;
2144 let Inst{19-16} = 0b1101; // SP
2145 let Inst{15-5} = 0b00000101000;
2146 let Inst{4-0} = mode;
2149 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2150 let Inst{24-23} = 0;
2152 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2153 let Inst{24-23} = 0;
2155 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2156 let Inst{24-23} = 0b10;
2158 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2159 let Inst{24-23} = 0b10;
2161 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2162 let Inst{24-23} = 0b01;
2164 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2165 let Inst{24-23} = 0b01;
2167 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2168 let Inst{24-23} = 0b11;
2170 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2171 let Inst{24-23} = 0b11;
2174 // Return From Exception
2175 class RFEI<bit wb, string asm>
2176 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2177 NoItinerary, asm, "", []> {
2179 let Inst{31-28} = 0b1111;
2180 let Inst{27-25} = 0b100;
2184 let Inst{19-16} = Rn;
2185 let Inst{15-0} = 0xa00;
2188 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2189 let Inst{24-23} = 0;
2191 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2192 let Inst{24-23} = 0;
2194 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2195 let Inst{24-23} = 0b10;
2197 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2198 let Inst{24-23} = 0b10;
2200 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2201 let Inst{24-23} = 0b01;
2203 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2204 let Inst{24-23} = 0b01;
2206 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2207 let Inst{24-23} = 0b11;
2209 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2210 let Inst{24-23} = 0b11;
2213 //===----------------------------------------------------------------------===//
2214 // Load / Store Instructions.
2220 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2221 UnOpFrag<(load node:$Src)>>;
2222 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2223 UnOpFrag<(zextloadi8 node:$Src)>>;
2224 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2225 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2226 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2227 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2229 // Special LDR for loads from non-pc-relative constpools.
2230 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2231 isReMaterializable = 1, isCodeGenOnly = 1 in
2232 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2233 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2237 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2238 let Inst{19-16} = 0b1111;
2239 let Inst{15-12} = Rt;
2240 let Inst{11-0} = addr{11-0}; // imm12
2243 // Loads with zero extension
2244 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2245 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2246 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2248 // Loads with sign extension
2249 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2250 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2251 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2253 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2254 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2255 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2257 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2259 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2260 (ins addrmode3:$addr), LdMiscFrm,
2261 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2262 []>, Requires<[IsARM, HasV5TE]>;
2266 multiclass AI2_ldridx<bit isByte, string opc,
2267 InstrItinClass iii, InstrItinClass iir> {
2268 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2269 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2270 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2273 let Inst{23} = addr{12};
2274 let Inst{19-16} = addr{16-13};
2275 let Inst{11-0} = addr{11-0};
2276 let DecoderMethod = "DecodeLDRPreImm";
2277 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2280 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2281 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2282 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2285 let Inst{23} = addr{12};
2286 let Inst{19-16} = addr{16-13};
2287 let Inst{11-0} = addr{11-0};
2289 let DecoderMethod = "DecodeLDRPreReg";
2290 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2293 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2294 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2295 IndexModePost, LdFrm, iir,
2296 opc, "\t$Rt, $addr, $offset",
2297 "$addr.base = $Rn_wb", []> {
2303 let Inst{23} = offset{12};
2304 let Inst{19-16} = addr;
2305 let Inst{11-0} = offset{11-0};
2307 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2310 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2311 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2312 IndexModePost, LdFrm, iii,
2313 opc, "\t$Rt, $addr, $offset",
2314 "$addr.base = $Rn_wb", []> {
2320 let Inst{23} = offset{12};
2321 let Inst{19-16} = addr;
2322 let Inst{11-0} = offset{11-0};
2324 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2329 let mayLoad = 1, neverHasSideEffects = 1 in {
2330 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2331 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2332 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2333 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2336 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2337 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2338 (ins addrmode3:$addr), IndexModePre,
2340 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2342 let Inst{23} = addr{8}; // U bit
2343 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2344 let Inst{19-16} = addr{12-9}; // Rn
2345 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2346 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2347 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2348 let DecoderMethod = "DecodeAddrMode3Instruction";
2350 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2351 (ins addr_offset_none:$addr, am3offset:$offset),
2352 IndexModePost, LdMiscFrm, itin,
2353 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2357 let Inst{23} = offset{8}; // U bit
2358 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2359 let Inst{19-16} = addr;
2360 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2361 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2362 let DecoderMethod = "DecodeAddrMode3Instruction";
2366 let mayLoad = 1, neverHasSideEffects = 1 in {
2367 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2368 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2369 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2370 let hasExtraDefRegAllocReq = 1 in {
2371 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2372 (ins addrmode3:$addr), IndexModePre,
2373 LdMiscFrm, IIC_iLoad_d_ru,
2374 "ldrd", "\t$Rt, $Rt2, $addr!",
2375 "$addr.base = $Rn_wb", []> {
2377 let Inst{23} = addr{8}; // U bit
2378 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2379 let Inst{19-16} = addr{12-9}; // Rn
2380 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2381 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2382 let DecoderMethod = "DecodeAddrMode3Instruction";
2383 let AsmMatchConverter = "cvtLdrdPre";
2385 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2386 (ins addr_offset_none:$addr, am3offset:$offset),
2387 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2388 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2389 "$addr.base = $Rn_wb", []> {
2392 let Inst{23} = offset{8}; // U bit
2393 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2394 let Inst{19-16} = addr;
2395 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2396 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2397 let DecoderMethod = "DecodeAddrMode3Instruction";
2399 } // hasExtraDefRegAllocReq = 1
2400 } // mayLoad = 1, neverHasSideEffects = 1
2402 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2403 let mayLoad = 1, neverHasSideEffects = 1 in {
2404 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2405 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2406 IndexModePost, LdFrm, IIC_iLoad_ru,
2407 "ldrt", "\t$Rt, $addr, $offset",
2408 "$addr.base = $Rn_wb", []> {
2414 let Inst{23} = offset{12};
2415 let Inst{21} = 1; // overwrite
2416 let Inst{19-16} = addr;
2417 let Inst{11-5} = offset{11-5};
2419 let Inst{3-0} = offset{3-0};
2420 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2423 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2424 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2425 IndexModePost, LdFrm, IIC_iLoad_ru,
2426 "ldrt", "\t$Rt, $addr, $offset",
2427 "$addr.base = $Rn_wb", []> {
2433 let Inst{23} = offset{12};
2434 let Inst{21} = 1; // overwrite
2435 let Inst{19-16} = addr;
2436 let Inst{11-0} = offset{11-0};
2437 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2440 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2441 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2442 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2443 "ldrbt", "\t$Rt, $addr, $offset",
2444 "$addr.base = $Rn_wb", []> {
2450 let Inst{23} = offset{12};
2451 let Inst{21} = 1; // overwrite
2452 let Inst{19-16} = addr;
2453 let Inst{11-5} = offset{11-5};
2455 let Inst{3-0} = offset{3-0};
2456 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2459 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2460 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2461 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2462 "ldrbt", "\t$Rt, $addr, $offset",
2463 "$addr.base = $Rn_wb", []> {
2469 let Inst{23} = offset{12};
2470 let Inst{21} = 1; // overwrite
2471 let Inst{19-16} = addr;
2472 let Inst{11-0} = offset{11-0};
2473 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2476 multiclass AI3ldrT<bits<4> op, string opc> {
2477 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2478 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2479 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2480 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2482 let Inst{23} = offset{8};
2484 let Inst{11-8} = offset{7-4};
2485 let Inst{3-0} = offset{3-0};
2486 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2488 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2489 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2490 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2491 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2493 let Inst{23} = Rm{4};
2496 let Unpredictable{11-8} = 0b1111;
2497 let Inst{3-0} = Rm{3-0};
2498 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2499 let DecoderMethod = "DecodeLDR";
2503 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2504 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2505 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2510 // Stores with truncate
2511 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2512 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2513 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2516 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2517 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2518 StMiscFrm, IIC_iStore_d_r,
2519 "strd", "\t$Rt, $src2, $addr", []>,
2520 Requires<[IsARM, HasV5TE]> {
2525 multiclass AI2_stridx<bit isByte, string opc,
2526 InstrItinClass iii, InstrItinClass iir> {
2527 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2528 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2530 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2533 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2534 let Inst{19-16} = addr{16-13}; // Rn
2535 let Inst{11-0} = addr{11-0}; // imm12
2536 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2537 let DecoderMethod = "DecodeSTRPreImm";
2540 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2541 (ins GPR:$Rt, ldst_so_reg:$addr),
2542 IndexModePre, StFrm, iir,
2543 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2546 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2547 let Inst{19-16} = addr{16-13}; // Rn
2548 let Inst{11-0} = addr{11-0};
2549 let Inst{4} = 0; // Inst{4} = 0
2550 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2551 let DecoderMethod = "DecodeSTRPreReg";
2553 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2554 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2555 IndexModePost, StFrm, iir,
2556 opc, "\t$Rt, $addr, $offset",
2557 "$addr.base = $Rn_wb", []> {
2563 let Inst{23} = offset{12};
2564 let Inst{19-16} = addr;
2565 let Inst{11-0} = offset{11-0};
2567 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2570 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2571 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2572 IndexModePost, StFrm, iii,
2573 opc, "\t$Rt, $addr, $offset",
2574 "$addr.base = $Rn_wb", []> {
2580 let Inst{23} = offset{12};
2581 let Inst{19-16} = addr;
2582 let Inst{11-0} = offset{11-0};
2584 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2588 let mayStore = 1, neverHasSideEffects = 1 in {
2589 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2590 // IIC_iStore_siu depending on whether it the offset register is shifted.
2591 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2592 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2595 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2596 am2offset_reg:$offset),
2597 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2598 am2offset_reg:$offset)>;
2599 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2600 am2offset_imm:$offset),
2601 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2602 am2offset_imm:$offset)>;
2603 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2604 am2offset_reg:$offset),
2605 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2606 am2offset_reg:$offset)>;
2607 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2608 am2offset_imm:$offset),
2609 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2610 am2offset_imm:$offset)>;
2612 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2613 // put the patterns on the instruction definitions directly as ISel wants
2614 // the address base and offset to be separate operands, not a single
2615 // complex operand like we represent the instructions themselves. The
2616 // pseudos map between the two.
2617 let usesCustomInserter = 1,
2618 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2619 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2620 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2623 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2624 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2625 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2628 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2629 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2630 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2633 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2634 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2635 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2638 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2639 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2640 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2643 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2648 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2649 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2650 StMiscFrm, IIC_iStore_bh_ru,
2651 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2653 let Inst{23} = addr{8}; // U bit
2654 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2655 let Inst{19-16} = addr{12-9}; // Rn
2656 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2657 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2658 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2659 let DecoderMethod = "DecodeAddrMode3Instruction";
2662 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2663 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2664 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2665 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2666 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2667 addr_offset_none:$addr,
2668 am3offset:$offset))]> {
2671 let Inst{23} = offset{8}; // U bit
2672 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2673 let Inst{19-16} = addr;
2674 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2675 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2676 let DecoderMethod = "DecodeAddrMode3Instruction";
2679 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2680 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2681 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2682 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2683 "strd", "\t$Rt, $Rt2, $addr!",
2684 "$addr.base = $Rn_wb", []> {
2686 let Inst{23} = addr{8}; // U bit
2687 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2688 let Inst{19-16} = addr{12-9}; // Rn
2689 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2690 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2691 let DecoderMethod = "DecodeAddrMode3Instruction";
2692 let AsmMatchConverter = "cvtStrdPre";
2695 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2696 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2698 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2699 "strd", "\t$Rt, $Rt2, $addr, $offset",
2700 "$addr.base = $Rn_wb", []> {
2703 let Inst{23} = offset{8}; // U bit
2704 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2705 let Inst{19-16} = addr;
2706 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2707 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2708 let DecoderMethod = "DecodeAddrMode3Instruction";
2710 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2712 // STRT, STRBT, and STRHT
2714 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2715 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2716 IndexModePost, StFrm, IIC_iStore_bh_ru,
2717 "strbt", "\t$Rt, $addr, $offset",
2718 "$addr.base = $Rn_wb", []> {
2724 let Inst{23} = offset{12};
2725 let Inst{21} = 1; // overwrite
2726 let Inst{19-16} = addr;
2727 let Inst{11-5} = offset{11-5};
2729 let Inst{3-0} = offset{3-0};
2730 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2733 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2734 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2735 IndexModePost, StFrm, IIC_iStore_bh_ru,
2736 "strbt", "\t$Rt, $addr, $offset",
2737 "$addr.base = $Rn_wb", []> {
2743 let Inst{23} = offset{12};
2744 let Inst{21} = 1; // overwrite
2745 let Inst{19-16} = addr;
2746 let Inst{11-0} = offset{11-0};
2747 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2750 let mayStore = 1, neverHasSideEffects = 1 in {
2751 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2752 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2753 IndexModePost, StFrm, IIC_iStore_ru,
2754 "strt", "\t$Rt, $addr, $offset",
2755 "$addr.base = $Rn_wb", []> {
2761 let Inst{23} = offset{12};
2762 let Inst{21} = 1; // overwrite
2763 let Inst{19-16} = addr;
2764 let Inst{11-5} = offset{11-5};
2766 let Inst{3-0} = offset{3-0};
2767 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2770 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2771 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2772 IndexModePost, StFrm, IIC_iStore_ru,
2773 "strt", "\t$Rt, $addr, $offset",
2774 "$addr.base = $Rn_wb", []> {
2780 let Inst{23} = offset{12};
2781 let Inst{21} = 1; // overwrite
2782 let Inst{19-16} = addr;
2783 let Inst{11-0} = offset{11-0};
2784 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2789 multiclass AI3strT<bits<4> op, string opc> {
2790 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2791 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2792 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2793 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2795 let Inst{23} = offset{8};
2797 let Inst{11-8} = offset{7-4};
2798 let Inst{3-0} = offset{3-0};
2799 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2801 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2802 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2803 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2804 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2806 let Inst{23} = Rm{4};
2809 let Inst{3-0} = Rm{3-0};
2810 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2815 defm STRHT : AI3strT<0b1011, "strht">;
2818 //===----------------------------------------------------------------------===//
2819 // Load / store multiple Instructions.
2822 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2823 InstrItinClass itin, InstrItinClass itin_upd> {
2824 // IA is the default, so no need for an explicit suffix on the
2825 // mnemonic here. Without it is the cannonical spelling.
2827 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2828 IndexModeNone, f, itin,
2829 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2830 let Inst{24-23} = 0b01; // Increment After
2831 let Inst{22} = P_bit;
2832 let Inst{21} = 0; // No writeback
2833 let Inst{20} = L_bit;
2836 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2837 IndexModeUpd, f, itin_upd,
2838 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2839 let Inst{24-23} = 0b01; // Increment After
2840 let Inst{22} = P_bit;
2841 let Inst{21} = 1; // Writeback
2842 let Inst{20} = L_bit;
2844 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2847 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2848 IndexModeNone, f, itin,
2849 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2850 let Inst{24-23} = 0b00; // Decrement After
2851 let Inst{22} = P_bit;
2852 let Inst{21} = 0; // No writeback
2853 let Inst{20} = L_bit;
2856 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2857 IndexModeUpd, f, itin_upd,
2858 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2859 let Inst{24-23} = 0b00; // Decrement After
2860 let Inst{22} = P_bit;
2861 let Inst{21} = 1; // Writeback
2862 let Inst{20} = L_bit;
2864 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2867 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2868 IndexModeNone, f, itin,
2869 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2870 let Inst{24-23} = 0b10; // Decrement Before
2871 let Inst{22} = P_bit;
2872 let Inst{21} = 0; // No writeback
2873 let Inst{20} = L_bit;
2876 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2877 IndexModeUpd, f, itin_upd,
2878 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2879 let Inst{24-23} = 0b10; // Decrement Before
2880 let Inst{22} = P_bit;
2881 let Inst{21} = 1; // Writeback
2882 let Inst{20} = L_bit;
2884 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2887 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2888 IndexModeNone, f, itin,
2889 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2890 let Inst{24-23} = 0b11; // Increment Before
2891 let Inst{22} = P_bit;
2892 let Inst{21} = 0; // No writeback
2893 let Inst{20} = L_bit;
2896 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2897 IndexModeUpd, f, itin_upd,
2898 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2899 let Inst{24-23} = 0b11; // Increment Before
2900 let Inst{22} = P_bit;
2901 let Inst{21} = 1; // Writeback
2902 let Inst{20} = L_bit;
2904 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2908 let neverHasSideEffects = 1 in {
2910 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2911 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2914 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2915 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2918 } // neverHasSideEffects
2920 // FIXME: remove when we have a way to marking a MI with these properties.
2921 // FIXME: Should pc be an implicit operand like PICADD, etc?
2922 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2923 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2924 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2925 reglist:$regs, variable_ops),
2926 4, IIC_iLoad_mBr, [],
2927 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2928 RegConstraint<"$Rn = $wb">;
2930 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2931 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2934 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2935 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2940 //===----------------------------------------------------------------------===//
2941 // Move Instructions.
2944 let neverHasSideEffects = 1 in
2945 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2946 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2950 let Inst{19-16} = 0b0000;
2951 let Inst{11-4} = 0b00000000;
2954 let Inst{15-12} = Rd;
2957 def : ARMInstAlias<"movs${p} $Rd, $Rm",
2958 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
2960 // A version for the smaller set of tail call registers.
2961 let neverHasSideEffects = 1 in
2962 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2963 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2967 let Inst{11-4} = 0b00000000;
2970 let Inst{15-12} = Rd;
2973 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2974 DPSoRegRegFrm, IIC_iMOVsr,
2975 "mov", "\t$Rd, $src",
2976 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2979 let Inst{15-12} = Rd;
2980 let Inst{19-16} = 0b0000;
2981 let Inst{11-8} = src{11-8};
2983 let Inst{6-5} = src{6-5};
2985 let Inst{3-0} = src{3-0};
2989 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2990 DPSoRegImmFrm, IIC_iMOVsr,
2991 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2995 let Inst{15-12} = Rd;
2996 let Inst{19-16} = 0b0000;
2997 let Inst{11-5} = src{11-5};
2999 let Inst{3-0} = src{3-0};
3003 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3004 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3005 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
3009 let Inst{15-12} = Rd;
3010 let Inst{19-16} = 0b0000;
3011 let Inst{11-0} = imm;
3014 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3015 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3017 "movw", "\t$Rd, $imm",
3018 [(set GPR:$Rd, imm0_65535:$imm)]>,
3019 Requires<[IsARM, HasV6T2]>, UnaryDP {
3022 let Inst{15-12} = Rd;
3023 let Inst{11-0} = imm{11-0};
3024 let Inst{19-16} = imm{15-12};
3027 let DecoderMethod = "DecodeArmMOVTWInstruction";
3030 def : InstAlias<"mov${p} $Rd, $imm",
3031 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3034 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3035 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3037 let Constraints = "$src = $Rd" in {
3038 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3039 (ins GPR:$src, imm0_65535_expr:$imm),
3041 "movt", "\t$Rd, $imm",
3043 (or (and GPR:$src, 0xffff),
3044 lo16AllZero:$imm))]>, UnaryDP,
3045 Requires<[IsARM, HasV6T2]> {
3048 let Inst{15-12} = Rd;
3049 let Inst{11-0} = imm{11-0};
3050 let Inst{19-16} = imm{15-12};
3053 let DecoderMethod = "DecodeArmMOVTWInstruction";
3056 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3057 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3061 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3062 Requires<[IsARM, HasV6T2]>;
3064 let Uses = [CPSR] in
3065 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3066 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3069 // These aren't really mov instructions, but we have to define them this way
3070 // due to flag operands.
3072 let Defs = [CPSR] in {
3073 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3074 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3076 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3077 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3081 //===----------------------------------------------------------------------===//
3082 // Extend Instructions.
3087 def SXTB : AI_ext_rrot<0b01101010,
3088 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3089 def SXTH : AI_ext_rrot<0b01101011,
3090 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3092 def SXTAB : AI_exta_rrot<0b01101010,
3093 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3094 def SXTAH : AI_exta_rrot<0b01101011,
3095 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3097 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3099 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3103 let AddedComplexity = 16 in {
3104 def UXTB : AI_ext_rrot<0b01101110,
3105 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3106 def UXTH : AI_ext_rrot<0b01101111,
3107 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3108 def UXTB16 : AI_ext_rrot<0b01101100,
3109 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3111 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3112 // The transformation should probably be done as a combiner action
3113 // instead so we can include a check for masking back in the upper
3114 // eight bits of the source into the lower eight bits of the result.
3115 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3116 // (UXTB16r_rot GPR:$Src, 3)>;
3117 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3118 (UXTB16 GPR:$Src, 1)>;
3120 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3121 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3122 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3123 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3126 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3127 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3130 def SBFX : I<(outs GPRnopc:$Rd),
3131 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3132 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3133 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3134 Requires<[IsARM, HasV6T2]> {
3139 let Inst{27-21} = 0b0111101;
3140 let Inst{6-4} = 0b101;
3141 let Inst{20-16} = width;
3142 let Inst{15-12} = Rd;
3143 let Inst{11-7} = lsb;
3147 def UBFX : I<(outs GPR:$Rd),
3148 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3149 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3150 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3151 Requires<[IsARM, HasV6T2]> {
3156 let Inst{27-21} = 0b0111111;
3157 let Inst{6-4} = 0b101;
3158 let Inst{20-16} = width;
3159 let Inst{15-12} = Rd;
3160 let Inst{11-7} = lsb;
3164 //===----------------------------------------------------------------------===//
3165 // Arithmetic Instructions.
3168 defm ADD : AsI1_bin_irs<0b0100, "add",
3169 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3170 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3171 defm SUB : AsI1_bin_irs<0b0010, "sub",
3172 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3173 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3175 // ADD and SUB with 's' bit set.
3177 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3178 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3179 // AdjustInstrPostInstrSelection where we determine whether or not to
3180 // set the "s" bit based on CPSR liveness.
3182 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3183 // support for an optional CPSR definition that corresponds to the DAG
3184 // node's second value. We can then eliminate the implicit def of CPSR.
3185 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3186 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3187 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3188 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3190 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3191 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3193 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3194 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3197 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3198 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3199 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3201 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3202 // CPSR and the implicit def of CPSR is not needed.
3203 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3204 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3206 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3207 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3210 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3211 // The assume-no-carry-in form uses the negation of the input since add/sub
3212 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3213 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3215 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3216 (SUBri GPR:$src, so_imm_neg:$imm)>;
3217 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3218 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3220 // The with-carry-in form matches bitwise not instead of the negation.
3221 // Effectively, the inverse interpretation of the carry flag already accounts
3222 // for part of the negation.
3223 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3224 (SBCri GPR:$src, so_imm_not:$imm)>;
3226 // Note: These are implemented in C++ code, because they have to generate
3227 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3229 // (mul X, 2^n+1) -> (add (X << n), X)
3230 // (mul X, 2^n-1) -> (rsb X, (X << n))
3232 // ARM Arithmetic Instruction
3233 // GPR:$dst = GPR:$a op GPR:$b
3234 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3235 list<dag> pattern = [],
3236 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3237 string asm = "\t$Rd, $Rn, $Rm">
3238 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3242 let Inst{27-20} = op27_20;
3243 let Inst{11-4} = op11_4;
3244 let Inst{19-16} = Rn;
3245 let Inst{15-12} = Rd;
3249 // Saturating add/subtract
3251 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3252 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3253 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3254 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3255 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3256 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3257 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3258 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3260 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3261 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3264 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3265 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3266 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3267 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3268 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3269 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3270 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3271 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3272 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3273 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3274 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3275 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3277 // Signed/Unsigned add/subtract
3279 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3280 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3281 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3282 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3283 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3284 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3285 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3286 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3287 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3288 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3289 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3290 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3292 // Signed/Unsigned halving add/subtract
3294 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3295 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3296 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3297 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3298 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3299 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3300 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3301 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3302 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3303 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3304 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3305 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3307 // Unsigned Sum of Absolute Differences [and Accumulate].
3309 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3310 MulFrm /* for convenience */, NoItinerary, "usad8",
3311 "\t$Rd, $Rn, $Rm", []>,
3312 Requires<[IsARM, HasV6]> {
3316 let Inst{27-20} = 0b01111000;
3317 let Inst{15-12} = 0b1111;
3318 let Inst{7-4} = 0b0001;
3319 let Inst{19-16} = Rd;
3320 let Inst{11-8} = Rm;
3323 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3324 MulFrm /* for convenience */, NoItinerary, "usada8",
3325 "\t$Rd, $Rn, $Rm, $Ra", []>,
3326 Requires<[IsARM, HasV6]> {
3331 let Inst{27-20} = 0b01111000;
3332 let Inst{7-4} = 0b0001;
3333 let Inst{19-16} = Rd;
3334 let Inst{15-12} = Ra;
3335 let Inst{11-8} = Rm;
3339 // Signed/Unsigned saturate
3341 def SSAT : AI<(outs GPRnopc:$Rd),
3342 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3343 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3348 let Inst{27-21} = 0b0110101;
3349 let Inst{5-4} = 0b01;
3350 let Inst{20-16} = sat_imm;
3351 let Inst{15-12} = Rd;
3352 let Inst{11-7} = sh{4-0};
3353 let Inst{6} = sh{5};
3357 def SSAT16 : AI<(outs GPRnopc:$Rd),
3358 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3359 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3363 let Inst{27-20} = 0b01101010;
3364 let Inst{11-4} = 0b11110011;
3365 let Inst{15-12} = Rd;
3366 let Inst{19-16} = sat_imm;
3370 def USAT : AI<(outs GPRnopc:$Rd),
3371 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3372 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3377 let Inst{27-21} = 0b0110111;
3378 let Inst{5-4} = 0b01;
3379 let Inst{15-12} = Rd;
3380 let Inst{11-7} = sh{4-0};
3381 let Inst{6} = sh{5};
3382 let Inst{20-16} = sat_imm;
3386 def USAT16 : AI<(outs GPRnopc:$Rd),
3387 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3388 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3392 let Inst{27-20} = 0b01101110;
3393 let Inst{11-4} = 0b11110011;
3394 let Inst{15-12} = Rd;
3395 let Inst{19-16} = sat_imm;
3399 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3400 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3401 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3402 (USAT imm:$pos, GPRnopc:$a, 0)>;
3404 //===----------------------------------------------------------------------===//
3405 // Bitwise Instructions.
3408 defm AND : AsI1_bin_irs<0b0000, "and",
3409 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3410 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3411 defm ORR : AsI1_bin_irs<0b1100, "orr",
3412 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3413 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3414 defm EOR : AsI1_bin_irs<0b0001, "eor",
3415 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3416 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3417 defm BIC : AsI1_bin_irs<0b1110, "bic",
3418 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3419 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3421 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3422 // like in the actual instruction encoding. The complexity of mapping the mask
3423 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3424 // instruction description.
3425 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3426 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3427 "bfc", "\t$Rd, $imm", "$src = $Rd",
3428 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3429 Requires<[IsARM, HasV6T2]> {
3432 let Inst{27-21} = 0b0111110;
3433 let Inst{6-0} = 0b0011111;
3434 let Inst{15-12} = Rd;
3435 let Inst{11-7} = imm{4-0}; // lsb
3436 let Inst{20-16} = imm{9-5}; // msb
3439 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3440 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3441 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3442 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3443 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3444 bf_inv_mask_imm:$imm))]>,
3445 Requires<[IsARM, HasV6T2]> {
3449 let Inst{27-21} = 0b0111110;
3450 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3451 let Inst{15-12} = Rd;
3452 let Inst{11-7} = imm{4-0}; // lsb
3453 let Inst{20-16} = imm{9-5}; // width
3457 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3458 "mvn", "\t$Rd, $Rm",
3459 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3463 let Inst{19-16} = 0b0000;
3464 let Inst{11-4} = 0b00000000;
3465 let Inst{15-12} = Rd;
3468 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3469 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3470 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3474 let Inst{19-16} = 0b0000;
3475 let Inst{15-12} = Rd;
3476 let Inst{11-5} = shift{11-5};
3478 let Inst{3-0} = shift{3-0};
3480 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3481 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3482 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3486 let Inst{19-16} = 0b0000;
3487 let Inst{15-12} = Rd;
3488 let Inst{11-8} = shift{11-8};
3490 let Inst{6-5} = shift{6-5};
3492 let Inst{3-0} = shift{3-0};
3494 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3495 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3496 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3497 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3501 let Inst{19-16} = 0b0000;
3502 let Inst{15-12} = Rd;
3503 let Inst{11-0} = imm;
3506 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3507 (BICri GPR:$src, so_imm_not:$imm)>;
3509 //===----------------------------------------------------------------------===//
3510 // Multiply Instructions.
3512 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3513 string opc, string asm, list<dag> pattern>
3514 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3518 let Inst{19-16} = Rd;
3519 let Inst{11-8} = Rm;
3522 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3523 string opc, string asm, list<dag> pattern>
3524 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3529 let Inst{19-16} = RdHi;
3530 let Inst{15-12} = RdLo;
3531 let Inst{11-8} = Rm;
3535 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3536 // property. Remove them when it's possible to add those properties
3537 // on an individual MachineInstr, not just an instuction description.
3538 let isCommutable = 1 in {
3539 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3540 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3541 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3542 Requires<[IsARM, HasV6]> {
3543 let Inst{15-12} = 0b0000;
3544 let Unpredictable{15-12} = 0b1111;
3547 let Constraints = "@earlyclobber $Rd" in
3548 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3549 pred:$p, cc_out:$s),
3551 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3552 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3553 Requires<[IsARM, NoV6]>;
3556 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3557 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3558 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3559 Requires<[IsARM, HasV6]> {
3561 let Inst{15-12} = Ra;
3564 let Constraints = "@earlyclobber $Rd" in
3565 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3566 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3568 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3569 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3570 Requires<[IsARM, NoV6]>;
3572 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3573 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3574 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3575 Requires<[IsARM, HasV6T2]> {
3580 let Inst{19-16} = Rd;
3581 let Inst{15-12} = Ra;
3582 let Inst{11-8} = Rm;
3586 // Extra precision multiplies with low / high results
3587 let neverHasSideEffects = 1 in {
3588 let isCommutable = 1 in {
3589 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3590 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3591 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3592 Requires<[IsARM, HasV6]>;
3594 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3595 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3596 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3597 Requires<[IsARM, HasV6]>;
3599 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3600 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3601 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3603 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3604 Requires<[IsARM, NoV6]>;
3606 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3607 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3609 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3610 Requires<[IsARM, NoV6]>;
3614 // Multiply + accumulate
3615 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3616 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3617 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3618 Requires<[IsARM, HasV6]>;
3619 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3620 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3621 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3622 Requires<[IsARM, HasV6]>;
3624 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3625 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3626 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3627 Requires<[IsARM, HasV6]> {
3632 let Inst{19-16} = RdHi;
3633 let Inst{15-12} = RdLo;
3634 let Inst{11-8} = Rm;
3638 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3639 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3640 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3642 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3643 Requires<[IsARM, NoV6]>;
3644 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3645 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3647 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3648 Requires<[IsARM, NoV6]>;
3649 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3650 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3652 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3653 Requires<[IsARM, NoV6]>;
3656 } // neverHasSideEffects
3658 // Most significant word multiply
3659 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3660 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3661 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3662 Requires<[IsARM, HasV6]> {
3663 let Inst{15-12} = 0b1111;
3666 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3667 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3668 Requires<[IsARM, HasV6]> {
3669 let Inst{15-12} = 0b1111;
3672 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3673 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3674 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3675 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3676 Requires<[IsARM, HasV6]>;
3678 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3679 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3680 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3681 Requires<[IsARM, HasV6]>;
3683 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3684 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3685 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3686 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3687 Requires<[IsARM, HasV6]>;
3689 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3690 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3691 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3692 Requires<[IsARM, HasV6]>;
3694 multiclass AI_smul<string opc, PatFrag opnode> {
3695 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3696 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3697 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3698 (sext_inreg GPR:$Rm, i16)))]>,
3699 Requires<[IsARM, HasV5TE]>;
3701 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3702 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3703 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3704 (sra GPR:$Rm, (i32 16))))]>,
3705 Requires<[IsARM, HasV5TE]>;
3707 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3708 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3709 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3710 (sext_inreg GPR:$Rm, i16)))]>,
3711 Requires<[IsARM, HasV5TE]>;
3713 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3714 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3715 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3716 (sra GPR:$Rm, (i32 16))))]>,
3717 Requires<[IsARM, HasV5TE]>;
3719 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3720 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3721 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3722 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3723 Requires<[IsARM, HasV5TE]>;
3725 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3726 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3727 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3728 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3729 Requires<[IsARM, HasV5TE]>;
3733 multiclass AI_smla<string opc, PatFrag opnode> {
3734 let DecoderMethod = "DecodeSMLAInstruction" in {
3735 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3736 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3737 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3738 [(set GPRnopc:$Rd, (add GPR:$Ra,
3739 (opnode (sext_inreg GPRnopc:$Rn, i16),
3740 (sext_inreg GPRnopc:$Rm, i16))))]>,
3741 Requires<[IsARM, HasV5TE]>;
3743 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3744 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3745 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3747 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3748 (sra GPRnopc:$Rm, (i32 16)))))]>,
3749 Requires<[IsARM, HasV5TE]>;
3751 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3752 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3753 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3755 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3756 (sext_inreg GPRnopc:$Rm, i16))))]>,
3757 Requires<[IsARM, HasV5TE]>;
3759 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3760 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3761 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3763 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3764 (sra GPRnopc:$Rm, (i32 16)))))]>,
3765 Requires<[IsARM, HasV5TE]>;
3767 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3768 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3769 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3771 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3772 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3773 Requires<[IsARM, HasV5TE]>;
3775 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3776 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3777 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3779 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3780 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3781 Requires<[IsARM, HasV5TE]>;
3785 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3786 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3788 // Halfword multiply accumulate long: SMLAL<x><y>.
3789 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3790 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3791 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3792 Requires<[IsARM, HasV5TE]>;
3794 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3795 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3796 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3797 Requires<[IsARM, HasV5TE]>;
3799 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3800 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3801 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3802 Requires<[IsARM, HasV5TE]>;
3804 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3805 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3806 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3807 Requires<[IsARM, HasV5TE]>;
3809 // Helper class for AI_smld.
3810 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3811 InstrItinClass itin, string opc, string asm>
3812 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3815 let Inst{27-23} = 0b01110;
3816 let Inst{22} = long;
3817 let Inst{21-20} = 0b00;
3818 let Inst{11-8} = Rm;
3825 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3826 InstrItinClass itin, string opc, string asm>
3827 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3829 let Inst{15-12} = 0b1111;
3830 let Inst{19-16} = Rd;
3832 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3833 InstrItinClass itin, string opc, string asm>
3834 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3837 let Inst{19-16} = Rd;
3838 let Inst{15-12} = Ra;
3840 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3841 InstrItinClass itin, string opc, string asm>
3842 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3845 let Inst{19-16} = RdHi;
3846 let Inst{15-12} = RdLo;
3849 multiclass AI_smld<bit sub, string opc> {
3851 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3852 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3853 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3855 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3856 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3857 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3859 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3860 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3861 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3863 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3864 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3865 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3869 defm SMLA : AI_smld<0, "smla">;
3870 defm SMLS : AI_smld<1, "smls">;
3872 multiclass AI_sdml<bit sub, string opc> {
3874 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3875 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3876 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3877 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3880 defm SMUA : AI_sdml<0, "smua">;
3881 defm SMUS : AI_sdml<1, "smus">;
3883 //===----------------------------------------------------------------------===//
3884 // Misc. Arithmetic Instructions.
3887 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3888 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3889 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3891 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3892 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3893 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3894 Requires<[IsARM, HasV6T2]>;
3896 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3897 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3898 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3900 let AddedComplexity = 5 in
3901 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3902 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3903 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3904 Requires<[IsARM, HasV6]>;
3906 let AddedComplexity = 5 in
3907 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3908 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3909 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3910 Requires<[IsARM, HasV6]>;
3912 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3913 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3916 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3917 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3918 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3919 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3920 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3922 Requires<[IsARM, HasV6]>;
3924 // Alternate cases for PKHBT where identities eliminate some nodes.
3925 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3926 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3927 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3928 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3930 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3931 // will match the pattern below.
3932 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3933 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3934 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3935 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3936 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3938 Requires<[IsARM, HasV6]>;
3940 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3941 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3942 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3943 (srl GPRnopc:$src2, imm16_31:$sh)),
3944 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3945 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3946 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3947 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3949 //===----------------------------------------------------------------------===//
3950 // Comparison Instructions...
3953 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3954 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3955 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3957 // ARMcmpZ can re-use the above instruction definitions.
3958 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3959 (CMPri GPR:$src, so_imm:$imm)>;
3960 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3961 (CMPrr GPR:$src, GPR:$rhs)>;
3962 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3963 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3964 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3965 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3967 // FIXME: We have to be careful when using the CMN instruction and comparison
3968 // with 0. One would expect these two pieces of code should give identical
3984 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3985 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3986 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3987 // value of r0 and the carry bit (because the "carry bit" parameter to
3988 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3989 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3990 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3991 // parameter to AddWithCarry is defined as 0).
3993 // When x is 0 and unsigned:
3997 // ~x + 1 = 0x1 0000 0000
3998 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
4000 // Therefore, we should disable CMN when comparing against zero, until we can
4001 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
4002 // when it's a comparison which doesn't look at the 'carry' flag).
4004 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
4006 // This is related to <rdar://problem/7569620>.
4008 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
4009 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
4011 // Note that TST/TEQ don't set all the same flags that CMP does!
4012 defm TST : AI1_cmp_irs<0b1000, "tst",
4013 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4014 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4015 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4016 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4017 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4019 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
4020 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4021 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
4023 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4024 // (CMNri GPR:$src, so_imm_neg:$imm)>;
4026 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4027 (CMNzri GPR:$src, so_imm_neg:$imm)>;
4029 // Pseudo i64 compares for some floating point compares.
4030 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4032 def BCCi64 : PseudoInst<(outs),
4033 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4035 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4037 def BCCZi64 : PseudoInst<(outs),
4038 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4039 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4040 } // usesCustomInserter
4043 // Conditional moves
4044 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4045 // a two-value operand where a dag node expects two operands. :(
4046 let neverHasSideEffects = 1 in {
4048 let isCommutable = 1 in
4049 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4051 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4052 RegConstraint<"$false = $Rd">;
4054 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4055 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4057 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4058 imm:$cc, CCR:$ccr))*/]>,
4059 RegConstraint<"$false = $Rd">;
4060 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4061 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4063 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4064 imm:$cc, CCR:$ccr))*/]>,
4065 RegConstraint<"$false = $Rd">;
4068 let isMoveImm = 1 in
4069 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4070 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4073 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4075 let isMoveImm = 1 in
4076 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4077 (ins GPR:$false, so_imm:$imm, pred:$p),
4079 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4080 RegConstraint<"$false = $Rd">;
4082 // Two instruction predicate mov immediate.
4083 let isMoveImm = 1 in
4084 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4085 (ins GPR:$false, i32imm:$src, pred:$p),
4086 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4088 let isMoveImm = 1 in
4089 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4090 (ins GPR:$false, so_imm:$imm, pred:$p),
4092 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4093 RegConstraint<"$false = $Rd">;
4095 // Conditional instructions
4096 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
4098 InstrItinClass iii, InstrItinClass iir,
4099 InstrItinClass iis> {
4100 def ri : ARMPseudoExpand<(outs GPR:$Rd),
4101 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
4103 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
4104 RegConstraint<"$Rn = $Rd">;
4105 def rr : ARMPseudoExpand<(outs GPR:$Rd),
4106 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4108 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4109 RegConstraint<"$Rn = $Rd">;
4110 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
4111 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
4113 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
4114 RegConstraint<"$Rn = $Rd">;
4115 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
4116 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
4118 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
4119 RegConstraint<"$Rn = $Rd">;
4122 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4123 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4124 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4125 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4126 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4127 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4129 } // neverHasSideEffects
4132 //===----------------------------------------------------------------------===//
4133 // Atomic operations intrinsics
4136 def MemBarrierOptOperand : AsmOperandClass {
4137 let Name = "MemBarrierOpt";
4138 let ParserMethod = "parseMemBarrierOptOperand";
4140 def memb_opt : Operand<i32> {
4141 let PrintMethod = "printMemBOption";
4142 let ParserMatchClass = MemBarrierOptOperand;
4143 let DecoderMethod = "DecodeMemBarrierOption";
4146 // memory barriers protect the atomic sequences
4147 let hasSideEffects = 1 in {
4148 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4149 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4150 Requires<[IsARM, HasDB]> {
4152 let Inst{31-4} = 0xf57ff05;
4153 let Inst{3-0} = opt;
4157 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4158 "dsb", "\t$opt", []>,
4159 Requires<[IsARM, HasDB]> {
4161 let Inst{31-4} = 0xf57ff04;
4162 let Inst{3-0} = opt;
4165 // ISB has only full system option
4166 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4167 "isb", "\t$opt", []>,
4168 Requires<[IsARM, HasDB]> {
4170 let Inst{31-4} = 0xf57ff06;
4171 let Inst{3-0} = opt;
4174 // Pseudo isntruction that combines movs + predicated rsbmi
4175 // to implement integer ABS
4176 let usesCustomInserter = 1, Defs = [CPSR] in {
4177 def ABS : ARMPseudoInst<
4178 (outs GPR:$dst), (ins GPR:$src),
4179 8, NoItinerary, []>;
4182 let usesCustomInserter = 1 in {
4183 let Defs = [CPSR] in {
4184 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4185 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4186 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4187 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4188 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4189 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4190 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4191 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4192 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4193 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4194 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4195 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4196 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4197 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4198 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4199 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4200 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4201 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4202 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4203 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4204 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4205 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4206 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4207 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4208 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4209 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4210 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4211 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4212 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4213 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4214 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4215 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4216 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4217 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4218 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4219 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4220 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4221 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4222 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4223 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4224 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4225 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4226 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4227 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4228 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4229 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4230 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4231 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4232 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4233 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4234 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4235 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4236 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4237 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4238 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4239 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4240 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4241 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4242 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4243 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4244 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4245 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4246 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4247 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4248 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4249 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4250 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4251 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4252 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4253 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4254 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4255 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4256 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4257 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4258 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4259 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4261 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4262 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4264 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4265 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4267 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4268 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4270 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4271 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4273 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4275 def ATOMIC_SWAP_I8 : PseudoInst<
4276 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4277 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4278 def ATOMIC_SWAP_I16 : PseudoInst<
4279 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4280 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4281 def ATOMIC_SWAP_I32 : PseudoInst<
4282 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4283 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4285 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4287 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4288 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4289 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4290 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4291 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4292 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4293 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4297 let mayLoad = 1 in {
4298 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4300 "ldrexb", "\t$Rt, $addr", []>;
4301 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4302 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4303 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4304 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4305 let hasExtraDefRegAllocReq = 1 in
4306 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4307 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4308 let DecoderMethod = "DecodeDoubleRegLoad";
4312 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4313 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4314 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4315 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4316 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4317 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4318 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4319 let hasExtraSrcRegAllocReq = 1 in
4320 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4321 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4322 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4323 let DecoderMethod = "DecodeDoubleRegStore";
4328 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4329 Requires<[IsARM, HasV7]> {
4330 let Inst{31-0} = 0b11110101011111111111000000011111;
4333 // SWP/SWPB are deprecated in V6/V7.
4334 let mayLoad = 1, mayStore = 1 in {
4335 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4337 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4341 //===----------------------------------------------------------------------===//
4342 // Coprocessor Instructions.
4345 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4346 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4347 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4348 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4349 imm:$CRm, imm:$opc2)]> {
4357 let Inst{3-0} = CRm;
4359 let Inst{7-5} = opc2;
4360 let Inst{11-8} = cop;
4361 let Inst{15-12} = CRd;
4362 let Inst{19-16} = CRn;
4363 let Inst{23-20} = opc1;
4366 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4367 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4368 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4369 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4370 imm:$CRm, imm:$opc2)]> {
4371 let Inst{31-28} = 0b1111;
4379 let Inst{3-0} = CRm;
4381 let Inst{7-5} = opc2;
4382 let Inst{11-8} = cop;
4383 let Inst{15-12} = CRd;
4384 let Inst{19-16} = CRn;
4385 let Inst{23-20} = opc1;
4388 class ACI<dag oops, dag iops, string opc, string asm,
4389 IndexMode im = IndexModeNone>
4390 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4392 let Inst{27-25} = 0b110;
4394 class ACInoP<dag oops, dag iops, string opc, string asm,
4395 IndexMode im = IndexModeNone>
4396 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4398 let Inst{31-28} = 0b1111;
4399 let Inst{27-25} = 0b110;
4401 multiclass LdStCop<bit load, bit Dbit, string asm> {
4402 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4403 asm, "\t$cop, $CRd, $addr"> {
4407 let Inst{24} = 1; // P = 1
4408 let Inst{23} = addr{8};
4409 let Inst{22} = Dbit;
4410 let Inst{21} = 0; // W = 0
4411 let Inst{20} = load;
4412 let Inst{19-16} = addr{12-9};
4413 let Inst{15-12} = CRd;
4414 let Inst{11-8} = cop;
4415 let Inst{7-0} = addr{7-0};
4416 let DecoderMethod = "DecodeCopMemInstruction";
4418 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4419 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4423 let Inst{24} = 1; // P = 1
4424 let Inst{23} = addr{8};
4425 let Inst{22} = Dbit;
4426 let Inst{21} = 1; // W = 1
4427 let Inst{20} = load;
4428 let Inst{19-16} = addr{12-9};
4429 let Inst{15-12} = CRd;
4430 let Inst{11-8} = cop;
4431 let Inst{7-0} = addr{7-0};
4432 let DecoderMethod = "DecodeCopMemInstruction";
4434 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4435 postidx_imm8s4:$offset),
4436 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4441 let Inst{24} = 0; // P = 0
4442 let Inst{23} = offset{8};
4443 let Inst{22} = Dbit;
4444 let Inst{21} = 1; // W = 1
4445 let Inst{20} = load;
4446 let Inst{19-16} = addr;
4447 let Inst{15-12} = CRd;
4448 let Inst{11-8} = cop;
4449 let Inst{7-0} = offset{7-0};
4450 let DecoderMethod = "DecodeCopMemInstruction";
4452 def _OPTION : ACI<(outs),
4453 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4454 coproc_option_imm:$option),
4455 asm, "\t$cop, $CRd, $addr, $option"> {
4460 let Inst{24} = 0; // P = 0
4461 let Inst{23} = 1; // U = 1
4462 let Inst{22} = Dbit;
4463 let Inst{21} = 0; // W = 0
4464 let Inst{20} = load;
4465 let Inst{19-16} = addr;
4466 let Inst{15-12} = CRd;
4467 let Inst{11-8} = cop;
4468 let Inst{7-0} = option;
4469 let DecoderMethod = "DecodeCopMemInstruction";
4472 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4473 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4474 asm, "\t$cop, $CRd, $addr"> {
4478 let Inst{24} = 1; // P = 1
4479 let Inst{23} = addr{8};
4480 let Inst{22} = Dbit;
4481 let Inst{21} = 0; // W = 0
4482 let Inst{20} = load;
4483 let Inst{19-16} = addr{12-9};
4484 let Inst{15-12} = CRd;
4485 let Inst{11-8} = cop;
4486 let Inst{7-0} = addr{7-0};
4487 let DecoderMethod = "DecodeCopMemInstruction";
4489 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4490 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4494 let Inst{24} = 1; // P = 1
4495 let Inst{23} = addr{8};
4496 let Inst{22} = Dbit;
4497 let Inst{21} = 1; // W = 1
4498 let Inst{20} = load;
4499 let Inst{19-16} = addr{12-9};
4500 let Inst{15-12} = CRd;
4501 let Inst{11-8} = cop;
4502 let Inst{7-0} = addr{7-0};
4503 let DecoderMethod = "DecodeCopMemInstruction";
4505 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4506 postidx_imm8s4:$offset),
4507 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4512 let Inst{24} = 0; // P = 0
4513 let Inst{23} = offset{8};
4514 let Inst{22} = Dbit;
4515 let Inst{21} = 1; // W = 1
4516 let Inst{20} = load;
4517 let Inst{19-16} = addr;
4518 let Inst{15-12} = CRd;
4519 let Inst{11-8} = cop;
4520 let Inst{7-0} = offset{7-0};
4521 let DecoderMethod = "DecodeCopMemInstruction";
4523 def _OPTION : ACInoP<(outs),
4524 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4525 coproc_option_imm:$option),
4526 asm, "\t$cop, $CRd, $addr, $option"> {
4531 let Inst{24} = 0; // P = 0
4532 let Inst{23} = 1; // U = 1
4533 let Inst{22} = Dbit;
4534 let Inst{21} = 0; // W = 0
4535 let Inst{20} = load;
4536 let Inst{19-16} = addr;
4537 let Inst{15-12} = CRd;
4538 let Inst{11-8} = cop;
4539 let Inst{7-0} = option;
4540 let DecoderMethod = "DecodeCopMemInstruction";
4544 defm LDC : LdStCop <1, 0, "ldc">;
4545 defm LDCL : LdStCop <1, 1, "ldcl">;
4546 defm STC : LdStCop <0, 0, "stc">;
4547 defm STCL : LdStCop <0, 1, "stcl">;
4548 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4549 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4550 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4551 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4553 //===----------------------------------------------------------------------===//
4554 // Move between coprocessor and ARM core register.
4557 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4559 : ABI<0b1110, oops, iops, NoItinerary, opc,
4560 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4561 let Inst{20} = direction;
4571 let Inst{15-12} = Rt;
4572 let Inst{11-8} = cop;
4573 let Inst{23-21} = opc1;
4574 let Inst{7-5} = opc2;
4575 let Inst{3-0} = CRm;
4576 let Inst{19-16} = CRn;
4579 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4581 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4582 c_imm:$CRm, imm0_7:$opc2),
4583 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4584 imm:$CRm, imm:$opc2)]>;
4585 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4586 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4587 c_imm:$CRm, 0, pred:$p)>;
4588 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4590 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4592 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4593 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4594 c_imm:$CRm, 0, pred:$p)>;
4596 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4597 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4599 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4601 : ABXI<0b1110, oops, iops, NoItinerary,
4602 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4603 let Inst{31-28} = 0b1111;
4604 let Inst{20} = direction;
4614 let Inst{15-12} = Rt;
4615 let Inst{11-8} = cop;
4616 let Inst{23-21} = opc1;
4617 let Inst{7-5} = opc2;
4618 let Inst{3-0} = CRm;
4619 let Inst{19-16} = CRn;
4622 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4624 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4625 c_imm:$CRm, imm0_7:$opc2),
4626 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4627 imm:$CRm, imm:$opc2)]>;
4628 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4629 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4631 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4633 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4635 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4636 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4639 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4640 imm:$CRm, imm:$opc2),
4641 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4643 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4644 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4645 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4646 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4647 let Inst{23-21} = 0b010;
4648 let Inst{20} = direction;
4656 let Inst{15-12} = Rt;
4657 let Inst{19-16} = Rt2;
4658 let Inst{11-8} = cop;
4659 let Inst{7-4} = opc1;
4660 let Inst{3-0} = CRm;
4663 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4664 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4666 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4668 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4669 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4670 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4671 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4672 let Inst{31-28} = 0b1111;
4673 let Inst{23-21} = 0b010;
4674 let Inst{20} = direction;
4682 let Inst{15-12} = Rt;
4683 let Inst{19-16} = Rt2;
4684 let Inst{11-8} = cop;
4685 let Inst{7-4} = opc1;
4686 let Inst{3-0} = CRm;
4689 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4690 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4692 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4694 //===----------------------------------------------------------------------===//
4695 // Move between special register and ARM core register
4698 // Move to ARM core register from Special Register
4699 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4700 "mrs", "\t$Rd, apsr", []> {
4702 let Inst{23-16} = 0b00001111;
4703 let Inst{15-12} = Rd;
4704 let Inst{7-4} = 0b0000;
4707 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4709 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4710 "mrs", "\t$Rd, spsr", []> {
4712 let Inst{23-16} = 0b01001111;
4713 let Inst{15-12} = Rd;
4714 let Inst{7-4} = 0b0000;
4717 // Move from ARM core register to Special Register
4719 // No need to have both system and application versions, the encodings are the
4720 // same and the assembly parser has no way to distinguish between them. The mask
4721 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4722 // the mask with the fields to be accessed in the special register.
4723 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4724 "msr", "\t$mask, $Rn", []> {
4729 let Inst{22} = mask{4}; // R bit
4730 let Inst{21-20} = 0b10;
4731 let Inst{19-16} = mask{3-0};
4732 let Inst{15-12} = 0b1111;
4733 let Inst{11-4} = 0b00000000;
4737 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4738 "msr", "\t$mask, $a", []> {
4743 let Inst{22} = mask{4}; // R bit
4744 let Inst{21-20} = 0b10;
4745 let Inst{19-16} = mask{3-0};
4746 let Inst{15-12} = 0b1111;
4750 //===----------------------------------------------------------------------===//
4754 // __aeabi_read_tp preserves the registers r1-r3.
4755 // This is a pseudo inst so that we can get the encoding right,
4756 // complete with fixup for the aeabi_read_tp function.
4758 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4759 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4760 [(set R0, ARMthread_pointer)]>;
4763 //===----------------------------------------------------------------------===//
4764 // SJLJ Exception handling intrinsics
4765 // eh_sjlj_setjmp() is an instruction sequence to store the return
4766 // address and save #0 in R0 for the non-longjmp case.
4767 // Since by its nature we may be coming from some other function to get
4768 // here, and we're using the stack frame for the containing function to
4769 // save/restore registers, we can't keep anything live in regs across
4770 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4771 // when we get here from a longjmp(). We force everything out of registers
4772 // except for our own input by listing the relevant registers in Defs. By
4773 // doing so, we also cause the prologue/epilogue code to actively preserve
4774 // all of the callee-saved resgisters, which is exactly what we want.
4775 // A constant value is passed in $val, and we use the location as a scratch.
4777 // These are pseudo-instructions and are lowered to individual MC-insts, so
4778 // no encoding information is necessary.
4780 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4781 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4782 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4783 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4785 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4786 Requires<[IsARM, HasVFP2]>;
4790 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4791 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4792 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4794 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4795 Requires<[IsARM, NoVFP]>;
4798 // FIXME: Non-IOS version(s)
4799 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4800 Defs = [ R7, LR, SP ] in {
4801 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4803 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4804 Requires<[IsARM, IsIOS]>;
4807 // eh.sjlj.dispatchsetup pseudo-instructions.
4808 // These pseudos are used for both ARM and Thumb2. Any differences are
4809 // handled when the pseudo is expanded (which happens before any passes
4810 // that need the instruction size).
4812 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4813 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4815 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4818 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4820 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4823 //===----------------------------------------------------------------------===//
4824 // Non-Instruction Patterns
4827 // ARMv4 indirect branch using (MOVr PC, dst)
4828 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4829 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4830 4, IIC_Br, [(brind GPR:$dst)],
4831 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4832 Requires<[IsARM, NoV4T]>;
4834 // Large immediate handling.
4836 // 32-bit immediate using two piece so_imms or movw + movt.
4837 // This is a single pseudo instruction, the benefit is that it can be remat'd
4838 // as a single unit instead of having to handle reg inputs.
4839 // FIXME: Remove this when we can do generalized remat.
4840 let isReMaterializable = 1, isMoveImm = 1 in
4841 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4842 [(set GPR:$dst, (arm_i32imm:$src))]>,
4845 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4846 // It also makes it possible to rematerialize the instructions.
4847 // FIXME: Remove this when we can do generalized remat and when machine licm
4848 // can properly the instructions.
4849 let isReMaterializable = 1 in {
4850 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4852 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4853 Requires<[IsARM, UseMovt]>;
4855 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4857 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4858 Requires<[IsARM, UseMovt]>;
4860 let AddedComplexity = 10 in
4861 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4863 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4864 Requires<[IsARM, UseMovt]>;
4865 } // isReMaterializable
4867 // ConstantPool, GlobalAddress, and JumpTable
4868 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4869 Requires<[IsARM, DontUseMovt]>;
4870 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4871 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4872 Requires<[IsARM, UseMovt]>;
4873 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4874 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4876 // TODO: add,sub,and, 3-instr forms?
4879 def : ARMPat<(ARMtcret tcGPR:$dst),
4880 (TCRETURNri tcGPR:$dst)>, Requires<[IsIOS]>;
4882 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4883 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4885 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4886 (TCRETURNdi texternalsym:$dst)>, Requires<[IsIOS]>;
4888 def : ARMPat<(ARMtcret tcGPR:$dst),
4889 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotIOS]>;
4891 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4892 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4894 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4895 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotIOS]>;
4898 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4899 Requires<[IsARM, IsNotIOS]>;
4900 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4901 Requires<[IsARM, IsIOS]>;
4902 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4903 (BMOVPCB_CALL texternalsym:$func)>,
4904 Requires<[IsARM, IsNotIOS]>;
4905 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4906 (BMOVPCBr9_CALL texternalsym:$func)>,
4907 Requires<[IsARM, IsIOS]>;
4909 // zextload i1 -> zextload i8
4910 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4911 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4913 // extload -> zextload
4914 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4915 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4916 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4917 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4919 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4921 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4922 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4925 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4926 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4927 (SMULBB GPR:$a, GPR:$b)>;
4928 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4929 (SMULBB GPR:$a, GPR:$b)>;
4930 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4931 (sra GPR:$b, (i32 16))),
4932 (SMULBT GPR:$a, GPR:$b)>;
4933 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4934 (SMULBT GPR:$a, GPR:$b)>;
4935 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4936 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4937 (SMULTB GPR:$a, GPR:$b)>;
4938 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4939 (SMULTB GPR:$a, GPR:$b)>;
4940 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4942 (SMULWB GPR:$a, GPR:$b)>;
4943 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4944 (SMULWB GPR:$a, GPR:$b)>;
4946 def : ARMV5TEPat<(add GPR:$acc,
4947 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4948 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4949 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4950 def : ARMV5TEPat<(add GPR:$acc,
4951 (mul sext_16_node:$a, sext_16_node:$b)),
4952 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4953 def : ARMV5TEPat<(add GPR:$acc,
4954 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4955 (sra GPR:$b, (i32 16)))),
4956 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4957 def : ARMV5TEPat<(add GPR:$acc,
4958 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4959 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4960 def : ARMV5TEPat<(add GPR:$acc,
4961 (mul (sra GPR:$a, (i32 16)),
4962 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4963 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4964 def : ARMV5TEPat<(add GPR:$acc,
4965 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4966 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4967 def : ARMV5TEPat<(add GPR:$acc,
4968 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4970 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4971 def : ARMV5TEPat<(add GPR:$acc,
4972 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4973 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4976 // Pre-v7 uses MCR for synchronization barriers.
4977 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4978 Requires<[IsARM, HasV6]>;
4980 // SXT/UXT with no rotate
4981 let AddedComplexity = 16 in {
4982 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4983 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4984 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4985 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4986 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4987 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4988 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4991 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4992 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4994 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4995 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4996 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4997 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4999 // Atomic load/store patterns
5000 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5001 (LDRBrs ldst_so_reg:$src)>;
5002 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5003 (LDRBi12 addrmode_imm12:$src)>;
5004 def : ARMPat<(atomic_load_16 addrmode3:$src),
5005 (LDRH addrmode3:$src)>;
5006 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5007 (LDRrs ldst_so_reg:$src)>;
5008 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5009 (LDRi12 addrmode_imm12:$src)>;
5010 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5011 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5012 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5013 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5014 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5015 (STRH GPR:$val, addrmode3:$ptr)>;
5016 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5017 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5018 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5019 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5022 //===----------------------------------------------------------------------===//
5026 include "ARMInstrThumb.td"
5028 //===----------------------------------------------------------------------===//
5032 include "ARMInstrThumb2.td"
5034 //===----------------------------------------------------------------------===//
5035 // Floating Point Support
5038 include "ARMInstrVFP.td"
5040 //===----------------------------------------------------------------------===//
5041 // Advanced SIMD (NEON) Support
5044 include "ARMInstrNEON.td"
5046 //===----------------------------------------------------------------------===//
5047 // Assembler aliases
5051 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5052 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5053 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5055 // System instructions
5056 def : MnemonicAlias<"swi", "svc">;
5058 // Load / Store Multiple
5059 def : MnemonicAlias<"ldmfd", "ldm">;
5060 def : MnemonicAlias<"ldmia", "ldm">;
5061 def : MnemonicAlias<"ldmea", "ldmdb">;
5062 def : MnemonicAlias<"stmfd", "stmdb">;
5063 def : MnemonicAlias<"stmia", "stm">;
5064 def : MnemonicAlias<"stmea", "stm">;
5066 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5067 // shift amount is zero (i.e., unspecified).
5068 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5069 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5070 Requires<[IsARM, HasV6]>;
5071 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5072 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5073 Requires<[IsARM, HasV6]>;
5075 // PUSH/POP aliases for STM/LDM
5076 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5077 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5079 // SSAT/USAT optional shift operand.
5080 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5081 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5082 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5083 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5086 // Extend instruction optional rotate operand.
5087 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5088 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5089 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5090 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5091 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5092 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5093 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5094 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5095 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5096 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5097 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5098 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5100 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5101 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5102 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5103 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5104 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5105 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5106 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5107 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5108 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5109 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5110 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5111 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5115 def : MnemonicAlias<"rfefa", "rfeda">;
5116 def : MnemonicAlias<"rfeea", "rfedb">;
5117 def : MnemonicAlias<"rfefd", "rfeia">;
5118 def : MnemonicAlias<"rfeed", "rfeib">;
5119 def : MnemonicAlias<"rfe", "rfeia">;
5122 def : MnemonicAlias<"srsfa", "srsda">;
5123 def : MnemonicAlias<"srsea", "srsdb">;
5124 def : MnemonicAlias<"srsfd", "srsia">;
5125 def : MnemonicAlias<"srsed", "srsib">;
5126 def : MnemonicAlias<"srs", "srsia">;
5129 def : MnemonicAlias<"qsubaddx", "qsax">;
5131 def : MnemonicAlias<"saddsubx", "sasx">;
5132 // SHASX == SHADDSUBX
5133 def : MnemonicAlias<"shaddsubx", "shasx">;
5134 // SHSAX == SHSUBADDX
5135 def : MnemonicAlias<"shsubaddx", "shsax">;
5137 def : MnemonicAlias<"ssubaddx", "ssax">;
5139 def : MnemonicAlias<"uaddsubx", "uasx">;
5140 // UHASX == UHADDSUBX
5141 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5142 // UHSAX == UHSUBADDX
5143 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5144 // UQASX == UQADDSUBX
5145 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5146 // UQSAX == UQSUBADDX
5147 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5149 def : MnemonicAlias<"usubaddx", "usax">;
5151 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5153 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5154 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5155 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5156 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5157 // Same for AND <--> BIC
5158 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5159 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5160 pred:$p, cc_out:$s)>;
5161 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5162 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5163 pred:$p, cc_out:$s)>;
5164 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5165 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5166 pred:$p, cc_out:$s)>;
5167 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5168 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5169 pred:$p, cc_out:$s)>;
5171 // Likewise, "add Rd, so_imm_neg" -> sub
5172 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5173 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5174 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5175 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5176 // Same for CMP <--> CMN via so_imm_neg
5177 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5178 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5179 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5180 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5182 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5183 // LSR, ROR, and RRX instructions.
5184 // FIXME: We need C++ parser hooks to map the alias to the MOV
5185 // encoding. It seems we should be able to do that sort of thing
5186 // in tblgen, but it could get ugly.
5187 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5188 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5190 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5191 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5193 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5194 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5196 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5197 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5199 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5200 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5201 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5202 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5204 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5205 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5207 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5208 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5210 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5211 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5213 // shifter instructions also support a two-operand form.
5214 def : ARMInstAlias<"asr${s}${p} $Rm, $imm",
5215 (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5216 def : ARMInstAlias<"lsr${s}${p} $Rm, $imm",
5217 (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>;
5218 def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
5219 (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5220 def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
5221 (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
5222 def : ARMInstAlias<"asr${s}${p} $Rn, $Rm",
5223 (ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5225 def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm",
5226 (LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5228 def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm",
5229 (LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5231 def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
5232 (RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5236 // 'mul' instruction can be specified with only two operands.
5237 def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
5238 (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>;
5240 // "neg" is and alias for "rsb rd, rn, #0"
5241 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5242 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5244 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5245 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5246 Requires<[IsARM, NoV6]>;
5248 // UMULL/SMULL are available on all arches, but the instruction definitions
5249 // need difference constraints pre-v6. Use these aliases for the assembly
5250 // parsing on pre-v6.
5251 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5252 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5253 Requires<[IsARM, NoV6]>;
5254 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5255 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5256 Requires<[IsARM, NoV6]>;
5258 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5260 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;