1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
134 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
136 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
137 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
142 //===----------------------------------------------------------------------===//
143 // ARM Instruction Predicate Definitions.
145 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
146 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
147 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
148 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
149 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
150 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
151 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
152 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
153 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
154 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
155 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
156 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
157 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
158 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
160 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
162 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
163 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
164 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
165 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
166 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
167 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
168 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
169 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
171 // FIXME: Eventually this will be just "hasV6T2Ops".
172 def UseMovt : Predicate<"Subtarget->useMovt()">;
173 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
174 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
176 //===----------------------------------------------------------------------===//
177 // ARM Flag Definitions.
179 class RegConstraint<string C> {
180 string Constraints = C;
183 //===----------------------------------------------------------------------===//
184 // ARM specific transformation functions and pattern fragments.
187 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
188 // so_imm_neg def below.
189 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
190 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
193 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_not def below.
195 def so_imm_not_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
199 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
200 def imm1_15 : PatLeaf<(i32 imm), [{
201 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
204 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
205 def imm16_31 : PatLeaf<(i32 imm), [{
206 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
211 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
212 }], so_imm_neg_XFORM>;
216 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
217 }], so_imm_not_XFORM>;
219 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
220 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
221 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
224 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
226 def bf_inv_mask_imm : Operand<i32>,
228 return ARM::isBitFieldInvertedMask(N->getZExtValue());
230 string EncoderMethod = "getBitfieldInvertedMaskOpValue";
231 let PrintMethod = "printBitfieldInvMaskImmOperand";
234 /// Split a 32-bit immediate into two 16 bit parts.
235 def hi16 : SDNodeXForm<imm, [{
236 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
239 def lo16AllZero : PatLeaf<(i32 imm), [{
240 // Returns true if all low 16-bits are 0.
241 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
244 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
246 def imm0_65535 : PatLeaf<(i32 imm), [{
247 return (uint32_t)N->getZExtValue() < 65536;
250 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
251 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
253 /// adde and sube predicates - True based on whether the carry flag output
254 /// will be needed or not.
255 def adde_dead_carry :
256 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
257 [{return !N->hasAnyUseOfValue(1);}]>;
258 def sube_dead_carry :
259 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
260 [{return !N->hasAnyUseOfValue(1);}]>;
261 def adde_live_carry :
262 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
263 [{return N->hasAnyUseOfValue(1);}]>;
264 def sube_live_carry :
265 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
266 [{return N->hasAnyUseOfValue(1);}]>;
268 //===----------------------------------------------------------------------===//
269 // Operand Definitions.
273 def brtarget : Operand<OtherVT>;
275 // A list of registers separated by comma. Used by load/store multiple.
276 def reglist : Operand<i32> {
277 string EncoderMethod = "getRegisterListOpValue";
278 let PrintMethod = "printRegisterList";
281 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
282 def cpinst_operand : Operand<i32> {
283 let PrintMethod = "printCPInstOperand";
286 def jtblock_operand : Operand<i32> {
287 let PrintMethod = "printJTBlockOperand";
289 def jt2block_operand : Operand<i32> {
290 let PrintMethod = "printJT2BlockOperand";
294 def pclabel : Operand<i32> {
295 let PrintMethod = "printPCLabel";
298 def neon_vcvt_imm32 : Operand<i32> {
299 string EncoderMethod = "getNEONVcvtImm32OpValue";
302 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
303 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
304 int32_t v = (int32_t)N->getZExtValue();
305 return v == 8 || v == 16 || v == 24; }]> {
306 string EncoderMethod = "getRotImmOpValue";
309 // shift_imm: An integer that encodes a shift amount and the type of shift
310 // (currently either asr or lsl) using the same encoding used for the
311 // immediates in so_reg operands.
312 def shift_imm : Operand<i32> {
313 let PrintMethod = "printShiftImmOperand";
316 // shifter_operand operands: so_reg and so_imm.
317 def so_reg : Operand<i32>, // reg reg imm
318 ComplexPattern<i32, 3, "SelectShifterOperandReg",
319 [shl,srl,sra,rotr]> {
320 string EncoderMethod = "getSORegOpValue";
321 let PrintMethod = "printSORegOperand";
322 let MIOperandInfo = (ops GPR, GPR, i32imm);
324 def shift_so_reg : Operand<i32>, // reg reg imm
325 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
326 [shl,srl,sra,rotr]> {
327 string EncoderMethod = "getSORegOpValue";
328 let PrintMethod = "printSORegOperand";
329 let MIOperandInfo = (ops GPR, GPR, i32imm);
332 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
333 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
334 // represented in the imm field in the same 12-bit form that they are encoded
335 // into so_imm instructions: the 8-bit immediate is the least significant bits
336 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
337 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
338 string EncoderMethod = "getSOImmOpValue";
339 let PrintMethod = "printSOImmOperand";
342 // Break so_imm's up into two pieces. This handles immediates with up to 16
343 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
344 // get the first/second pieces.
345 def so_imm2part : Operand<i32>,
347 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
349 let PrintMethod = "printSOImm2PartOperand";
352 def so_imm2part_1 : SDNodeXForm<imm, [{
353 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
354 return CurDAG->getTargetConstant(V, MVT::i32);
357 def so_imm2part_2 : SDNodeXForm<imm, [{
358 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
359 return CurDAG->getTargetConstant(V, MVT::i32);
362 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
363 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
365 let PrintMethod = "printSOImm2PartOperand";
368 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
369 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
370 return CurDAG->getTargetConstant(V, MVT::i32);
373 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
374 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
375 return CurDAG->getTargetConstant(V, MVT::i32);
378 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
379 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
380 return (int32_t)N->getZExtValue() < 32;
383 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
384 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
385 return (int32_t)N->getZExtValue() < 32;
387 string EncoderMethod = "getImmMinusOneOpValue";
390 // Define ARM specific addressing modes.
393 // addrmode_imm12 := reg +/- imm12
395 def addrmode_imm12 : Operand<i32>,
396 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
397 // 12-bit immediate operand. Note that instructions using this encode
398 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
399 // immediate values are as normal.
401 string EncoderMethod = "getAddrModeImm12OpValue";
402 let PrintMethod = "printAddrModeImm12Operand";
403 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
405 // ldst_so_reg := reg +/- reg shop imm
407 def ldst_so_reg : Operand<i32>,
408 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
409 // FIXME: Simplify the printer
410 // FIXME: Add EncoderMethod for this addressing mode
411 let PrintMethod = "printAddrMode2Operand";
412 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
415 // addrmode2 := reg +/- imm12
416 // := reg +/- reg shop imm
418 def addrmode2 : Operand<i32>,
419 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
420 let PrintMethod = "printAddrMode2Operand";
421 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
424 def am2offset : Operand<i32>,
425 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
426 [], [SDNPWantRoot]> {
427 let PrintMethod = "printAddrMode2OffsetOperand";
428 let MIOperandInfo = (ops GPR, i32imm);
431 // addrmode3 := reg +/- reg
432 // addrmode3 := reg +/- imm8
434 def addrmode3 : Operand<i32>,
435 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
436 let PrintMethod = "printAddrMode3Operand";
437 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
440 def am3offset : Operand<i32>,
441 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
442 [], [SDNPWantRoot]> {
443 let PrintMethod = "printAddrMode3OffsetOperand";
444 let MIOperandInfo = (ops GPR, i32imm);
447 // addrmode4 := reg, <mode|W>
449 def addrmode4 : Operand<i32>,
450 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
451 let PrintMethod = "printAddrMode4Operand";
452 let MIOperandInfo = (ops GPR:$addr, i32imm);
455 def ARMMemMode5AsmOperand : AsmOperandClass {
456 let Name = "MemMode5";
457 let SuperClasses = [];
460 // addrmode5 := reg +/- imm8*4
462 def addrmode5 : Operand<i32>,
463 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
464 let PrintMethod = "printAddrMode5Operand";
465 let MIOperandInfo = (ops GPR:$base, i32imm);
466 let ParserMatchClass = ARMMemMode5AsmOperand;
469 // addrmode6 := reg with optional writeback
471 def addrmode6 : Operand<i32>,
472 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
473 let PrintMethod = "printAddrMode6Operand";
474 let MIOperandInfo = (ops GPR:$addr, i32imm);
475 string EncoderMethod = "getAddrMode6AddressOpValue";
478 def am6offset : Operand<i32> {
479 let PrintMethod = "printAddrMode6OffsetOperand";
480 let MIOperandInfo = (ops GPR);
481 string EncoderMethod = "getAddrMode6OffsetOpValue";
484 // addrmodepc := pc + reg
486 def addrmodepc : Operand<i32>,
487 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
488 let PrintMethod = "printAddrModePCOperand";
489 let MIOperandInfo = (ops GPR, i32imm);
492 def nohash_imm : Operand<i32> {
493 let PrintMethod = "printNoHashImmediate";
496 //===----------------------------------------------------------------------===//
498 include "ARMInstrFormats.td"
500 //===----------------------------------------------------------------------===//
501 // Multiclass helpers...
504 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
505 /// binop that produces a value.
506 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
507 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
508 PatFrag opnode, bit Commutable = 0> {
509 // The register-immediate version is re-materializable. This is useful
510 // in particular for taking the address of a local.
511 let isReMaterializable = 1 in {
512 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
513 iii, opc, "\t$Rd, $Rn, $imm",
514 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
519 let Inst{19-16} = Rn;
520 let Inst{15-12} = Rd;
521 let Inst{11-0} = imm;
524 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
525 iir, opc, "\t$Rd, $Rn, $Rm",
526 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
531 let isCommutable = Commutable;
532 let Inst{19-16} = Rn;
533 let Inst{15-12} = Rd;
534 let Inst{11-4} = 0b00000000;
537 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
538 iis, opc, "\t$Rd, $Rn, $shift",
539 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
544 let Inst{19-16} = Rn;
545 let Inst{15-12} = Rd;
546 let Inst{11-0} = shift;
550 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
551 /// instruction modifies the CPSR register.
552 let Defs = [CPSR] in {
553 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
554 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
555 PatFrag opnode, bit Commutable = 0> {
556 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
557 iii, opc, "\t$Rd, $Rn, $imm",
558 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
564 let Inst{19-16} = Rn;
565 let Inst{15-12} = Rd;
566 let Inst{11-0} = imm;
568 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
569 iir, opc, "\t$Rd, $Rn, $Rm",
570 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
574 let isCommutable = Commutable;
577 let Inst{19-16} = Rn;
578 let Inst{15-12} = Rd;
579 let Inst{11-4} = 0b00000000;
582 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
583 iis, opc, "\t$Rd, $Rn, $shift",
584 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
590 let Inst{19-16} = Rn;
591 let Inst{15-12} = Rd;
592 let Inst{11-0} = shift;
597 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
598 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
599 /// a explicit result, only implicitly set CPSR.
600 let isCompare = 1, Defs = [CPSR] in {
601 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
602 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
603 PatFrag opnode, bit Commutable = 0> {
604 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
606 [(opnode GPR:$Rn, so_imm:$imm)]> {
611 let Inst{19-16} = Rn;
612 let Inst{15-12} = 0b0000;
613 let Inst{11-0} = imm;
615 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
617 [(opnode GPR:$Rn, GPR:$Rm)]> {
620 let isCommutable = Commutable;
623 let Inst{19-16} = Rn;
624 let Inst{15-12} = 0b0000;
625 let Inst{11-4} = 0b00000000;
628 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
629 opc, "\t$Rn, $shift",
630 [(opnode GPR:$Rn, so_reg:$shift)]> {
635 let Inst{19-16} = Rn;
636 let Inst{15-12} = 0b0000;
637 let Inst{11-0} = shift;
642 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
643 /// register and one whose operand is a register rotated by 8/16/24.
644 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
645 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
646 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
647 IIC_iEXTr, opc, "\t$Rd, $Rm",
648 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
649 Requires<[IsARM, HasV6]> {
652 let Inst{19-16} = 0b1111;
653 let Inst{15-12} = Rd;
654 let Inst{11-10} = 0b00;
657 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
658 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
659 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
660 Requires<[IsARM, HasV6]> {
664 let Inst{19-16} = 0b1111;
665 let Inst{15-12} = Rd;
666 let Inst{11-10} = rot;
671 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
672 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
673 IIC_iEXTr, opc, "\t$Rd, $Rm",
674 [/* For disassembly only; pattern left blank */]>,
675 Requires<[IsARM, HasV6]> {
676 let Inst{19-16} = 0b1111;
677 let Inst{11-10} = 0b00;
679 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
680 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
681 [/* For disassembly only; pattern left blank */]>,
682 Requires<[IsARM, HasV6]> {
684 let Inst{19-16} = 0b1111;
685 let Inst{11-10} = rot;
689 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
690 /// register and one whose operand is a register rotated by 8/16/24.
691 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
692 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
693 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
694 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
695 Requires<[IsARM, HasV6]> {
696 let Inst{11-10} = 0b00;
698 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
700 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
701 [(set GPR:$Rd, (opnode GPR:$Rn,
702 (rotr GPR:$Rm, rot_imm:$rot)))]>,
703 Requires<[IsARM, HasV6]> {
706 let Inst{19-16} = Rn;
707 let Inst{11-10} = rot;
711 // For disassembly only.
712 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
713 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
714 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
715 [/* For disassembly only; pattern left blank */]>,
716 Requires<[IsARM, HasV6]> {
717 let Inst{11-10} = 0b00;
719 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
721 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
722 [/* For disassembly only; pattern left blank */]>,
723 Requires<[IsARM, HasV6]> {
726 let Inst{19-16} = Rn;
727 let Inst{11-10} = rot;
731 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
732 let Uses = [CPSR] in {
733 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
734 bit Commutable = 0> {
735 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
736 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
737 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
743 let Inst{15-12} = Rd;
744 let Inst{19-16} = Rn;
745 let Inst{11-0} = imm;
747 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
748 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
749 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
754 let Inst{11-4} = 0b00000000;
756 let isCommutable = Commutable;
758 let Inst{15-12} = Rd;
759 let Inst{19-16} = Rn;
761 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
762 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
763 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
769 let Inst{11-0} = shift;
770 let Inst{15-12} = Rd;
771 let Inst{19-16} = Rn;
774 // Carry setting variants
775 let Defs = [CPSR] in {
776 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
777 bit Commutable = 0> {
778 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
779 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
780 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
785 let Inst{15-12} = Rd;
786 let Inst{19-16} = Rn;
787 let Inst{11-0} = imm;
791 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
792 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
793 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
798 let Inst{11-4} = 0b00000000;
799 let isCommutable = Commutable;
801 let Inst{15-12} = Rd;
802 let Inst{19-16} = Rn;
806 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
807 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
808 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
813 let Inst{11-0} = shift;
814 let Inst{15-12} = Rd;
815 let Inst{19-16} = Rn;
823 let canFoldAsLoad = 1, isReMaterializable = 1 in {
824 multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
825 InstrItinClass iir, PatFrag opnode> {
826 // Note: We use the complex addrmode_imm12 rather than just an input
827 // GPR and a constrained immediate so that we can use this to match
828 // frame index references and avoid matching constant pool references.
829 def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
830 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
831 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
834 let Inst{23} = addr{12}; // U (add = ('U' == 1))
835 let Inst{19-16} = addr{16-13}; // Rn
836 let Inst{15-12} = Rt;
837 let Inst{11-0} = addr{11-0}; // imm12
839 def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
840 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
841 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
844 let Inst{23} = shift{12}; // U (add = ('U' == 1))
845 let Inst{19-16} = shift{16-13}; // Rn
846 let Inst{11-0} = shift{11-0};
851 multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
852 InstrItinClass iir, PatFrag opnode> {
853 // Note: We use the complex addrmode_imm12 rather than just an input
854 // GPR and a constrained immediate so that we can use this to match
855 // frame index references and avoid matching constant pool references.
856 def i12 : AIldst1<0b010, opc22, 0, (outs),
857 (ins GPR:$Rt, addrmode_imm12:$addr),
858 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
859 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
862 let Inst{23} = addr{12}; // U (add = ('U' == 1))
863 let Inst{19-16} = addr{16-13}; // Rn
864 let Inst{15-12} = Rt;
865 let Inst{11-0} = addr{11-0}; // imm12
867 def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
868 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
869 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
872 let Inst{23} = shift{12}; // U (add = ('U' == 1))
873 let Inst{19-16} = shift{16-13}; // Rn
874 let Inst{11-0} = shift{11-0};
877 //===----------------------------------------------------------------------===//
879 //===----------------------------------------------------------------------===//
881 //===----------------------------------------------------------------------===//
882 // Miscellaneous Instructions.
885 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
886 /// the function. The first operand is the ID# for this instruction, the second
887 /// is the index into the MachineConstantPool that this is, the third is the
888 /// size in bytes of this constant pool entry.
889 let neverHasSideEffects = 1, isNotDuplicable = 1 in
890 def CONSTPOOL_ENTRY :
891 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
892 i32imm:$size), NoItinerary, "", []>;
894 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
895 // from removing one half of the matched pairs. That breaks PEI, which assumes
896 // these will always be in pairs, and asserts if it finds otherwise. Better way?
897 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
899 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
900 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
902 def ADJCALLSTACKDOWN :
903 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
904 [(ARMcallseq_start timm:$amt)]>;
907 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
908 [/* For disassembly only; pattern left blank */]>,
909 Requires<[IsARM, HasV6T2]> {
910 let Inst{27-16} = 0b001100100000;
911 let Inst{15-8} = 0b11110000;
912 let Inst{7-0} = 0b00000000;
915 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
916 [/* For disassembly only; pattern left blank */]>,
917 Requires<[IsARM, HasV6T2]> {
918 let Inst{27-16} = 0b001100100000;
919 let Inst{15-8} = 0b11110000;
920 let Inst{7-0} = 0b00000001;
923 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
924 [/* For disassembly only; pattern left blank */]>,
925 Requires<[IsARM, HasV6T2]> {
926 let Inst{27-16} = 0b001100100000;
927 let Inst{15-8} = 0b11110000;
928 let Inst{7-0} = 0b00000010;
931 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
932 [/* For disassembly only; pattern left blank */]>,
933 Requires<[IsARM, HasV6T2]> {
934 let Inst{27-16} = 0b001100100000;
935 let Inst{15-8} = 0b11110000;
936 let Inst{7-0} = 0b00000011;
939 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
941 [/* For disassembly only; pattern left blank */]>,
942 Requires<[IsARM, HasV6]> {
947 let Inst{15-12} = Rd;
948 let Inst{19-16} = Rn;
949 let Inst{27-20} = 0b01101000;
950 let Inst{7-4} = 0b1011;
951 let Inst{11-8} = 0b1111;
954 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
955 [/* For disassembly only; pattern left blank */]>,
956 Requires<[IsARM, HasV6T2]> {
957 let Inst{27-16} = 0b001100100000;
958 let Inst{15-8} = 0b11110000;
959 let Inst{7-0} = 0b00000100;
962 // The i32imm operand $val can be used by a debugger to store more information
963 // about the breakpoint.
964 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
965 [/* For disassembly only; pattern left blank */]>,
968 let Inst{3-0} = val{3-0};
969 let Inst{19-8} = val{15-4};
970 let Inst{27-20} = 0b00010010;
971 let Inst{7-4} = 0b0111;
974 // Change Processor State is a system instruction -- for disassembly only.
975 // The singleton $opt operand contains the following information:
976 // opt{4-0} = mode from Inst{4-0}
977 // opt{5} = changemode from Inst{17}
978 // opt{8-6} = AIF from Inst{8-6}
979 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
980 // FIXME: Integrated assembler will need these split out.
981 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
982 [/* For disassembly only; pattern left blank */]>,
984 let Inst{31-28} = 0b1111;
985 let Inst{27-20} = 0b00010000;
990 // Preload signals the memory system of possible future data/instruction access.
991 // These are for disassembly only.
993 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
994 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
995 multiclass APreLoad<bit data, bit read, string opc> {
997 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, NoItinerary,
998 !strconcat(opc, "\t$addr"), []> {
1001 let Inst{31-26} = 0b111101;
1002 let Inst{25} = 0; // 0 for immediate form
1003 let Inst{24} = data;
1004 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1005 let Inst{22} = read;
1006 let Inst{21-20} = 0b01;
1007 let Inst{19-16} = addr{16-13}; // Rn
1008 let Inst{15-12} = Rt;
1009 let Inst{11-0} = addr{11-0}; // imm12
1012 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, NoItinerary,
1013 !strconcat(opc, "\t$shift"), []> {
1016 let Inst{31-26} = 0b111101;
1017 let Inst{25} = 1; // 1 for register form
1018 let Inst{24} = data;
1019 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1020 let Inst{22} = read;
1021 let Inst{21-20} = 0b01;
1022 let Inst{19-16} = shift{16-13}; // Rn
1023 let Inst{11-0} = shift{11-0};
1027 defm PLD : APreLoad<1, 1, "pld">;
1028 defm PLDW : APreLoad<1, 0, "pldw">;
1029 defm PLI : APreLoad<0, 1, "pli">;
1031 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1033 [/* For disassembly only; pattern left blank */]>,
1036 let Inst{31-10} = 0b1111000100000001000000;
1041 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1042 [/* For disassembly only; pattern left blank */]>,
1043 Requires<[IsARM, HasV7]> {
1045 let Inst{27-4} = 0b001100100000111100001111;
1046 let Inst{3-0} = opt;
1049 // A5.4 Permanently UNDEFINED instructions.
1050 let isBarrier = 1, isTerminator = 1 in
1051 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1054 let Inst{27-25} = 0b011;
1055 let Inst{24-20} = 0b11111;
1056 let Inst{7-5} = 0b111;
1060 // Address computation and loads and stores in PIC mode.
1061 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1062 // classes (AXI1, et.al.) and so have encoding information and such,
1063 // which is suboptimal. Once the rest of the code emitter (including
1064 // JIT) is MC-ized we should look at refactoring these into true
1065 // pseudos. As is, the encoding information ends up being ignored,
1066 // as these instructions are lowered to individual MC-insts.
1067 let isNotDuplicable = 1 in {
1068 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1069 Pseudo, IIC_iALUr, "",
1070 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1072 let AddedComplexity = 10 in {
1073 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1074 Pseudo, IIC_iLoad_r, "",
1075 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1077 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1078 Pseudo, IIC_iLoad_bh_r, "",
1079 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1081 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1082 Pseudo, IIC_iLoad_bh_r, "",
1083 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1085 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1086 Pseudo, IIC_iLoad_bh_r, "",
1087 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1089 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1090 Pseudo, IIC_iLoad_bh_r, "",
1091 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1093 let AddedComplexity = 10 in {
1094 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1095 Pseudo, IIC_iStore_r, "",
1096 [(store GPR:$src, addrmodepc:$addr)]>;
1098 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1099 Pseudo, IIC_iStore_bh_r, "",
1100 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1102 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1103 Pseudo, IIC_iStore_bh_r, "",
1104 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1106 } // isNotDuplicable = 1
1109 // LEApcrel - Load a pc-relative address into a register without offending the
1111 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1112 // the ADR instruction. Is this the right way to handle that? They need
1113 // encoding information regardless.
1114 let neverHasSideEffects = 1 in {
1115 let isReMaterializable = 1 in
1116 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1118 "adr$p\t$dst, #$label", []>;
1120 } // neverHasSideEffects
1121 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1122 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1124 "adr$p\t$dst, #${label}_${id}", []> {
1128 //===----------------------------------------------------------------------===//
1129 // Control Flow Instructions.
1132 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1134 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1135 "bx", "\tlr", [(ARMretflag)]>,
1136 Requires<[IsARM, HasV4T]> {
1137 let Inst{27-0} = 0b0001001011111111111100011110;
1141 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1142 "mov", "\tpc, lr", [(ARMretflag)]>,
1143 Requires<[IsARM, NoV4T]> {
1144 let Inst{27-0} = 0b0001101000001111000000001110;
1148 // Indirect branches
1149 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1151 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1152 [(brind GPR:$dst)]>,
1153 Requires<[IsARM, HasV4T]> {
1155 let Inst{31-4} = 0b1110000100101111111111110001;
1156 let Inst{3-0} = dst;
1160 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1161 [(brind GPR:$dst)]>,
1162 Requires<[IsARM, NoV4T]> {
1164 let Inst{31-4} = 0b1110000110100000111100000000;
1165 let Inst{3-0} = dst;
1169 // FIXME: remove when we have a way to marking a MI with these properties.
1170 // FIXME: Should pc be an implicit operand like PICADD, etc?
1171 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1172 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1173 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1174 reglist:$dsts, variable_ops),
1175 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1176 "ldm${addr:submode}${p}\t$addr!, $dsts",
1177 "$addr.addr = $wb", []>;
1179 // On non-Darwin platforms R9 is callee-saved.
1181 Defs = [R0, R1, R2, R3, R12, LR,
1182 D0, D1, D2, D3, D4, D5, D6, D7,
1183 D16, D17, D18, D19, D20, D21, D22, D23,
1184 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1185 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1186 IIC_Br, "bl\t$func",
1187 [(ARMcall tglobaladdr:$func)]>,
1188 Requires<[IsARM, IsNotDarwin]> {
1189 let Inst{31-28} = 0b1110;
1190 // FIXME: Encoding info for $func. Needs fixups bits.
1193 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1194 IIC_Br, "bl", "\t$func",
1195 [(ARMcall_pred tglobaladdr:$func)]>,
1196 Requires<[IsARM, IsNotDarwin]>;
1199 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1200 IIC_Br, "blx\t$func",
1201 [(ARMcall GPR:$func)]>,
1202 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1204 let Inst{27-4} = 0b000100101111111111110011;
1205 let Inst{3-0} = func;
1209 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1210 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1211 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1212 [(ARMcall_nolink tGPR:$func)]>,
1213 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1215 let Inst{27-4} = 0b000100101111111111110001;
1216 let Inst{3-0} = func;
1220 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1221 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1222 [(ARMcall_nolink tGPR:$func)]>,
1223 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1225 let Inst{27-4} = 0b000110100000111100000000;
1226 let Inst{3-0} = func;
1230 // On Darwin R9 is call-clobbered.
1232 Defs = [R0, R1, R2, R3, R9, R12, LR,
1233 D0, D1, D2, D3, D4, D5, D6, D7,
1234 D16, D17, D18, D19, D20, D21, D22, D23,
1235 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1236 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1237 IIC_Br, "bl\t$func",
1238 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1239 let Inst{31-28} = 0b1110;
1240 // FIXME: Encoding info for $func. Needs fixups bits.
1243 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1244 IIC_Br, "bl", "\t$func",
1245 [(ARMcall_pred tglobaladdr:$func)]>,
1246 Requires<[IsARM, IsDarwin]>;
1249 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1250 IIC_Br, "blx\t$func",
1251 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1253 let Inst{27-4} = 0b000100101111111111110011;
1254 let Inst{3-0} = func;
1258 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1259 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1260 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1261 [(ARMcall_nolink tGPR:$func)]>,
1262 Requires<[IsARM, HasV4T, IsDarwin]> {
1264 let Inst{27-4} = 0b000100101111111111110001;
1265 let Inst{3-0} = func;
1269 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1270 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1271 [(ARMcall_nolink tGPR:$func)]>,
1272 Requires<[IsARM, NoV4T, IsDarwin]> {
1274 let Inst{27-4} = 0b000110100000111100000000;
1275 let Inst{3-0} = func;
1281 // FIXME: These should probably be xformed into the non-TC versions of the
1282 // instructions as part of MC lowering.
1283 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1285 let Defs = [R0, R1, R2, R3, R9, R12,
1286 D0, D1, D2, D3, D4, D5, D6, D7,
1287 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1288 D27, D28, D29, D30, D31, PC],
1290 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1292 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1294 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1296 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1298 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1299 IIC_Br, "b\t$dst @ TAILCALL",
1300 []>, Requires<[IsDarwin]>;
1302 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1303 IIC_Br, "b.w\t$dst @ TAILCALL",
1304 []>, Requires<[IsDarwin]>;
1306 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1307 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1308 []>, Requires<[IsDarwin]> {
1310 let Inst{31-4} = 0b1110000100101111111111110001;
1311 let Inst{3-0} = dst;
1315 // Non-Darwin versions (the difference is R9).
1316 let Defs = [R0, R1, R2, R3, R12,
1317 D0, D1, D2, D3, D4, D5, D6, D7,
1318 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1319 D27, D28, D29, D30, D31, PC],
1321 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1323 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1325 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1327 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1329 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1330 IIC_Br, "b\t$dst @ TAILCALL",
1331 []>, Requires<[IsARM, IsNotDarwin]>;
1333 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1334 IIC_Br, "b.w\t$dst @ TAILCALL",
1335 []>, Requires<[IsThumb, IsNotDarwin]>;
1337 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1338 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1339 []>, Requires<[IsNotDarwin]> {
1341 let Inst{31-4} = 0b1110000100101111111111110001;
1342 let Inst{3-0} = dst;
1347 let isBranch = 1, isTerminator = 1 in {
1348 // B is "predicable" since it can be xformed into a Bcc.
1349 let isBarrier = 1 in {
1350 let isPredicable = 1 in
1351 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1352 "b\t$target", [(br bb:$target)]>;
1354 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1355 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1356 IIC_Br, "mov\tpc, $target$jt",
1357 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1358 let Inst{11-4} = 0b00000000;
1359 let Inst{15-12} = 0b1111;
1360 let Inst{20} = 0; // S Bit
1361 let Inst{24-21} = 0b1101;
1362 let Inst{27-25} = 0b000;
1364 def BR_JTm : JTI<(outs),
1365 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1366 IIC_Br, "ldr\tpc, $target$jt",
1367 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1369 let Inst{15-12} = 0b1111;
1370 let Inst{20} = 1; // L bit
1371 let Inst{21} = 0; // W bit
1372 let Inst{22} = 0; // B bit
1373 let Inst{24} = 1; // P bit
1374 let Inst{27-25} = 0b011;
1376 def BR_JTadd : JTI<(outs),
1377 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1378 IIC_Br, "add\tpc, $target, $idx$jt",
1379 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1381 let Inst{15-12} = 0b1111;
1382 let Inst{20} = 0; // S bit
1383 let Inst{24-21} = 0b0100;
1384 let Inst{27-25} = 0b000;
1386 } // isNotDuplicable = 1, isIndirectBranch = 1
1389 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1390 // a two-value operand where a dag node expects two operands. :(
1391 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1392 IIC_Br, "b", "\t$target",
1393 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1396 // Branch and Exchange Jazelle -- for disassembly only
1397 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1398 [/* For disassembly only; pattern left blank */]> {
1399 let Inst{23-20} = 0b0010;
1400 //let Inst{19-8} = 0xfff;
1401 let Inst{7-4} = 0b0010;
1404 // Secure Monitor Call is a system instruction -- for disassembly only
1405 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1406 [/* For disassembly only; pattern left blank */]> {
1408 let Inst{23-4} = 0b01100000000000000111;
1409 let Inst{3-0} = opt;
1412 // Supervisor Call (Software Interrupt) -- for disassembly only
1414 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1415 [/* For disassembly only; pattern left blank */]> {
1417 let Inst{23-0} = svc;
1421 // Store Return State is a system instruction -- for disassembly only
1422 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1423 def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1424 NoItinerary, "srs${addr:submode}\tsp!, $mode",
1425 [/* For disassembly only; pattern left blank */]> {
1426 let Inst{31-28} = 0b1111;
1427 let Inst{22-20} = 0b110; // W = 1
1430 def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
1431 NoItinerary, "srs${addr:submode}\tsp, $mode",
1432 [/* For disassembly only; pattern left blank */]> {
1433 let Inst{31-28} = 0b1111;
1434 let Inst{22-20} = 0b100; // W = 0
1437 // Return From Exception is a system instruction -- for disassembly only
1438 def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1439 NoItinerary, "rfe${addr:submode}\t$base!",
1440 [/* For disassembly only; pattern left blank */]> {
1441 let Inst{31-28} = 0b1111;
1442 let Inst{22-20} = 0b011; // W = 1
1445 def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
1446 NoItinerary, "rfe${addr:submode}\t$base",
1447 [/* For disassembly only; pattern left blank */]> {
1448 let Inst{31-28} = 0b1111;
1449 let Inst{22-20} = 0b001; // W = 0
1451 } // isCodeGenOnly = 1
1453 //===----------------------------------------------------------------------===//
1454 // Load / store Instructions.
1460 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1461 UnOpFrag<(load node:$Src)>>;
1462 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1463 UnOpFrag<(zextloadi8 node:$Src)>>;
1464 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1465 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1466 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1467 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1469 // Special LDR for loads from non-pc-relative constpools.
1470 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1471 isReMaterializable = 1 in
1472 def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1473 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1476 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1477 let Inst{19-16} = 0b1111;
1478 let Inst{15-12} = Rt;
1479 let Inst{11-0} = addr{11-0}; // imm12
1482 // Loads with zero extension
1483 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1484 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1485 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1487 // Loads with sign extension
1488 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1489 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1490 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1492 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1493 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1494 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1496 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1498 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1499 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1500 []>, Requires<[IsARM, HasV5TE]>;
1503 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1504 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
1505 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1507 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1508 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1509 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1511 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1512 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1513 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1515 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1516 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1517 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1519 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1520 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
1521 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1523 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1524 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1525 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1527 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1528 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1529 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1531 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1532 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1533 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1535 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1536 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1537 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1539 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1540 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1541 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1543 // For disassembly only
1544 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1545 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1546 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1547 Requires<[IsARM, HasV5TE]>;
1549 // For disassembly only
1550 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1551 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1552 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1553 Requires<[IsARM, HasV5TE]>;
1555 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1557 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1559 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1560 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1561 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1562 let Inst{21} = 1; // overwrite
1565 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1566 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1567 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1568 let Inst{21} = 1; // overwrite
1571 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1572 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1573 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1574 let Inst{21} = 1; // overwrite
1577 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1578 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1579 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1580 let Inst{21} = 1; // overwrite
1583 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1584 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1585 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1586 let Inst{21} = 1; // overwrite
1591 // Stores with truncate
1592 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1593 IIC_iStore_bh_r, "strh", "\t$src, $addr",
1594 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1597 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1598 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1599 StMiscFrm, IIC_iStore_d_r,
1600 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1603 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1604 (ins GPR:$src, GPR:$base, am2offset:$offset),
1605 StFrm, IIC_iStore_ru,
1606 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1608 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1610 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1611 (ins GPR:$src, GPR:$base,am2offset:$offset),
1612 StFrm, IIC_iStore_ru,
1613 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1615 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1617 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1618 (ins GPR:$src, GPR:$base,am3offset:$offset),
1619 StMiscFrm, IIC_iStore_ru,
1620 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1622 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1624 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1625 (ins GPR:$src, GPR:$base,am3offset:$offset),
1626 StMiscFrm, IIC_iStore_bh_ru,
1627 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1628 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1629 GPR:$base, am3offset:$offset))]>;
1631 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1632 (ins GPR:$src, GPR:$base,am2offset:$offset),
1633 StFrm, IIC_iStore_bh_ru,
1634 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1635 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1636 GPR:$base, am2offset:$offset))]>;
1638 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1639 (ins GPR:$src, GPR:$base,am2offset:$offset),
1640 StFrm, IIC_iStore_bh_ru,
1641 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1642 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1643 GPR:$base, am2offset:$offset))]>;
1645 // For disassembly only
1646 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1647 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1648 StMiscFrm, IIC_iStore_d_ru,
1649 "strd", "\t$src1, $src2, [$base, $offset]!",
1650 "$base = $base_wb", []>;
1652 // For disassembly only
1653 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1654 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1655 StMiscFrm, IIC_iStore_d_ru,
1656 "strd", "\t$src1, $src2, [$base], $offset",
1657 "$base = $base_wb", []>;
1659 // STRT, STRBT, and STRHT are for disassembly only.
1661 def STRT : AI2stwpo<(outs GPR:$base_wb),
1662 (ins GPR:$src, GPR:$base,am2offset:$offset),
1663 StFrm, IIC_iStore_ru,
1664 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1665 [/* For disassembly only; pattern left blank */]> {
1666 let Inst{21} = 1; // overwrite
1669 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1670 (ins GPR:$src, GPR:$base,am2offset:$offset),
1671 StFrm, IIC_iStore_bh_ru,
1672 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1673 [/* For disassembly only; pattern left blank */]> {
1674 let Inst{21} = 1; // overwrite
1677 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1678 (ins GPR:$src, GPR:$base,am3offset:$offset),
1679 StMiscFrm, IIC_iStore_bh_ru,
1680 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1681 [/* For disassembly only; pattern left blank */]> {
1682 let Inst{21} = 1; // overwrite
1685 //===----------------------------------------------------------------------===//
1686 // Load / store multiple Instructions.
1689 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1690 isCodeGenOnly = 1 in {
1691 def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
1692 reglist:$dsts, variable_ops),
1693 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1694 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
1696 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1697 reglist:$dsts, variable_ops),
1698 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1699 "ldm${addr:submode}${p}\t$addr!, $dsts",
1700 "$addr.addr = $wb", []>;
1701 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1703 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1704 isCodeGenOnly = 1 in {
1705 def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
1706 reglist:$srcs, variable_ops),
1707 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1708 "stm${addr:submode}${p}\t$addr, $srcs", "", []>;
1710 def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
1711 reglist:$srcs, variable_ops),
1712 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1713 "stm${addr:submode}${p}\t$addr!, $srcs",
1714 "$addr.addr = $wb", []>;
1715 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1717 //===----------------------------------------------------------------------===//
1718 // Move Instructions.
1721 let neverHasSideEffects = 1 in
1722 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1723 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1727 let Inst{11-4} = 0b00000000;
1730 let Inst{15-12} = Rd;
1733 // A version for the smaller set of tail call registers.
1734 let neverHasSideEffects = 1 in
1735 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1736 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1740 let Inst{11-4} = 0b00000000;
1743 let Inst{15-12} = Rd;
1746 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1747 DPSoRegFrm, IIC_iMOVsr,
1748 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1752 let Inst{15-12} = Rd;
1753 let Inst{11-0} = src;
1757 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1758 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1759 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1763 let Inst{15-12} = Rd;
1764 let Inst{19-16} = 0b0000;
1765 let Inst{11-0} = imm;
1768 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1769 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1771 "movw", "\t$Rd, $imm",
1772 [(set GPR:$Rd, imm0_65535:$imm)]>,
1773 Requires<[IsARM, HasV6T2]>, UnaryDP {
1776 let Inst{15-12} = Rd;
1777 let Inst{11-0} = imm{11-0};
1778 let Inst{19-16} = imm{15-12};
1783 let Constraints = "$src = $Rd" in
1784 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1786 "movt", "\t$Rd, $imm",
1788 (or (and GPR:$src, 0xffff),
1789 lo16AllZero:$imm))]>, UnaryDP,
1790 Requires<[IsARM, HasV6T2]> {
1793 let Inst{15-12} = Rd;
1794 let Inst{11-0} = imm{11-0};
1795 let Inst{19-16} = imm{15-12};
1800 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1801 Requires<[IsARM, HasV6T2]>;
1803 let Uses = [CPSR] in
1804 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1805 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1808 // These aren't really mov instructions, but we have to define them this way
1809 // due to flag operands.
1811 let Defs = [CPSR] in {
1812 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1813 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1815 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1816 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1820 //===----------------------------------------------------------------------===//
1821 // Extend Instructions.
1826 defm SXTB : AI_ext_rrot<0b01101010,
1827 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1828 defm SXTH : AI_ext_rrot<0b01101011,
1829 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1831 defm SXTAB : AI_exta_rrot<0b01101010,
1832 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1833 defm SXTAH : AI_exta_rrot<0b01101011,
1834 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1836 // For disassembly only
1837 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1839 // For disassembly only
1840 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1844 let AddedComplexity = 16 in {
1845 defm UXTB : AI_ext_rrot<0b01101110,
1846 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1847 defm UXTH : AI_ext_rrot<0b01101111,
1848 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1849 defm UXTB16 : AI_ext_rrot<0b01101100,
1850 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1852 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1853 // The transformation should probably be done as a combiner action
1854 // instead so we can include a check for masking back in the upper
1855 // eight bits of the source into the lower eight bits of the result.
1856 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1857 // (UXTB16r_rot GPR:$Src, 24)>;
1858 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1859 (UXTB16r_rot GPR:$Src, 8)>;
1861 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
1862 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1863 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
1864 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1867 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1868 // For disassembly only
1869 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
1872 def SBFX : I<(outs GPR:$Rd),
1873 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1874 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1875 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1876 Requires<[IsARM, HasV6T2]> {
1881 let Inst{27-21} = 0b0111101;
1882 let Inst{6-4} = 0b101;
1883 let Inst{20-16} = width;
1884 let Inst{15-12} = Rd;
1885 let Inst{11-7} = lsb;
1889 def UBFX : I<(outs GPR:$Rd),
1890 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1891 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1892 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1893 Requires<[IsARM, HasV6T2]> {
1898 let Inst{27-21} = 0b0111111;
1899 let Inst{6-4} = 0b101;
1900 let Inst{20-16} = width;
1901 let Inst{15-12} = Rd;
1902 let Inst{11-7} = lsb;
1906 //===----------------------------------------------------------------------===//
1907 // Arithmetic Instructions.
1910 defm ADD : AsI1_bin_irs<0b0100, "add",
1911 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1912 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1913 defm SUB : AsI1_bin_irs<0b0010, "sub",
1914 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1915 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1917 // ADD and SUB with 's' bit set.
1918 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1919 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1920 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1921 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1922 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1923 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1925 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1926 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1927 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1928 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1929 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1930 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1931 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1932 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1934 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1935 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
1936 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
1941 let Inst{15-12} = Rd;
1942 let Inst{19-16} = Rn;
1943 let Inst{11-0} = imm;
1946 // The reg/reg form is only defined for the disassembler; for codegen it is
1947 // equivalent to SUBrr.
1948 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1949 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
1950 [/* For disassembly only; pattern left blank */]> {
1954 let Inst{11-4} = 0b00000000;
1957 let Inst{15-12} = Rd;
1958 let Inst{19-16} = Rn;
1961 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1962 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
1963 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
1968 let Inst{11-0} = shift;
1969 let Inst{15-12} = Rd;
1970 let Inst{19-16} = Rn;
1973 // RSB with 's' bit set.
1974 let Defs = [CPSR] in {
1975 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1976 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
1977 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
1983 let Inst{15-12} = Rd;
1984 let Inst{19-16} = Rn;
1985 let Inst{11-0} = imm;
1987 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1988 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
1989 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
1995 let Inst{11-0} = shift;
1996 let Inst{15-12} = Rd;
1997 let Inst{19-16} = Rn;
2001 let Uses = [CPSR] in {
2002 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2003 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2004 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2010 let Inst{15-12} = Rd;
2011 let Inst{19-16} = Rn;
2012 let Inst{11-0} = imm;
2014 // The reg/reg form is only defined for the disassembler; for codegen it is
2015 // equivalent to SUBrr.
2016 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2017 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2018 [/* For disassembly only; pattern left blank */]> {
2022 let Inst{11-4} = 0b00000000;
2025 let Inst{15-12} = Rd;
2026 let Inst{19-16} = Rn;
2028 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2029 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2030 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2036 let Inst{11-0} = shift;
2037 let Inst{15-12} = Rd;
2038 let Inst{19-16} = Rn;
2042 // FIXME: Allow these to be predicated.
2043 let Defs = [CPSR], Uses = [CPSR] in {
2044 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2045 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2046 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2053 let Inst{15-12} = Rd;
2054 let Inst{19-16} = Rn;
2055 let Inst{11-0} = imm;
2057 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2058 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2059 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2066 let Inst{11-0} = shift;
2067 let Inst{15-12} = Rd;
2068 let Inst{19-16} = Rn;
2072 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2073 // The assume-no-carry-in form uses the negation of the input since add/sub
2074 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2075 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2077 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2078 (SUBri GPR:$src, so_imm_neg:$imm)>;
2079 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2080 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2081 // The with-carry-in form matches bitwise not instead of the negation.
2082 // Effectively, the inverse interpretation of the carry flag already accounts
2083 // for part of the negation.
2084 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2085 (SBCri GPR:$src, so_imm_not:$imm)>;
2087 // Note: These are implemented in C++ code, because they have to generate
2088 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2090 // (mul X, 2^n+1) -> (add (X << n), X)
2091 // (mul X, 2^n-1) -> (rsb X, (X << n))
2093 // ARM Arithmetic Instruction -- for disassembly only
2094 // GPR:$dst = GPR:$a op GPR:$b
2095 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2096 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2097 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2098 opc, "\t$Rd, $Rn, $Rm", pattern> {
2102 let Inst{27-20} = op27_20;
2103 let Inst{11-4} = op11_4;
2104 let Inst{19-16} = Rn;
2105 let Inst{15-12} = Rd;
2109 // Saturating add/subtract -- for disassembly only
2111 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2112 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2113 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2114 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2115 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2116 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2118 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2119 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2120 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2121 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2122 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2123 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2124 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2125 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2126 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2127 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2128 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2129 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2131 // Signed/Unsigned add/subtract -- for disassembly only
2133 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2134 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2135 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2136 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2137 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2138 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2139 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2140 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2141 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2142 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2143 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2144 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2146 // Signed/Unsigned halving add/subtract -- for disassembly only
2148 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2149 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2150 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2151 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2152 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2153 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2154 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2155 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2156 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2157 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2158 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2159 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2161 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2163 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2164 MulFrm /* for convenience */, NoItinerary, "usad8",
2165 "\t$Rd, $Rn, $Rm", []>,
2166 Requires<[IsARM, HasV6]> {
2170 let Inst{27-20} = 0b01111000;
2171 let Inst{15-12} = 0b1111;
2172 let Inst{7-4} = 0b0001;
2173 let Inst{19-16} = Rd;
2174 let Inst{11-8} = Rm;
2177 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2178 MulFrm /* for convenience */, NoItinerary, "usada8",
2179 "\t$Rd, $Rn, $Rm, $Ra", []>,
2180 Requires<[IsARM, HasV6]> {
2185 let Inst{27-20} = 0b01111000;
2186 let Inst{7-4} = 0b0001;
2187 let Inst{19-16} = Rd;
2188 let Inst{15-12} = Ra;
2189 let Inst{11-8} = Rm;
2193 // Signed/Unsigned saturate -- for disassembly only
2195 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2196 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2197 [/* For disassembly only; pattern left blank */]> {
2202 let Inst{27-21} = 0b0110101;
2203 let Inst{5-4} = 0b01;
2204 let Inst{20-16} = sat_imm;
2205 let Inst{15-12} = Rd;
2206 let Inst{11-7} = sh{7-3};
2207 let Inst{6} = sh{0};
2211 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2212 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2213 [/* For disassembly only; pattern left blank */]> {
2217 let Inst{27-20} = 0b01101010;
2218 let Inst{11-4} = 0b11110011;
2219 let Inst{15-12} = Rd;
2220 let Inst{19-16} = sat_imm;
2224 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2225 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2226 [/* For disassembly only; pattern left blank */]> {
2231 let Inst{27-21} = 0b0110111;
2232 let Inst{5-4} = 0b01;
2233 let Inst{15-12} = Rd;
2234 let Inst{11-7} = sh{7-3};
2235 let Inst{6} = sh{0};
2236 let Inst{20-16} = sat_imm;
2240 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2241 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2242 [/* For disassembly only; pattern left blank */]> {
2246 let Inst{27-20} = 0b01101110;
2247 let Inst{11-4} = 0b11110011;
2248 let Inst{15-12} = Rd;
2249 let Inst{19-16} = sat_imm;
2253 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2254 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2256 //===----------------------------------------------------------------------===//
2257 // Bitwise Instructions.
2260 defm AND : AsI1_bin_irs<0b0000, "and",
2261 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2262 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2263 defm ORR : AsI1_bin_irs<0b1100, "orr",
2264 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2265 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2266 defm EOR : AsI1_bin_irs<0b0001, "eor",
2267 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2268 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2269 defm BIC : AsI1_bin_irs<0b1110, "bic",
2270 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2271 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2273 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2274 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2275 "bfc", "\t$Rd, $imm", "$src = $Rd",
2276 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2277 Requires<[IsARM, HasV6T2]> {
2280 let Inst{27-21} = 0b0111110;
2281 let Inst{6-0} = 0b0011111;
2282 let Inst{15-12} = Rd;
2283 let Inst{11-7} = imm{4-0}; // lsb
2284 let Inst{20-16} = imm{9-5}; // width
2287 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2288 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2289 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2290 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2291 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2292 bf_inv_mask_imm:$imm))]>,
2293 Requires<[IsARM, HasV6T2]> {
2297 let Inst{27-21} = 0b0111110;
2298 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2299 let Inst{15-12} = Rd;
2300 let Inst{11-7} = imm{4-0}; // lsb
2301 let Inst{20-16} = imm{9-5}; // width
2305 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2306 "mvn", "\t$Rd, $Rm",
2307 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2311 let Inst{19-16} = 0b0000;
2312 let Inst{11-4} = 0b00000000;
2313 let Inst{15-12} = Rd;
2316 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2317 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2318 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2323 let Inst{19-16} = 0b0000;
2324 let Inst{15-12} = Rd;
2325 let Inst{11-0} = shift;
2327 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2328 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2329 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2330 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2335 let Inst{19-16} = 0b0000;
2336 let Inst{15-12} = Rd;
2337 let Inst{11-0} = imm;
2340 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2341 (BICri GPR:$src, so_imm_not:$imm)>;
2343 //===----------------------------------------------------------------------===//
2344 // Multiply Instructions.
2346 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2347 string opc, string asm, list<dag> pattern>
2348 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2352 let Inst{19-16} = Rd;
2353 let Inst{11-8} = Rm;
2356 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2357 string opc, string asm, list<dag> pattern>
2358 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2363 let Inst{19-16} = RdHi;
2364 let Inst{15-12} = RdLo;
2365 let Inst{11-8} = Rm;
2369 let isCommutable = 1 in
2370 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2371 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2372 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2374 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2375 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2376 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2378 let Inst{15-12} = Ra;
2381 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2382 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2383 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2384 Requires<[IsARM, HasV6T2]> {
2388 let Inst{19-16} = Rd;
2389 let Inst{11-8} = Rm;
2393 // Extra precision multiplies with low / high results
2395 let neverHasSideEffects = 1 in {
2396 let isCommutable = 1 in {
2397 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2398 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2399 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2401 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2402 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2403 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2406 // Multiply + accumulate
2407 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2408 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2409 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2411 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2412 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2413 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2415 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2416 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2417 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2418 Requires<[IsARM, HasV6]> {
2423 let Inst{19-16} = RdLo;
2424 let Inst{15-12} = RdHi;
2425 let Inst{11-8} = Rm;
2428 } // neverHasSideEffects
2430 // Most significant word multiply
2431 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2432 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2433 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2434 Requires<[IsARM, HasV6]> {
2435 let Inst{15-12} = 0b1111;
2438 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2439 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2440 [/* For disassembly only; pattern left blank */]>,
2441 Requires<[IsARM, HasV6]> {
2442 let Inst{15-12} = 0b1111;
2445 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2446 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2447 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2448 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2449 Requires<[IsARM, HasV6]>;
2451 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2452 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2453 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2454 [/* For disassembly only; pattern left blank */]>,
2455 Requires<[IsARM, HasV6]>;
2457 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2458 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2459 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2460 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2461 Requires<[IsARM, HasV6]>;
2463 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2464 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2465 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2466 [/* For disassembly only; pattern left blank */]>,
2467 Requires<[IsARM, HasV6]>;
2469 multiclass AI_smul<string opc, PatFrag opnode> {
2470 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2471 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2472 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2473 (sext_inreg GPR:$Rm, i16)))]>,
2474 Requires<[IsARM, HasV5TE]>;
2476 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2477 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2478 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2479 (sra GPR:$Rm, (i32 16))))]>,
2480 Requires<[IsARM, HasV5TE]>;
2482 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2483 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2484 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2485 (sext_inreg GPR:$Rm, i16)))]>,
2486 Requires<[IsARM, HasV5TE]>;
2488 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2489 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2490 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2491 (sra GPR:$Rm, (i32 16))))]>,
2492 Requires<[IsARM, HasV5TE]>;
2494 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2495 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2496 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2497 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2498 Requires<[IsARM, HasV5TE]>;
2500 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2501 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2502 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2503 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2504 Requires<[IsARM, HasV5TE]>;
2508 multiclass AI_smla<string opc, PatFrag opnode> {
2509 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
2510 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2511 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2512 [(set GPR:$Rd, (add GPR:$Ra,
2513 (opnode (sext_inreg GPR:$Rn, i16),
2514 (sext_inreg GPR:$Rm, i16))))]>,
2515 Requires<[IsARM, HasV5TE]>;
2517 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
2518 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2519 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2520 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2521 (sra GPR:$Rm, (i32 16)))))]>,
2522 Requires<[IsARM, HasV5TE]>;
2524 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
2525 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2526 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2527 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2528 (sext_inreg GPR:$Rm, i16))))]>,
2529 Requires<[IsARM, HasV5TE]>;
2531 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
2532 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2533 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2534 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2535 (sra GPR:$Rm, (i32 16)))))]>,
2536 Requires<[IsARM, HasV5TE]>;
2538 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
2539 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2540 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2541 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2542 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2543 Requires<[IsARM, HasV5TE]>;
2545 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
2546 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2547 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2548 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2549 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2550 Requires<[IsARM, HasV5TE]>;
2553 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2554 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2556 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2557 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2558 (ins GPR:$Rn, GPR:$Rm),
2559 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2560 [/* For disassembly only; pattern left blank */]>,
2561 Requires<[IsARM, HasV5TE]>;
2563 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2564 (ins GPR:$Rn, GPR:$Rm),
2565 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2566 [/* For disassembly only; pattern left blank */]>,
2567 Requires<[IsARM, HasV5TE]>;
2569 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2570 (ins GPR:$Rn, GPR:$Rm),
2571 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2572 [/* For disassembly only; pattern left blank */]>,
2573 Requires<[IsARM, HasV5TE]>;
2575 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2576 (ins GPR:$Rn, GPR:$Rm),
2577 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2578 [/* For disassembly only; pattern left blank */]>,
2579 Requires<[IsARM, HasV5TE]>;
2581 // Helper class for AI_smld -- for disassembly only
2582 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2583 InstrItinClass itin, string opc, string asm>
2584 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2591 let Inst{21-20} = 0b00;
2592 let Inst{22} = long;
2593 let Inst{27-23} = 0b01110;
2594 let Inst{11-8} = Rm;
2597 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2598 InstrItinClass itin, string opc, string asm>
2599 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2601 let Inst{15-12} = 0b1111;
2602 let Inst{19-16} = Rd;
2604 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2605 InstrItinClass itin, string opc, string asm>
2606 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2608 let Inst{15-12} = Ra;
2610 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2611 InstrItinClass itin, string opc, string asm>
2612 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2615 let Inst{19-16} = RdHi;
2616 let Inst{15-12} = RdLo;
2619 multiclass AI_smld<bit sub, string opc> {
2621 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2622 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2624 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2625 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2627 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2628 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2629 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2631 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2632 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2633 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2637 defm SMLA : AI_smld<0, "smla">;
2638 defm SMLS : AI_smld<1, "smls">;
2640 multiclass AI_sdml<bit sub, string opc> {
2642 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2643 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2644 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2645 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2648 defm SMUA : AI_sdml<0, "smua">;
2649 defm SMUS : AI_sdml<1, "smus">;
2651 //===----------------------------------------------------------------------===//
2652 // Misc. Arithmetic Instructions.
2655 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2656 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2657 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2659 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2660 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2661 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2662 Requires<[IsARM, HasV6T2]>;
2664 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2665 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2666 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2668 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2669 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2671 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2672 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2673 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2674 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2675 Requires<[IsARM, HasV6]>;
2677 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2678 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2681 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2682 (shl GPR:$Rm, (i32 8))), i16))]>,
2683 Requires<[IsARM, HasV6]>;
2685 def lsl_shift_imm : SDNodeXForm<imm, [{
2686 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2687 return CurDAG->getTargetConstant(Sh, MVT::i32);
2690 def lsl_amt : PatLeaf<(i32 imm), [{
2691 return (N->getZExtValue() < 32);
2694 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2695 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2696 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2697 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2698 (and (shl GPR:$Rm, lsl_amt:$sh),
2700 Requires<[IsARM, HasV6]>;
2702 // Alternate cases for PKHBT where identities eliminate some nodes.
2703 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2704 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2705 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2706 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2708 def asr_shift_imm : SDNodeXForm<imm, [{
2709 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2710 return CurDAG->getTargetConstant(Sh, MVT::i32);
2713 def asr_amt : PatLeaf<(i32 imm), [{
2714 return (N->getZExtValue() <= 32);
2717 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2718 // will match the pattern below.
2719 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2720 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2721 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2722 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2723 (and (sra GPR:$Rm, asr_amt:$sh),
2725 Requires<[IsARM, HasV6]>;
2727 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2728 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2729 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2730 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2731 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2732 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2733 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2735 //===----------------------------------------------------------------------===//
2736 // Comparison Instructions...
2739 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2740 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2741 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2743 // FIXME: We have to be careful when using the CMN instruction and comparison
2744 // with 0. One would expect these two pieces of code should give identical
2760 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2761 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2762 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2763 // value of r0 and the carry bit (because the "carry bit" parameter to
2764 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2765 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2766 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2767 // parameter to AddWithCarry is defined as 0).
2769 // When x is 0 and unsigned:
2773 // ~x + 1 = 0x1 0000 0000
2774 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2776 // Therefore, we should disable CMN when comparing against zero, until we can
2777 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2778 // when it's a comparison which doesn't look at the 'carry' flag).
2780 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2782 // This is related to <rdar://problem/7569620>.
2784 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2785 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2787 // Note that TST/TEQ don't set all the same flags that CMP does!
2788 defm TST : AI1_cmp_irs<0b1000, "tst",
2789 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2790 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2791 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2792 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2793 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2795 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2796 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2797 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2798 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2799 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2800 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2802 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2803 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2805 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2806 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2808 // Pseudo i64 compares for some floating point compares.
2809 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2811 def BCCi64 : PseudoInst<(outs),
2812 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2814 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2816 def BCCZi64 : PseudoInst<(outs),
2817 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2818 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2819 } // usesCustomInserter
2822 // Conditional moves
2823 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2824 // a two-value operand where a dag node expects two operands. :(
2825 // FIXME: These should all be pseudo-instructions that get expanded to
2826 // the normal MOV instructions. That would fix the dependency on
2827 // special casing them in tblgen.
2828 let neverHasSideEffects = 1 in {
2829 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2830 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2831 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2832 RegConstraint<"$false = $Rd">, UnaryDP {
2837 let Inst{15-12} = Rd;
2838 let Inst{11-4} = 0b00000000;
2842 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2843 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2844 "mov", "\t$Rd, $shift",
2845 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2846 RegConstraint<"$false = $Rd">, UnaryDP {
2852 let Inst{19-16} = Rn;
2853 let Inst{15-12} = Rd;
2854 let Inst{11-0} = shift;
2857 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2859 "movw", "\t$Rd, $imm",
2861 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
2867 let Inst{19-16} = imm{15-12};
2868 let Inst{15-12} = Rd;
2869 let Inst{11-0} = imm{11-0};
2872 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
2873 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
2874 "mov", "\t$Rd, $imm",
2875 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2876 RegConstraint<"$false = $Rd">, UnaryDP {
2881 let Inst{19-16} = 0b0000;
2882 let Inst{15-12} = Rd;
2883 let Inst{11-0} = imm;
2885 } // neverHasSideEffects
2887 //===----------------------------------------------------------------------===//
2888 // Atomic operations intrinsics
2891 def memb_opt : Operand<i32> {
2892 let PrintMethod = "printMemBOption";
2895 // memory barriers protect the atomic sequences
2896 let hasSideEffects = 1 in {
2897 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2898 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2899 Requires<[IsARM, HasDB]> {
2901 let Inst{31-4} = 0xf57ff05;
2902 let Inst{3-0} = opt;
2905 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2906 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2907 [(ARMMemBarrierMCR GPR:$zero)]>,
2908 Requires<[IsARM, HasV6]> {
2909 // FIXME: add encoding
2913 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2915 [/* For disassembly only; pattern left blank */]>,
2916 Requires<[IsARM, HasDB]> {
2918 let Inst{31-4} = 0xf57ff04;
2919 let Inst{3-0} = opt;
2922 // ISB has only full system option -- for disassembly only
2923 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2924 Requires<[IsARM, HasDB]> {
2925 let Inst{31-4} = 0xf57ff06;
2926 let Inst{3-0} = 0b1111;
2929 let usesCustomInserter = 1 in {
2930 let Uses = [CPSR] in {
2931 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2932 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2933 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2934 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2935 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2936 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2937 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2938 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2939 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2940 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2941 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2942 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2943 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2944 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2945 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2946 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2947 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2948 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2949 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2950 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2951 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2952 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2953 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2954 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2955 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2956 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2957 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2958 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2959 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2960 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2961 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2962 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2963 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2964 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2965 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2966 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2967 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2968 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2969 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2970 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2971 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2972 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2973 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2974 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2975 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2976 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2977 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2978 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2979 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2980 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2981 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2982 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2983 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2984 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2986 def ATOMIC_SWAP_I8 : PseudoInst<
2987 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2988 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2989 def ATOMIC_SWAP_I16 : PseudoInst<
2990 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2991 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2992 def ATOMIC_SWAP_I32 : PseudoInst<
2993 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2994 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
2996 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
2997 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
2998 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
2999 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3000 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3001 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3002 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3003 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3004 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3008 let mayLoad = 1 in {
3009 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3010 "ldrexb", "\t$Rt, [$Rn]",
3012 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3013 "ldrexh", "\t$Rt, [$Rn]",
3015 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3016 "ldrex", "\t$Rt, [$Rn]",
3018 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3020 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3024 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3025 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3027 "strexb", "\t$Rd, $src, [$Rn]",
3029 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3031 "strexh", "\t$Rd, $Rt, [$Rn]",
3033 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3035 "strex", "\t$Rd, $Rt, [$Rn]",
3037 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3038 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3040 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3044 // Clear-Exclusive is for disassembly only.
3045 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3046 [/* For disassembly only; pattern left blank */]>,
3047 Requires<[IsARM, HasV7]> {
3048 let Inst{31-0} = 0b11110101011111111111000000011111;
3051 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3052 let mayLoad = 1 in {
3053 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3054 [/* For disassembly only; pattern left blank */]>;
3055 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3056 [/* For disassembly only; pattern left blank */]>;
3059 //===----------------------------------------------------------------------===//
3063 // __aeabi_read_tp preserves the registers r1-r3.
3064 // FIXME: This needs to be a pseudo of some sort so that we can get the
3065 // encoding right, complete with fixup for the aeabi_read_tp function.
3067 Defs = [R0, R12, LR, CPSR] in {
3068 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3069 "bl\t__aeabi_read_tp",
3070 [(set R0, ARMthread_pointer)]>;
3073 //===----------------------------------------------------------------------===//
3074 // SJLJ Exception handling intrinsics
3075 // eh_sjlj_setjmp() is an instruction sequence to store the return
3076 // address and save #0 in R0 for the non-longjmp case.
3077 // Since by its nature we may be coming from some other function to get
3078 // here, and we're using the stack frame for the containing function to
3079 // save/restore registers, we can't keep anything live in regs across
3080 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3081 // when we get here from a longjmp(). We force everthing out of registers
3082 // except for our own input by listing the relevant registers in Defs. By
3083 // doing so, we also cause the prologue/epilogue code to actively preserve
3084 // all of the callee-saved resgisters, which is exactly what we want.
3085 // A constant value is passed in $val, and we use the location as a scratch.
3087 // These are pseudo-instructions and are lowered to individual MC-insts, so
3088 // no encoding information is necessary.
3090 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3091 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3092 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3093 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3094 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3095 AddrModeNone, SizeSpecial, IndexModeNone,
3096 Pseudo, NoItinerary, "", "",
3097 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3098 Requires<[IsARM, HasVFP2]>;
3102 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3103 hasSideEffects = 1, isBarrier = 1 in {
3104 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3105 AddrModeNone, SizeSpecial, IndexModeNone,
3106 Pseudo, NoItinerary, "", "",
3107 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3108 Requires<[IsARM, NoVFP]>;
3111 // FIXME: Non-Darwin version(s)
3112 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3113 Defs = [ R7, LR, SP ] in {
3114 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3115 AddrModeNone, SizeSpecial, IndexModeNone,
3116 Pseudo, NoItinerary, "", "",
3117 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3118 Requires<[IsARM, IsDarwin]>;
3121 // eh.sjlj.dispatchsetup pseudo-instruction.
3122 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3123 // handled when the pseudo is expanded (which happens before any passes
3124 // that need the instruction size).
3125 let isBarrier = 1, hasSideEffects = 1 in
3126 def Int_eh_sjlj_dispatchsetup :
3127 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3128 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3129 Requires<[IsDarwin]>;
3131 //===----------------------------------------------------------------------===//
3132 // Non-Instruction Patterns
3135 // Large immediate handling.
3137 // Two piece so_imms.
3138 // FIXME: Remove this when we can do generalized remat.
3139 let isReMaterializable = 1 in
3140 def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
3142 [(set GPR:$dst, (so_imm2part:$src))]>,
3143 Requires<[IsARM, NoV6T2]>;
3145 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3146 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3147 (so_imm2part_2 imm:$RHS))>;
3148 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3149 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3150 (so_imm2part_2 imm:$RHS))>;
3151 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3152 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3153 (so_imm2part_2 imm:$RHS))>;
3154 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3155 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3156 (so_neg_imm2part_2 imm:$RHS))>;
3158 // 32-bit immediate using movw + movt.
3159 // This is a single pseudo instruction, the benefit is that it can be remat'd
3160 // as a single unit instead of having to handle reg inputs.
3161 // FIXME: Remove this when we can do generalized remat.
3162 let isReMaterializable = 1 in
3163 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3164 [(set GPR:$dst, (i32 imm:$src))]>,
3165 Requires<[IsARM, HasV6T2]>;
3167 // ConstantPool, GlobalAddress, and JumpTable
3168 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3169 Requires<[IsARM, DontUseMovt]>;
3170 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3171 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3172 Requires<[IsARM, UseMovt]>;
3173 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3174 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3176 // TODO: add,sub,and, 3-instr forms?
3179 def : ARMPat<(ARMtcret tcGPR:$dst),
3180 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3182 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3183 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3185 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3186 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3188 def : ARMPat<(ARMtcret tcGPR:$dst),
3189 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3191 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3192 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3194 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3195 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3198 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3199 Requires<[IsARM, IsNotDarwin]>;
3200 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3201 Requires<[IsARM, IsDarwin]>;
3203 // zextload i1 -> zextload i8
3204 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3205 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3207 // extload -> zextload
3208 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3209 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3210 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3211 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3213 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3215 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3216 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3219 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3220 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3221 (SMULBB GPR:$a, GPR:$b)>;
3222 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3223 (SMULBB GPR:$a, GPR:$b)>;
3224 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3225 (sra GPR:$b, (i32 16))),
3226 (SMULBT GPR:$a, GPR:$b)>;
3227 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3228 (SMULBT GPR:$a, GPR:$b)>;
3229 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3230 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3231 (SMULTB GPR:$a, GPR:$b)>;
3232 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3233 (SMULTB GPR:$a, GPR:$b)>;
3234 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3236 (SMULWB GPR:$a, GPR:$b)>;
3237 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3238 (SMULWB GPR:$a, GPR:$b)>;
3240 def : ARMV5TEPat<(add GPR:$acc,
3241 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3242 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3243 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3244 def : ARMV5TEPat<(add GPR:$acc,
3245 (mul sext_16_node:$a, sext_16_node:$b)),
3246 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3247 def : ARMV5TEPat<(add GPR:$acc,
3248 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3249 (sra GPR:$b, (i32 16)))),
3250 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3251 def : ARMV5TEPat<(add GPR:$acc,
3252 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3253 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3254 def : ARMV5TEPat<(add GPR:$acc,
3255 (mul (sra GPR:$a, (i32 16)),
3256 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3257 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3258 def : ARMV5TEPat<(add GPR:$acc,
3259 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3260 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3261 def : ARMV5TEPat<(add GPR:$acc,
3262 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3264 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3265 def : ARMV5TEPat<(add GPR:$acc,
3266 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3267 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3269 //===----------------------------------------------------------------------===//
3273 include "ARMInstrThumb.td"
3275 //===----------------------------------------------------------------------===//
3279 include "ARMInstrThumb2.td"
3281 //===----------------------------------------------------------------------===//
3282 // Floating Point Support
3285 include "ARMInstrVFP.td"
3287 //===----------------------------------------------------------------------===//
3288 // Advanced SIMD (NEON) Support
3291 include "ARMInstrNEON.td"
3293 //===----------------------------------------------------------------------===//
3294 // Coprocessor Instructions. For disassembly only.
3297 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3298 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3299 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3300 [/* For disassembly only; pattern left blank */]> {
3304 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3305 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3306 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3307 [/* For disassembly only; pattern left blank */]> {
3308 let Inst{31-28} = 0b1111;
3312 class ACI<dag oops, dag iops, string opc, string asm>
3313 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3314 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3315 let Inst{27-25} = 0b110;
3318 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3320 def _OFFSET : ACI<(outs),
3321 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3322 opc, "\tp$cop, cr$CRd, $addr"> {
3323 let Inst{31-28} = op31_28;
3324 let Inst{24} = 1; // P = 1
3325 let Inst{21} = 0; // W = 0
3326 let Inst{22} = 0; // D = 0
3327 let Inst{20} = load;
3330 def _PRE : ACI<(outs),
3331 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3332 opc, "\tp$cop, cr$CRd, $addr!"> {
3333 let Inst{31-28} = op31_28;
3334 let Inst{24} = 1; // P = 1
3335 let Inst{21} = 1; // W = 1
3336 let Inst{22} = 0; // D = 0
3337 let Inst{20} = load;
3340 def _POST : ACI<(outs),
3341 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3342 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3343 let Inst{31-28} = op31_28;
3344 let Inst{24} = 0; // P = 0
3345 let Inst{21} = 1; // W = 1
3346 let Inst{22} = 0; // D = 0
3347 let Inst{20} = load;
3350 def _OPTION : ACI<(outs),
3351 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3352 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3353 let Inst{31-28} = op31_28;
3354 let Inst{24} = 0; // P = 0
3355 let Inst{23} = 1; // U = 1
3356 let Inst{21} = 0; // W = 0
3357 let Inst{22} = 0; // D = 0
3358 let Inst{20} = load;
3361 def L_OFFSET : ACI<(outs),
3362 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3363 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3364 let Inst{31-28} = op31_28;
3365 let Inst{24} = 1; // P = 1
3366 let Inst{21} = 0; // W = 0
3367 let Inst{22} = 1; // D = 1
3368 let Inst{20} = load;
3371 def L_PRE : ACI<(outs),
3372 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3373 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3374 let Inst{31-28} = op31_28;
3375 let Inst{24} = 1; // P = 1
3376 let Inst{21} = 1; // W = 1
3377 let Inst{22} = 1; // D = 1
3378 let Inst{20} = load;
3381 def L_POST : ACI<(outs),
3382 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3383 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3384 let Inst{31-28} = op31_28;
3385 let Inst{24} = 0; // P = 0
3386 let Inst{21} = 1; // W = 1
3387 let Inst{22} = 1; // D = 1
3388 let Inst{20} = load;
3391 def L_OPTION : ACI<(outs),
3392 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3393 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3394 let Inst{31-28} = op31_28;
3395 let Inst{24} = 0; // P = 0
3396 let Inst{23} = 1; // U = 1
3397 let Inst{21} = 0; // W = 0
3398 let Inst{22} = 1; // D = 1
3399 let Inst{20} = load;
3403 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3404 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3405 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3406 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3408 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3409 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3410 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3411 [/* For disassembly only; pattern left blank */]> {
3416 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3417 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3418 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3419 [/* For disassembly only; pattern left blank */]> {
3420 let Inst{31-28} = 0b1111;
3425 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3426 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3427 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3428 [/* For disassembly only; pattern left blank */]> {
3433 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3434 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3435 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3436 [/* For disassembly only; pattern left blank */]> {
3437 let Inst{31-28} = 0b1111;
3442 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3443 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3444 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3445 [/* For disassembly only; pattern left blank */]> {
3446 let Inst{23-20} = 0b0100;
3449 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3450 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3451 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3452 [/* For disassembly only; pattern left blank */]> {
3453 let Inst{31-28} = 0b1111;
3454 let Inst{23-20} = 0b0100;
3457 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3458 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3459 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3460 [/* For disassembly only; pattern left blank */]> {
3461 let Inst{23-20} = 0b0101;
3464 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3465 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3466 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3467 [/* For disassembly only; pattern left blank */]> {
3468 let Inst{31-28} = 0b1111;
3469 let Inst{23-20} = 0b0101;
3472 //===----------------------------------------------------------------------===//
3473 // Move between special register and ARM core register -- for disassembly only
3476 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3477 [/* For disassembly only; pattern left blank */]> {
3478 let Inst{23-20} = 0b0000;
3479 let Inst{7-4} = 0b0000;
3482 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3483 [/* For disassembly only; pattern left blank */]> {
3484 let Inst{23-20} = 0b0100;
3485 let Inst{7-4} = 0b0000;
3488 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3489 "msr", "\tcpsr$mask, $src",
3490 [/* For disassembly only; pattern left blank */]> {
3491 let Inst{23-20} = 0b0010;
3492 let Inst{7-4} = 0b0000;
3495 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3496 "msr", "\tcpsr$mask, $a",
3497 [/* For disassembly only; pattern left blank */]> {
3498 let Inst{23-20} = 0b0010;
3499 let Inst{7-4} = 0b0000;
3502 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3503 "msr", "\tspsr$mask, $src",
3504 [/* For disassembly only; pattern left blank */]> {
3505 let Inst{23-20} = 0b0110;
3506 let Inst{7-4} = 0b0000;
3509 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3510 "msr", "\tspsr$mask, $a",
3511 [/* For disassembly only; pattern left blank */]> {
3512 let Inst{23-20} = 0b0110;
3513 let Inst{7-4} = 0b0000;