1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
74 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
76 def SDT_ARMMCOPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
77 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
80 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
83 SDTCisInt<0>, SDTCisVT<1, i32>]>;
85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
86 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
93 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
94 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
95 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
96 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
97 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
100 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
101 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
102 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
104 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
105 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
106 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
107 [SDNPHasChain, SDNPSideEffect,
108 SDNPOptInGlue, SDNPOutGlue]>;
109 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
112 SDNPMayStore, SDNPMayLoad]>;
114 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
121 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
124 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
127 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
128 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
131 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
132 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
134 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
136 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
139 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
142 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
145 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
148 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
149 [SDNPOutGlue, SDNPCommutative]>;
151 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
153 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
154 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
155 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
157 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
159 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
160 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
161 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
163 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
164 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
165 SDT_ARMEH_SJLJ_Setjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
168 SDT_ARMEH_SJLJ_Longjmp,
169 [SDNPHasChain, SDNPSideEffect]>;
171 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
172 [SDNPHasChain, SDNPSideEffect]>;
173 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
174 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
176 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
178 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
179 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
181 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
183 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
184 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
186 def ARMmcopy : SDNode<"ARMISD::MCOPY", SDT_ARMMCOPY,
187 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
188 SDNPMayStore, SDNPMayLoad]>;
190 //===----------------------------------------------------------------------===//
191 // ARM Instruction Predicate Definitions.
193 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
194 AssemblerPredicate<"HasV4TOps", "armv4t">;
195 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
196 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
197 AssemblerPredicate<"HasV5TOps", "armv5t">;
198 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
199 AssemblerPredicate<"HasV5TEOps", "armv5te">;
200 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
201 AssemblerPredicate<"HasV6Ops", "armv6">;
202 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
203 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
204 AssemblerPredicate<"HasV6MOps",
205 "armv6m or armv6t2">;
206 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
207 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
208 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
209 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
210 AssemblerPredicate<"HasV6KOps", "armv6k">;
211 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
212 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
213 AssemblerPredicate<"HasV7Ops", "armv7">;
214 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
215 AssemblerPredicate<"HasV8Ops", "armv8">;
216 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
217 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
218 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
219 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
220 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
221 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
222 AssemblerPredicate<"FeatureVFP2", "VFP2">;
223 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
224 AssemblerPredicate<"FeatureVFP3", "VFP3">;
225 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
226 AssemblerPredicate<"FeatureVFP4", "VFP4">;
227 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
228 AssemblerPredicate<"!FeatureVFPOnlySP",
229 "double precision VFP">;
230 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
231 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
232 def HasNEON : Predicate<"Subtarget->hasNEON()">,
233 AssemblerPredicate<"FeatureNEON", "NEON">;
234 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
235 AssemblerPredicate<"FeatureCrypto", "crypto">;
236 def HasCRC : Predicate<"Subtarget->hasCRC()">,
237 AssemblerPredicate<"FeatureCRC", "crc">;
238 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
239 AssemblerPredicate<"FeatureFP16","half-float">;
240 def HasDivide : Predicate<"Subtarget->hasDivide()">,
241 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
242 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
243 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
244 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
245 AssemblerPredicate<"FeatureT2XtPk",
247 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
248 AssemblerPredicate<"FeatureDSPThumb2",
250 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
251 AssemblerPredicate<"FeatureDB",
253 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
254 AssemblerPredicate<"FeatureMP",
256 def HasVirtualization: Predicate<"false">,
257 AssemblerPredicate<"FeatureVirtualization",
258 "virtualization-extensions">;
259 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
260 AssemblerPredicate<"FeatureTrustZone",
262 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
263 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
264 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
265 def IsThumb : Predicate<"Subtarget->isThumb()">,
266 AssemblerPredicate<"ModeThumb", "thumb">;
267 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
268 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
269 AssemblerPredicate<"ModeThumb,FeatureThumb2",
271 def IsMClass : Predicate<"Subtarget->isMClass()">,
272 AssemblerPredicate<"FeatureMClass", "armv*m">;
273 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
274 AssemblerPredicate<"!FeatureMClass",
276 def IsARM : Predicate<"!Subtarget->isThumb()">,
277 AssemblerPredicate<"!ModeThumb", "arm-mode">;
278 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
279 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
280 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
281 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
282 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
283 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
285 // FIXME: Eventually this will be just "hasV6T2Ops".
286 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
287 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
288 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
289 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
291 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
292 // But only select them if more precision in FP computation is allowed.
293 // Do not use them for Darwin platforms.
294 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
295 " FPOpFusion::Fast && "
296 " Subtarget->hasVFP4()) && "
297 "!Subtarget->isTargetDarwin()">;
298 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
299 " FPOpFusion::Fast &&"
300 " Subtarget->hasVFP4()) || "
301 "Subtarget->isTargetDarwin()">;
303 // VGETLNi32 is microcoded on Swift - prefer VMOV.
304 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
305 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
307 // VDUP.32 is microcoded on Swift - prefer VMOV.
308 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
309 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
311 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
312 // this allows more effective execution domain optimization. See
313 // setExecutionDomain().
314 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
315 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
317 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
318 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
320 //===----------------------------------------------------------------------===//
321 // ARM Flag Definitions.
323 class RegConstraint<string C> {
324 string Constraints = C;
327 //===----------------------------------------------------------------------===//
328 // ARM specific transformation functions and pattern fragments.
331 // imm_neg_XFORM - Return the negation of an i32 immediate value.
332 def imm_neg_XFORM : SDNodeXForm<imm, [{
333 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
336 // imm_not_XFORM - Return the complement of a i32 immediate value.
337 def imm_not_XFORM : SDNodeXForm<imm, [{
338 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
341 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
342 def imm16_31 : ImmLeaf<i32, [{
343 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
346 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
347 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
348 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
351 /// Split a 32-bit immediate into two 16 bit parts.
352 def hi16 : SDNodeXForm<imm, [{
353 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
357 def lo16AllZero : PatLeaf<(i32 imm), [{
358 // Returns true if all low 16-bits are 0.
359 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
362 class BinOpWithFlagFrag<dag res> :
363 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
364 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
365 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
367 // An 'and' node with a single use.
368 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
369 return N->hasOneUse();
372 // An 'xor' node with a single use.
373 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
374 return N->hasOneUse();
377 // An 'fmul' node with a single use.
378 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
379 return N->hasOneUse();
382 // An 'fadd' node which checks for single non-hazardous use.
383 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
384 return hasNoVMLxHazardUse(N);
387 // An 'fsub' node which checks for single non-hazardous use.
388 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
389 return hasNoVMLxHazardUse(N);
392 //===----------------------------------------------------------------------===//
393 // Operand Definitions.
396 // Immediate operands with a shared generic asm render method.
397 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
399 // Operands that are part of a memory addressing mode.
400 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
403 // FIXME: rename brtarget to t2_brtarget
404 def brtarget : Operand<OtherVT> {
405 let EncoderMethod = "getBranchTargetOpValue";
406 let OperandType = "OPERAND_PCREL";
407 let DecoderMethod = "DecodeT2BROperand";
410 // FIXME: get rid of this one?
411 def uncondbrtarget : Operand<OtherVT> {
412 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
413 let OperandType = "OPERAND_PCREL";
416 // Branch target for ARM. Handles conditional/unconditional
417 def br_target : Operand<OtherVT> {
418 let EncoderMethod = "getARMBranchTargetOpValue";
419 let OperandType = "OPERAND_PCREL";
423 // FIXME: rename bltarget to t2_bl_target?
424 def bltarget : Operand<i32> {
425 // Encoded the same as branch targets.
426 let EncoderMethod = "getBranchTargetOpValue";
427 let OperandType = "OPERAND_PCREL";
430 // Call target for ARM. Handles conditional/unconditional
431 // FIXME: rename bl_target to t2_bltarget?
432 def bl_target : Operand<i32> {
433 let EncoderMethod = "getARMBLTargetOpValue";
434 let OperandType = "OPERAND_PCREL";
437 def blx_target : Operand<i32> {
438 let EncoderMethod = "getARMBLXTargetOpValue";
439 let OperandType = "OPERAND_PCREL";
442 // A list of registers separated by comma. Used by load/store multiple.
443 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
444 def reglist : Operand<i32> {
445 let EncoderMethod = "getRegisterListOpValue";
446 let ParserMatchClass = RegListAsmOperand;
447 let PrintMethod = "printRegisterList";
448 let DecoderMethod = "DecodeRegListOperand";
451 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
453 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
454 def dpr_reglist : Operand<i32> {
455 let EncoderMethod = "getRegisterListOpValue";
456 let ParserMatchClass = DPRRegListAsmOperand;
457 let PrintMethod = "printRegisterList";
458 let DecoderMethod = "DecodeDPRRegListOperand";
461 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
462 def spr_reglist : Operand<i32> {
463 let EncoderMethod = "getRegisterListOpValue";
464 let ParserMatchClass = SPRRegListAsmOperand;
465 let PrintMethod = "printRegisterList";
466 let DecoderMethod = "DecodeSPRRegListOperand";
469 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
470 def cpinst_operand : Operand<i32> {
471 let PrintMethod = "printCPInstOperand";
475 def pclabel : Operand<i32> {
476 let PrintMethod = "printPCLabel";
479 // ADR instruction labels.
480 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
481 def adrlabel : Operand<i32> {
482 let EncoderMethod = "getAdrLabelOpValue";
483 let ParserMatchClass = AdrLabelAsmOperand;
484 let PrintMethod = "printAdrLabelOperand<0>";
487 def neon_vcvt_imm32 : Operand<i32> {
488 let EncoderMethod = "getNEONVcvtImm32OpValue";
489 let DecoderMethod = "DecodeVCVTImmOperand";
492 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
493 def rot_imm_XFORM: SDNodeXForm<imm, [{
494 switch (N->getZExtValue()){
495 default: llvm_unreachable(nullptr);
496 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
497 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
498 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
499 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
502 def RotImmAsmOperand : AsmOperandClass {
504 let ParserMethod = "parseRotImm";
506 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
507 int32_t v = N->getZExtValue();
508 return v == 8 || v == 16 || v == 24; }],
510 let PrintMethod = "printRotImmOperand";
511 let ParserMatchClass = RotImmAsmOperand;
514 // shift_imm: An integer that encodes a shift amount and the type of shift
515 // (asr or lsl). The 6-bit immediate encodes as:
518 // {4-0} imm5 shift amount.
519 // asr #32 encoded as imm5 == 0.
520 def ShifterImmAsmOperand : AsmOperandClass {
521 let Name = "ShifterImm";
522 let ParserMethod = "parseShifterImm";
524 def shift_imm : Operand<i32> {
525 let PrintMethod = "printShiftImmOperand";
526 let ParserMatchClass = ShifterImmAsmOperand;
529 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
530 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
531 def so_reg_reg : Operand<i32>, // reg reg imm
532 ComplexPattern<i32, 3, "SelectRegShifterOperand",
533 [shl, srl, sra, rotr]> {
534 let EncoderMethod = "getSORegRegOpValue";
535 let PrintMethod = "printSORegRegOperand";
536 let DecoderMethod = "DecodeSORegRegOperand";
537 let ParserMatchClass = ShiftedRegAsmOperand;
538 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
541 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
542 def so_reg_imm : Operand<i32>, // reg imm
543 ComplexPattern<i32, 2, "SelectImmShifterOperand",
544 [shl, srl, sra, rotr]> {
545 let EncoderMethod = "getSORegImmOpValue";
546 let PrintMethod = "printSORegImmOperand";
547 let DecoderMethod = "DecodeSORegImmOperand";
548 let ParserMatchClass = ShiftedImmAsmOperand;
549 let MIOperandInfo = (ops GPR, i32imm);
552 // FIXME: Does this need to be distinct from so_reg?
553 def shift_so_reg_reg : Operand<i32>, // reg reg imm
554 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
555 [shl,srl,sra,rotr]> {
556 let EncoderMethod = "getSORegRegOpValue";
557 let PrintMethod = "printSORegRegOperand";
558 let DecoderMethod = "DecodeSORegRegOperand";
559 let ParserMatchClass = ShiftedRegAsmOperand;
560 let MIOperandInfo = (ops GPR, GPR, i32imm);
563 // FIXME: Does this need to be distinct from so_reg?
564 def shift_so_reg_imm : Operand<i32>, // reg reg imm
565 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
566 [shl,srl,sra,rotr]> {
567 let EncoderMethod = "getSORegImmOpValue";
568 let PrintMethod = "printSORegImmOperand";
569 let DecoderMethod = "DecodeSORegImmOperand";
570 let ParserMatchClass = ShiftedImmAsmOperand;
571 let MIOperandInfo = (ops GPR, i32imm);
574 // mod_imm: match a 32-bit immediate operand, which can be encoded into
575 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
576 // - "Modified Immediate Constants"). Within the MC layer we keep this
577 // immediate in its encoded form.
578 def ModImmAsmOperand: AsmOperandClass {
580 let ParserMethod = "parseModImm";
582 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
583 return ARM_AM::getSOImmVal(Imm) != -1;
585 let EncoderMethod = "getModImmOpValue";
586 let PrintMethod = "printModImmOperand";
587 let ParserMatchClass = ModImmAsmOperand;
590 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
591 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
592 // The actual parsing, encoding, decoding are handled by the destination
593 // instructions, which use mod_imm.
595 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
596 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
597 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
599 let ParserMatchClass = ModImmNotAsmOperand;
602 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
603 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
604 unsigned Value = -(unsigned)N->getZExtValue();
605 return Value && ARM_AM::getSOImmVal(Value) != -1;
607 let ParserMatchClass = ModImmNegAsmOperand;
610 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
611 def arm_i32imm : PatLeaf<(imm), [{
612 if (Subtarget->useMovt(*MF))
614 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
617 /// imm0_1 predicate - Immediate in the range [0,1].
618 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
619 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
621 /// imm0_3 predicate - Immediate in the range [0,3].
622 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
623 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
625 /// imm0_7 predicate - Immediate in the range [0,7].
626 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
627 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
628 return Imm >= 0 && Imm < 8;
630 let ParserMatchClass = Imm0_7AsmOperand;
633 /// imm8 predicate - Immediate is exactly 8.
634 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
635 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
636 let ParserMatchClass = Imm8AsmOperand;
639 /// imm16 predicate - Immediate is exactly 16.
640 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
641 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
642 let ParserMatchClass = Imm16AsmOperand;
645 /// imm32 predicate - Immediate is exactly 32.
646 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
647 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
648 let ParserMatchClass = Imm32AsmOperand;
651 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
653 /// imm1_7 predicate - Immediate in the range [1,7].
654 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
655 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
656 let ParserMatchClass = Imm1_7AsmOperand;
659 /// imm1_15 predicate - Immediate in the range [1,15].
660 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
661 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
662 let ParserMatchClass = Imm1_15AsmOperand;
665 /// imm1_31 predicate - Immediate in the range [1,31].
666 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
667 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
668 let ParserMatchClass = Imm1_31AsmOperand;
671 /// imm0_15 predicate - Immediate in the range [0,15].
672 def Imm0_15AsmOperand: ImmAsmOperand {
673 let Name = "Imm0_15";
674 let DiagnosticType = "ImmRange0_15";
676 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
677 return Imm >= 0 && Imm < 16;
679 let ParserMatchClass = Imm0_15AsmOperand;
682 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
683 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
684 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
685 return Imm >= 0 && Imm < 32;
687 let ParserMatchClass = Imm0_31AsmOperand;
690 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
691 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
692 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
693 return Imm >= 0 && Imm < 32;
695 let ParserMatchClass = Imm0_32AsmOperand;
698 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
699 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
700 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
701 return Imm >= 0 && Imm < 64;
703 let ParserMatchClass = Imm0_63AsmOperand;
706 /// imm0_239 predicate - Immediate in the range [0,239].
707 def Imm0_239AsmOperand : ImmAsmOperand {
708 let Name = "Imm0_239";
709 let DiagnosticType = "ImmRange0_239";
711 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
712 let ParserMatchClass = Imm0_239AsmOperand;
715 /// imm0_255 predicate - Immediate in the range [0,255].
716 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
717 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
718 let ParserMatchClass = Imm0_255AsmOperand;
721 /// imm0_65535 - An immediate is in the range [0.65535].
722 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
723 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
724 return Imm >= 0 && Imm < 65536;
726 let ParserMatchClass = Imm0_65535AsmOperand;
729 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
730 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
731 return -Imm >= 0 && -Imm < 65536;
734 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
735 // a relocatable expression.
737 // FIXME: This really needs a Thumb version separate from the ARM version.
738 // While the range is the same, and can thus use the same match class,
739 // the encoding is different so it should have a different encoder method.
740 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
741 def imm0_65535_expr : Operand<i32> {
742 let EncoderMethod = "getHiLo16ImmOpValue";
743 let ParserMatchClass = Imm0_65535ExprAsmOperand;
746 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
747 def imm256_65535_expr : Operand<i32> {
748 let ParserMatchClass = Imm256_65535ExprAsmOperand;
751 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
752 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
753 def imm24b : Operand<i32>, ImmLeaf<i32, [{
754 return Imm >= 0 && Imm <= 0xffffff;
756 let ParserMatchClass = Imm24bitAsmOperand;
760 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
762 def BitfieldAsmOperand : AsmOperandClass {
763 let Name = "Bitfield";
764 let ParserMethod = "parseBitfield";
767 def bf_inv_mask_imm : Operand<i32>,
769 return ARM::isBitFieldInvertedMask(N->getZExtValue());
771 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
772 let PrintMethod = "printBitfieldInvMaskImmOperand";
773 let DecoderMethod = "DecodeBitfieldMaskOperand";
774 let ParserMatchClass = BitfieldAsmOperand;
777 def imm1_32_XFORM: SDNodeXForm<imm, [{
778 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
781 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
782 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
783 uint64_t Imm = N->getZExtValue();
784 return Imm > 0 && Imm <= 32;
787 let PrintMethod = "printImmPlusOneOperand";
788 let ParserMatchClass = Imm1_32AsmOperand;
791 def imm1_16_XFORM: SDNodeXForm<imm, [{
792 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
795 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
796 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
798 let PrintMethod = "printImmPlusOneOperand";
799 let ParserMatchClass = Imm1_16AsmOperand;
802 // Define ARM specific addressing modes.
803 // addrmode_imm12 := reg +/- imm12
805 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
806 class AddrMode_Imm12 : MemOperand,
807 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
808 // 12-bit immediate operand. Note that instructions using this encode
809 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
810 // immediate values are as normal.
812 let EncoderMethod = "getAddrModeImm12OpValue";
813 let DecoderMethod = "DecodeAddrModeImm12Operand";
814 let ParserMatchClass = MemImm12OffsetAsmOperand;
815 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
818 def addrmode_imm12 : AddrMode_Imm12 {
819 let PrintMethod = "printAddrModeImm12Operand<false>";
822 def addrmode_imm12_pre : AddrMode_Imm12 {
823 let PrintMethod = "printAddrModeImm12Operand<true>";
826 // ldst_so_reg := reg +/- reg shop imm
828 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
829 def ldst_so_reg : MemOperand,
830 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
831 let EncoderMethod = "getLdStSORegOpValue";
832 // FIXME: Simplify the printer
833 let PrintMethod = "printAddrMode2Operand";
834 let DecoderMethod = "DecodeSORegMemOperand";
835 let ParserMatchClass = MemRegOffsetAsmOperand;
836 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
839 // postidx_imm8 := +/- [0,255]
842 // {8} 1 is imm8 is non-negative. 0 otherwise.
843 // {7-0} [0,255] imm8 value.
844 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
845 def postidx_imm8 : MemOperand {
846 let PrintMethod = "printPostIdxImm8Operand";
847 let ParserMatchClass = PostIdxImm8AsmOperand;
848 let MIOperandInfo = (ops i32imm);
851 // postidx_imm8s4 := +/- [0,1020]
854 // {8} 1 is imm8 is non-negative. 0 otherwise.
855 // {7-0} [0,255] imm8 value, scaled by 4.
856 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
857 def postidx_imm8s4 : MemOperand {
858 let PrintMethod = "printPostIdxImm8s4Operand";
859 let ParserMatchClass = PostIdxImm8s4AsmOperand;
860 let MIOperandInfo = (ops i32imm);
864 // postidx_reg := +/- reg
866 def PostIdxRegAsmOperand : AsmOperandClass {
867 let Name = "PostIdxReg";
868 let ParserMethod = "parsePostIdxReg";
870 def postidx_reg : MemOperand {
871 let EncoderMethod = "getPostIdxRegOpValue";
872 let DecoderMethod = "DecodePostIdxReg";
873 let PrintMethod = "printPostIdxRegOperand";
874 let ParserMatchClass = PostIdxRegAsmOperand;
875 let MIOperandInfo = (ops GPRnopc, i32imm);
879 // addrmode2 := reg +/- imm12
880 // := reg +/- reg shop imm
882 // FIXME: addrmode2 should be refactored the rest of the way to always
883 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
884 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
885 def addrmode2 : MemOperand,
886 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
887 let EncoderMethod = "getAddrMode2OpValue";
888 let PrintMethod = "printAddrMode2Operand";
889 let ParserMatchClass = AddrMode2AsmOperand;
890 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
893 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
894 let Name = "PostIdxRegShifted";
895 let ParserMethod = "parsePostIdxReg";
897 def am2offset_reg : MemOperand,
898 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
899 [], [SDNPWantRoot]> {
900 let EncoderMethod = "getAddrMode2OffsetOpValue";
901 let PrintMethod = "printAddrMode2OffsetOperand";
902 // When using this for assembly, it's always as a post-index offset.
903 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
904 let MIOperandInfo = (ops GPRnopc, i32imm);
907 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
908 // the GPR is purely vestigal at this point.
909 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
910 def am2offset_imm : MemOperand,
911 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
912 [], [SDNPWantRoot]> {
913 let EncoderMethod = "getAddrMode2OffsetOpValue";
914 let PrintMethod = "printAddrMode2OffsetOperand";
915 let ParserMatchClass = AM2OffsetImmAsmOperand;
916 let MIOperandInfo = (ops GPRnopc, i32imm);
920 // addrmode3 := reg +/- reg
921 // addrmode3 := reg +/- imm8
923 // FIXME: split into imm vs. reg versions.
924 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
925 class AddrMode3 : MemOperand,
926 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
927 let EncoderMethod = "getAddrMode3OpValue";
928 let ParserMatchClass = AddrMode3AsmOperand;
929 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
932 def addrmode3 : AddrMode3
934 let PrintMethod = "printAddrMode3Operand<false>";
937 def addrmode3_pre : AddrMode3
939 let PrintMethod = "printAddrMode3Operand<true>";
942 // FIXME: split into imm vs. reg versions.
943 // FIXME: parser method to handle +/- register.
944 def AM3OffsetAsmOperand : AsmOperandClass {
945 let Name = "AM3Offset";
946 let ParserMethod = "parseAM3Offset";
948 def am3offset : MemOperand,
949 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
950 [], [SDNPWantRoot]> {
951 let EncoderMethod = "getAddrMode3OffsetOpValue";
952 let PrintMethod = "printAddrMode3OffsetOperand";
953 let ParserMatchClass = AM3OffsetAsmOperand;
954 let MIOperandInfo = (ops GPR, i32imm);
957 // ldstm_mode := {ia, ib, da, db}
959 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
960 let EncoderMethod = "getLdStmModeOpValue";
961 let PrintMethod = "printLdStmModeOperand";
964 // addrmode5 := reg +/- imm8*4
966 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
967 class AddrMode5 : MemOperand,
968 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
969 let EncoderMethod = "getAddrMode5OpValue";
970 let DecoderMethod = "DecodeAddrMode5Operand";
971 let ParserMatchClass = AddrMode5AsmOperand;
972 let MIOperandInfo = (ops GPR:$base, i32imm);
975 def addrmode5 : AddrMode5 {
976 let PrintMethod = "printAddrMode5Operand<false>";
979 def addrmode5_pre : AddrMode5 {
980 let PrintMethod = "printAddrMode5Operand<true>";
983 // addrmode6 := reg with optional alignment
985 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
986 def addrmode6 : MemOperand,
987 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
988 let PrintMethod = "printAddrMode6Operand";
989 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
990 let EncoderMethod = "getAddrMode6AddressOpValue";
991 let DecoderMethod = "DecodeAddrMode6Operand";
992 let ParserMatchClass = AddrMode6AsmOperand;
995 def am6offset : MemOperand,
996 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
997 [], [SDNPWantRoot]> {
998 let PrintMethod = "printAddrMode6OffsetOperand";
999 let MIOperandInfo = (ops GPR);
1000 let EncoderMethod = "getAddrMode6OffsetOpValue";
1001 let DecoderMethod = "DecodeGPRRegisterClass";
1004 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
1005 // (single element from one lane) for size 32.
1006 def addrmode6oneL32 : MemOperand,
1007 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1008 let PrintMethod = "printAddrMode6Operand";
1009 let MIOperandInfo = (ops GPR:$addr, i32imm);
1010 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1013 // Base class for addrmode6 with specific alignment restrictions.
1014 class AddrMode6Align : MemOperand,
1015 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1016 let PrintMethod = "printAddrMode6Operand";
1017 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1018 let EncoderMethod = "getAddrMode6AddressOpValue";
1019 let DecoderMethod = "DecodeAddrMode6Operand";
1022 // Special version of addrmode6 to handle no allowed alignment encoding for
1023 // VLD/VST instructions and checking the alignment is not specified.
1024 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1025 let Name = "AlignedMemoryNone";
1026 let DiagnosticType = "AlignedMemoryRequiresNone";
1028 def addrmode6alignNone : AddrMode6Align {
1029 // The alignment specifier can only be omitted.
1030 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1033 // Special version of addrmode6 to handle 16-bit alignment encoding for
1034 // VLD/VST instructions and checking the alignment value.
1035 def AddrMode6Align16AsmOperand : AsmOperandClass {
1036 let Name = "AlignedMemory16";
1037 let DiagnosticType = "AlignedMemoryRequires16";
1039 def addrmode6align16 : AddrMode6Align {
1040 // The alignment specifier can only be 16 or omitted.
1041 let ParserMatchClass = AddrMode6Align16AsmOperand;
1044 // Special version of addrmode6 to handle 32-bit alignment encoding for
1045 // VLD/VST instructions and checking the alignment value.
1046 def AddrMode6Align32AsmOperand : AsmOperandClass {
1047 let Name = "AlignedMemory32";
1048 let DiagnosticType = "AlignedMemoryRequires32";
1050 def addrmode6align32 : AddrMode6Align {
1051 // The alignment specifier can only be 32 or omitted.
1052 let ParserMatchClass = AddrMode6Align32AsmOperand;
1055 // Special version of addrmode6 to handle 64-bit alignment encoding for
1056 // VLD/VST instructions and checking the alignment value.
1057 def AddrMode6Align64AsmOperand : AsmOperandClass {
1058 let Name = "AlignedMemory64";
1059 let DiagnosticType = "AlignedMemoryRequires64";
1061 def addrmode6align64 : AddrMode6Align {
1062 // The alignment specifier can only be 64 or omitted.
1063 let ParserMatchClass = AddrMode6Align64AsmOperand;
1066 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1067 // for VLD/VST instructions and checking the alignment value.
1068 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1069 let Name = "AlignedMemory64or128";
1070 let DiagnosticType = "AlignedMemoryRequires64or128";
1072 def addrmode6align64or128 : AddrMode6Align {
1073 // The alignment specifier can only be 64, 128 or omitted.
1074 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1077 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1078 // encoding for VLD/VST instructions and checking the alignment value.
1079 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1080 let Name = "AlignedMemory64or128or256";
1081 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1083 def addrmode6align64or128or256 : AddrMode6Align {
1084 // The alignment specifier can only be 64, 128, 256 or omitted.
1085 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1088 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1089 // instructions, specifically VLD4-dup.
1090 def addrmode6dup : MemOperand,
1091 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1092 let PrintMethod = "printAddrMode6Operand";
1093 let MIOperandInfo = (ops GPR:$addr, i32imm);
1094 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1095 // FIXME: This is close, but not quite right. The alignment specifier is
1097 let ParserMatchClass = AddrMode6AsmOperand;
1100 // Base class for addrmode6dup with specific alignment restrictions.
1101 class AddrMode6DupAlign : MemOperand,
1102 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1103 let PrintMethod = "printAddrMode6Operand";
1104 let MIOperandInfo = (ops GPR:$addr, i32imm);
1105 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1108 // Special version of addrmode6 to handle no allowed alignment encoding for
1109 // VLD-dup instruction and checking the alignment is not specified.
1110 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1111 let Name = "DupAlignedMemoryNone";
1112 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1114 def addrmode6dupalignNone : AddrMode6DupAlign {
1115 // The alignment specifier can only be omitted.
1116 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1119 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1120 // instruction and checking the alignment value.
1121 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1122 let Name = "DupAlignedMemory16";
1123 let DiagnosticType = "DupAlignedMemoryRequires16";
1125 def addrmode6dupalign16 : AddrMode6DupAlign {
1126 // The alignment specifier can only be 16 or omitted.
1127 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1130 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1131 // instruction and checking the alignment value.
1132 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1133 let Name = "DupAlignedMemory32";
1134 let DiagnosticType = "DupAlignedMemoryRequires32";
1136 def addrmode6dupalign32 : AddrMode6DupAlign {
1137 // The alignment specifier can only be 32 or omitted.
1138 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1141 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1142 // instructions and checking the alignment value.
1143 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1144 let Name = "DupAlignedMemory64";
1145 let DiagnosticType = "DupAlignedMemoryRequires64";
1147 def addrmode6dupalign64 : AddrMode6DupAlign {
1148 // The alignment specifier can only be 64 or omitted.
1149 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1152 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1153 // for VLD instructions and checking the alignment value.
1154 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1155 let Name = "DupAlignedMemory64or128";
1156 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1158 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1159 // The alignment specifier can only be 64, 128 or omitted.
1160 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1163 // addrmodepc := pc + reg
1165 def addrmodepc : MemOperand,
1166 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1167 let PrintMethod = "printAddrModePCOperand";
1168 let MIOperandInfo = (ops GPR, i32imm);
1171 // addr_offset_none := reg
1173 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1174 def addr_offset_none : MemOperand,
1175 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1176 let PrintMethod = "printAddrMode7Operand";
1177 let DecoderMethod = "DecodeAddrMode7Operand";
1178 let ParserMatchClass = MemNoOffsetAsmOperand;
1179 let MIOperandInfo = (ops GPR:$base);
1182 def nohash_imm : Operand<i32> {
1183 let PrintMethod = "printNoHashImmediate";
1186 def CoprocNumAsmOperand : AsmOperandClass {
1187 let Name = "CoprocNum";
1188 let ParserMethod = "parseCoprocNumOperand";
1190 def p_imm : Operand<i32> {
1191 let PrintMethod = "printPImmediate";
1192 let ParserMatchClass = CoprocNumAsmOperand;
1193 let DecoderMethod = "DecodeCoprocessor";
1196 def CoprocRegAsmOperand : AsmOperandClass {
1197 let Name = "CoprocReg";
1198 let ParserMethod = "parseCoprocRegOperand";
1200 def c_imm : Operand<i32> {
1201 let PrintMethod = "printCImmediate";
1202 let ParserMatchClass = CoprocRegAsmOperand;
1204 def CoprocOptionAsmOperand : AsmOperandClass {
1205 let Name = "CoprocOption";
1206 let ParserMethod = "parseCoprocOptionOperand";
1208 def coproc_option_imm : Operand<i32> {
1209 let PrintMethod = "printCoprocOptionImm";
1210 let ParserMatchClass = CoprocOptionAsmOperand;
1213 //===----------------------------------------------------------------------===//
1215 include "ARMInstrFormats.td"
1217 //===----------------------------------------------------------------------===//
1218 // Multiclass helpers...
1221 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1222 /// binop that produces a value.
1223 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1224 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1225 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1226 PatFrag opnode, bit Commutable = 0> {
1227 // The register-immediate version is re-materializable. This is useful
1228 // in particular for taking the address of a local.
1229 let isReMaterializable = 1 in {
1230 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1231 iii, opc, "\t$Rd, $Rn, $imm",
1232 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1233 Sched<[WriteALU, ReadALU]> {
1238 let Inst{19-16} = Rn;
1239 let Inst{15-12} = Rd;
1240 let Inst{11-0} = imm;
1243 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1244 iir, opc, "\t$Rd, $Rn, $Rm",
1245 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1246 Sched<[WriteALU, ReadALU, ReadALU]> {
1251 let isCommutable = Commutable;
1252 let Inst{19-16} = Rn;
1253 let Inst{15-12} = Rd;
1254 let Inst{11-4} = 0b00000000;
1258 def rsi : AsI1<opcod, (outs GPR:$Rd),
1259 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1260 iis, opc, "\t$Rd, $Rn, $shift",
1261 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1262 Sched<[WriteALUsi, ReadALU]> {
1267 let Inst{19-16} = Rn;
1268 let Inst{15-12} = Rd;
1269 let Inst{11-5} = shift{11-5};
1271 let Inst{3-0} = shift{3-0};
1274 def rsr : AsI1<opcod, (outs GPR:$Rd),
1275 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1276 iis, opc, "\t$Rd, $Rn, $shift",
1277 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1278 Sched<[WriteALUsr, ReadALUsr]> {
1283 let Inst{19-16} = Rn;
1284 let Inst{15-12} = Rd;
1285 let Inst{11-8} = shift{11-8};
1287 let Inst{6-5} = shift{6-5};
1289 let Inst{3-0} = shift{3-0};
1293 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1294 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1295 /// it is equivalent to the AsI1_bin_irs counterpart.
1296 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1297 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1298 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1299 PatFrag opnode, bit Commutable = 0> {
1300 // The register-immediate version is re-materializable. This is useful
1301 // in particular for taking the address of a local.
1302 let isReMaterializable = 1 in {
1303 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1304 iii, opc, "\t$Rd, $Rn, $imm",
1305 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1306 Sched<[WriteALU, ReadALU]> {
1311 let Inst{19-16} = Rn;
1312 let Inst{15-12} = Rd;
1313 let Inst{11-0} = imm;
1316 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1317 iir, opc, "\t$Rd, $Rn, $Rm",
1318 [/* pattern left blank */]>,
1319 Sched<[WriteALU, ReadALU, ReadALU]> {
1323 let Inst{11-4} = 0b00000000;
1326 let Inst{15-12} = Rd;
1327 let Inst{19-16} = Rn;
1330 def rsi : AsI1<opcod, (outs GPR:$Rd),
1331 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1332 iis, opc, "\t$Rd, $Rn, $shift",
1333 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1334 Sched<[WriteALUsi, ReadALU]> {
1339 let Inst{19-16} = Rn;
1340 let Inst{15-12} = Rd;
1341 let Inst{11-5} = shift{11-5};
1343 let Inst{3-0} = shift{3-0};
1346 def rsr : AsI1<opcod, (outs GPR:$Rd),
1347 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1348 iis, opc, "\t$Rd, $Rn, $shift",
1349 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1350 Sched<[WriteALUsr, ReadALUsr]> {
1355 let Inst{19-16} = Rn;
1356 let Inst{15-12} = Rd;
1357 let Inst{11-8} = shift{11-8};
1359 let Inst{6-5} = shift{6-5};
1361 let Inst{3-0} = shift{3-0};
1365 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1367 /// These opcodes will be converted to the real non-S opcodes by
1368 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1369 let hasPostISelHook = 1, Defs = [CPSR] in {
1370 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1371 InstrItinClass iis, PatFrag opnode,
1372 bit Commutable = 0> {
1373 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1375 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1376 Sched<[WriteALU, ReadALU]>;
1378 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1380 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1381 Sched<[WriteALU, ReadALU, ReadALU]> {
1382 let isCommutable = Commutable;
1384 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1385 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1387 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1388 so_reg_imm:$shift))]>,
1389 Sched<[WriteALUsi, ReadALU]>;
1391 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1392 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1394 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1395 so_reg_reg:$shift))]>,
1396 Sched<[WriteALUSsr, ReadALUsr]>;
1400 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1401 /// operands are reversed.
1402 let hasPostISelHook = 1, Defs = [CPSR] in {
1403 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1404 InstrItinClass iis, PatFrag opnode,
1405 bit Commutable = 0> {
1406 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1408 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1409 Sched<[WriteALU, ReadALU]>;
1411 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1412 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1414 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1416 Sched<[WriteALUsi, ReadALU]>;
1418 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1419 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1421 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1423 Sched<[WriteALUSsr, ReadALUsr]>;
1427 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1428 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1429 /// a explicit result, only implicitly set CPSR.
1430 let isCompare = 1, Defs = [CPSR] in {
1431 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1432 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1433 PatFrag opnode, bit Commutable = 0,
1434 string rrDecoderMethod = ""> {
1435 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1437 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1438 Sched<[WriteCMP, ReadALU]> {
1443 let Inst{19-16} = Rn;
1444 let Inst{15-12} = 0b0000;
1445 let Inst{11-0} = imm;
1447 let Unpredictable{15-12} = 0b1111;
1449 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1451 [(opnode GPR:$Rn, GPR:$Rm)]>,
1452 Sched<[WriteCMP, ReadALU, ReadALU]> {
1455 let isCommutable = Commutable;
1458 let Inst{19-16} = Rn;
1459 let Inst{15-12} = 0b0000;
1460 let Inst{11-4} = 0b00000000;
1462 let DecoderMethod = rrDecoderMethod;
1464 let Unpredictable{15-12} = 0b1111;
1466 def rsi : AI1<opcod, (outs),
1467 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1468 opc, "\t$Rn, $shift",
1469 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1470 Sched<[WriteCMPsi, ReadALU]> {
1475 let Inst{19-16} = Rn;
1476 let Inst{15-12} = 0b0000;
1477 let Inst{11-5} = shift{11-5};
1479 let Inst{3-0} = shift{3-0};
1481 let Unpredictable{15-12} = 0b1111;
1483 def rsr : AI1<opcod, (outs),
1484 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1485 opc, "\t$Rn, $shift",
1486 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1487 Sched<[WriteCMPsr, ReadALU]> {
1492 let Inst{19-16} = Rn;
1493 let Inst{15-12} = 0b0000;
1494 let Inst{11-8} = shift{11-8};
1496 let Inst{6-5} = shift{6-5};
1498 let Inst{3-0} = shift{3-0};
1500 let Unpredictable{15-12} = 0b1111;
1506 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1507 /// register and one whose operand is a register rotated by 8/16/24.
1508 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1509 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1510 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1511 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1512 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1513 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1517 let Inst{19-16} = 0b1111;
1518 let Inst{15-12} = Rd;
1519 let Inst{11-10} = rot;
1523 class AI_ext_rrot_np<bits<8> opcod, string opc>
1524 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1525 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1526 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1528 let Inst{19-16} = 0b1111;
1529 let Inst{11-10} = rot;
1532 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1533 /// register and one whose operand is a register rotated by 8/16/24.
1534 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1535 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1536 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1537 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1538 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1539 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1544 let Inst{19-16} = Rn;
1545 let Inst{15-12} = Rd;
1546 let Inst{11-10} = rot;
1547 let Inst{9-4} = 0b000111;
1551 class AI_exta_rrot_np<bits<8> opcod, string opc>
1552 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1553 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1554 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1557 let Inst{19-16} = Rn;
1558 let Inst{11-10} = rot;
1561 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1562 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1563 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1564 bit Commutable = 0> {
1565 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1566 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1567 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1568 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1570 Sched<[WriteALU, ReadALU]> {
1575 let Inst{15-12} = Rd;
1576 let Inst{19-16} = Rn;
1577 let Inst{11-0} = imm;
1579 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1580 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1581 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1583 Sched<[WriteALU, ReadALU, ReadALU]> {
1587 let Inst{11-4} = 0b00000000;
1589 let isCommutable = Commutable;
1591 let Inst{15-12} = Rd;
1592 let Inst{19-16} = Rn;
1594 def rsi : AsI1<opcod, (outs GPR:$Rd),
1595 (ins GPR:$Rn, so_reg_imm:$shift),
1596 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1597 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1599 Sched<[WriteALUsi, ReadALU]> {
1604 let Inst{19-16} = Rn;
1605 let Inst{15-12} = Rd;
1606 let Inst{11-5} = shift{11-5};
1608 let Inst{3-0} = shift{3-0};
1610 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1611 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1612 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1613 [(set GPRnopc:$Rd, CPSR,
1614 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1616 Sched<[WriteALUsr, ReadALUsr]> {
1621 let Inst{19-16} = Rn;
1622 let Inst{15-12} = Rd;
1623 let Inst{11-8} = shift{11-8};
1625 let Inst{6-5} = shift{6-5};
1627 let Inst{3-0} = shift{3-0};
1632 /// AI1_rsc_irs - Define instructions and patterns for rsc
1633 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1634 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1635 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1636 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1637 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1638 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1640 Sched<[WriteALU, ReadALU]> {
1645 let Inst{15-12} = Rd;
1646 let Inst{19-16} = Rn;
1647 let Inst{11-0} = imm;
1649 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1650 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1651 [/* pattern left blank */]>,
1652 Sched<[WriteALU, ReadALU, ReadALU]> {
1656 let Inst{11-4} = 0b00000000;
1659 let Inst{15-12} = Rd;
1660 let Inst{19-16} = Rn;
1662 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1663 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1664 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1666 Sched<[WriteALUsi, ReadALU]> {
1671 let Inst{19-16} = Rn;
1672 let Inst{15-12} = Rd;
1673 let Inst{11-5} = shift{11-5};
1675 let Inst{3-0} = shift{3-0};
1677 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1678 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1679 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1681 Sched<[WriteALUsr, ReadALUsr]> {
1686 let Inst{19-16} = Rn;
1687 let Inst{15-12} = Rd;
1688 let Inst{11-8} = shift{11-8};
1690 let Inst{6-5} = shift{6-5};
1692 let Inst{3-0} = shift{3-0};
1697 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1698 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1699 InstrItinClass iir, PatFrag opnode> {
1700 // Note: We use the complex addrmode_imm12 rather than just an input
1701 // GPR and a constrained immediate so that we can use this to match
1702 // frame index references and avoid matching constant pool references.
1703 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1704 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1705 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1708 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1709 let Inst{19-16} = addr{16-13}; // Rn
1710 let Inst{15-12} = Rt;
1711 let Inst{11-0} = addr{11-0}; // imm12
1713 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1714 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1715 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1718 let shift{4} = 0; // Inst{4} = 0
1719 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1720 let Inst{19-16} = shift{16-13}; // Rn
1721 let Inst{15-12} = Rt;
1722 let Inst{11-0} = shift{11-0};
1727 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1728 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1729 InstrItinClass iir, PatFrag opnode> {
1730 // Note: We use the complex addrmode_imm12 rather than just an input
1731 // GPR and a constrained immediate so that we can use this to match
1732 // frame index references and avoid matching constant pool references.
1733 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1734 (ins addrmode_imm12:$addr),
1735 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1736 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1739 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1740 let Inst{19-16} = addr{16-13}; // Rn
1741 let Inst{15-12} = Rt;
1742 let Inst{11-0} = addr{11-0}; // imm12
1744 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1745 (ins ldst_so_reg:$shift),
1746 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1747 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1750 let shift{4} = 0; // Inst{4} = 0
1751 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1752 let Inst{19-16} = shift{16-13}; // Rn
1753 let Inst{15-12} = Rt;
1754 let Inst{11-0} = shift{11-0};
1760 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1761 InstrItinClass iir, PatFrag opnode> {
1762 // Note: We use the complex addrmode_imm12 rather than just an input
1763 // GPR and a constrained immediate so that we can use this to match
1764 // frame index references and avoid matching constant pool references.
1765 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1766 (ins GPR:$Rt, addrmode_imm12:$addr),
1767 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1768 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1771 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1772 let Inst{19-16} = addr{16-13}; // Rn
1773 let Inst{15-12} = Rt;
1774 let Inst{11-0} = addr{11-0}; // imm12
1776 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1777 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1778 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1781 let shift{4} = 0; // Inst{4} = 0
1782 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1783 let Inst{19-16} = shift{16-13}; // Rn
1784 let Inst{15-12} = Rt;
1785 let Inst{11-0} = shift{11-0};
1789 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1790 InstrItinClass iir, PatFrag opnode> {
1791 // Note: We use the complex addrmode_imm12 rather than just an input
1792 // GPR and a constrained immediate so that we can use this to match
1793 // frame index references and avoid matching constant pool references.
1794 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1795 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1796 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1797 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1800 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1801 let Inst{19-16} = addr{16-13}; // Rn
1802 let Inst{15-12} = Rt;
1803 let Inst{11-0} = addr{11-0}; // imm12
1805 def rs : AI2ldst<0b011, 0, isByte, (outs),
1806 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1807 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1808 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1811 let shift{4} = 0; // Inst{4} = 0
1812 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1813 let Inst{19-16} = shift{16-13}; // Rn
1814 let Inst{15-12} = Rt;
1815 let Inst{11-0} = shift{11-0};
1820 //===----------------------------------------------------------------------===//
1822 //===----------------------------------------------------------------------===//
1824 //===----------------------------------------------------------------------===//
1825 // Miscellaneous Instructions.
1828 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1829 /// the function. The first operand is the ID# for this instruction, the second
1830 /// is the index into the MachineConstantPool that this is, the third is the
1831 /// size in bytes of this constant pool entry.
1832 let hasSideEffects = 0, isNotDuplicable = 1 in
1833 def CONSTPOOL_ENTRY :
1834 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1835 i32imm:$size), NoItinerary, []>;
1837 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1838 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1839 /// mode). Used mostly in ARM and Thumb-1 modes.
1840 def JUMPTABLE_ADDRS :
1841 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1842 i32imm:$size), NoItinerary, []>;
1844 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1845 /// that cannot be optimised to use TBB or TBH.
1846 def JUMPTABLE_INSTS :
1847 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1848 i32imm:$size), NoItinerary, []>;
1850 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1851 /// a TBB instruction.
1853 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1854 i32imm:$size), NoItinerary, []>;
1856 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1857 /// a TBH instruction.
1859 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1860 i32imm:$size), NoItinerary, []>;
1863 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1864 // from removing one half of the matched pairs. That breaks PEI, which assumes
1865 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1866 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1867 def ADJCALLSTACKUP :
1868 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1869 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1871 def ADJCALLSTACKDOWN :
1872 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1873 [(ARMcallseq_start timm:$amt)]>;
1876 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1877 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1878 Requires<[IsARM, HasV6]> {
1880 let Inst{27-8} = 0b00110010000011110000;
1881 let Inst{7-0} = imm;
1884 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1885 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1886 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1887 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1888 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1889 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1891 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1892 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1897 let Inst{15-12} = Rd;
1898 let Inst{19-16} = Rn;
1899 let Inst{27-20} = 0b01101000;
1900 let Inst{7-4} = 0b1011;
1901 let Inst{11-8} = 0b1111;
1902 let Unpredictable{11-8} = 0b1111;
1905 // The 16-bit operand $val can be used by a debugger to store more information
1906 // about the breakpoint.
1907 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1908 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1910 let Inst{3-0} = val{3-0};
1911 let Inst{19-8} = val{15-4};
1912 let Inst{27-20} = 0b00010010;
1913 let Inst{31-28} = 0xe; // AL
1914 let Inst{7-4} = 0b0111;
1916 // default immediate for breakpoint mnemonic
1917 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1919 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1920 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1922 let Inst{3-0} = val{3-0};
1923 let Inst{19-8} = val{15-4};
1924 let Inst{27-20} = 0b00010000;
1925 let Inst{31-28} = 0xe; // AL
1926 let Inst{7-4} = 0b0111;
1929 // Change Processor State
1930 // FIXME: We should use InstAlias to handle the optional operands.
1931 class CPS<dag iops, string asm_ops>
1932 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1933 []>, Requires<[IsARM]> {
1939 let Inst{31-28} = 0b1111;
1940 let Inst{27-20} = 0b00010000;
1941 let Inst{19-18} = imod;
1942 let Inst{17} = M; // Enabled if mode is set;
1943 let Inst{16-9} = 0b00000000;
1944 let Inst{8-6} = iflags;
1946 let Inst{4-0} = mode;
1949 let DecoderMethod = "DecodeCPSInstruction" in {
1951 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1952 "$imod\t$iflags, $mode">;
1953 let mode = 0, M = 0 in
1954 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1956 let imod = 0, iflags = 0, M = 1 in
1957 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1960 // Preload signals the memory system of possible future data/instruction access.
1961 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1963 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1964 IIC_Preload, !strconcat(opc, "\t$addr"),
1965 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1966 Sched<[WritePreLd]> {
1969 let Inst{31-26} = 0b111101;
1970 let Inst{25} = 0; // 0 for immediate form
1971 let Inst{24} = data;
1972 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1973 let Inst{22} = read;
1974 let Inst{21-20} = 0b01;
1975 let Inst{19-16} = addr{16-13}; // Rn
1976 let Inst{15-12} = 0b1111;
1977 let Inst{11-0} = addr{11-0}; // imm12
1980 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1981 !strconcat(opc, "\t$shift"),
1982 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1983 Sched<[WritePreLd]> {
1985 let Inst{31-26} = 0b111101;
1986 let Inst{25} = 1; // 1 for register form
1987 let Inst{24} = data;
1988 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1989 let Inst{22} = read;
1990 let Inst{21-20} = 0b01;
1991 let Inst{19-16} = shift{16-13}; // Rn
1992 let Inst{15-12} = 0b1111;
1993 let Inst{11-0} = shift{11-0};
1998 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1999 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
2000 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
2002 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
2003 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
2005 let Inst{31-10} = 0b1111000100000001000000;
2010 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2011 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2013 let Inst{27-4} = 0b001100100000111100001111;
2014 let Inst{3-0} = opt;
2017 // A8.8.247 UDF - Undefined (Encoding A1)
2018 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2019 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2021 let Inst{31-28} = 0b1110; // AL
2022 let Inst{27-25} = 0b011;
2023 let Inst{24-20} = 0b11111;
2024 let Inst{19-8} = imm16{15-4};
2025 let Inst{7-4} = 0b1111;
2026 let Inst{3-0} = imm16{3-0};
2030 * A5.4 Permanently UNDEFINED instructions.
2032 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2033 * Other UDF encodings generate SIGILL.
2035 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2037 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2039 * 1101 1110 iiii iiii
2040 * It uses the following encoding:
2041 * 1110 0111 1111 1110 1101 1110 1111 0000
2042 * - In ARM: UDF #60896;
2043 * - In Thumb: UDF #254 followed by a branch-to-self.
2045 let isBarrier = 1, isTerminator = 1 in
2046 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2048 Requires<[IsARM,UseNaClTrap]> {
2049 let Inst = 0xe7fedef0;
2051 let isBarrier = 1, isTerminator = 1 in
2052 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2054 Requires<[IsARM,DontUseNaClTrap]> {
2055 let Inst = 0xe7ffdefe;
2058 // Address computation and loads and stores in PIC mode.
2059 let isNotDuplicable = 1 in {
2060 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2062 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2063 Sched<[WriteALU, ReadALU]>;
2065 let AddedComplexity = 10 in {
2066 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2068 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2070 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2072 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2074 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2076 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2078 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2080 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2082 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2084 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2086 let AddedComplexity = 10 in {
2087 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2088 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2090 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2091 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2092 addrmodepc:$addr)]>;
2094 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2095 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2097 } // isNotDuplicable = 1
2100 // LEApcrel - Load a pc-relative address into a register without offending the
2102 let hasSideEffects = 0, isReMaterializable = 1 in
2103 // The 'adr' mnemonic encodes differently if the label is before or after
2104 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2105 // know until then which form of the instruction will be used.
2106 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2107 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2108 Sched<[WriteALU, ReadALU]> {
2111 let Inst{27-25} = 0b001;
2113 let Inst{23-22} = label{13-12};
2116 let Inst{19-16} = 0b1111;
2117 let Inst{15-12} = Rd;
2118 let Inst{11-0} = label{11-0};
2121 let hasSideEffects = 1 in {
2122 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2123 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2125 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2126 (ins i32imm:$label, pred:$p),
2127 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2130 //===----------------------------------------------------------------------===//
2131 // Control Flow Instructions.
2134 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2136 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2137 "bx", "\tlr", [(ARMretflag)]>,
2138 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2139 let Inst{27-0} = 0b0001001011111111111100011110;
2143 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2144 "mov", "\tpc, lr", [(ARMretflag)]>,
2145 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2146 let Inst{27-0} = 0b0001101000001111000000001110;
2149 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2150 // the user-space one).
2151 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2153 [(ARMintretflag imm:$offset)]>;
2156 // Indirect branches
2157 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2159 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2160 [(brind GPR:$dst)]>,
2161 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2163 let Inst{31-4} = 0b1110000100101111111111110001;
2164 let Inst{3-0} = dst;
2167 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2168 "bx", "\t$dst", [/* pattern left blank */]>,
2169 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2171 let Inst{27-4} = 0b000100101111111111110001;
2172 let Inst{3-0} = dst;
2176 // SP is marked as a use to prevent stack-pointer assignments that appear
2177 // immediately before calls from potentially appearing dead.
2179 // FIXME: Do we really need a non-predicated version? If so, it should
2180 // at least be a pseudo instruction expanding to the predicated version
2181 // at MC lowering time.
2182 Defs = [LR], Uses = [SP] in {
2183 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2184 IIC_Br, "bl\t$func",
2185 [(ARMcall tglobaladdr:$func)]>,
2186 Requires<[IsARM]>, Sched<[WriteBrL]> {
2187 let Inst{31-28} = 0b1110;
2189 let Inst{23-0} = func;
2190 let DecoderMethod = "DecodeBranchImmInstruction";
2193 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2194 IIC_Br, "bl", "\t$func",
2195 [(ARMcall_pred tglobaladdr:$func)]>,
2196 Requires<[IsARM]>, Sched<[WriteBrL]> {
2198 let Inst{23-0} = func;
2199 let DecoderMethod = "DecodeBranchImmInstruction";
2203 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2204 IIC_Br, "blx\t$func",
2205 [(ARMcall GPR:$func)]>,
2206 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2208 let Inst{31-4} = 0b1110000100101111111111110011;
2209 let Inst{3-0} = func;
2212 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2213 IIC_Br, "blx", "\t$func",
2214 [(ARMcall_pred GPR:$func)]>,
2215 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2217 let Inst{27-4} = 0b000100101111111111110011;
2218 let Inst{3-0} = func;
2222 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2223 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2224 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2225 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2228 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2229 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2230 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2232 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2233 // return stack predictor.
2234 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2235 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2236 Requires<[IsARM]>, Sched<[WriteBr]>;
2239 let isBranch = 1, isTerminator = 1 in {
2240 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2241 // a two-value operand where a dag node expects two operands. :(
2242 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2243 IIC_Br, "b", "\t$target",
2244 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2247 let Inst{23-0} = target;
2248 let DecoderMethod = "DecodeBranchImmInstruction";
2251 let isBarrier = 1 in {
2252 // B is "predicable" since it's just a Bcc with an 'always' condition.
2253 let isPredicable = 1 in
2254 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2255 // should be sufficient.
2256 // FIXME: Is B really a Barrier? That doesn't seem right.
2257 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2258 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2261 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2262 def BR_JTr : ARMPseudoInst<(outs),
2263 (ins GPR:$target, i32imm:$jt),
2265 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2267 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2268 // into i12 and rs suffixed versions.
2269 def BR_JTm : ARMPseudoInst<(outs),
2270 (ins addrmode2:$target, i32imm:$jt),
2272 [(ARMbrjt (i32 (load addrmode2:$target)),
2273 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2274 def BR_JTadd : ARMPseudoInst<(outs),
2275 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2277 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2278 Sched<[WriteBrTbl]>;
2279 } // isNotDuplicable = 1, isIndirectBranch = 1
2285 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2286 "blx\t$target", []>,
2287 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2288 let Inst{31-25} = 0b1111101;
2290 let Inst{23-0} = target{24-1};
2291 let Inst{24} = target{0};
2295 // Branch and Exchange Jazelle
2296 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2297 [/* pattern left blank */]>, Sched<[WriteBr]> {
2299 let Inst{23-20} = 0b0010;
2300 let Inst{19-8} = 0xfff;
2301 let Inst{7-4} = 0b0010;
2302 let Inst{3-0} = func;
2308 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2309 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2312 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2315 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2317 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2318 Requires<[IsARM]>, Sched<[WriteBr]>;
2320 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2322 (BX GPR:$dst)>, Sched<[WriteBr]>,
2326 // Secure Monitor Call is a system instruction.
2327 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2328 []>, Requires<[IsARM, HasTrustZone]> {
2330 let Inst{23-4} = 0b01100000000000000111;
2331 let Inst{3-0} = opt;
2334 // Supervisor Call (Software Interrupt)
2335 let isCall = 1, Uses = [SP] in {
2336 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2339 let Inst{23-0} = svc;
2343 // Store Return State
2344 class SRSI<bit wb, string asm>
2345 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2346 NoItinerary, asm, "", []> {
2348 let Inst{31-28} = 0b1111;
2349 let Inst{27-25} = 0b100;
2353 let Inst{19-16} = 0b1101; // SP
2354 let Inst{15-5} = 0b00000101000;
2355 let Inst{4-0} = mode;
2358 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2359 let Inst{24-23} = 0;
2361 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2362 let Inst{24-23} = 0;
2364 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2365 let Inst{24-23} = 0b10;
2367 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2368 let Inst{24-23} = 0b10;
2370 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2371 let Inst{24-23} = 0b01;
2373 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2374 let Inst{24-23} = 0b01;
2376 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2377 let Inst{24-23} = 0b11;
2379 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2380 let Inst{24-23} = 0b11;
2383 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2384 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2386 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2387 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2389 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2390 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2392 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2393 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2395 // Return From Exception
2396 class RFEI<bit wb, string asm>
2397 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2398 NoItinerary, asm, "", []> {
2400 let Inst{31-28} = 0b1111;
2401 let Inst{27-25} = 0b100;
2405 let Inst{19-16} = Rn;
2406 let Inst{15-0} = 0xa00;
2409 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2410 let Inst{24-23} = 0;
2412 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2413 let Inst{24-23} = 0;
2415 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2416 let Inst{24-23} = 0b10;
2418 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2419 let Inst{24-23} = 0b10;
2421 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2422 let Inst{24-23} = 0b01;
2424 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2425 let Inst{24-23} = 0b01;
2427 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2428 let Inst{24-23} = 0b11;
2430 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2431 let Inst{24-23} = 0b11;
2434 // Hypervisor Call is a system instruction
2436 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2437 "hvc", "\t$imm", []>,
2438 Requires<[IsARM, HasVirtualization]> {
2441 // Even though HVC isn't predicable, it's encoding includes a condition field.
2442 // The instruction is undefined if the condition field is 0xf otherwise it is
2443 // unpredictable if it isn't condition AL (0xe).
2444 let Inst{31-28} = 0b1110;
2445 let Unpredictable{31-28} = 0b1111;
2446 let Inst{27-24} = 0b0001;
2447 let Inst{23-20} = 0b0100;
2448 let Inst{19-8} = imm{15-4};
2449 let Inst{7-4} = 0b0111;
2450 let Inst{3-0} = imm{3-0};
2454 // Return from exception in Hypervisor mode.
2455 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2456 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2457 Requires<[IsARM, HasVirtualization]> {
2458 let Inst{23-0} = 0b011000000000000001101110;
2461 //===----------------------------------------------------------------------===//
2462 // Load / Store Instructions.
2468 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2469 UnOpFrag<(load node:$Src)>>;
2470 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2471 UnOpFrag<(zextloadi8 node:$Src)>>;
2472 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2473 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2474 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2475 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2477 // Special LDR for loads from non-pc-relative constpools.
2478 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2479 isReMaterializable = 1, isCodeGenOnly = 1 in
2480 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2481 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2485 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2486 let Inst{19-16} = 0b1111;
2487 let Inst{15-12} = Rt;
2488 let Inst{11-0} = addr{11-0}; // imm12
2491 // Loads with zero extension
2492 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2493 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2494 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2496 // Loads with sign extension
2497 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2498 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2499 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2501 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2502 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2503 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2505 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2507 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2508 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2509 Requires<[IsARM, HasV5TE]>;
2512 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2513 NoItinerary, "lda", "\t$Rt, $addr", []>;
2514 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2515 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2516 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2517 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2520 multiclass AI2_ldridx<bit isByte, string opc,
2521 InstrItinClass iii, InstrItinClass iir> {
2522 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2523 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2524 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2527 let Inst{23} = addr{12};
2528 let Inst{19-16} = addr{16-13};
2529 let Inst{11-0} = addr{11-0};
2530 let DecoderMethod = "DecodeLDRPreImm";
2533 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2534 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2535 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2538 let Inst{23} = addr{12};
2539 let Inst{19-16} = addr{16-13};
2540 let Inst{11-0} = addr{11-0};
2542 let DecoderMethod = "DecodeLDRPreReg";
2545 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2546 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2547 IndexModePost, LdFrm, iir,
2548 opc, "\t$Rt, $addr, $offset",
2549 "$addr.base = $Rn_wb", []> {
2555 let Inst{23} = offset{12};
2556 let Inst{19-16} = addr;
2557 let Inst{11-0} = offset{11-0};
2560 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2563 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2564 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2565 IndexModePost, LdFrm, iii,
2566 opc, "\t$Rt, $addr, $offset",
2567 "$addr.base = $Rn_wb", []> {
2573 let Inst{23} = offset{12};
2574 let Inst{19-16} = addr;
2575 let Inst{11-0} = offset{11-0};
2577 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2582 let mayLoad = 1, hasSideEffects = 0 in {
2583 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2584 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2585 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2586 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2589 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2590 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2591 (ins addrmode3_pre:$addr), IndexModePre,
2593 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2595 let Inst{23} = addr{8}; // U bit
2596 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2597 let Inst{19-16} = addr{12-9}; // Rn
2598 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2599 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2600 let DecoderMethod = "DecodeAddrMode3Instruction";
2602 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2603 (ins addr_offset_none:$addr, am3offset:$offset),
2604 IndexModePost, LdMiscFrm, itin,
2605 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2609 let Inst{23} = offset{8}; // U bit
2610 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2611 let Inst{19-16} = addr;
2612 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2613 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2614 let DecoderMethod = "DecodeAddrMode3Instruction";
2618 let mayLoad = 1, hasSideEffects = 0 in {
2619 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2620 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2621 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2622 let hasExtraDefRegAllocReq = 1 in {
2623 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2624 (ins addrmode3_pre:$addr), IndexModePre,
2625 LdMiscFrm, IIC_iLoad_d_ru,
2626 "ldrd", "\t$Rt, $Rt2, $addr!",
2627 "$addr.base = $Rn_wb", []> {
2629 let Inst{23} = addr{8}; // U bit
2630 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2631 let Inst{19-16} = addr{12-9}; // Rn
2632 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2633 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2634 let DecoderMethod = "DecodeAddrMode3Instruction";
2636 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2637 (ins addr_offset_none:$addr, am3offset:$offset),
2638 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2639 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2640 "$addr.base = $Rn_wb", []> {
2643 let Inst{23} = offset{8}; // U bit
2644 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2645 let Inst{19-16} = addr;
2646 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2647 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2648 let DecoderMethod = "DecodeAddrMode3Instruction";
2650 } // hasExtraDefRegAllocReq = 1
2651 } // mayLoad = 1, hasSideEffects = 0
2653 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2654 let mayLoad = 1, hasSideEffects = 0 in {
2655 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2656 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2657 IndexModePost, LdFrm, IIC_iLoad_ru,
2658 "ldrt", "\t$Rt, $addr, $offset",
2659 "$addr.base = $Rn_wb", []> {
2665 let Inst{23} = offset{12};
2666 let Inst{21} = 1; // overwrite
2667 let Inst{19-16} = addr;
2668 let Inst{11-5} = offset{11-5};
2670 let Inst{3-0} = offset{3-0};
2671 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2675 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2676 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2677 IndexModePost, LdFrm, IIC_iLoad_ru,
2678 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2684 let Inst{23} = offset{12};
2685 let Inst{21} = 1; // overwrite
2686 let Inst{19-16} = addr;
2687 let Inst{11-0} = offset{11-0};
2688 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2691 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2692 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2693 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2694 "ldrbt", "\t$Rt, $addr, $offset",
2695 "$addr.base = $Rn_wb", []> {
2701 let Inst{23} = offset{12};
2702 let Inst{21} = 1; // overwrite
2703 let Inst{19-16} = addr;
2704 let Inst{11-5} = offset{11-5};
2706 let Inst{3-0} = offset{3-0};
2707 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2711 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2712 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2713 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2714 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2720 let Inst{23} = offset{12};
2721 let Inst{21} = 1; // overwrite
2722 let Inst{19-16} = addr;
2723 let Inst{11-0} = offset{11-0};
2724 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2727 multiclass AI3ldrT<bits<4> op, string opc> {
2728 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2729 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2730 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2731 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2733 let Inst{23} = offset{8};
2735 let Inst{11-8} = offset{7-4};
2736 let Inst{3-0} = offset{3-0};
2738 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2739 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2740 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2741 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2743 let Inst{23} = Rm{4};
2746 let Unpredictable{11-8} = 0b1111;
2747 let Inst{3-0} = Rm{3-0};
2748 let DecoderMethod = "DecodeLDR";
2752 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2753 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2754 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2758 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2762 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2767 // Stores with truncate
2768 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2769 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2770 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2773 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2774 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2775 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2776 Requires<[IsARM, HasV5TE]> {
2782 multiclass AI2_stridx<bit isByte, string opc,
2783 InstrItinClass iii, InstrItinClass iir> {
2784 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2785 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2787 opc, "\t$Rt, $addr!",
2788 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2791 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2792 let Inst{19-16} = addr{16-13}; // Rn
2793 let Inst{11-0} = addr{11-0}; // imm12
2794 let DecoderMethod = "DecodeSTRPreImm";
2797 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2798 (ins GPR:$Rt, ldst_so_reg:$addr),
2799 IndexModePre, StFrm, iir,
2800 opc, "\t$Rt, $addr!",
2801 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2804 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2805 let Inst{19-16} = addr{16-13}; // Rn
2806 let Inst{11-0} = addr{11-0};
2807 let Inst{4} = 0; // Inst{4} = 0
2808 let DecoderMethod = "DecodeSTRPreReg";
2810 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2811 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2812 IndexModePost, StFrm, iir,
2813 opc, "\t$Rt, $addr, $offset",
2814 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2820 let Inst{23} = offset{12};
2821 let Inst{19-16} = addr;
2822 let Inst{11-0} = offset{11-0};
2825 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2828 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2829 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2830 IndexModePost, StFrm, iii,
2831 opc, "\t$Rt, $addr, $offset",
2832 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2838 let Inst{23} = offset{12};
2839 let Inst{19-16} = addr;
2840 let Inst{11-0} = offset{11-0};
2842 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2846 let mayStore = 1, hasSideEffects = 0 in {
2847 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2848 // IIC_iStore_siu depending on whether it the offset register is shifted.
2849 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2850 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2853 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2854 am2offset_reg:$offset),
2855 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2856 am2offset_reg:$offset)>;
2857 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2858 am2offset_imm:$offset),
2859 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2860 am2offset_imm:$offset)>;
2861 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2862 am2offset_reg:$offset),
2863 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2864 am2offset_reg:$offset)>;
2865 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2866 am2offset_imm:$offset),
2867 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2868 am2offset_imm:$offset)>;
2870 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2871 // put the patterns on the instruction definitions directly as ISel wants
2872 // the address base and offset to be separate operands, not a single
2873 // complex operand like we represent the instructions themselves. The
2874 // pseudos map between the two.
2875 let usesCustomInserter = 1,
2876 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2877 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2878 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2881 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2882 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2883 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2886 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2887 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2888 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2891 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2892 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2893 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2896 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2897 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2898 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2901 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2906 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2907 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2908 StMiscFrm, IIC_iStore_bh_ru,
2909 "strh", "\t$Rt, $addr!",
2910 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2912 let Inst{23} = addr{8}; // U bit
2913 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2914 let Inst{19-16} = addr{12-9}; // Rn
2915 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2916 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2917 let DecoderMethod = "DecodeAddrMode3Instruction";
2920 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2921 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2922 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2923 "strh", "\t$Rt, $addr, $offset",
2924 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2925 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2926 addr_offset_none:$addr,
2927 am3offset:$offset))]> {
2930 let Inst{23} = offset{8}; // U bit
2931 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2932 let Inst{19-16} = addr;
2933 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2934 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2935 let DecoderMethod = "DecodeAddrMode3Instruction";
2938 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2939 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2940 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2941 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2942 "strd", "\t$Rt, $Rt2, $addr!",
2943 "$addr.base = $Rn_wb", []> {
2945 let Inst{23} = addr{8}; // U bit
2946 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2947 let Inst{19-16} = addr{12-9}; // Rn
2948 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2949 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2950 let DecoderMethod = "DecodeAddrMode3Instruction";
2953 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2954 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2956 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2957 "strd", "\t$Rt, $Rt2, $addr, $offset",
2958 "$addr.base = $Rn_wb", []> {
2961 let Inst{23} = offset{8}; // U bit
2962 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2963 let Inst{19-16} = addr;
2964 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2965 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2966 let DecoderMethod = "DecodeAddrMode3Instruction";
2968 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2970 // STRT, STRBT, and STRHT
2972 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2973 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2974 IndexModePost, StFrm, IIC_iStore_bh_ru,
2975 "strbt", "\t$Rt, $addr, $offset",
2976 "$addr.base = $Rn_wb", []> {
2982 let Inst{23} = offset{12};
2983 let Inst{21} = 1; // overwrite
2984 let Inst{19-16} = addr;
2985 let Inst{11-5} = offset{11-5};
2987 let Inst{3-0} = offset{3-0};
2988 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2992 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2993 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2994 IndexModePost, StFrm, IIC_iStore_bh_ru,
2995 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3001 let Inst{23} = offset{12};
3002 let Inst{21} = 1; // overwrite
3003 let Inst{19-16} = addr;
3004 let Inst{11-0} = offset{11-0};
3005 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3009 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3010 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3012 let mayStore = 1, hasSideEffects = 0 in {
3013 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3014 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3015 IndexModePost, StFrm, IIC_iStore_ru,
3016 "strt", "\t$Rt, $addr, $offset",
3017 "$addr.base = $Rn_wb", []> {
3023 let Inst{23} = offset{12};
3024 let Inst{21} = 1; // overwrite
3025 let Inst{19-16} = addr;
3026 let Inst{11-5} = offset{11-5};
3028 let Inst{3-0} = offset{3-0};
3029 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3033 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3034 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3035 IndexModePost, StFrm, IIC_iStore_ru,
3036 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3042 let Inst{23} = offset{12};
3043 let Inst{21} = 1; // overwrite
3044 let Inst{19-16} = addr;
3045 let Inst{11-0} = offset{11-0};
3046 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3051 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3052 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3054 multiclass AI3strT<bits<4> op, string opc> {
3055 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3056 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3057 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3058 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3060 let Inst{23} = offset{8};
3062 let Inst{11-8} = offset{7-4};
3063 let Inst{3-0} = offset{3-0};
3065 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3066 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3067 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3068 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3070 let Inst{23} = Rm{4};
3073 let Inst{3-0} = Rm{3-0};
3078 defm STRHT : AI3strT<0b1011, "strht">;
3080 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3081 NoItinerary, "stl", "\t$Rt, $addr", []>;
3082 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3083 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3084 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3085 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3087 //===----------------------------------------------------------------------===//
3088 // Load / store multiple Instructions.
3091 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3092 InstrItinClass itin, InstrItinClass itin_upd> {
3093 // IA is the default, so no need for an explicit suffix on the
3094 // mnemonic here. Without it is the canonical spelling.
3096 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3097 IndexModeNone, f, itin,
3098 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3099 let Inst{24-23} = 0b01; // Increment After
3100 let Inst{22} = P_bit;
3101 let Inst{21} = 0; // No writeback
3102 let Inst{20} = L_bit;
3105 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3106 IndexModeUpd, f, itin_upd,
3107 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3108 let Inst{24-23} = 0b01; // Increment After
3109 let Inst{22} = P_bit;
3110 let Inst{21} = 1; // Writeback
3111 let Inst{20} = L_bit;
3113 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3116 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3117 IndexModeNone, f, itin,
3118 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3119 let Inst{24-23} = 0b00; // Decrement After
3120 let Inst{22} = P_bit;
3121 let Inst{21} = 0; // No writeback
3122 let Inst{20} = L_bit;
3125 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3126 IndexModeUpd, f, itin_upd,
3127 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3128 let Inst{24-23} = 0b00; // Decrement After
3129 let Inst{22} = P_bit;
3130 let Inst{21} = 1; // Writeback
3131 let Inst{20} = L_bit;
3133 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3136 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3137 IndexModeNone, f, itin,
3138 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3139 let Inst{24-23} = 0b10; // Decrement Before
3140 let Inst{22} = P_bit;
3141 let Inst{21} = 0; // No writeback
3142 let Inst{20} = L_bit;
3145 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3146 IndexModeUpd, f, itin_upd,
3147 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3148 let Inst{24-23} = 0b10; // Decrement Before
3149 let Inst{22} = P_bit;
3150 let Inst{21} = 1; // Writeback
3151 let Inst{20} = L_bit;
3153 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3156 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3157 IndexModeNone, f, itin,
3158 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3159 let Inst{24-23} = 0b11; // Increment Before
3160 let Inst{22} = P_bit;
3161 let Inst{21} = 0; // No writeback
3162 let Inst{20} = L_bit;
3165 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3166 IndexModeUpd, f, itin_upd,
3167 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3168 let Inst{24-23} = 0b11; // Increment Before
3169 let Inst{22} = P_bit;
3170 let Inst{21} = 1; // Writeback
3171 let Inst{20} = L_bit;
3173 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3177 let hasSideEffects = 0 in {
3179 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3180 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3181 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3183 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3184 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3186 ComplexDeprecationPredicate<"ARMStore">;
3190 // FIXME: remove when we have a way to marking a MI with these properties.
3191 // FIXME: Should pc be an implicit operand like PICADD, etc?
3192 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3193 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3194 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3195 reglist:$regs, variable_ops),
3196 4, IIC_iLoad_mBr, [],
3197 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3198 RegConstraint<"$Rn = $wb">;
3200 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3201 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3204 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3205 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3210 //===----------------------------------------------------------------------===//
3211 // Move Instructions.
3214 let hasSideEffects = 0 in
3215 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3216 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3220 let Inst{19-16} = 0b0000;
3221 let Inst{11-4} = 0b00000000;
3224 let Inst{15-12} = Rd;
3227 // A version for the smaller set of tail call registers.
3228 let hasSideEffects = 0 in
3229 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3230 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3234 let Inst{11-4} = 0b00000000;
3237 let Inst{15-12} = Rd;
3240 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3241 DPSoRegRegFrm, IIC_iMOVsr,
3242 "mov", "\t$Rd, $src",
3243 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3247 let Inst{15-12} = Rd;
3248 let Inst{19-16} = 0b0000;
3249 let Inst{11-8} = src{11-8};
3251 let Inst{6-5} = src{6-5};
3253 let Inst{3-0} = src{3-0};
3257 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3258 DPSoRegImmFrm, IIC_iMOVsr,
3259 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3260 UnaryDP, Sched<[WriteALU]> {
3263 let Inst{15-12} = Rd;
3264 let Inst{19-16} = 0b0000;
3265 let Inst{11-5} = src{11-5};
3267 let Inst{3-0} = src{3-0};
3271 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3272 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3273 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3278 let Inst{15-12} = Rd;
3279 let Inst{19-16} = 0b0000;
3280 let Inst{11-0} = imm;
3283 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3284 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3286 "movw", "\t$Rd, $imm",
3287 [(set GPR:$Rd, imm0_65535:$imm)]>,
3288 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3291 let Inst{15-12} = Rd;
3292 let Inst{11-0} = imm{11-0};
3293 let Inst{19-16} = imm{15-12};
3296 let DecoderMethod = "DecodeArmMOVTWInstruction";
3299 def : InstAlias<"mov${p} $Rd, $imm",
3300 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3303 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3304 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3307 let Constraints = "$src = $Rd" in {
3308 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3309 (ins GPR:$src, imm0_65535_expr:$imm),
3311 "movt", "\t$Rd, $imm",
3313 (or (and GPR:$src, 0xffff),
3314 lo16AllZero:$imm))]>, UnaryDP,
3315 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3318 let Inst{15-12} = Rd;
3319 let Inst{11-0} = imm{11-0};
3320 let Inst{19-16} = imm{15-12};
3323 let DecoderMethod = "DecodeArmMOVTWInstruction";
3326 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3327 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3332 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3333 Requires<[IsARM, HasV6T2]>;
3335 let Uses = [CPSR] in
3336 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3337 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3338 Requires<[IsARM]>, Sched<[WriteALU]>;
3340 // These aren't really mov instructions, but we have to define them this way
3341 // due to flag operands.
3343 let Defs = [CPSR] in {
3344 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3345 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3346 Sched<[WriteALU]>, Requires<[IsARM]>;
3347 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3348 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3349 Sched<[WriteALU]>, Requires<[IsARM]>;
3352 //===----------------------------------------------------------------------===//
3353 // Extend Instructions.
3358 def SXTB : AI_ext_rrot<0b01101010,
3359 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3360 def SXTH : AI_ext_rrot<0b01101011,
3361 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3363 def SXTAB : AI_exta_rrot<0b01101010,
3364 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3365 def SXTAH : AI_exta_rrot<0b01101011,
3366 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3368 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3370 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3374 let AddedComplexity = 16 in {
3375 def UXTB : AI_ext_rrot<0b01101110,
3376 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3377 def UXTH : AI_ext_rrot<0b01101111,
3378 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3379 def UXTB16 : AI_ext_rrot<0b01101100,
3380 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3382 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3383 // The transformation should probably be done as a combiner action
3384 // instead so we can include a check for masking back in the upper
3385 // eight bits of the source into the lower eight bits of the result.
3386 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3387 // (UXTB16r_rot GPR:$Src, 3)>;
3388 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3389 (UXTB16 GPR:$Src, 1)>;
3391 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3392 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3393 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3394 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3397 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3398 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3401 def SBFX : I<(outs GPRnopc:$Rd),
3402 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3403 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3404 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3405 Requires<[IsARM, HasV6T2]> {
3410 let Inst{27-21} = 0b0111101;
3411 let Inst{6-4} = 0b101;
3412 let Inst{20-16} = width;
3413 let Inst{15-12} = Rd;
3414 let Inst{11-7} = lsb;
3418 def UBFX : I<(outs GPRnopc:$Rd),
3419 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3420 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3421 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3422 Requires<[IsARM, HasV6T2]> {
3427 let Inst{27-21} = 0b0111111;
3428 let Inst{6-4} = 0b101;
3429 let Inst{20-16} = width;
3430 let Inst{15-12} = Rd;
3431 let Inst{11-7} = lsb;
3435 //===----------------------------------------------------------------------===//
3436 // Arithmetic Instructions.
3439 defm ADD : AsI1_bin_irs<0b0100, "add",
3440 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3441 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3442 defm SUB : AsI1_bin_irs<0b0010, "sub",
3443 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3444 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3446 // ADD and SUB with 's' bit set.
3448 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3449 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3450 // AdjustInstrPostInstrSelection where we determine whether or not to
3451 // set the "s" bit based on CPSR liveness.
3453 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3454 // support for an optional CPSR definition that corresponds to the DAG
3455 // node's second value. We can then eliminate the implicit def of CPSR.
3456 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3457 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3458 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3459 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3461 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3462 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3463 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3464 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3466 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3467 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3468 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3470 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3471 // CPSR and the implicit def of CPSR is not needed.
3472 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3473 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3475 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3476 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3478 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3479 // The assume-no-carry-in form uses the negation of the input since add/sub
3480 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3481 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3483 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3484 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3485 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3486 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3488 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3489 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3490 Requires<[IsARM, HasV6T2]>;
3491 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3492 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3493 Requires<[IsARM, HasV6T2]>;
3495 // The with-carry-in form matches bitwise not instead of the negation.
3496 // Effectively, the inverse interpretation of the carry flag already accounts
3497 // for part of the negation.
3498 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3499 (SBCri GPR:$src, mod_imm_not:$imm)>;
3500 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3501 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3502 Requires<[IsARM, HasV6T2]>;
3504 // Note: These are implemented in C++ code, because they have to generate
3505 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3507 // (mul X, 2^n+1) -> (add (X << n), X)
3508 // (mul X, 2^n-1) -> (rsb X, (X << n))
3510 // ARM Arithmetic Instruction
3511 // GPR:$dst = GPR:$a op GPR:$b
3512 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3513 list<dag> pattern = [],
3514 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3515 string asm = "\t$Rd, $Rn, $Rm">
3516 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3517 Sched<[WriteALU, ReadALU, ReadALU]> {
3521 let Inst{27-20} = op27_20;
3522 let Inst{11-4} = op11_4;
3523 let Inst{19-16} = Rn;
3524 let Inst{15-12} = Rd;
3527 let Unpredictable{11-8} = 0b1111;
3530 // Saturating add/subtract
3532 let DecoderMethod = "DecodeQADDInstruction" in
3533 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3534 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3535 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3537 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3538 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3539 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3540 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3541 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3543 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3544 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3547 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3548 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3549 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3550 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3551 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3552 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3553 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3554 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3555 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3556 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3557 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3558 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3560 // Signed/Unsigned add/subtract
3562 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3563 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3564 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3565 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3566 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3567 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3568 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3569 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3570 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3571 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3572 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3573 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3575 // Signed/Unsigned halving add/subtract
3577 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3578 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3579 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3580 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3581 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3582 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3583 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3584 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3585 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3586 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3587 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3588 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3590 // Unsigned Sum of Absolute Differences [and Accumulate].
3592 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3593 MulFrm /* for convenience */, NoItinerary, "usad8",
3594 "\t$Rd, $Rn, $Rm", []>,
3595 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3599 let Inst{27-20} = 0b01111000;
3600 let Inst{15-12} = 0b1111;
3601 let Inst{7-4} = 0b0001;
3602 let Inst{19-16} = Rd;
3603 let Inst{11-8} = Rm;
3606 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3607 MulFrm /* for convenience */, NoItinerary, "usada8",
3608 "\t$Rd, $Rn, $Rm, $Ra", []>,
3609 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3614 let Inst{27-20} = 0b01111000;
3615 let Inst{7-4} = 0b0001;
3616 let Inst{19-16} = Rd;
3617 let Inst{15-12} = Ra;
3618 let Inst{11-8} = Rm;
3622 // Signed/Unsigned saturate
3624 def SSAT : AI<(outs GPRnopc:$Rd),
3625 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3626 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3631 let Inst{27-21} = 0b0110101;
3632 let Inst{5-4} = 0b01;
3633 let Inst{20-16} = sat_imm;
3634 let Inst{15-12} = Rd;
3635 let Inst{11-7} = sh{4-0};
3636 let Inst{6} = sh{5};
3640 def SSAT16 : AI<(outs GPRnopc:$Rd),
3641 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3642 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3646 let Inst{27-20} = 0b01101010;
3647 let Inst{11-4} = 0b11110011;
3648 let Inst{15-12} = Rd;
3649 let Inst{19-16} = sat_imm;
3653 def USAT : AI<(outs GPRnopc:$Rd),
3654 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3655 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3660 let Inst{27-21} = 0b0110111;
3661 let Inst{5-4} = 0b01;
3662 let Inst{15-12} = Rd;
3663 let Inst{11-7} = sh{4-0};
3664 let Inst{6} = sh{5};
3665 let Inst{20-16} = sat_imm;
3669 def USAT16 : AI<(outs GPRnopc:$Rd),
3670 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3671 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3675 let Inst{27-20} = 0b01101110;
3676 let Inst{11-4} = 0b11110011;
3677 let Inst{15-12} = Rd;
3678 let Inst{19-16} = sat_imm;
3682 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3683 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3684 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3685 (USAT imm:$pos, GPRnopc:$a, 0)>;
3687 //===----------------------------------------------------------------------===//
3688 // Bitwise Instructions.
3691 defm AND : AsI1_bin_irs<0b0000, "and",
3692 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3693 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3694 defm ORR : AsI1_bin_irs<0b1100, "orr",
3695 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3696 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3697 defm EOR : AsI1_bin_irs<0b0001, "eor",
3698 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3699 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3700 defm BIC : AsI1_bin_irs<0b1110, "bic",
3701 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3702 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3704 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3705 // like in the actual instruction encoding. The complexity of mapping the mask
3706 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3707 // instruction description.
3708 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3709 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3710 "bfc", "\t$Rd, $imm", "$src = $Rd",
3711 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3712 Requires<[IsARM, HasV6T2]> {
3715 let Inst{27-21} = 0b0111110;
3716 let Inst{6-0} = 0b0011111;
3717 let Inst{15-12} = Rd;
3718 let Inst{11-7} = imm{4-0}; // lsb
3719 let Inst{20-16} = imm{9-5}; // msb
3722 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3723 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3724 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3725 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3726 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3727 bf_inv_mask_imm:$imm))]>,
3728 Requires<[IsARM, HasV6T2]> {
3732 let Inst{27-21} = 0b0111110;
3733 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3734 let Inst{15-12} = Rd;
3735 let Inst{11-7} = imm{4-0}; // lsb
3736 let Inst{20-16} = imm{9-5}; // width
3740 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3741 "mvn", "\t$Rd, $Rm",
3742 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3746 let Inst{19-16} = 0b0000;
3747 let Inst{11-4} = 0b00000000;
3748 let Inst{15-12} = Rd;
3751 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3752 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3753 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3758 let Inst{19-16} = 0b0000;
3759 let Inst{15-12} = Rd;
3760 let Inst{11-5} = shift{11-5};
3762 let Inst{3-0} = shift{3-0};
3764 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3765 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3766 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3771 let Inst{19-16} = 0b0000;
3772 let Inst{15-12} = Rd;
3773 let Inst{11-8} = shift{11-8};
3775 let Inst{6-5} = shift{6-5};
3777 let Inst{3-0} = shift{3-0};
3779 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3780 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3781 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3782 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3786 let Inst{19-16} = 0b0000;
3787 let Inst{15-12} = Rd;
3788 let Inst{11-0} = imm;
3791 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3792 (BICri GPR:$src, mod_imm_not:$imm)>;
3794 //===----------------------------------------------------------------------===//
3795 // Multiply Instructions.
3797 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3798 string opc, string asm, list<dag> pattern>
3799 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3803 let Inst{19-16} = Rd;
3804 let Inst{11-8} = Rm;
3807 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3808 string opc, string asm, list<dag> pattern>
3809 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3814 let Inst{19-16} = RdHi;
3815 let Inst{15-12} = RdLo;
3816 let Inst{11-8} = Rm;
3819 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3820 string opc, string asm, list<dag> pattern>
3821 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3826 let Inst{19-16} = RdHi;
3827 let Inst{15-12} = RdLo;
3828 let Inst{11-8} = Rm;
3832 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3833 // property. Remove them when it's possible to add those properties
3834 // on an individual MachineInstr, not just an instruction description.
3835 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3836 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3837 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3838 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3839 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3840 Requires<[IsARM, HasV6]> {
3841 let Inst{15-12} = 0b0000;
3842 let Unpredictable{15-12} = 0b1111;
3845 let Constraints = "@earlyclobber $Rd" in
3846 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3847 pred:$p, cc_out:$s),
3849 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3850 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3851 Requires<[IsARM, NoV6, UseMulOps]>;
3854 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3855 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3856 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3857 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3858 Requires<[IsARM, HasV6, UseMulOps]> {
3860 let Inst{15-12} = Ra;
3863 let Constraints = "@earlyclobber $Rd" in
3864 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3865 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3866 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3867 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3868 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3869 Requires<[IsARM, NoV6]>;
3871 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3872 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3873 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3874 Requires<[IsARM, HasV6T2, UseMulOps]> {
3879 let Inst{19-16} = Rd;
3880 let Inst{15-12} = Ra;
3881 let Inst{11-8} = Rm;
3885 // Extra precision multiplies with low / high results
3886 let hasSideEffects = 0 in {
3887 let isCommutable = 1 in {
3888 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3889 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3890 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3891 Requires<[IsARM, HasV6]>;
3893 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3894 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3895 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3896 Requires<[IsARM, HasV6]>;
3898 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3899 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3900 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3902 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3903 Requires<[IsARM, NoV6]>;
3905 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3906 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3908 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3909 Requires<[IsARM, NoV6]>;
3913 // Multiply + accumulate
3914 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3915 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3916 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3917 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3918 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3919 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3920 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3921 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3923 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3924 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3925 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3926 Requires<[IsARM, HasV6]> {
3931 let Inst{19-16} = RdHi;
3932 let Inst{15-12} = RdLo;
3933 let Inst{11-8} = Rm;
3938 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3939 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3940 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3942 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3943 pred:$p, cc_out:$s)>,
3944 Requires<[IsARM, NoV6]>;
3945 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3946 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3948 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3949 pred:$p, cc_out:$s)>,
3950 Requires<[IsARM, NoV6]>;
3955 // Most significant word multiply
3956 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3957 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3958 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3959 Requires<[IsARM, HasV6]> {
3960 let Inst{15-12} = 0b1111;
3963 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3964 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3965 Requires<[IsARM, HasV6]> {
3966 let Inst{15-12} = 0b1111;
3969 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3970 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3971 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3972 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3973 Requires<[IsARM, HasV6, UseMulOps]>;
3975 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3976 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3977 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3978 Requires<[IsARM, HasV6]>;
3980 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3981 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3982 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3983 Requires<[IsARM, HasV6, UseMulOps]>;
3985 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3986 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3987 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3988 Requires<[IsARM, HasV6]>;
3990 multiclass AI_smul<string opc, PatFrag opnode> {
3991 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3992 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3993 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3994 (sext_inreg GPR:$Rm, i16)))]>,
3995 Requires<[IsARM, HasV5TE]>;
3997 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3998 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3999 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
4000 (sra GPR:$Rm, (i32 16))))]>,
4001 Requires<[IsARM, HasV5TE]>;
4003 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4004 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4005 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4006 (sext_inreg GPR:$Rm, i16)))]>,
4007 Requires<[IsARM, HasV5TE]>;
4009 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4010 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4011 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4012 (sra GPR:$Rm, (i32 16))))]>,
4013 Requires<[IsARM, HasV5TE]>;
4015 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4016 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4018 Requires<[IsARM, HasV5TE]>;
4020 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4021 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4023 Requires<[IsARM, HasV5TE]>;
4027 multiclass AI_smla<string opc, PatFrag opnode> {
4028 let DecoderMethod = "DecodeSMLAInstruction" in {
4029 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4030 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4031 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4032 [(set GPRnopc:$Rd, (add GPR:$Ra,
4033 (opnode (sext_inreg GPRnopc:$Rn, i16),
4034 (sext_inreg GPRnopc:$Rm, i16))))]>,
4035 Requires<[IsARM, HasV5TE, UseMulOps]>;
4037 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4038 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4039 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4041 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4042 (sra GPRnopc:$Rm, (i32 16)))))]>,
4043 Requires<[IsARM, HasV5TE, UseMulOps]>;
4045 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4046 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4047 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4049 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4050 (sext_inreg GPRnopc:$Rm, i16))))]>,
4051 Requires<[IsARM, HasV5TE, UseMulOps]>;
4053 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4054 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4055 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4057 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4058 (sra GPRnopc:$Rm, (i32 16)))))]>,
4059 Requires<[IsARM, HasV5TE, UseMulOps]>;
4061 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4062 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4063 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4065 Requires<[IsARM, HasV5TE, UseMulOps]>;
4067 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4068 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4069 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4071 Requires<[IsARM, HasV5TE, UseMulOps]>;
4075 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4076 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4078 // Halfword multiply accumulate long: SMLAL<x><y>.
4079 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4080 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4081 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4082 Requires<[IsARM, HasV5TE]>;
4084 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4085 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4086 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4087 Requires<[IsARM, HasV5TE]>;
4089 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4090 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4091 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4092 Requires<[IsARM, HasV5TE]>;
4094 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4095 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4096 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4097 Requires<[IsARM, HasV5TE]>;
4099 // Helper class for AI_smld.
4100 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4101 InstrItinClass itin, string opc, string asm>
4102 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4105 let Inst{27-23} = 0b01110;
4106 let Inst{22} = long;
4107 let Inst{21-20} = 0b00;
4108 let Inst{11-8} = Rm;
4115 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4116 InstrItinClass itin, string opc, string asm>
4117 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4119 let Inst{15-12} = 0b1111;
4120 let Inst{19-16} = Rd;
4122 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4123 InstrItinClass itin, string opc, string asm>
4124 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4127 let Inst{19-16} = Rd;
4128 let Inst{15-12} = Ra;
4130 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4131 InstrItinClass itin, string opc, string asm>
4132 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4135 let Inst{19-16} = RdHi;
4136 let Inst{15-12} = RdLo;
4139 multiclass AI_smld<bit sub, string opc> {
4141 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4142 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4143 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4145 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4146 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4147 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4149 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4150 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4151 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4153 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4154 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4155 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4159 defm SMLA : AI_smld<0, "smla">;
4160 defm SMLS : AI_smld<1, "smls">;
4162 multiclass AI_sdml<bit sub, string opc> {
4164 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4165 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4166 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4167 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4170 defm SMUA : AI_sdml<0, "smua">;
4171 defm SMUS : AI_sdml<1, "smus">;
4173 //===----------------------------------------------------------------------===//
4174 // Division Instructions (ARMv7-A with virtualization extension)
4176 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4177 "sdiv", "\t$Rd, $Rn, $Rm",
4178 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4179 Requires<[IsARM, HasDivideInARM]>;
4181 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4182 "udiv", "\t$Rd, $Rn, $Rm",
4183 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4184 Requires<[IsARM, HasDivideInARM]>;
4186 //===----------------------------------------------------------------------===//
4187 // Misc. Arithmetic Instructions.
4190 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4191 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4192 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4195 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4196 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4197 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4198 Requires<[IsARM, HasV6T2]>,
4201 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4202 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4203 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4206 let AddedComplexity = 5 in
4207 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4208 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4209 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4210 Requires<[IsARM, HasV6]>,
4213 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4214 (REV16 (LDRH addrmode3:$addr))>;
4215 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4216 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4218 let AddedComplexity = 5 in
4219 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4220 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4221 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4222 Requires<[IsARM, HasV6]>,
4225 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4226 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4229 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4230 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4231 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4232 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4233 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4235 Requires<[IsARM, HasV6]>,
4236 Sched<[WriteALUsi, ReadALU]>;
4238 // Alternate cases for PKHBT where identities eliminate some nodes.
4239 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4240 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4241 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4242 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4244 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4245 // will match the pattern below.
4246 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4247 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4248 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4249 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4250 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4252 Requires<[IsARM, HasV6]>,
4253 Sched<[WriteALUsi, ReadALU]>;
4255 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4256 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4257 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4258 // pkhtb src1, src2, asr (17..31).
4259 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4260 (srl GPRnopc:$src2, imm16:$sh)),
4261 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4262 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4263 (sra GPRnopc:$src2, imm16_31:$sh)),
4264 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4265 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4266 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4267 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4269 //===----------------------------------------------------------------------===//
4273 // + CRC32{B,H,W} 0x04C11DB7
4274 // + CRC32C{B,H,W} 0x1EDC6F41
4277 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4278 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4279 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4280 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4281 Requires<[IsARM, HasV8, HasCRC]> {
4286 let Inst{31-28} = 0b1110;
4287 let Inst{27-23} = 0b00010;
4288 let Inst{22-21} = sz;
4290 let Inst{19-16} = Rn;
4291 let Inst{15-12} = Rd;
4292 let Inst{11-10} = 0b00;
4295 let Inst{7-4} = 0b0100;
4298 let Unpredictable{11-8} = 0b1101;
4301 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4302 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4303 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4304 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4305 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4306 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4308 //===----------------------------------------------------------------------===//
4309 // ARMv8.1a Privilege Access Never extension
4313 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4314 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4317 let Inst{31-28} = 0b1111;
4318 let Inst{27-20} = 0b00010001;
4319 let Inst{19-16} = 0b0000;
4320 let Inst{15-10} = 0b000000;
4323 let Inst{7-4} = 0b0000;
4324 let Inst{3-0} = 0b0000;
4326 let Unpredictable{19-16} = 0b1111;
4327 let Unpredictable{15-10} = 0b111111;
4328 let Unpredictable{8} = 0b1;
4329 let Unpredictable{3-0} = 0b1111;
4332 //===----------------------------------------------------------------------===//
4333 // Comparison Instructions...
4336 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4337 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4338 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4340 // ARMcmpZ can re-use the above instruction definitions.
4341 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4342 (CMPri GPR:$src, mod_imm:$imm)>;
4343 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4344 (CMPrr GPR:$src, GPR:$rhs)>;
4345 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4346 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4347 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4348 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4350 // CMN register-integer
4351 let isCompare = 1, Defs = [CPSR] in {
4352 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4353 "cmn", "\t$Rn, $imm",
4354 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4355 Sched<[WriteCMP, ReadALU]> {
4360 let Inst{19-16} = Rn;
4361 let Inst{15-12} = 0b0000;
4362 let Inst{11-0} = imm;
4364 let Unpredictable{15-12} = 0b1111;
4367 // CMN register-register/shift
4368 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4369 "cmn", "\t$Rn, $Rm",
4370 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4371 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4374 let isCommutable = 1;
4377 let Inst{19-16} = Rn;
4378 let Inst{15-12} = 0b0000;
4379 let Inst{11-4} = 0b00000000;
4382 let Unpredictable{15-12} = 0b1111;
4385 def CMNzrsi : AI1<0b1011, (outs),
4386 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4387 "cmn", "\t$Rn, $shift",
4388 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4389 GPR:$Rn, so_reg_imm:$shift)]>,
4390 Sched<[WriteCMPsi, ReadALU]> {
4395 let Inst{19-16} = Rn;
4396 let Inst{15-12} = 0b0000;
4397 let Inst{11-5} = shift{11-5};
4399 let Inst{3-0} = shift{3-0};
4401 let Unpredictable{15-12} = 0b1111;
4404 def CMNzrsr : AI1<0b1011, (outs),
4405 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4406 "cmn", "\t$Rn, $shift",
4407 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4408 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4409 Sched<[WriteCMPsr, ReadALU]> {
4414 let Inst{19-16} = Rn;
4415 let Inst{15-12} = 0b0000;
4416 let Inst{11-8} = shift{11-8};
4418 let Inst{6-5} = shift{6-5};
4420 let Inst{3-0} = shift{3-0};
4422 let Unpredictable{15-12} = 0b1111;
4427 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4428 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4430 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4431 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4433 // Note that TST/TEQ don't set all the same flags that CMP does!
4434 defm TST : AI1_cmp_irs<0b1000, "tst",
4435 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4436 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4437 "DecodeTSTInstruction">;
4438 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4439 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4440 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4442 // Pseudo i64 compares for some floating point compares.
4443 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4445 def BCCi64 : PseudoInst<(outs),
4446 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4448 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4451 def BCCZi64 : PseudoInst<(outs),
4452 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4453 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4455 } // usesCustomInserter
4458 // Conditional moves
4459 let hasSideEffects = 0 in {
4461 let isCommutable = 1, isSelect = 1 in
4462 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4463 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4465 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4467 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4469 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4470 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4473 (ARMcmov GPR:$false, so_reg_imm:$shift,
4475 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4476 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4477 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4479 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4481 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4484 let isMoveImm = 1 in
4486 : ARMPseudoInst<(outs GPR:$Rd),
4487 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4489 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4491 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4494 let isMoveImm = 1 in
4495 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4496 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4498 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4500 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4502 // Two instruction predicate mov immediate.
4503 let isMoveImm = 1 in
4505 : ARMPseudoInst<(outs GPR:$Rd),
4506 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4508 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4510 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4512 let isMoveImm = 1 in
4513 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4514 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4516 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4518 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4523 //===----------------------------------------------------------------------===//
4524 // Atomic operations intrinsics
4527 def MemBarrierOptOperand : AsmOperandClass {
4528 let Name = "MemBarrierOpt";
4529 let ParserMethod = "parseMemBarrierOptOperand";
4531 def memb_opt : Operand<i32> {
4532 let PrintMethod = "printMemBOption";
4533 let ParserMatchClass = MemBarrierOptOperand;
4534 let DecoderMethod = "DecodeMemBarrierOption";
4537 def InstSyncBarrierOptOperand : AsmOperandClass {
4538 let Name = "InstSyncBarrierOpt";
4539 let ParserMethod = "parseInstSyncBarrierOptOperand";
4541 def instsyncb_opt : Operand<i32> {
4542 let PrintMethod = "printInstSyncBOption";
4543 let ParserMatchClass = InstSyncBarrierOptOperand;
4544 let DecoderMethod = "DecodeInstSyncBarrierOption";
4547 // Memory barriers protect the atomic sequences
4548 let hasSideEffects = 1 in {
4549 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4550 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4551 Requires<[IsARM, HasDB]> {
4553 let Inst{31-4} = 0xf57ff05;
4554 let Inst{3-0} = opt;
4557 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4558 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4559 Requires<[IsARM, HasDB]> {
4561 let Inst{31-4} = 0xf57ff04;
4562 let Inst{3-0} = opt;
4565 // ISB has only full system option
4566 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4567 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4568 Requires<[IsARM, HasDB]> {
4570 let Inst{31-4} = 0xf57ff06;
4571 let Inst{3-0} = opt;
4575 let usesCustomInserter = 1, Defs = [CPSR] in {
4577 // Pseudo instruction that combines movs + predicated rsbmi
4578 // to implement integer ABS
4579 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4582 let usesCustomInserter = 1 in {
4583 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4584 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4586 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4589 let hasPostISelHook = 1 in {
4590 def MCOPY : PseudoInst<
4591 (outs GPR:$newdst, GPR:$newsrc), (ins GPR:$dst, GPR:$src, i32imm:$nreg),
4593 [(set GPR:$newdst, GPR:$newsrc, (ARMmcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4596 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4597 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4600 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4601 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4604 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4605 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4608 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4609 (int_arm_strex node:$val, node:$ptr), [{
4610 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4613 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4614 (int_arm_strex node:$val, node:$ptr), [{
4615 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4618 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4619 (int_arm_strex node:$val, node:$ptr), [{
4620 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4623 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4624 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4627 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4628 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4631 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4632 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4635 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4636 (int_arm_stlex node:$val, node:$ptr), [{
4637 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4640 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4641 (int_arm_stlex node:$val, node:$ptr), [{
4642 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4645 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4646 (int_arm_stlex node:$val, node:$ptr), [{
4647 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4650 let mayLoad = 1 in {
4651 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4652 NoItinerary, "ldrexb", "\t$Rt, $addr",
4653 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4654 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4655 NoItinerary, "ldrexh", "\t$Rt, $addr",
4656 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4657 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4658 NoItinerary, "ldrex", "\t$Rt, $addr",
4659 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4660 let hasExtraDefRegAllocReq = 1 in
4661 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4662 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4663 let DecoderMethod = "DecodeDoubleRegLoad";
4666 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4667 NoItinerary, "ldaexb", "\t$Rt, $addr",
4668 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4669 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4670 NoItinerary, "ldaexh", "\t$Rt, $addr",
4671 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4672 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4673 NoItinerary, "ldaex", "\t$Rt, $addr",
4674 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4675 let hasExtraDefRegAllocReq = 1 in
4676 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4677 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4678 let DecoderMethod = "DecodeDoubleRegLoad";
4682 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4683 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4684 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4685 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4686 addr_offset_none:$addr))]>;
4687 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4688 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4689 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4690 addr_offset_none:$addr))]>;
4691 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4692 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4693 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4694 addr_offset_none:$addr))]>;
4695 let hasExtraSrcRegAllocReq = 1 in
4696 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4697 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4698 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4699 let DecoderMethod = "DecodeDoubleRegStore";
4701 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4702 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4704 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4705 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4706 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4708 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4709 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4710 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4712 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4713 let hasExtraSrcRegAllocReq = 1 in
4714 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4715 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4716 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4717 let DecoderMethod = "DecodeDoubleRegStore";
4721 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4723 Requires<[IsARM, HasV7]> {
4724 let Inst{31-0} = 0b11110101011111111111000000011111;
4727 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4728 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4729 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4730 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4732 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4733 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4734 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4735 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4737 class acquiring_load<PatFrag base>
4738 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4739 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4740 return isAtLeastAcquire(Ordering);
4743 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4744 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4745 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4747 class releasing_store<PatFrag base>
4748 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4749 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4750 return isAtLeastRelease(Ordering);
4753 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4754 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4755 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4757 let AddedComplexity = 8 in {
4758 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4759 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4760 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4761 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4762 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4763 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4766 // SWP/SWPB are deprecated in V6/V7.
4767 let mayLoad = 1, mayStore = 1 in {
4768 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4769 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4771 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4772 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4776 //===----------------------------------------------------------------------===//
4777 // Coprocessor Instructions.
4780 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4781 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4782 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4783 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4784 imm:$CRm, imm:$opc2)]>,
4793 let Inst{3-0} = CRm;
4795 let Inst{7-5} = opc2;
4796 let Inst{11-8} = cop;
4797 let Inst{15-12} = CRd;
4798 let Inst{19-16} = CRn;
4799 let Inst{23-20} = opc1;
4802 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4803 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4804 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4805 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4806 imm:$CRm, imm:$opc2)]>,
4808 let Inst{31-28} = 0b1111;
4816 let Inst{3-0} = CRm;
4818 let Inst{7-5} = opc2;
4819 let Inst{11-8} = cop;
4820 let Inst{15-12} = CRd;
4821 let Inst{19-16} = CRn;
4822 let Inst{23-20} = opc1;
4825 class ACI<dag oops, dag iops, string opc, string asm,
4826 IndexMode im = IndexModeNone>
4827 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4829 let Inst{27-25} = 0b110;
4831 class ACInoP<dag oops, dag iops, string opc, string asm,
4832 IndexMode im = IndexModeNone>
4833 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4835 let Inst{31-28} = 0b1111;
4836 let Inst{27-25} = 0b110;
4838 multiclass LdStCop<bit load, bit Dbit, string asm> {
4839 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4840 asm, "\t$cop, $CRd, $addr"> {
4844 let Inst{24} = 1; // P = 1
4845 let Inst{23} = addr{8};
4846 let Inst{22} = Dbit;
4847 let Inst{21} = 0; // W = 0
4848 let Inst{20} = load;
4849 let Inst{19-16} = addr{12-9};
4850 let Inst{15-12} = CRd;
4851 let Inst{11-8} = cop;
4852 let Inst{7-0} = addr{7-0};
4853 let DecoderMethod = "DecodeCopMemInstruction";
4855 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4856 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4860 let Inst{24} = 1; // P = 1
4861 let Inst{23} = addr{8};
4862 let Inst{22} = Dbit;
4863 let Inst{21} = 1; // W = 1
4864 let Inst{20} = load;
4865 let Inst{19-16} = addr{12-9};
4866 let Inst{15-12} = CRd;
4867 let Inst{11-8} = cop;
4868 let Inst{7-0} = addr{7-0};
4869 let DecoderMethod = "DecodeCopMemInstruction";
4871 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4872 postidx_imm8s4:$offset),
4873 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4878 let Inst{24} = 0; // P = 0
4879 let Inst{23} = offset{8};
4880 let Inst{22} = Dbit;
4881 let Inst{21} = 1; // W = 1
4882 let Inst{20} = load;
4883 let Inst{19-16} = addr;
4884 let Inst{15-12} = CRd;
4885 let Inst{11-8} = cop;
4886 let Inst{7-0} = offset{7-0};
4887 let DecoderMethod = "DecodeCopMemInstruction";
4889 def _OPTION : ACI<(outs),
4890 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4891 coproc_option_imm:$option),
4892 asm, "\t$cop, $CRd, $addr, $option"> {
4897 let Inst{24} = 0; // P = 0
4898 let Inst{23} = 1; // U = 1
4899 let Inst{22} = Dbit;
4900 let Inst{21} = 0; // W = 0
4901 let Inst{20} = load;
4902 let Inst{19-16} = addr;
4903 let Inst{15-12} = CRd;
4904 let Inst{11-8} = cop;
4905 let Inst{7-0} = option;
4906 let DecoderMethod = "DecodeCopMemInstruction";
4909 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4910 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4911 asm, "\t$cop, $CRd, $addr"> {
4915 let Inst{24} = 1; // P = 1
4916 let Inst{23} = addr{8};
4917 let Inst{22} = Dbit;
4918 let Inst{21} = 0; // W = 0
4919 let Inst{20} = load;
4920 let Inst{19-16} = addr{12-9};
4921 let Inst{15-12} = CRd;
4922 let Inst{11-8} = cop;
4923 let Inst{7-0} = addr{7-0};
4924 let DecoderMethod = "DecodeCopMemInstruction";
4926 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4927 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4931 let Inst{24} = 1; // P = 1
4932 let Inst{23} = addr{8};
4933 let Inst{22} = Dbit;
4934 let Inst{21} = 1; // W = 1
4935 let Inst{20} = load;
4936 let Inst{19-16} = addr{12-9};
4937 let Inst{15-12} = CRd;
4938 let Inst{11-8} = cop;
4939 let Inst{7-0} = addr{7-0};
4940 let DecoderMethod = "DecodeCopMemInstruction";
4942 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4943 postidx_imm8s4:$offset),
4944 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4949 let Inst{24} = 0; // P = 0
4950 let Inst{23} = offset{8};
4951 let Inst{22} = Dbit;
4952 let Inst{21} = 1; // W = 1
4953 let Inst{20} = load;
4954 let Inst{19-16} = addr;
4955 let Inst{15-12} = CRd;
4956 let Inst{11-8} = cop;
4957 let Inst{7-0} = offset{7-0};
4958 let DecoderMethod = "DecodeCopMemInstruction";
4960 def _OPTION : ACInoP<(outs),
4961 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4962 coproc_option_imm:$option),
4963 asm, "\t$cop, $CRd, $addr, $option"> {
4968 let Inst{24} = 0; // P = 0
4969 let Inst{23} = 1; // U = 1
4970 let Inst{22} = Dbit;
4971 let Inst{21} = 0; // W = 0
4972 let Inst{20} = load;
4973 let Inst{19-16} = addr;
4974 let Inst{15-12} = CRd;
4975 let Inst{11-8} = cop;
4976 let Inst{7-0} = option;
4977 let DecoderMethod = "DecodeCopMemInstruction";
4981 defm LDC : LdStCop <1, 0, "ldc">;
4982 defm LDCL : LdStCop <1, 1, "ldcl">;
4983 defm STC : LdStCop <0, 0, "stc">;
4984 defm STCL : LdStCop <0, 1, "stcl">;
4985 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4986 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4987 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4988 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4990 //===----------------------------------------------------------------------===//
4991 // Move between coprocessor and ARM core register.
4994 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4996 : ABI<0b1110, oops, iops, NoItinerary, opc,
4997 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4998 let Inst{20} = direction;
5008 let Inst{15-12} = Rt;
5009 let Inst{11-8} = cop;
5010 let Inst{23-21} = opc1;
5011 let Inst{7-5} = opc2;
5012 let Inst{3-0} = CRm;
5013 let Inst{19-16} = CRn;
5016 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5018 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5019 c_imm:$CRm, imm0_7:$opc2),
5020 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5021 imm:$CRm, imm:$opc2)]>,
5022 ComplexDeprecationPredicate<"MCR">;
5023 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5024 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5025 c_imm:$CRm, 0, pred:$p)>;
5026 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5027 (outs GPRwithAPSR:$Rt),
5028 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5030 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5031 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5032 c_imm:$CRm, 0, pred:$p)>;
5034 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5035 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5037 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5039 : ABXI<0b1110, oops, iops, NoItinerary,
5040 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5041 let Inst{31-24} = 0b11111110;
5042 let Inst{20} = direction;
5052 let Inst{15-12} = Rt;
5053 let Inst{11-8} = cop;
5054 let Inst{23-21} = opc1;
5055 let Inst{7-5} = opc2;
5056 let Inst{3-0} = CRm;
5057 let Inst{19-16} = CRn;
5060 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5062 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5063 c_imm:$CRm, imm0_7:$opc2),
5064 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5065 imm:$CRm, imm:$opc2)]>,
5067 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5068 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5070 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5071 (outs GPRwithAPSR:$Rt),
5072 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5075 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5076 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5079 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5080 imm:$CRm, imm:$opc2),
5081 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5083 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
5084 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5085 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
5086 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
5087 let Inst{23-21} = 0b010;
5088 let Inst{20} = direction;
5096 let Inst{15-12} = Rt;
5097 let Inst{19-16} = Rt2;
5098 let Inst{11-8} = cop;
5099 let Inst{7-4} = opc1;
5100 let Inst{3-0} = CRm;
5103 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5104 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5105 GPRnopc:$Rt2, imm:$CRm)]>;
5106 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
5108 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5109 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5110 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5111 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5113 let Inst{31-28} = 0b1111;
5114 let Inst{23-21} = 0b010;
5115 let Inst{20} = direction;
5123 let Inst{15-12} = Rt;
5124 let Inst{19-16} = Rt2;
5125 let Inst{11-8} = cop;
5126 let Inst{7-4} = opc1;
5127 let Inst{3-0} = CRm;
5129 let DecoderMethod = "DecodeMRRC2";
5132 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5133 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5134 GPRnopc:$Rt2, imm:$CRm)]>;
5135 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5137 //===----------------------------------------------------------------------===//
5138 // Move between special register and ARM core register
5141 // Move to ARM core register from Special Register
5142 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5143 "mrs", "\t$Rd, apsr", []> {
5145 let Inst{23-16} = 0b00001111;
5146 let Unpredictable{19-17} = 0b111;
5148 let Inst{15-12} = Rd;
5150 let Inst{11-0} = 0b000000000000;
5151 let Unpredictable{11-0} = 0b110100001111;
5154 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5157 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5158 // section B9.3.9, with the R bit set to 1.
5159 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5160 "mrs", "\t$Rd, spsr", []> {
5162 let Inst{23-16} = 0b01001111;
5163 let Unpredictable{19-16} = 0b1111;
5165 let Inst{15-12} = Rd;
5167 let Inst{11-0} = 0b000000000000;
5168 let Unpredictable{11-0} = 0b110100001111;
5171 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5172 // separate encoding (distinguished by bit 5.
5173 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5174 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5175 Requires<[IsARM, HasVirtualization]> {
5180 let Inst{22} = banked{5}; // R bit
5181 let Inst{21-20} = 0b00;
5182 let Inst{19-16} = banked{3-0};
5183 let Inst{15-12} = Rd;
5184 let Inst{11-9} = 0b001;
5185 let Inst{8} = banked{4};
5186 let Inst{7-0} = 0b00000000;
5189 // Move from ARM core register to Special Register
5191 // No need to have both system and application versions of MSR (immediate) or
5192 // MSR (register), the encodings are the same and the assembly parser has no way
5193 // to distinguish between them. The mask operand contains the special register
5194 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5195 // accessed in the special register.
5196 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5197 "msr", "\t$mask, $Rn", []> {
5202 let Inst{22} = mask{4}; // R bit
5203 let Inst{21-20} = 0b10;
5204 let Inst{19-16} = mask{3-0};
5205 let Inst{15-12} = 0b1111;
5206 let Inst{11-4} = 0b00000000;
5210 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5211 "msr", "\t$mask, $imm", []> {
5216 let Inst{22} = mask{4}; // R bit
5217 let Inst{21-20} = 0b10;
5218 let Inst{19-16} = mask{3-0};
5219 let Inst{15-12} = 0b1111;
5220 let Inst{11-0} = imm;
5223 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5224 // separate encoding (distinguished by bit 5.
5225 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5226 NoItinerary, "msr", "\t$banked, $Rn", []>,
5227 Requires<[IsARM, HasVirtualization]> {
5232 let Inst{22} = banked{5}; // R bit
5233 let Inst{21-20} = 0b10;
5234 let Inst{19-16} = banked{3-0};
5235 let Inst{15-12} = 0b1111;
5236 let Inst{11-9} = 0b001;
5237 let Inst{8} = banked{4};
5238 let Inst{7-4} = 0b0000;
5242 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5243 // are needed to probe the stack when allocating more than
5244 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5245 // ensure that the guard pages used by the OS virtual memory manager are
5246 // allocated in correct sequence.
5247 // The main point of having separate instruction are extra unmodelled effects
5248 // (compared to ordinary calls) like stack pointer change.
5250 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5251 [SDNPHasChain, SDNPSideEffect]>;
5252 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5253 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5255 //===----------------------------------------------------------------------===//
5259 // __aeabi_read_tp preserves the registers r1-r3.
5260 // This is a pseudo inst so that we can get the encoding right,
5261 // complete with fixup for the aeabi_read_tp function.
5262 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5263 // is defined in "ARMInstrThumb.td".
5265 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5266 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5267 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5270 //===----------------------------------------------------------------------===//
5271 // SJLJ Exception handling intrinsics
5272 // eh_sjlj_setjmp() is an instruction sequence to store the return
5273 // address and save #0 in R0 for the non-longjmp case.
5274 // Since by its nature we may be coming from some other function to get
5275 // here, and we're using the stack frame for the containing function to
5276 // save/restore registers, we can't keep anything live in regs across
5277 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5278 // when we get here from a longjmp(). We force everything out of registers
5279 // except for our own input by listing the relevant registers in Defs. By
5280 // doing so, we also cause the prologue/epilogue code to actively preserve
5281 // all of the callee-saved resgisters, which is exactly what we want.
5282 // A constant value is passed in $val, and we use the location as a scratch.
5284 // These are pseudo-instructions and are lowered to individual MC-insts, so
5285 // no encoding information is necessary.
5287 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5288 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5289 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5290 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5292 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5293 Requires<[IsARM, HasVFP2]>;
5297 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5298 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5299 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5301 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5302 Requires<[IsARM, NoVFP]>;
5305 // FIXME: Non-IOS version(s)
5306 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5307 Defs = [ R7, LR, SP ] in {
5308 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5310 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5314 // eh.sjlj.dispatchsetup pseudo-instruction.
5315 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5316 // the pseudo is expanded (which happens before any passes that need the
5317 // instruction size).
5318 let isBarrier = 1 in
5319 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5322 //===----------------------------------------------------------------------===//
5323 // Non-Instruction Patterns
5326 // ARMv4 indirect branch using (MOVr PC, dst)
5327 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5328 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5329 4, IIC_Br, [(brind GPR:$dst)],
5330 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5331 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5333 // Large immediate handling.
5335 // 32-bit immediate using two piece mod_imms or movw + movt.
5336 // This is a single pseudo instruction, the benefit is that it can be remat'd
5337 // as a single unit instead of having to handle reg inputs.
5338 // FIXME: Remove this when we can do generalized remat.
5339 let isReMaterializable = 1, isMoveImm = 1 in
5340 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5341 [(set GPR:$dst, (arm_i32imm:$src))]>,
5344 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5345 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5346 Requires<[IsARM, DontUseMovt]>;
5348 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5349 // It also makes it possible to rematerialize the instructions.
5350 // FIXME: Remove this when we can do generalized remat and when machine licm
5351 // can properly the instructions.
5352 let isReMaterializable = 1 in {
5353 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5355 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5356 Requires<[IsARM, UseMovt]>;
5358 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5361 (ARMWrapperPIC tglobaladdr:$addr))]>,
5362 Requires<[IsARM, DontUseMovt]>;
5364 let AddedComplexity = 10 in
5365 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5368 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5369 Requires<[IsARM, DontUseMovt]>;
5371 let AddedComplexity = 10 in
5372 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5374 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5375 Requires<[IsARM, UseMovt]>;
5376 } // isReMaterializable
5378 // ConstantPool, GlobalAddress, and JumpTable
5379 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5380 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5381 Requires<[IsARM, UseMovt]>;
5382 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5383 (LEApcrelJT tjumptable:$dst)>;
5385 // TODO: add,sub,and, 3-instr forms?
5387 // Tail calls. These patterns also apply to Thumb mode.
5388 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5389 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5390 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5393 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5394 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5395 (BMOVPCB_CALL texternalsym:$func)>;
5397 // zextload i1 -> zextload i8
5398 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5399 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5401 // extload -> zextload
5402 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5403 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5404 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5405 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5407 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5409 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5410 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5413 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5414 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5415 (SMULBB GPR:$a, GPR:$b)>;
5416 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5417 (SMULBB GPR:$a, GPR:$b)>;
5418 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5419 (sra GPR:$b, (i32 16))),
5420 (SMULBT GPR:$a, GPR:$b)>;
5421 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5422 (SMULBT GPR:$a, GPR:$b)>;
5423 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5424 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5425 (SMULTB GPR:$a, GPR:$b)>;
5426 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5427 (SMULTB GPR:$a, GPR:$b)>;
5429 def : ARMV5MOPat<(add GPR:$acc,
5430 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5431 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5432 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5433 def : ARMV5MOPat<(add GPR:$acc,
5434 (mul sext_16_node:$a, sext_16_node:$b)),
5435 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5436 def : ARMV5MOPat<(add GPR:$acc,
5437 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5438 (sra GPR:$b, (i32 16)))),
5439 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5440 def : ARMV5MOPat<(add GPR:$acc,
5441 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5442 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5443 def : ARMV5MOPat<(add GPR:$acc,
5444 (mul (sra GPR:$a, (i32 16)),
5445 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5446 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5447 def : ARMV5MOPat<(add GPR:$acc,
5448 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5449 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5452 // Pre-v7 uses MCR for synchronization barriers.
5453 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5454 Requires<[IsARM, HasV6]>;
5456 // SXT/UXT with no rotate
5457 let AddedComplexity = 16 in {
5458 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5459 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5460 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5461 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5462 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5463 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5464 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5467 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5468 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5470 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5471 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5472 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5473 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5475 // Atomic load/store patterns
5476 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5477 (LDRBrs ldst_so_reg:$src)>;
5478 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5479 (LDRBi12 addrmode_imm12:$src)>;
5480 def : ARMPat<(atomic_load_16 addrmode3:$src),
5481 (LDRH addrmode3:$src)>;
5482 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5483 (LDRrs ldst_so_reg:$src)>;
5484 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5485 (LDRi12 addrmode_imm12:$src)>;
5486 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5487 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5488 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5489 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5490 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5491 (STRH GPR:$val, addrmode3:$ptr)>;
5492 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5493 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5494 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5495 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5498 //===----------------------------------------------------------------------===//
5502 include "ARMInstrThumb.td"
5504 //===----------------------------------------------------------------------===//
5508 include "ARMInstrThumb2.td"
5510 //===----------------------------------------------------------------------===//
5511 // Floating Point Support
5514 include "ARMInstrVFP.td"
5516 //===----------------------------------------------------------------------===//
5517 // Advanced SIMD (NEON) Support
5520 include "ARMInstrNEON.td"
5522 //===----------------------------------------------------------------------===//
5523 // Assembler aliases
5527 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5528 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5529 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5531 // System instructions
5532 def : MnemonicAlias<"swi", "svc">;
5534 // Load / Store Multiple
5535 def : MnemonicAlias<"ldmfd", "ldm">;
5536 def : MnemonicAlias<"ldmia", "ldm">;
5537 def : MnemonicAlias<"ldmea", "ldmdb">;
5538 def : MnemonicAlias<"stmfd", "stmdb">;
5539 def : MnemonicAlias<"stmia", "stm">;
5540 def : MnemonicAlias<"stmea", "stm">;
5542 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5543 // shift amount is zero (i.e., unspecified).
5544 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5545 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5546 Requires<[IsARM, HasV6]>;
5547 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5548 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5549 Requires<[IsARM, HasV6]>;
5551 // PUSH/POP aliases for STM/LDM
5552 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5553 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5555 // SSAT/USAT optional shift operand.
5556 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5557 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5558 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5559 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5562 // Extend instruction optional rotate operand.
5563 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5564 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5565 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5566 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5567 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5568 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5569 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5570 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5571 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5572 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5573 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5574 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5576 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5577 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5578 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5579 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5580 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5581 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5582 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5583 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5584 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5585 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5586 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5587 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5591 def : MnemonicAlias<"rfefa", "rfeda">;
5592 def : MnemonicAlias<"rfeea", "rfedb">;
5593 def : MnemonicAlias<"rfefd", "rfeia">;
5594 def : MnemonicAlias<"rfeed", "rfeib">;
5595 def : MnemonicAlias<"rfe", "rfeia">;
5598 def : MnemonicAlias<"srsfa", "srsib">;
5599 def : MnemonicAlias<"srsea", "srsia">;
5600 def : MnemonicAlias<"srsfd", "srsdb">;
5601 def : MnemonicAlias<"srsed", "srsda">;
5602 def : MnemonicAlias<"srs", "srsia">;
5605 def : MnemonicAlias<"qsubaddx", "qsax">;
5607 def : MnemonicAlias<"saddsubx", "sasx">;
5608 // SHASX == SHADDSUBX
5609 def : MnemonicAlias<"shaddsubx", "shasx">;
5610 // SHSAX == SHSUBADDX
5611 def : MnemonicAlias<"shsubaddx", "shsax">;
5613 def : MnemonicAlias<"ssubaddx", "ssax">;
5615 def : MnemonicAlias<"uaddsubx", "uasx">;
5616 // UHASX == UHADDSUBX
5617 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5618 // UHSAX == UHSUBADDX
5619 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5620 // UQASX == UQADDSUBX
5621 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5622 // UQSAX == UQSUBADDX
5623 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5625 def : MnemonicAlias<"usubaddx", "usax">;
5627 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5629 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5630 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5631 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5632 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5633 // Same for AND <--> BIC
5634 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5635 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5636 pred:$p, cc_out:$s)>;
5637 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5638 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5639 pred:$p, cc_out:$s)>;
5640 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5641 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5642 pred:$p, cc_out:$s)>;
5643 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5644 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5645 pred:$p, cc_out:$s)>;
5647 // Likewise, "add Rd, mod_imm_neg" -> sub
5648 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5649 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5650 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5651 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5652 // Same for CMP <--> CMN via mod_imm_neg
5653 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5654 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5655 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5656 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5658 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5659 // LSR, ROR, and RRX instructions.
5660 // FIXME: We need C++ parser hooks to map the alias to the MOV
5661 // encoding. It seems we should be able to do that sort of thing
5662 // in tblgen, but it could get ugly.
5663 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5664 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5665 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5667 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5668 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5670 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5671 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5673 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5674 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5677 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5678 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5679 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5680 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5681 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5683 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5684 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5686 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5687 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5689 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5690 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5694 // "neg" is and alias for "rsb rd, rn, #0"
5695 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5696 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5698 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5699 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5700 Requires<[IsARM, NoV6]>;
5702 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5703 // the instruction definitions need difference constraints pre-v6.
5704 // Use these aliases for the assembly parsing on pre-v6.
5705 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5706 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5707 Requires<[IsARM, NoV6]>;
5708 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5709 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5710 pred:$p, cc_out:$s)>,
5711 Requires<[IsARM, NoV6]>;
5712 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5713 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5714 Requires<[IsARM, NoV6]>;
5715 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5716 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5717 Requires<[IsARM, NoV6]>;
5718 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5719 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5720 Requires<[IsARM, NoV6]>;
5721 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5722 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5723 Requires<[IsARM, NoV6]>;
5725 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5727 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5728 ComplexDeprecationPredicate<"IT">;
5730 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5731 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5733 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;