1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 string EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 //===----------------------------------------------------------------------===//
273 // Operand Definitions.
277 def brtarget : Operand<OtherVT>;
279 // A list of registers separated by comma. Used by load/store multiple.
280 def reglist : Operand<i32> {
281 string EncoderMethod = "getRegisterListOpValue";
282 let PrintMethod = "printRegisterList";
285 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
286 def cpinst_operand : Operand<i32> {
287 let PrintMethod = "printCPInstOperand";
290 def jtblock_operand : Operand<i32> {
291 let PrintMethod = "printJTBlockOperand";
293 def jt2block_operand : Operand<i32> {
294 let PrintMethod = "printJT2BlockOperand";
298 def pclabel : Operand<i32> {
299 let PrintMethod = "printPCLabel";
302 def neon_vcvt_imm32 : Operand<i32> {
303 string EncoderMethod = "getNEONVcvtImm32OpValue";
306 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
307 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
308 int32_t v = (int32_t)N->getZExtValue();
309 return v == 8 || v == 16 || v == 24; }]> {
310 string EncoderMethod = "getRotImmOpValue";
313 // shift_imm: An integer that encodes a shift amount and the type of shift
314 // (currently either asr or lsl) using the same encoding used for the
315 // immediates in so_reg operands.
316 def shift_imm : Operand<i32> {
317 let PrintMethod = "printShiftImmOperand";
320 // shifter_operand operands: so_reg and so_imm.
321 def so_reg : Operand<i32>, // reg reg imm
322 ComplexPattern<i32, 3, "SelectShifterOperandReg",
323 [shl,srl,sra,rotr]> {
324 string EncoderMethod = "getSORegOpValue";
325 let PrintMethod = "printSORegOperand";
326 let MIOperandInfo = (ops GPR, GPR, i32imm);
328 def shift_so_reg : Operand<i32>, // reg reg imm
329 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
330 [shl,srl,sra,rotr]> {
331 string EncoderMethod = "getSORegOpValue";
332 let PrintMethod = "printSORegOperand";
333 let MIOperandInfo = (ops GPR, GPR, i32imm);
336 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
337 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
338 // represented in the imm field in the same 12-bit form that they are encoded
339 // into so_imm instructions: the 8-bit immediate is the least significant bits
340 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
341 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
342 string EncoderMethod = "getSOImmOpValue";
343 let PrintMethod = "printSOImmOperand";
346 // Break so_imm's up into two pieces. This handles immediates with up to 16
347 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
348 // get the first/second pieces.
349 def so_imm2part : Operand<i32>,
351 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
353 let PrintMethod = "printSOImm2PartOperand";
356 def so_imm2part_1 : SDNodeXForm<imm, [{
357 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
358 return CurDAG->getTargetConstant(V, MVT::i32);
361 def so_imm2part_2 : SDNodeXForm<imm, [{
362 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
363 return CurDAG->getTargetConstant(V, MVT::i32);
366 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
367 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
369 let PrintMethod = "printSOImm2PartOperand";
372 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
373 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
374 return CurDAG->getTargetConstant(V, MVT::i32);
377 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
378 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
379 return CurDAG->getTargetConstant(V, MVT::i32);
382 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
383 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
384 return (int32_t)N->getZExtValue() < 32;
387 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
388 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
389 return (int32_t)N->getZExtValue() < 32;
391 string EncoderMethod = "getImmMinusOneOpValue";
394 // Define ARM specific addressing modes.
397 // addrmode_imm12 := reg +/- imm12
399 def addrmode_imm12 : Operand<i32>,
400 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
401 // 12-bit immediate operand. Note that instructions using this encode
402 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
403 // immediate values are as normal.
405 string EncoderMethod = "getAddrModeImm12OpValue";
406 let PrintMethod = "printAddrModeImm12Operand";
407 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
409 // ldst_so_reg := reg +/- reg shop imm
411 def ldst_so_reg : Operand<i32>,
412 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
413 // FIXME: Simplify the printer
414 // FIXME: Add EncoderMethod for this addressing mode
415 let PrintMethod = "printAddrMode2Operand";
416 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
419 // addrmode2 := reg +/- imm12
420 // := reg +/- reg shop imm
422 def addrmode2 : Operand<i32>,
423 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
424 let PrintMethod = "printAddrMode2Operand";
425 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
428 def am2offset : Operand<i32>,
429 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
430 [], [SDNPWantRoot]> {
431 let PrintMethod = "printAddrMode2OffsetOperand";
432 let MIOperandInfo = (ops GPR, i32imm);
435 // addrmode3 := reg +/- reg
436 // addrmode3 := reg +/- imm8
438 def addrmode3 : Operand<i32>,
439 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
440 let PrintMethod = "printAddrMode3Operand";
441 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
444 def am3offset : Operand<i32>,
445 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
446 [], [SDNPWantRoot]> {
447 let PrintMethod = "printAddrMode3OffsetOperand";
448 let MIOperandInfo = (ops GPR, i32imm);
451 // ldstm_mode := {ia, ib, da, db}
453 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
454 let PrintMethod = "printLdStmModeOperand";
457 def ARMMemMode5AsmOperand : AsmOperandClass {
458 let Name = "MemMode5";
459 let SuperClasses = [];
462 // addrmode5 := reg +/- imm8*4
464 def addrmode5 : Operand<i32>,
465 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
466 let PrintMethod = "printAddrMode5Operand";
467 let MIOperandInfo = (ops GPR:$base, i32imm);
468 let ParserMatchClass = ARMMemMode5AsmOperand;
469 string EncoderMethod = "getAddrMode5OpValue";
472 // addrmode6 := reg with optional writeback
474 def addrmode6 : Operand<i32>,
475 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
476 let PrintMethod = "printAddrMode6Operand";
477 let MIOperandInfo = (ops GPR:$addr, i32imm);
478 string EncoderMethod = "getAddrMode6AddressOpValue";
481 def am6offset : Operand<i32> {
482 let PrintMethod = "printAddrMode6OffsetOperand";
483 let MIOperandInfo = (ops GPR);
484 string EncoderMethod = "getAddrMode6OffsetOpValue";
487 // addrmodepc := pc + reg
489 def addrmodepc : Operand<i32>,
490 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
491 let PrintMethod = "printAddrModePCOperand";
492 let MIOperandInfo = (ops GPR, i32imm);
495 def nohash_imm : Operand<i32> {
496 let PrintMethod = "printNoHashImmediate";
499 //===----------------------------------------------------------------------===//
501 include "ARMInstrFormats.td"
503 //===----------------------------------------------------------------------===//
504 // Multiclass helpers...
507 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
508 /// binop that produces a value.
509 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
510 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
511 PatFrag opnode, bit Commutable = 0> {
512 // The register-immediate version is re-materializable. This is useful
513 // in particular for taking the address of a local.
514 let isReMaterializable = 1 in {
515 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
516 iii, opc, "\t$Rd, $Rn, $imm",
517 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
522 let Inst{19-16} = Rn;
523 let Inst{15-12} = Rd;
524 let Inst{11-0} = imm;
527 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
528 iir, opc, "\t$Rd, $Rn, $Rm",
529 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
534 let isCommutable = Commutable;
535 let Inst{19-16} = Rn;
536 let Inst{15-12} = Rd;
537 let Inst{11-4} = 0b00000000;
540 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
541 iis, opc, "\t$Rd, $Rn, $shift",
542 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
547 let Inst{19-16} = Rn;
548 let Inst{15-12} = Rd;
549 let Inst{11-0} = shift;
553 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
554 /// instruction modifies the CPSR register.
555 let Defs = [CPSR] in {
556 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
557 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
558 PatFrag opnode, bit Commutable = 0> {
559 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
560 iii, opc, "\t$Rd, $Rn, $imm",
561 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
567 let Inst{19-16} = Rn;
568 let Inst{15-12} = Rd;
569 let Inst{11-0} = imm;
571 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
572 iir, opc, "\t$Rd, $Rn, $Rm",
573 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
577 let isCommutable = Commutable;
580 let Inst{19-16} = Rn;
581 let Inst{15-12} = Rd;
582 let Inst{11-4} = 0b00000000;
585 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
586 iis, opc, "\t$Rd, $Rn, $shift",
587 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
593 let Inst{19-16} = Rn;
594 let Inst{15-12} = Rd;
595 let Inst{11-0} = shift;
600 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
601 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
602 /// a explicit result, only implicitly set CPSR.
603 let isCompare = 1, Defs = [CPSR] in {
604 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
605 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
606 PatFrag opnode, bit Commutable = 0> {
607 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
609 [(opnode GPR:$Rn, so_imm:$imm)]> {
614 let Inst{19-16} = Rn;
615 let Inst{15-12} = 0b0000;
616 let Inst{11-0} = imm;
618 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
620 [(opnode GPR:$Rn, GPR:$Rm)]> {
623 let isCommutable = Commutable;
626 let Inst{19-16} = Rn;
627 let Inst{15-12} = 0b0000;
628 let Inst{11-4} = 0b00000000;
631 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
632 opc, "\t$Rn, $shift",
633 [(opnode GPR:$Rn, so_reg:$shift)]> {
638 let Inst{19-16} = Rn;
639 let Inst{15-12} = 0b0000;
640 let Inst{11-0} = shift;
645 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
646 /// register and one whose operand is a register rotated by 8/16/24.
647 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
648 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
649 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
650 IIC_iEXTr, opc, "\t$Rd, $Rm",
651 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
652 Requires<[IsARM, HasV6]> {
655 let Inst{19-16} = 0b1111;
656 let Inst{15-12} = Rd;
657 let Inst{11-10} = 0b00;
660 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
661 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
662 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
663 Requires<[IsARM, HasV6]> {
667 let Inst{19-16} = 0b1111;
668 let Inst{15-12} = Rd;
669 let Inst{11-10} = rot;
674 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
675 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
676 IIC_iEXTr, opc, "\t$Rd, $Rm",
677 [/* For disassembly only; pattern left blank */]>,
678 Requires<[IsARM, HasV6]> {
679 let Inst{19-16} = 0b1111;
680 let Inst{11-10} = 0b00;
682 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
683 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
684 [/* For disassembly only; pattern left blank */]>,
685 Requires<[IsARM, HasV6]> {
687 let Inst{19-16} = 0b1111;
688 let Inst{11-10} = rot;
692 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
693 /// register and one whose operand is a register rotated by 8/16/24.
694 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
695 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
696 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
697 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
698 Requires<[IsARM, HasV6]> {
699 let Inst{11-10} = 0b00;
701 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
703 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
704 [(set GPR:$Rd, (opnode GPR:$Rn,
705 (rotr GPR:$Rm, rot_imm:$rot)))]>,
706 Requires<[IsARM, HasV6]> {
709 let Inst{19-16} = Rn;
710 let Inst{11-10} = rot;
714 // For disassembly only.
715 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
716 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
717 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
718 [/* For disassembly only; pattern left blank */]>,
719 Requires<[IsARM, HasV6]> {
720 let Inst{11-10} = 0b00;
722 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
724 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
725 [/* For disassembly only; pattern left blank */]>,
726 Requires<[IsARM, HasV6]> {
729 let Inst{19-16} = Rn;
730 let Inst{11-10} = rot;
734 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
735 let Uses = [CPSR] in {
736 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
737 bit Commutable = 0> {
738 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
739 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
740 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
746 let Inst{15-12} = Rd;
747 let Inst{19-16} = Rn;
748 let Inst{11-0} = imm;
750 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
751 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
752 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
757 let Inst{11-4} = 0b00000000;
759 let isCommutable = Commutable;
761 let Inst{15-12} = Rd;
762 let Inst{19-16} = Rn;
764 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
765 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
766 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
772 let Inst{11-0} = shift;
773 let Inst{15-12} = Rd;
774 let Inst{19-16} = Rn;
777 // Carry setting variants
778 let Defs = [CPSR] in {
779 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
780 bit Commutable = 0> {
781 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
782 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
783 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
788 let Inst{15-12} = Rd;
789 let Inst{19-16} = Rn;
790 let Inst{11-0} = imm;
794 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
795 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
796 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
801 let Inst{11-4} = 0b00000000;
802 let isCommutable = Commutable;
804 let Inst{15-12} = Rd;
805 let Inst{19-16} = Rn;
809 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
810 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
811 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
816 let Inst{11-0} = shift;
817 let Inst{15-12} = Rd;
818 let Inst{19-16} = Rn;
826 let canFoldAsLoad = 1, isReMaterializable = 1 in {
827 multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
828 InstrItinClass iir, PatFrag opnode> {
829 // Note: We use the complex addrmode_imm12 rather than just an input
830 // GPR and a constrained immediate so that we can use this to match
831 // frame index references and avoid matching constant pool references.
832 def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
833 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
834 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
837 let Inst{23} = addr{12}; // U (add = ('U' == 1))
838 let Inst{19-16} = addr{16-13}; // Rn
839 let Inst{15-12} = Rt;
840 let Inst{11-0} = addr{11-0}; // imm12
842 def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
843 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
844 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
847 let Inst{23} = shift{12}; // U (add = ('U' == 1))
848 let Inst{19-16} = shift{16-13}; // Rn
849 let Inst{11-0} = shift{11-0};
854 multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
855 InstrItinClass iir, PatFrag opnode> {
856 // Note: We use the complex addrmode_imm12 rather than just an input
857 // GPR and a constrained immediate so that we can use this to match
858 // frame index references and avoid matching constant pool references.
859 def i12 : AIldst1<0b010, opc22, 0, (outs),
860 (ins GPR:$Rt, addrmode_imm12:$addr),
861 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
862 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
865 let Inst{23} = addr{12}; // U (add = ('U' == 1))
866 let Inst{19-16} = addr{16-13}; // Rn
867 let Inst{15-12} = Rt;
868 let Inst{11-0} = addr{11-0}; // imm12
870 def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
871 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
872 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
875 let Inst{23} = shift{12}; // U (add = ('U' == 1))
876 let Inst{19-16} = shift{16-13}; // Rn
877 let Inst{11-0} = shift{11-0};
880 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
884 //===----------------------------------------------------------------------===//
885 // Miscellaneous Instructions.
888 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
889 /// the function. The first operand is the ID# for this instruction, the second
890 /// is the index into the MachineConstantPool that this is, the third is the
891 /// size in bytes of this constant pool entry.
892 let neverHasSideEffects = 1, isNotDuplicable = 1 in
893 def CONSTPOOL_ENTRY :
894 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
895 i32imm:$size), NoItinerary, "", []>;
897 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
898 // from removing one half of the matched pairs. That breaks PEI, which assumes
899 // these will always be in pairs, and asserts if it finds otherwise. Better way?
900 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
902 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, "",
903 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
905 def ADJCALLSTACKDOWN :
906 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, "",
907 [(ARMcallseq_start timm:$amt)]>;
910 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
911 [/* For disassembly only; pattern left blank */]>,
912 Requires<[IsARM, HasV6T2]> {
913 let Inst{27-16} = 0b001100100000;
914 let Inst{15-8} = 0b11110000;
915 let Inst{7-0} = 0b00000000;
918 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
919 [/* For disassembly only; pattern left blank */]>,
920 Requires<[IsARM, HasV6T2]> {
921 let Inst{27-16} = 0b001100100000;
922 let Inst{15-8} = 0b11110000;
923 let Inst{7-0} = 0b00000001;
926 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
927 [/* For disassembly only; pattern left blank */]>,
928 Requires<[IsARM, HasV6T2]> {
929 let Inst{27-16} = 0b001100100000;
930 let Inst{15-8} = 0b11110000;
931 let Inst{7-0} = 0b00000010;
934 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
935 [/* For disassembly only; pattern left blank */]>,
936 Requires<[IsARM, HasV6T2]> {
937 let Inst{27-16} = 0b001100100000;
938 let Inst{15-8} = 0b11110000;
939 let Inst{7-0} = 0b00000011;
942 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
944 [/* For disassembly only; pattern left blank */]>,
945 Requires<[IsARM, HasV6]> {
950 let Inst{15-12} = Rd;
951 let Inst{19-16} = Rn;
952 let Inst{27-20} = 0b01101000;
953 let Inst{7-4} = 0b1011;
954 let Inst{11-8} = 0b1111;
957 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
958 [/* For disassembly only; pattern left blank */]>,
959 Requires<[IsARM, HasV6T2]> {
960 let Inst{27-16} = 0b001100100000;
961 let Inst{15-8} = 0b11110000;
962 let Inst{7-0} = 0b00000100;
965 // The i32imm operand $val can be used by a debugger to store more information
966 // about the breakpoint.
967 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
968 [/* For disassembly only; pattern left blank */]>,
971 let Inst{3-0} = val{3-0};
972 let Inst{19-8} = val{15-4};
973 let Inst{27-20} = 0b00010010;
974 let Inst{7-4} = 0b0111;
977 // Change Processor State is a system instruction -- for disassembly only.
978 // The singleton $opt operand contains the following information:
979 // opt{4-0} = mode from Inst{4-0}
980 // opt{5} = changemode from Inst{17}
981 // opt{8-6} = AIF from Inst{8-6}
982 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
983 // FIXME: Integrated assembler will need these split out.
984 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
985 [/* For disassembly only; pattern left blank */]>,
987 let Inst{31-28} = 0b1111;
988 let Inst{27-20} = 0b00010000;
993 // Preload signals the memory system of possible future data/instruction access.
994 // These are for disassembly only.
995 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
997 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
998 !strconcat(opc, "\t$addr"),
999 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1002 let Inst{31-26} = 0b111101;
1003 let Inst{25} = 0; // 0 for immediate form
1004 let Inst{24} = data;
1005 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1006 let Inst{22} = read;
1007 let Inst{21-20} = 0b01;
1008 let Inst{19-16} = addr{16-13}; // Rn
1009 let Inst{15-12} = Rt;
1010 let Inst{11-0} = addr{11-0}; // imm12
1013 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1014 !strconcat(opc, "\t$shift"),
1015 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1018 let Inst{31-26} = 0b111101;
1019 let Inst{25} = 1; // 1 for register form
1020 let Inst{24} = data;
1021 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1022 let Inst{22} = read;
1023 let Inst{21-20} = 0b01;
1024 let Inst{19-16} = shift{16-13}; // Rn
1025 let Inst{11-0} = shift{11-0};
1029 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1030 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1031 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1033 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1035 [/* For disassembly only; pattern left blank */]>,
1038 let Inst{31-10} = 0b1111000100000001000000;
1043 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1044 [/* For disassembly only; pattern left blank */]>,
1045 Requires<[IsARM, HasV7]> {
1047 let Inst{27-4} = 0b001100100000111100001111;
1048 let Inst{3-0} = opt;
1051 // A5.4 Permanently UNDEFINED instructions.
1052 let isBarrier = 1, isTerminator = 1 in
1053 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1056 let Inst{27-25} = 0b011;
1057 let Inst{24-20} = 0b11111;
1058 let Inst{7-5} = 0b111;
1062 // Address computation and loads and stores in PIC mode.
1063 // FIXME: These PIC insn patterns are pseudos, but derive from the normal insn
1064 // classes (AXI1, et.al.) and so have encoding information and such,
1065 // which is suboptimal. Once the rest of the code emitter (including
1066 // JIT) is MC-ized we should look at refactoring these into true
1067 // pseudos. As is, the encoding information ends up being ignored,
1068 // as these instructions are lowered to individual MC-insts.
1069 let isNotDuplicable = 1 in {
1070 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1071 Pseudo, IIC_iALUr, "",
1072 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1074 let AddedComplexity = 10 in {
1075 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1076 Pseudo, IIC_iLoad_r, "",
1077 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1079 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1080 Pseudo, IIC_iLoad_bh_r, "",
1081 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
1083 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1084 Pseudo, IIC_iLoad_bh_r, "",
1085 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
1087 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1088 Pseudo, IIC_iLoad_bh_r, "",
1089 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
1091 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1092 Pseudo, IIC_iLoad_bh_r, "",
1093 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
1095 let AddedComplexity = 10 in {
1096 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1097 Pseudo, IIC_iStore_r, "",
1098 [(store GPR:$src, addrmodepc:$addr)]>;
1100 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1101 Pseudo, IIC_iStore_bh_r, "",
1102 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1104 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1105 Pseudo, IIC_iStore_bh_r, "",
1106 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1108 } // isNotDuplicable = 1
1111 // LEApcrel - Load a pc-relative address into a register without offending the
1113 // FIXME: These are marked as pseudos, but they're really not(?). They're just
1114 // the ADR instruction. Is this the right way to handle that? They need
1115 // encoding information regardless.
1116 let neverHasSideEffects = 1 in {
1117 let isReMaterializable = 1 in
1118 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
1120 "adr$p\t$dst, #$label", []>;
1122 } // neverHasSideEffects
1123 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
1124 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1126 "adr$p\t$dst, #${label}_${id}", []> {
1130 //===----------------------------------------------------------------------===//
1131 // Control Flow Instructions.
1134 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1136 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1137 "bx", "\tlr", [(ARMretflag)]>,
1138 Requires<[IsARM, HasV4T]> {
1139 let Inst{27-0} = 0b0001001011111111111100011110;
1143 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1144 "mov", "\tpc, lr", [(ARMretflag)]>,
1145 Requires<[IsARM, NoV4T]> {
1146 let Inst{27-0} = 0b0001101000001111000000001110;
1150 // Indirect branches
1151 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1153 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1154 [(brind GPR:$dst)]>,
1155 Requires<[IsARM, HasV4T]> {
1157 let Inst{31-4} = 0b1110000100101111111111110001;
1158 let Inst{3-0} = dst;
1162 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1163 [(brind GPR:$dst)]>,
1164 Requires<[IsARM, NoV4T]> {
1166 let Inst{31-4} = 0b1110000110100000111100000000;
1167 let Inst{3-0} = dst;
1171 // FIXME: remove when we have a way to marking a MI with these properties.
1172 // FIXME: Should pc be an implicit operand like PICADD, etc?
1173 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1174 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1175 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$mode, pred:$p,
1176 reglist:$dsts, variable_ops),
1177 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1178 "ldm${mode}${p}\t$Rn!, $dsts",
1181 // On non-Darwin platforms R9 is callee-saved.
1183 Defs = [R0, R1, R2, R3, R12, LR,
1184 D0, D1, D2, D3, D4, D5, D6, D7,
1185 D16, D17, D18, D19, D20, D21, D22, D23,
1186 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1187 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1188 IIC_Br, "bl\t$func",
1189 [(ARMcall tglobaladdr:$func)]>,
1190 Requires<[IsARM, IsNotDarwin]> {
1191 let Inst{31-28} = 0b1110;
1192 // FIXME: Encoding info for $func. Needs fixups bits.
1195 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1196 IIC_Br, "bl", "\t$func",
1197 [(ARMcall_pred tglobaladdr:$func)]>,
1198 Requires<[IsARM, IsNotDarwin]>;
1201 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1202 IIC_Br, "blx\t$func",
1203 [(ARMcall GPR:$func)]>,
1204 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1206 let Inst{27-4} = 0b000100101111111111110011;
1207 let Inst{3-0} = func;
1211 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1212 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1213 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1214 [(ARMcall_nolink tGPR:$func)]>,
1215 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1217 let Inst{27-4} = 0b000100101111111111110001;
1218 let Inst{3-0} = func;
1222 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1223 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1224 [(ARMcall_nolink tGPR:$func)]>,
1225 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1227 let Inst{27-4} = 0b000110100000111100000000;
1228 let Inst{3-0} = func;
1232 // On Darwin R9 is call-clobbered.
1234 Defs = [R0, R1, R2, R3, R9, R12, LR,
1235 D0, D1, D2, D3, D4, D5, D6, D7,
1236 D16, D17, D18, D19, D20, D21, D22, D23,
1237 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1238 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1239 IIC_Br, "bl\t$func",
1240 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1241 let Inst{31-28} = 0b1110;
1242 // FIXME: Encoding info for $func. Needs fixups bits.
1245 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
1246 IIC_Br, "bl", "\t$func",
1247 [(ARMcall_pred tglobaladdr:$func)]>,
1248 Requires<[IsARM, IsDarwin]>;
1251 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1252 IIC_Br, "blx\t$func",
1253 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1255 let Inst{27-4} = 0b000100101111111111110011;
1256 let Inst{3-0} = func;
1260 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1261 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1262 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1263 [(ARMcall_nolink tGPR:$func)]>,
1264 Requires<[IsARM, HasV4T, IsDarwin]> {
1266 let Inst{27-4} = 0b000100101111111111110001;
1267 let Inst{3-0} = func;
1271 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1272 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1273 [(ARMcall_nolink tGPR:$func)]>,
1274 Requires<[IsARM, NoV4T, IsDarwin]> {
1276 let Inst{27-4} = 0b000110100000111100000000;
1277 let Inst{3-0} = func;
1283 // FIXME: These should probably be xformed into the non-TC versions of the
1284 // instructions as part of MC lowering.
1285 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1287 let Defs = [R0, R1, R2, R3, R9, R12,
1288 D0, D1, D2, D3, D4, D5, D6, D7,
1289 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1290 D27, D28, D29, D30, D31, PC],
1292 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1294 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1296 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1298 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1300 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1301 IIC_Br, "b\t$dst @ TAILCALL",
1302 []>, Requires<[IsDarwin]>;
1304 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1305 IIC_Br, "b.w\t$dst @ TAILCALL",
1306 []>, Requires<[IsDarwin]>;
1308 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1309 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1310 []>, Requires<[IsDarwin]> {
1312 let Inst{31-4} = 0b1110000100101111111111110001;
1313 let Inst{3-0} = dst;
1317 // Non-Darwin versions (the difference is R9).
1318 let Defs = [R0, R1, R2, R3, R12,
1319 D0, D1, D2, D3, D4, D5, D6, D7,
1320 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1321 D27, D28, D29, D30, D31, PC],
1323 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1325 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1327 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1329 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1331 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1332 IIC_Br, "b\t$dst @ TAILCALL",
1333 []>, Requires<[IsARM, IsNotDarwin]>;
1335 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1336 IIC_Br, "b.w\t$dst @ TAILCALL",
1337 []>, Requires<[IsThumb, IsNotDarwin]>;
1339 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1340 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1341 []>, Requires<[IsNotDarwin]> {
1343 let Inst{31-4} = 0b1110000100101111111111110001;
1344 let Inst{3-0} = dst;
1349 let isBranch = 1, isTerminator = 1 in {
1350 // B is "predicable" since it can be xformed into a Bcc.
1351 let isBarrier = 1 in {
1352 let isPredicable = 1 in
1353 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1354 "b\t$target", [(br bb:$target)]>;
1356 let isNotDuplicable = 1, isIndirectBranch = 1,
1357 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1358 isCodeGenOnly = 1 in {
1359 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1360 IIC_Br, "mov\tpc, $target$jt",
1361 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1362 let Inst{11-4} = 0b00000000;
1363 let Inst{15-12} = 0b1111;
1364 let Inst{20} = 0; // S Bit
1365 let Inst{24-21} = 0b1101;
1366 let Inst{27-25} = 0b000;
1368 def BR_JTm : JTI<(outs),
1369 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1370 IIC_Br, "ldr\tpc, $target$jt",
1371 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1373 let Inst{15-12} = 0b1111;
1374 let Inst{20} = 1; // L bit
1375 let Inst{21} = 0; // W bit
1376 let Inst{22} = 0; // B bit
1377 let Inst{24} = 1; // P bit
1378 let Inst{27-25} = 0b011;
1380 def BR_JTadd : JTI<(outs),
1381 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1382 IIC_Br, "add\tpc, $target, $idx$jt",
1383 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1385 let Inst{15-12} = 0b1111;
1386 let Inst{20} = 0; // S bit
1387 let Inst{24-21} = 0b0100;
1388 let Inst{27-25} = 0b000;
1390 } // isNotDuplicable = 1, isIndirectBranch = 1
1393 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1394 // a two-value operand where a dag node expects two operands. :(
1395 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1396 IIC_Br, "b", "\t$target",
1397 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
1400 // Branch and Exchange Jazelle -- for disassembly only
1401 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1402 [/* For disassembly only; pattern left blank */]> {
1403 let Inst{23-20} = 0b0010;
1404 //let Inst{19-8} = 0xfff;
1405 let Inst{7-4} = 0b0010;
1408 // Secure Monitor Call is a system instruction -- for disassembly only
1409 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1410 [/* For disassembly only; pattern left blank */]> {
1412 let Inst{23-4} = 0b01100000000000000111;
1413 let Inst{3-0} = opt;
1416 // Supervisor Call (Software Interrupt) -- for disassembly only
1418 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1419 [/* For disassembly only; pattern left blank */]> {
1421 let Inst{23-0} = svc;
1425 // Store Return State is a system instruction -- for disassembly only
1426 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1427 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1428 NoItinerary, "srs${amode}\tsp!, $mode",
1429 [/* For disassembly only; pattern left blank */]> {
1430 let Inst{31-28} = 0b1111;
1431 let Inst{22-20} = 0b110; // W = 1
1434 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1435 NoItinerary, "srs${amode}\tsp, $mode",
1436 [/* For disassembly only; pattern left blank */]> {
1437 let Inst{31-28} = 0b1111;
1438 let Inst{22-20} = 0b100; // W = 0
1441 // Return From Exception is a system instruction -- for disassembly only
1442 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1443 NoItinerary, "rfe${amode}\t$base!",
1444 [/* For disassembly only; pattern left blank */]> {
1445 let Inst{31-28} = 0b1111;
1446 let Inst{22-20} = 0b011; // W = 1
1449 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1450 NoItinerary, "rfe${amode}\t$base",
1451 [/* For disassembly only; pattern left blank */]> {
1452 let Inst{31-28} = 0b1111;
1453 let Inst{22-20} = 0b001; // W = 0
1455 } // isCodeGenOnly = 1
1457 //===----------------------------------------------------------------------===//
1458 // Load / store Instructions.
1464 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1465 UnOpFrag<(load node:$Src)>>;
1466 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1467 UnOpFrag<(zextloadi8 node:$Src)>>;
1468 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1469 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1470 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1471 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1473 // Special LDR for loads from non-pc-relative constpools.
1474 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1475 isReMaterializable = 1 in
1476 def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1477 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
1480 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1481 let Inst{19-16} = 0b1111;
1482 let Inst{15-12} = Rt;
1483 let Inst{11-0} = addr{11-0}; // imm12
1486 // Loads with zero extension
1487 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1488 IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
1489 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
1491 // Loads with sign extension
1492 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1493 IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
1494 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
1496 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
1497 IIC_iLoad_bh_r, "ldrsb", "\t$dst, $addr",
1498 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
1500 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1501 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1503 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
1504 IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr",
1505 []>, Requires<[IsARM, HasV5TE]>;
1508 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
1509 (ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
1510 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1512 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1513 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1514 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1516 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
1517 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1518 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1520 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1521 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1522 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1524 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
1525 (ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
1526 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1528 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1529 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1530 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1532 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
1533 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1534 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1536 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1537 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1538 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1540 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
1541 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1542 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
1544 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1545 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1546 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
1548 // For disassembly only
1549 def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1550 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1551 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1552 Requires<[IsARM, HasV5TE]>;
1554 // For disassembly only
1555 def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1556 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1557 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1558 Requires<[IsARM, HasV5TE]>;
1560 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1562 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1564 def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
1565 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
1566 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1567 let Inst{21} = 1; // overwrite
1570 def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
1571 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
1572 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1573 let Inst{21} = 1; // overwrite
1576 def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1577 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1578 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1579 let Inst{21} = 1; // overwrite
1582 def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1583 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1584 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1585 let Inst{21} = 1; // overwrite
1588 def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1589 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1590 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1591 let Inst{21} = 1; // overwrite
1596 // Stores with truncate
1597 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
1598 IIC_iStore_bh_r, "strh", "\t$src, $addr",
1599 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
1602 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1603 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1604 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1605 StMiscFrm, IIC_iStore_d_r,
1606 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1609 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
1610 (ins GPR:$src, GPR:$base, am2offset:$offset),
1611 StFrm, IIC_iStore_ru,
1612 "str", "\t$src, [$base, $offset]!", "$base = $base_wb",
1614 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1616 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
1617 (ins GPR:$src, GPR:$base,am2offset:$offset),
1618 StFrm, IIC_iStore_ru,
1619 "str", "\t$src, [$base], $offset", "$base = $base_wb",
1621 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
1623 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1624 (ins GPR:$src, GPR:$base,am3offset:$offset),
1625 StMiscFrm, IIC_iStore_ru,
1626 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1628 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1630 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1631 (ins GPR:$src, GPR:$base,am3offset:$offset),
1632 StMiscFrm, IIC_iStore_bh_ru,
1633 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1634 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1635 GPR:$base, am3offset:$offset))]>;
1637 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
1638 (ins GPR:$src, GPR:$base,am2offset:$offset),
1639 StFrm, IIC_iStore_bh_ru,
1640 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
1641 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
1642 GPR:$base, am2offset:$offset))]>;
1644 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
1645 (ins GPR:$src, GPR:$base,am2offset:$offset),
1646 StFrm, IIC_iStore_bh_ru,
1647 "strb", "\t$src, [$base], $offset", "$base = $base_wb",
1648 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
1649 GPR:$base, am2offset:$offset))]>;
1651 // For disassembly only
1652 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1653 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1654 StMiscFrm, IIC_iStore_d_ru,
1655 "strd", "\t$src1, $src2, [$base, $offset]!",
1656 "$base = $base_wb", []>;
1658 // For disassembly only
1659 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1660 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1661 StMiscFrm, IIC_iStore_d_ru,
1662 "strd", "\t$src1, $src2, [$base], $offset",
1663 "$base = $base_wb", []>;
1665 // STRT, STRBT, and STRHT are for disassembly only.
1667 def STRT : AI2stwpo<(outs GPR:$base_wb),
1668 (ins GPR:$src, GPR:$base,am2offset:$offset),
1669 StFrm, IIC_iStore_ru,
1670 "strt", "\t$src, [$base], $offset", "$base = $base_wb",
1671 [/* For disassembly only; pattern left blank */]> {
1672 let Inst{21} = 1; // overwrite
1675 def STRBT : AI2stbpo<(outs GPR:$base_wb),
1676 (ins GPR:$src, GPR:$base,am2offset:$offset),
1677 StFrm, IIC_iStore_bh_ru,
1678 "strbt", "\t$src, [$base], $offset", "$base = $base_wb",
1679 [/* For disassembly only; pattern left blank */]> {
1680 let Inst{21} = 1; // overwrite
1683 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1684 (ins GPR:$src, GPR:$base,am3offset:$offset),
1685 StMiscFrm, IIC_iStore_bh_ru,
1686 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1687 [/* For disassembly only; pattern left blank */]> {
1688 let Inst{21} = 1; // overwrite
1691 //===----------------------------------------------------------------------===//
1692 // Load / store multiple Instructions.
1695 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1696 isCodeGenOnly = 1 in {
1697 def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1698 reglist:$dsts, variable_ops),
1699 IndexModeNone, LdStMulFrm, IIC_iLoad_m,
1700 "ldm${amode}${p}\t$Rn, $dsts", "", []>;
1702 def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1703 reglist:$dsts, variable_ops),
1704 IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
1705 "ldm${amode}${p}\t$Rn!, $dsts",
1707 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
1709 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1710 isCodeGenOnly = 1 in {
1711 def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1712 reglist:$srcs, variable_ops),
1713 IndexModeNone, LdStMulFrm, IIC_iStore_m,
1714 "stm${amode}${p}\t$Rn, $srcs", "", []>;
1716 def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
1717 reglist:$srcs, variable_ops),
1718 IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
1719 "stm${amode}${p}\t$Rn!, $srcs",
1721 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
1723 //===----------------------------------------------------------------------===//
1724 // Move Instructions.
1727 let neverHasSideEffects = 1 in
1728 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1729 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1733 let Inst{11-4} = 0b00000000;
1736 let Inst{15-12} = Rd;
1739 // A version for the smaller set of tail call registers.
1740 let neverHasSideEffects = 1 in
1741 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1742 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1746 let Inst{11-4} = 0b00000000;
1749 let Inst{15-12} = Rd;
1752 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1753 DPSoRegFrm, IIC_iMOVsr,
1754 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1758 let Inst{15-12} = Rd;
1759 let Inst{11-0} = src;
1763 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1764 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1765 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1769 let Inst{15-12} = Rd;
1770 let Inst{19-16} = 0b0000;
1771 let Inst{11-0} = imm;
1774 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1775 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm:$imm),
1777 "movw", "\t$Rd, $imm",
1778 [(set GPR:$Rd, imm0_65535:$imm)]>,
1779 Requires<[IsARM, HasV6T2]>, UnaryDP {
1782 let Inst{15-12} = Rd;
1783 let Inst{11-0} = imm{11-0};
1784 let Inst{19-16} = imm{15-12};
1789 let Constraints = "$src = $Rd" in
1790 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm:$imm),
1792 "movt", "\t$Rd, $imm",
1794 (or (and GPR:$src, 0xffff),
1795 lo16AllZero:$imm))]>, UnaryDP,
1796 Requires<[IsARM, HasV6T2]> {
1799 let Inst{15-12} = Rd;
1800 let Inst{11-0} = imm{11-0};
1801 let Inst{19-16} = imm{15-12};
1806 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1807 Requires<[IsARM, HasV6T2]>;
1809 let Uses = [CPSR] in
1810 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, "",
1811 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1814 // These aren't really mov instructions, but we have to define them this way
1815 // due to flag operands.
1817 let Defs = [CPSR] in {
1818 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1819 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1821 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, "",
1822 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1826 //===----------------------------------------------------------------------===//
1827 // Extend Instructions.
1832 defm SXTB : AI_ext_rrot<0b01101010,
1833 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1834 defm SXTH : AI_ext_rrot<0b01101011,
1835 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1837 defm SXTAB : AI_exta_rrot<0b01101010,
1838 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1839 defm SXTAH : AI_exta_rrot<0b01101011,
1840 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1842 // For disassembly only
1843 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
1845 // For disassembly only
1846 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
1850 let AddedComplexity = 16 in {
1851 defm UXTB : AI_ext_rrot<0b01101110,
1852 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
1853 defm UXTH : AI_ext_rrot<0b01101111,
1854 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1855 defm UXTB16 : AI_ext_rrot<0b01101100,
1856 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1858 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1859 // The transformation should probably be done as a combiner action
1860 // instead so we can include a check for masking back in the upper
1861 // eight bits of the source into the lower eight bits of the result.
1862 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
1863 // (UXTB16r_rot GPR:$Src, 24)>;
1864 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1865 (UXTB16r_rot GPR:$Src, 8)>;
1867 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
1868 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1869 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
1870 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1873 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1874 // For disassembly only
1875 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
1878 def SBFX : I<(outs GPR:$Rd),
1879 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1880 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1881 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1882 Requires<[IsARM, HasV6T2]> {
1887 let Inst{27-21} = 0b0111101;
1888 let Inst{6-4} = 0b101;
1889 let Inst{20-16} = width;
1890 let Inst{15-12} = Rd;
1891 let Inst{11-7} = lsb;
1895 def UBFX : I<(outs GPR:$Rd),
1896 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
1897 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
1898 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
1899 Requires<[IsARM, HasV6T2]> {
1904 let Inst{27-21} = 0b0111111;
1905 let Inst{6-4} = 0b101;
1906 let Inst{20-16} = width;
1907 let Inst{15-12} = Rd;
1908 let Inst{11-7} = lsb;
1912 //===----------------------------------------------------------------------===//
1913 // Arithmetic Instructions.
1916 defm ADD : AsI1_bin_irs<0b0100, "add",
1917 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1918 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1919 defm SUB : AsI1_bin_irs<0b0010, "sub",
1920 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1921 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1923 // ADD and SUB with 's' bit set.
1924 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
1925 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1926 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1927 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
1928 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
1929 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1931 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1932 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1933 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1934 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1935 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
1936 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1937 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
1938 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
1940 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1941 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
1942 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
1947 let Inst{15-12} = Rd;
1948 let Inst{19-16} = Rn;
1949 let Inst{11-0} = imm;
1952 // The reg/reg form is only defined for the disassembler; for codegen it is
1953 // equivalent to SUBrr.
1954 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1955 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
1956 [/* For disassembly only; pattern left blank */]> {
1960 let Inst{11-4} = 0b00000000;
1963 let Inst{15-12} = Rd;
1964 let Inst{19-16} = Rn;
1967 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1968 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
1969 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
1974 let Inst{11-0} = shift;
1975 let Inst{15-12} = Rd;
1976 let Inst{19-16} = Rn;
1979 // RSB with 's' bit set.
1980 let Defs = [CPSR] in {
1981 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1982 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
1983 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
1989 let Inst{15-12} = Rd;
1990 let Inst{19-16} = Rn;
1991 let Inst{11-0} = imm;
1993 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1994 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
1995 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2001 let Inst{11-0} = shift;
2002 let Inst{15-12} = Rd;
2003 let Inst{19-16} = Rn;
2007 let Uses = [CPSR] in {
2008 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2009 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2010 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2016 let Inst{15-12} = Rd;
2017 let Inst{19-16} = Rn;
2018 let Inst{11-0} = imm;
2020 // The reg/reg form is only defined for the disassembler; for codegen it is
2021 // equivalent to SUBrr.
2022 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2023 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2024 [/* For disassembly only; pattern left blank */]> {
2028 let Inst{11-4} = 0b00000000;
2031 let Inst{15-12} = Rd;
2032 let Inst{19-16} = Rn;
2034 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2035 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2036 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2042 let Inst{11-0} = shift;
2043 let Inst{15-12} = Rd;
2044 let Inst{19-16} = Rn;
2048 // FIXME: Allow these to be predicated.
2049 let Defs = [CPSR], Uses = [CPSR] in {
2050 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2051 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2052 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2059 let Inst{15-12} = Rd;
2060 let Inst{19-16} = Rn;
2061 let Inst{11-0} = imm;
2063 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2064 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2065 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2072 let Inst{11-0} = shift;
2073 let Inst{15-12} = Rd;
2074 let Inst{19-16} = Rn;
2078 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2079 // The assume-no-carry-in form uses the negation of the input since add/sub
2080 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2081 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2083 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2084 (SUBri GPR:$src, so_imm_neg:$imm)>;
2085 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2086 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2087 // The with-carry-in form matches bitwise not instead of the negation.
2088 // Effectively, the inverse interpretation of the carry flag already accounts
2089 // for part of the negation.
2090 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2091 (SBCri GPR:$src, so_imm_not:$imm)>;
2093 // Note: These are implemented in C++ code, because they have to generate
2094 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2096 // (mul X, 2^n+1) -> (add (X << n), X)
2097 // (mul X, 2^n-1) -> (rsb X, (X << n))
2099 // ARM Arithmetic Instruction -- for disassembly only
2100 // GPR:$dst = GPR:$a op GPR:$b
2101 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2102 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2103 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2104 opc, "\t$Rd, $Rn, $Rm", pattern> {
2108 let Inst{27-20} = op27_20;
2109 let Inst{11-4} = op11_4;
2110 let Inst{19-16} = Rn;
2111 let Inst{15-12} = Rd;
2115 // Saturating add/subtract -- for disassembly only
2117 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2118 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2119 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2120 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2121 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2122 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2124 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2125 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2126 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2127 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2128 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2129 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2130 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2131 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2132 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2133 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2134 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2135 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2137 // Signed/Unsigned add/subtract -- for disassembly only
2139 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2140 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2141 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2142 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2143 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2144 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2145 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2146 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2147 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2148 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2149 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2150 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2152 // Signed/Unsigned halving add/subtract -- for disassembly only
2154 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2155 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2156 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2157 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2158 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2159 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2160 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2161 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2162 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2163 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2164 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2165 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2167 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2169 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2170 MulFrm /* for convenience */, NoItinerary, "usad8",
2171 "\t$Rd, $Rn, $Rm", []>,
2172 Requires<[IsARM, HasV6]> {
2176 let Inst{27-20} = 0b01111000;
2177 let Inst{15-12} = 0b1111;
2178 let Inst{7-4} = 0b0001;
2179 let Inst{19-16} = Rd;
2180 let Inst{11-8} = Rm;
2183 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2184 MulFrm /* for convenience */, NoItinerary, "usada8",
2185 "\t$Rd, $Rn, $Rm, $Ra", []>,
2186 Requires<[IsARM, HasV6]> {
2191 let Inst{27-20} = 0b01111000;
2192 let Inst{7-4} = 0b0001;
2193 let Inst{19-16} = Rd;
2194 let Inst{15-12} = Ra;
2195 let Inst{11-8} = Rm;
2199 // Signed/Unsigned saturate -- for disassembly only
2201 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2202 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2203 [/* For disassembly only; pattern left blank */]> {
2208 let Inst{27-21} = 0b0110101;
2209 let Inst{5-4} = 0b01;
2210 let Inst{20-16} = sat_imm;
2211 let Inst{15-12} = Rd;
2212 let Inst{11-7} = sh{7-3};
2213 let Inst{6} = sh{0};
2217 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2218 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2219 [/* For disassembly only; pattern left blank */]> {
2223 let Inst{27-20} = 0b01101010;
2224 let Inst{11-4} = 0b11110011;
2225 let Inst{15-12} = Rd;
2226 let Inst{19-16} = sat_imm;
2230 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2231 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2232 [/* For disassembly only; pattern left blank */]> {
2237 let Inst{27-21} = 0b0110111;
2238 let Inst{5-4} = 0b01;
2239 let Inst{15-12} = Rd;
2240 let Inst{11-7} = sh{7-3};
2241 let Inst{6} = sh{0};
2242 let Inst{20-16} = sat_imm;
2246 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2247 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2248 [/* For disassembly only; pattern left blank */]> {
2252 let Inst{27-20} = 0b01101110;
2253 let Inst{11-4} = 0b11110011;
2254 let Inst{15-12} = Rd;
2255 let Inst{19-16} = sat_imm;
2259 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2260 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2262 //===----------------------------------------------------------------------===//
2263 // Bitwise Instructions.
2266 defm AND : AsI1_bin_irs<0b0000, "and",
2267 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2268 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2269 defm ORR : AsI1_bin_irs<0b1100, "orr",
2270 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2271 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2272 defm EOR : AsI1_bin_irs<0b0001, "eor",
2273 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2274 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2275 defm BIC : AsI1_bin_irs<0b1110, "bic",
2276 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2277 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2279 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2280 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2281 "bfc", "\t$Rd, $imm", "$src = $Rd",
2282 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2283 Requires<[IsARM, HasV6T2]> {
2286 let Inst{27-21} = 0b0111110;
2287 let Inst{6-0} = 0b0011111;
2288 let Inst{15-12} = Rd;
2289 let Inst{11-7} = imm{4-0}; // lsb
2290 let Inst{20-16} = imm{9-5}; // width
2293 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2294 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2295 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2296 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2297 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2298 bf_inv_mask_imm:$imm))]>,
2299 Requires<[IsARM, HasV6T2]> {
2303 let Inst{27-21} = 0b0111110;
2304 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2305 let Inst{15-12} = Rd;
2306 let Inst{11-7} = imm{4-0}; // lsb
2307 let Inst{20-16} = imm{9-5}; // width
2311 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2312 "mvn", "\t$Rd, $Rm",
2313 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2317 let Inst{19-16} = 0b0000;
2318 let Inst{11-4} = 0b00000000;
2319 let Inst{15-12} = Rd;
2322 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2323 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2324 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2329 let Inst{19-16} = 0b0000;
2330 let Inst{15-12} = Rd;
2331 let Inst{11-0} = shift;
2333 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2334 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2335 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2336 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2341 let Inst{19-16} = 0b0000;
2342 let Inst{15-12} = Rd;
2343 let Inst{11-0} = imm;
2346 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2347 (BICri GPR:$src, so_imm_not:$imm)>;
2349 //===----------------------------------------------------------------------===//
2350 // Multiply Instructions.
2352 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2353 string opc, string asm, list<dag> pattern>
2354 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2358 let Inst{19-16} = Rd;
2359 let Inst{11-8} = Rm;
2362 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2363 string opc, string asm, list<dag> pattern>
2364 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2369 let Inst{19-16} = RdHi;
2370 let Inst{15-12} = RdLo;
2371 let Inst{11-8} = Rm;
2375 let isCommutable = 1 in
2376 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2377 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2378 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2380 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2381 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2382 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2384 let Inst{15-12} = Ra;
2387 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
2388 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
2389 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
2390 Requires<[IsARM, HasV6T2]> {
2394 let Inst{19-16} = Rd;
2395 let Inst{11-8} = Rm;
2399 // Extra precision multiplies with low / high results
2401 let neverHasSideEffects = 1 in {
2402 let isCommutable = 1 in {
2403 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2404 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2405 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2407 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2408 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2409 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2412 // Multiply + accumulate
2413 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2414 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2415 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2417 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2418 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2419 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2421 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2422 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2423 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2424 Requires<[IsARM, HasV6]> {
2429 let Inst{19-16} = RdLo;
2430 let Inst{15-12} = RdHi;
2431 let Inst{11-8} = Rm;
2434 } // neverHasSideEffects
2436 // Most significant word multiply
2437 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2438 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2439 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2440 Requires<[IsARM, HasV6]> {
2441 let Inst{15-12} = 0b1111;
2444 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2445 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2446 [/* For disassembly only; pattern left blank */]>,
2447 Requires<[IsARM, HasV6]> {
2448 let Inst{15-12} = 0b1111;
2451 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2452 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2453 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2454 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2455 Requires<[IsARM, HasV6]>;
2457 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2458 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2459 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2460 [/* For disassembly only; pattern left blank */]>,
2461 Requires<[IsARM, HasV6]>;
2463 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2464 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2465 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2466 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2467 Requires<[IsARM, HasV6]>;
2469 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2470 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2471 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2472 [/* For disassembly only; pattern left blank */]>,
2473 Requires<[IsARM, HasV6]>;
2475 multiclass AI_smul<string opc, PatFrag opnode> {
2476 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2477 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2478 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2479 (sext_inreg GPR:$Rm, i16)))]>,
2480 Requires<[IsARM, HasV5TE]>;
2482 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2483 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2484 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2485 (sra GPR:$Rm, (i32 16))))]>,
2486 Requires<[IsARM, HasV5TE]>;
2488 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2489 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2490 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2491 (sext_inreg GPR:$Rm, i16)))]>,
2492 Requires<[IsARM, HasV5TE]>;
2494 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2495 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2496 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2497 (sra GPR:$Rm, (i32 16))))]>,
2498 Requires<[IsARM, HasV5TE]>;
2500 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2501 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2502 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2503 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2504 Requires<[IsARM, HasV5TE]>;
2506 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2507 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2508 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2509 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2510 Requires<[IsARM, HasV5TE]>;
2514 multiclass AI_smla<string opc, PatFrag opnode> {
2515 def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
2516 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2517 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2518 [(set GPR:$Rd, (add GPR:$Ra,
2519 (opnode (sext_inreg GPR:$Rn, i16),
2520 (sext_inreg GPR:$Rm, i16))))]>,
2521 Requires<[IsARM, HasV5TE]>;
2523 def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
2524 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2525 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2526 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2527 (sra GPR:$Rm, (i32 16)))))]>,
2528 Requires<[IsARM, HasV5TE]>;
2530 def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
2531 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2532 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2533 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2534 (sext_inreg GPR:$Rm, i16))))]>,
2535 Requires<[IsARM, HasV5TE]>;
2537 def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
2538 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2539 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2540 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2541 (sra GPR:$Rm, (i32 16)))))]>,
2542 Requires<[IsARM, HasV5TE]>;
2544 def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
2545 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2546 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2547 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2548 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2549 Requires<[IsARM, HasV5TE]>;
2551 def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
2552 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2553 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2554 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2555 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2556 Requires<[IsARM, HasV5TE]>;
2559 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2560 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2562 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2563 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2564 (ins GPR:$Rn, GPR:$Rm),
2565 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2566 [/* For disassembly only; pattern left blank */]>,
2567 Requires<[IsARM, HasV5TE]>;
2569 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2570 (ins GPR:$Rn, GPR:$Rm),
2571 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2572 [/* For disassembly only; pattern left blank */]>,
2573 Requires<[IsARM, HasV5TE]>;
2575 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2576 (ins GPR:$Rn, GPR:$Rm),
2577 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2578 [/* For disassembly only; pattern left blank */]>,
2579 Requires<[IsARM, HasV5TE]>;
2581 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2582 (ins GPR:$Rn, GPR:$Rm),
2583 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2584 [/* For disassembly only; pattern left blank */]>,
2585 Requires<[IsARM, HasV5TE]>;
2587 // Helper class for AI_smld -- for disassembly only
2588 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2589 InstrItinClass itin, string opc, string asm>
2590 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2597 let Inst{21-20} = 0b00;
2598 let Inst{22} = long;
2599 let Inst{27-23} = 0b01110;
2600 let Inst{11-8} = Rm;
2603 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2604 InstrItinClass itin, string opc, string asm>
2605 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2607 let Inst{15-12} = 0b1111;
2608 let Inst{19-16} = Rd;
2610 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2611 InstrItinClass itin, string opc, string asm>
2612 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2614 let Inst{15-12} = Ra;
2616 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2617 InstrItinClass itin, string opc, string asm>
2618 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2621 let Inst{19-16} = RdHi;
2622 let Inst{15-12} = RdLo;
2625 multiclass AI_smld<bit sub, string opc> {
2627 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2628 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2630 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2631 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2633 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2634 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2635 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2637 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2638 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2639 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2643 defm SMLA : AI_smld<0, "smla">;
2644 defm SMLS : AI_smld<1, "smls">;
2646 multiclass AI_sdml<bit sub, string opc> {
2648 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2649 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2650 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2651 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2654 defm SMUA : AI_sdml<0, "smua">;
2655 defm SMUS : AI_sdml<1, "smus">;
2657 //===----------------------------------------------------------------------===//
2658 // Misc. Arithmetic Instructions.
2661 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2662 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2663 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2665 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2666 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2667 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2668 Requires<[IsARM, HasV6T2]>;
2670 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2671 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2672 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2674 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2675 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2677 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2678 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2679 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2680 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2681 Requires<[IsARM, HasV6]>;
2683 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2684 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2687 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2688 (shl GPR:$Rm, (i32 8))), i16))]>,
2689 Requires<[IsARM, HasV6]>;
2691 def lsl_shift_imm : SDNodeXForm<imm, [{
2692 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2693 return CurDAG->getTargetConstant(Sh, MVT::i32);
2696 def lsl_amt : PatLeaf<(i32 imm), [{
2697 return (N->getZExtValue() < 32);
2700 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2701 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2702 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2703 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2704 (and (shl GPR:$Rm, lsl_amt:$sh),
2706 Requires<[IsARM, HasV6]>;
2708 // Alternate cases for PKHBT where identities eliminate some nodes.
2709 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2710 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2711 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2712 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2714 def asr_shift_imm : SDNodeXForm<imm, [{
2715 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2716 return CurDAG->getTargetConstant(Sh, MVT::i32);
2719 def asr_amt : PatLeaf<(i32 imm), [{
2720 return (N->getZExtValue() <= 32);
2723 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2724 // will match the pattern below.
2725 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2726 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2727 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2728 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2729 (and (sra GPR:$Rm, asr_amt:$sh),
2731 Requires<[IsARM, HasV6]>;
2733 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2734 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2735 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2736 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2737 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2738 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2739 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2741 //===----------------------------------------------------------------------===//
2742 // Comparison Instructions...
2745 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2746 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2747 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2749 // FIXME: We have to be careful when using the CMN instruction and comparison
2750 // with 0. One would expect these two pieces of code should give identical
2766 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2767 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2768 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2769 // value of r0 and the carry bit (because the "carry bit" parameter to
2770 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2771 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2772 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2773 // parameter to AddWithCarry is defined as 0).
2775 // When x is 0 and unsigned:
2779 // ~x + 1 = 0x1 0000 0000
2780 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2782 // Therefore, we should disable CMN when comparing against zero, until we can
2783 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2784 // when it's a comparison which doesn't look at the 'carry' flag).
2786 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2788 // This is related to <rdar://problem/7569620>.
2790 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2791 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2793 // Note that TST/TEQ don't set all the same flags that CMP does!
2794 defm TST : AI1_cmp_irs<0b1000, "tst",
2795 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2796 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
2797 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2798 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2799 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
2801 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2802 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2803 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2804 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2805 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2806 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2808 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2809 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2811 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2812 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2814 // Pseudo i64 compares for some floating point compares.
2815 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2817 def BCCi64 : PseudoInst<(outs),
2818 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2820 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2822 def BCCZi64 : PseudoInst<(outs),
2823 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, "",
2824 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2825 } // usesCustomInserter
2828 // Conditional moves
2829 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2830 // a two-value operand where a dag node expects two operands. :(
2831 // FIXME: These should all be pseudo-instructions that get expanded to
2832 // the normal MOV instructions. That would fix the dependency on
2833 // special casing them in tblgen.
2834 let neverHasSideEffects = 1 in {
2835 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2836 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2837 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2838 RegConstraint<"$false = $Rd">, UnaryDP {
2843 let Inst{15-12} = Rd;
2844 let Inst{11-4} = 0b00000000;
2848 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
2849 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
2850 "mov", "\t$Rd, $shift",
2851 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
2852 RegConstraint<"$false = $Rd">, UnaryDP {
2858 let Inst{19-16} = Rn;
2859 let Inst{15-12} = Rd;
2860 let Inst{11-0} = shift;
2863 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm),
2865 "movw", "\t$Rd, $imm",
2867 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
2873 let Inst{19-16} = imm{15-12};
2874 let Inst{15-12} = Rd;
2875 let Inst{11-0} = imm{11-0};
2878 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
2879 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
2880 "mov", "\t$Rd, $imm",
2881 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2882 RegConstraint<"$false = $Rd">, UnaryDP {
2887 let Inst{19-16} = 0b0000;
2888 let Inst{15-12} = Rd;
2889 let Inst{11-0} = imm;
2891 } // neverHasSideEffects
2893 //===----------------------------------------------------------------------===//
2894 // Atomic operations intrinsics
2897 def memb_opt : Operand<i32> {
2898 let PrintMethod = "printMemBOption";
2901 // memory barriers protect the atomic sequences
2902 let hasSideEffects = 1 in {
2903 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2904 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2905 Requires<[IsARM, HasDB]> {
2907 let Inst{31-4} = 0xf57ff05;
2908 let Inst{3-0} = opt;
2911 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
2912 "mcr", "\tp15, 0, $zero, c7, c10, 5",
2913 [(ARMMemBarrierMCR GPR:$zero)]>,
2914 Requires<[IsARM, HasV6]> {
2915 // FIXME: add encoding
2919 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
2921 [/* For disassembly only; pattern left blank */]>,
2922 Requires<[IsARM, HasDB]> {
2924 let Inst{31-4} = 0xf57ff04;
2925 let Inst{3-0} = opt;
2928 // ISB has only full system option -- for disassembly only
2929 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
2930 Requires<[IsARM, HasDB]> {
2931 let Inst{31-4} = 0xf57ff06;
2932 let Inst{3-0} = 0b1111;
2935 let usesCustomInserter = 1 in {
2936 let Uses = [CPSR] in {
2937 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
2938 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2939 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
2940 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
2941 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2942 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
2943 def ATOMIC_LOAD_AND_I8 : PseudoInst<
2944 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2945 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
2946 def ATOMIC_LOAD_OR_I8 : PseudoInst<
2947 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2948 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
2949 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
2950 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2951 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
2952 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
2953 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2954 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
2955 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
2956 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2957 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
2958 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
2959 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2960 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
2961 def ATOMIC_LOAD_AND_I16 : PseudoInst<
2962 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2963 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
2964 def ATOMIC_LOAD_OR_I16 : PseudoInst<
2965 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2966 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
2967 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
2968 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2969 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
2970 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
2971 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2972 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
2973 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
2974 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2975 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
2976 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
2977 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2978 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
2979 def ATOMIC_LOAD_AND_I32 : PseudoInst<
2980 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2981 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
2982 def ATOMIC_LOAD_OR_I32 : PseudoInst<
2983 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2984 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
2985 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
2986 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2987 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
2988 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
2989 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, "",
2990 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
2992 def ATOMIC_SWAP_I8 : PseudoInst<
2993 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2994 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
2995 def ATOMIC_SWAP_I16 : PseudoInst<
2996 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
2997 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
2998 def ATOMIC_SWAP_I32 : PseudoInst<
2999 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, "",
3000 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3002 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3003 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3004 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3005 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3006 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3007 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3008 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3009 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, "",
3010 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3014 let mayLoad = 1 in {
3015 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3016 "ldrexb", "\t$Rt, [$Rn]",
3018 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3019 "ldrexh", "\t$Rt, [$Rn]",
3021 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3022 "ldrex", "\t$Rt, [$Rn]",
3024 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3026 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3030 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3031 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3033 "strexb", "\t$Rd, $src, [$Rn]",
3035 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3037 "strexh", "\t$Rd, $Rt, [$Rn]",
3039 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3041 "strex", "\t$Rd, $Rt, [$Rn]",
3043 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3044 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3046 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3050 // Clear-Exclusive is for disassembly only.
3051 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3052 [/* For disassembly only; pattern left blank */]>,
3053 Requires<[IsARM, HasV7]> {
3054 let Inst{31-0} = 0b11110101011111111111000000011111;
3057 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3058 let mayLoad = 1 in {
3059 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3060 [/* For disassembly only; pattern left blank */]>;
3061 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3062 [/* For disassembly only; pattern left blank */]>;
3065 //===----------------------------------------------------------------------===//
3069 // __aeabi_read_tp preserves the registers r1-r3.
3070 // FIXME: This needs to be a pseudo of some sort so that we can get the
3071 // encoding right, complete with fixup for the aeabi_read_tp function.
3073 Defs = [R0, R12, LR, CPSR] in {
3074 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3075 "bl\t__aeabi_read_tp",
3076 [(set R0, ARMthread_pointer)]>;
3079 //===----------------------------------------------------------------------===//
3080 // SJLJ Exception handling intrinsics
3081 // eh_sjlj_setjmp() is an instruction sequence to store the return
3082 // address and save #0 in R0 for the non-longjmp case.
3083 // Since by its nature we may be coming from some other function to get
3084 // here, and we're using the stack frame for the containing function to
3085 // save/restore registers, we can't keep anything live in regs across
3086 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3087 // when we get here from a longjmp(). We force everthing out of registers
3088 // except for our own input by listing the relevant registers in Defs. By
3089 // doing so, we also cause the prologue/epilogue code to actively preserve
3090 // all of the callee-saved resgisters, which is exactly what we want.
3091 // A constant value is passed in $val, and we use the location as a scratch.
3093 // These are pseudo-instructions and are lowered to individual MC-insts, so
3094 // no encoding information is necessary.
3096 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3097 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3098 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3099 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3100 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3101 AddrModeNone, SizeSpecial, IndexModeNone,
3102 Pseudo, NoItinerary, "", "",
3103 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3104 Requires<[IsARM, HasVFP2]>;
3108 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3109 hasSideEffects = 1, isBarrier = 1 in {
3110 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3111 AddrModeNone, SizeSpecial, IndexModeNone,
3112 Pseudo, NoItinerary, "", "",
3113 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3114 Requires<[IsARM, NoVFP]>;
3117 // FIXME: Non-Darwin version(s)
3118 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3119 Defs = [ R7, LR, SP ] in {
3120 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3121 AddrModeNone, SizeSpecial, IndexModeNone,
3122 Pseudo, NoItinerary, "", "",
3123 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3124 Requires<[IsARM, IsDarwin]>;
3127 // eh.sjlj.dispatchsetup pseudo-instruction.
3128 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3129 // handled when the pseudo is expanded (which happens before any passes
3130 // that need the instruction size).
3131 let isBarrier = 1, hasSideEffects = 1 in
3132 def Int_eh_sjlj_dispatchsetup :
3133 PseudoInst<(outs), (ins GPR:$src), NoItinerary, "",
3134 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3135 Requires<[IsDarwin]>;
3137 //===----------------------------------------------------------------------===//
3138 // Non-Instruction Patterns
3141 // Large immediate handling.
3143 // Two piece so_imms.
3144 // FIXME: Remove this when we can do generalized remat.
3145 let isReMaterializable = 1 in
3146 def MOVi2pieces : PseudoInst<(outs GPR:$dst), (ins so_imm2part:$src),
3148 [(set GPR:$dst, (so_imm2part:$src))]>,
3149 Requires<[IsARM, NoV6T2]>;
3151 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
3152 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3153 (so_imm2part_2 imm:$RHS))>;
3154 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
3155 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3156 (so_imm2part_2 imm:$RHS))>;
3157 def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
3158 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
3159 (so_imm2part_2 imm:$RHS))>;
3160 def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
3161 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)),
3162 (so_neg_imm2part_2 imm:$RHS))>;
3164 // 32-bit immediate using movw + movt.
3165 // This is a single pseudo instruction, the benefit is that it can be remat'd
3166 // as a single unit instead of having to handle reg inputs.
3167 // FIXME: Remove this when we can do generalized remat.
3168 let isReMaterializable = 1 in
3169 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, "",
3170 [(set GPR:$dst, (i32 imm:$src))]>,
3171 Requires<[IsARM, HasV6T2]>;
3173 // ConstantPool, GlobalAddress, and JumpTable
3174 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3175 Requires<[IsARM, DontUseMovt]>;
3176 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3177 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3178 Requires<[IsARM, UseMovt]>;
3179 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3180 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3182 // TODO: add,sub,and, 3-instr forms?
3185 def : ARMPat<(ARMtcret tcGPR:$dst),
3186 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3188 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3189 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3191 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3192 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3194 def : ARMPat<(ARMtcret tcGPR:$dst),
3195 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3197 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3198 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3200 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3201 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3204 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3205 Requires<[IsARM, IsNotDarwin]>;
3206 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3207 Requires<[IsARM, IsDarwin]>;
3209 // zextload i1 -> zextload i8
3210 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3211 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3213 // extload -> zextload
3214 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3215 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3216 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3217 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3219 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3221 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3222 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3225 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3226 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3227 (SMULBB GPR:$a, GPR:$b)>;
3228 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3229 (SMULBB GPR:$a, GPR:$b)>;
3230 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3231 (sra GPR:$b, (i32 16))),
3232 (SMULBT GPR:$a, GPR:$b)>;
3233 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3234 (SMULBT GPR:$a, GPR:$b)>;
3235 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3236 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3237 (SMULTB GPR:$a, GPR:$b)>;
3238 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3239 (SMULTB GPR:$a, GPR:$b)>;
3240 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3242 (SMULWB GPR:$a, GPR:$b)>;
3243 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3244 (SMULWB GPR:$a, GPR:$b)>;
3246 def : ARMV5TEPat<(add GPR:$acc,
3247 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3248 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3249 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3250 def : ARMV5TEPat<(add GPR:$acc,
3251 (mul sext_16_node:$a, sext_16_node:$b)),
3252 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3253 def : ARMV5TEPat<(add GPR:$acc,
3254 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3255 (sra GPR:$b, (i32 16)))),
3256 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3257 def : ARMV5TEPat<(add GPR:$acc,
3258 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3259 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3260 def : ARMV5TEPat<(add GPR:$acc,
3261 (mul (sra GPR:$a, (i32 16)),
3262 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3263 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3264 def : ARMV5TEPat<(add GPR:$acc,
3265 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3266 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3267 def : ARMV5TEPat<(add GPR:$acc,
3268 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3270 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3271 def : ARMV5TEPat<(add GPR:$acc,
3272 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3273 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3275 //===----------------------------------------------------------------------===//
3279 include "ARMInstrThumb.td"
3281 //===----------------------------------------------------------------------===//
3285 include "ARMInstrThumb2.td"
3287 //===----------------------------------------------------------------------===//
3288 // Floating Point Support
3291 include "ARMInstrVFP.td"
3293 //===----------------------------------------------------------------------===//
3294 // Advanced SIMD (NEON) Support
3297 include "ARMInstrNEON.td"
3299 //===----------------------------------------------------------------------===//
3300 // Coprocessor Instructions. For disassembly only.
3303 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3304 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3305 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3306 [/* For disassembly only; pattern left blank */]> {
3310 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3311 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3312 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3313 [/* For disassembly only; pattern left blank */]> {
3314 let Inst{31-28} = 0b1111;
3318 class ACI<dag oops, dag iops, string opc, string asm>
3319 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3320 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3321 let Inst{27-25} = 0b110;
3324 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3326 def _OFFSET : ACI<(outs),
3327 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3328 opc, "\tp$cop, cr$CRd, $addr"> {
3329 let Inst{31-28} = op31_28;
3330 let Inst{24} = 1; // P = 1
3331 let Inst{21} = 0; // W = 0
3332 let Inst{22} = 0; // D = 0
3333 let Inst{20} = load;
3336 def _PRE : ACI<(outs),
3337 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3338 opc, "\tp$cop, cr$CRd, $addr!"> {
3339 let Inst{31-28} = op31_28;
3340 let Inst{24} = 1; // P = 1
3341 let Inst{21} = 1; // W = 1
3342 let Inst{22} = 0; // D = 0
3343 let Inst{20} = load;
3346 def _POST : ACI<(outs),
3347 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3348 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3349 let Inst{31-28} = op31_28;
3350 let Inst{24} = 0; // P = 0
3351 let Inst{21} = 1; // W = 1
3352 let Inst{22} = 0; // D = 0
3353 let Inst{20} = load;
3356 def _OPTION : ACI<(outs),
3357 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3358 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3359 let Inst{31-28} = op31_28;
3360 let Inst{24} = 0; // P = 0
3361 let Inst{23} = 1; // U = 1
3362 let Inst{21} = 0; // W = 0
3363 let Inst{22} = 0; // D = 0
3364 let Inst{20} = load;
3367 def L_OFFSET : ACI<(outs),
3368 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3369 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3370 let Inst{31-28} = op31_28;
3371 let Inst{24} = 1; // P = 1
3372 let Inst{21} = 0; // W = 0
3373 let Inst{22} = 1; // D = 1
3374 let Inst{20} = load;
3377 def L_PRE : ACI<(outs),
3378 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3379 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3380 let Inst{31-28} = op31_28;
3381 let Inst{24} = 1; // P = 1
3382 let Inst{21} = 1; // W = 1
3383 let Inst{22} = 1; // D = 1
3384 let Inst{20} = load;
3387 def L_POST : ACI<(outs),
3388 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3389 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3390 let Inst{31-28} = op31_28;
3391 let Inst{24} = 0; // P = 0
3392 let Inst{21} = 1; // W = 1
3393 let Inst{22} = 1; // D = 1
3394 let Inst{20} = load;
3397 def L_OPTION : ACI<(outs),
3398 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3399 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3400 let Inst{31-28} = op31_28;
3401 let Inst{24} = 0; // P = 0
3402 let Inst{23} = 1; // U = 1
3403 let Inst{21} = 0; // W = 0
3404 let Inst{22} = 1; // D = 1
3405 let Inst{20} = load;
3409 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3410 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3411 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3412 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3414 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3415 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3416 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3417 [/* For disassembly only; pattern left blank */]> {
3422 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3423 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3424 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3425 [/* For disassembly only; pattern left blank */]> {
3426 let Inst{31-28} = 0b1111;
3431 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3432 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3433 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3434 [/* For disassembly only; pattern left blank */]> {
3439 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3440 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3441 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3442 [/* For disassembly only; pattern left blank */]> {
3443 let Inst{31-28} = 0b1111;
3448 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3449 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3450 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3451 [/* For disassembly only; pattern left blank */]> {
3452 let Inst{23-20} = 0b0100;
3455 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3456 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3457 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3458 [/* For disassembly only; pattern left blank */]> {
3459 let Inst{31-28} = 0b1111;
3460 let Inst{23-20} = 0b0100;
3463 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3464 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3465 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3466 [/* For disassembly only; pattern left blank */]> {
3467 let Inst{23-20} = 0b0101;
3470 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3471 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3472 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3473 [/* For disassembly only; pattern left blank */]> {
3474 let Inst{31-28} = 0b1111;
3475 let Inst{23-20} = 0b0101;
3478 //===----------------------------------------------------------------------===//
3479 // Move between special register and ARM core register -- for disassembly only
3482 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3483 [/* For disassembly only; pattern left blank */]> {
3484 let Inst{23-20} = 0b0000;
3485 let Inst{7-4} = 0b0000;
3488 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3489 [/* For disassembly only; pattern left blank */]> {
3490 let Inst{23-20} = 0b0100;
3491 let Inst{7-4} = 0b0000;
3494 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3495 "msr", "\tcpsr$mask, $src",
3496 [/* For disassembly only; pattern left blank */]> {
3497 let Inst{23-20} = 0b0010;
3498 let Inst{7-4} = 0b0000;
3501 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3502 "msr", "\tcpsr$mask, $a",
3503 [/* For disassembly only; pattern left blank */]> {
3504 let Inst{23-20} = 0b0010;
3505 let Inst{7-4} = 0b0000;
3508 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3509 "msr", "\tspsr$mask, $src",
3510 [/* For disassembly only; pattern left blank */]> {
3511 let Inst{23-20} = 0b0110;
3512 let Inst{7-4} = 0b0000;
3515 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3516 "msr", "\tspsr$mask, $a",
3517 [/* For disassembly only; pattern left blank */]> {
3518 let Inst{23-20} = 0b0110;
3519 let Inst{7-4} = 0b0000;