1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
22 let Namespace = "ARM";
24 dag OperandList = ops;
25 let AsmString = asmstr;
26 let Pattern = pattern;
29 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
30 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
31 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
33 def SDT_ARMRetFlag : SDTypeProfile<0, 0, []>;
34 def retflag : SDNode<"ARMISD::RET_FLAG", SDT_ARMRetFlag,
35 [SDNPHasChain, SDNPOptInFlag]>;
37 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
38 "!ADJCALLSTACKUP $amt",
39 [(callseq_end imm:$amt)]>;
41 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
42 "!ADJCALLSTACKDOWN $amt",
43 [(callseq_start imm:$amt)]>;
45 //bx supports other registers as operands. So this looks like a
46 //hack. Maybe a ret should be expanded to a "branch lr" and bx
47 //declared as a regular instruction
49 def BX: InstARM<(ops), "bx lr", [(retflag)]>;
51 def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
53 [(set IntRegs:$dst, (load IntRegs:$addr))]>;
55 def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
57 [(store IntRegs:$src, IntRegs:$addr)]>;
59 def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
60 "mov $dst, $src", []>;
62 def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
63 "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;