1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 // An 'and' node with a single use.
273 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
274 return N->hasOneUse();
277 // An 'xor' node with a single use.
278 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
279 return N->hasOneUse();
282 //===----------------------------------------------------------------------===//
283 // Operand Definitions.
287 def brtarget : Operand<OtherVT> {
288 let EncoderMethod = "getBranchTargetOpValue";
292 def bltarget : Operand<i32> {
293 // Encoded the same as branch targets.
294 let EncoderMethod = "getBranchTargetOpValue";
297 // A list of registers separated by comma. Used by load/store multiple.
298 def RegListAsmOperand : AsmOperandClass {
299 let Name = "RegList";
300 let SuperClasses = [];
303 def DPRRegListAsmOperand : AsmOperandClass {
304 let Name = "DPRRegList";
305 let SuperClasses = [];
308 def SPRRegListAsmOperand : AsmOperandClass {
309 let Name = "SPRRegList";
310 let SuperClasses = [];
313 def reglist : Operand<i32> {
314 let EncoderMethod = "getRegisterListOpValue";
315 let ParserMatchClass = RegListAsmOperand;
316 let PrintMethod = "printRegisterList";
319 def dpr_reglist : Operand<i32> {
320 let EncoderMethod = "getRegisterListOpValue";
321 let ParserMatchClass = DPRRegListAsmOperand;
322 let PrintMethod = "printRegisterList";
325 def spr_reglist : Operand<i32> {
326 let EncoderMethod = "getRegisterListOpValue";
327 let ParserMatchClass = SPRRegListAsmOperand;
328 let PrintMethod = "printRegisterList";
331 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
332 def cpinst_operand : Operand<i32> {
333 let PrintMethod = "printCPInstOperand";
336 def jtblock_operand : Operand<i32> {
337 let PrintMethod = "printJTBlockOperand";
339 def jt2block_operand : Operand<i32> {
340 let PrintMethod = "printJT2BlockOperand";
344 def pclabel : Operand<i32> {
345 let PrintMethod = "printPCLabel";
348 def neon_vcvt_imm32 : Operand<i32> {
349 let EncoderMethod = "getNEONVcvtImm32OpValue";
352 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
353 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
354 int32_t v = (int32_t)N->getZExtValue();
355 return v == 8 || v == 16 || v == 24; }]> {
356 let EncoderMethod = "getRotImmOpValue";
359 // shift_imm: An integer that encodes a shift amount and the type of shift
360 // (currently either asr or lsl) using the same encoding used for the
361 // immediates in so_reg operands.
362 def shift_imm : Operand<i32> {
363 let PrintMethod = "printShiftImmOperand";
366 // shifter_operand operands: so_reg and so_imm.
367 def so_reg : Operand<i32>, // reg reg imm
368 ComplexPattern<i32, 3, "SelectShifterOperandReg",
369 [shl,srl,sra,rotr]> {
370 let EncoderMethod = "getSORegOpValue";
371 let PrintMethod = "printSORegOperand";
372 let MIOperandInfo = (ops GPR, GPR, i32imm);
374 def shift_so_reg : Operand<i32>, // reg reg imm
375 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
376 [shl,srl,sra,rotr]> {
377 let EncoderMethod = "getSORegOpValue";
378 let PrintMethod = "printSORegOperand";
379 let MIOperandInfo = (ops GPR, GPR, i32imm);
382 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
383 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
384 // represented in the imm field in the same 12-bit form that they are encoded
385 // into so_imm instructions: the 8-bit immediate is the least significant bits
386 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
387 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
388 let EncoderMethod = "getSOImmOpValue";
389 let PrintMethod = "printSOImmOperand";
392 // Break so_imm's up into two pieces. This handles immediates with up to 16
393 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
394 // get the first/second pieces.
395 def so_imm2part : PatLeaf<(imm), [{
396 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
399 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
401 def arm_i32imm : PatLeaf<(imm), [{
402 if (Subtarget->hasV6T2Ops())
404 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
407 def so_imm2part_1 : SDNodeXForm<imm, [{
408 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
409 return CurDAG->getTargetConstant(V, MVT::i32);
412 def so_imm2part_2 : SDNodeXForm<imm, [{
413 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
414 return CurDAG->getTargetConstant(V, MVT::i32);
417 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
418 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
420 let PrintMethod = "printSOImm2PartOperand";
423 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
424 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
425 return CurDAG->getTargetConstant(V, MVT::i32);
428 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
429 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
430 return CurDAG->getTargetConstant(V, MVT::i32);
433 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
434 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
435 return (int32_t)N->getZExtValue() < 32;
438 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
439 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
440 return (int32_t)N->getZExtValue() < 32;
442 let EncoderMethod = "getImmMinusOneOpValue";
445 // For movt/movw - sets the MC Encoder method.
446 // The imm is split into imm{15-12}, imm{11-0}
448 def movt_imm : Operand<i32> {
449 let EncoderMethod = "getMovtImmOpValue";
452 // Define ARM specific addressing modes.
455 // addrmode_imm12 := reg +/- imm12
457 def addrmode_imm12 : Operand<i32>,
458 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
459 // 12-bit immediate operand. Note that instructions using this encode
460 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
461 // immediate values are as normal.
463 let EncoderMethod = "getAddrModeImm12OpValue";
464 let PrintMethod = "printAddrModeImm12Operand";
465 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
467 // ldst_so_reg := reg +/- reg shop imm
469 def ldst_so_reg : Operand<i32>,
470 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
471 let EncoderMethod = "getLdStSORegOpValue";
472 // FIXME: Simplify the printer
473 let PrintMethod = "printAddrMode2Operand";
474 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
477 // addrmode2 := reg +/- imm12
478 // := reg +/- reg shop imm
480 def addrmode2 : Operand<i32>,
481 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
482 string EncoderMethod = "getAddrMode2OpValue";
483 let PrintMethod = "printAddrMode2Operand";
484 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
487 def am2offset : Operand<i32>,
488 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
489 [], [SDNPWantRoot]> {
490 string EncoderMethod = "getAddrMode2OffsetOpValue";
491 let PrintMethod = "printAddrMode2OffsetOperand";
492 let MIOperandInfo = (ops GPR, i32imm);
495 // addrmode3 := reg +/- reg
496 // addrmode3 := reg +/- imm8
498 def addrmode3 : Operand<i32>,
499 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
500 let EncoderMethod = "getAddrMode3OpValue";
501 let PrintMethod = "printAddrMode3Operand";
502 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
505 def am3offset : Operand<i32>,
506 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
507 [], [SDNPWantRoot]> {
508 let EncoderMethod = "getAddrMode3OffsetOpValue";
509 let PrintMethod = "printAddrMode3OffsetOperand";
510 let MIOperandInfo = (ops GPR, i32imm);
513 // ldstm_mode := {ia, ib, da, db}
515 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
516 let EncoderMethod = "getLdStmModeOpValue";
517 let PrintMethod = "printLdStmModeOperand";
520 def MemMode5AsmOperand : AsmOperandClass {
521 let Name = "MemMode5";
522 let SuperClasses = [];
525 // addrmode5 := reg +/- imm8*4
527 def addrmode5 : Operand<i32>,
528 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
529 let PrintMethod = "printAddrMode5Operand";
530 let MIOperandInfo = (ops GPR:$base, i32imm);
531 let ParserMatchClass = MemMode5AsmOperand;
532 let EncoderMethod = "getAddrMode5OpValue";
535 // addrmode6 := reg with optional writeback
537 def addrmode6 : Operand<i32>,
538 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
539 let PrintMethod = "printAddrMode6Operand";
540 let MIOperandInfo = (ops GPR:$addr, i32imm);
541 let EncoderMethod = "getAddrMode6AddressOpValue";
544 def am6offset : Operand<i32> {
545 let PrintMethod = "printAddrMode6OffsetOperand";
546 let MIOperandInfo = (ops GPR);
547 let EncoderMethod = "getAddrMode6OffsetOpValue";
550 // addrmodepc := pc + reg
552 def addrmodepc : Operand<i32>,
553 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
554 let PrintMethod = "printAddrModePCOperand";
555 let MIOperandInfo = (ops GPR, i32imm);
558 def nohash_imm : Operand<i32> {
559 let PrintMethod = "printNoHashImmediate";
562 //===----------------------------------------------------------------------===//
564 include "ARMInstrFormats.td"
566 //===----------------------------------------------------------------------===//
567 // Multiclass helpers...
570 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
571 /// binop that produces a value.
572 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
573 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
574 PatFrag opnode, bit Commutable = 0> {
575 // The register-immediate version is re-materializable. This is useful
576 // in particular for taking the address of a local.
577 let isReMaterializable = 1 in {
578 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
579 iii, opc, "\t$Rd, $Rn, $imm",
580 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
585 let Inst{19-16} = Rn;
586 let Inst{15-12} = Rd;
587 let Inst{11-0} = imm;
590 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
591 iir, opc, "\t$Rd, $Rn, $Rm",
592 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
597 let isCommutable = Commutable;
598 let Inst{19-16} = Rn;
599 let Inst{15-12} = Rd;
600 let Inst{11-4} = 0b00000000;
603 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
604 iis, opc, "\t$Rd, $Rn, $shift",
605 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
610 let Inst{19-16} = Rn;
611 let Inst{15-12} = Rd;
612 let Inst{11-0} = shift;
616 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
617 /// instruction modifies the CPSR register.
618 let Defs = [CPSR] in {
619 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
620 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
621 PatFrag opnode, bit Commutable = 0> {
622 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
623 iii, opc, "\t$Rd, $Rn, $imm",
624 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
630 let Inst{19-16} = Rn;
631 let Inst{15-12} = Rd;
632 let Inst{11-0} = imm;
634 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
635 iir, opc, "\t$Rd, $Rn, $Rm",
636 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
640 let isCommutable = Commutable;
643 let Inst{19-16} = Rn;
644 let Inst{15-12} = Rd;
645 let Inst{11-4} = 0b00000000;
648 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
649 iis, opc, "\t$Rd, $Rn, $shift",
650 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
656 let Inst{19-16} = Rn;
657 let Inst{15-12} = Rd;
658 let Inst{11-0} = shift;
663 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
664 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
665 /// a explicit result, only implicitly set CPSR.
666 let isCompare = 1, Defs = [CPSR] in {
667 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
668 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
669 PatFrag opnode, bit Commutable = 0> {
670 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
672 [(opnode GPR:$Rn, so_imm:$imm)]> {
677 let Inst{19-16} = Rn;
678 let Inst{15-12} = 0b0000;
679 let Inst{11-0} = imm;
681 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
683 [(opnode GPR:$Rn, GPR:$Rm)]> {
686 let isCommutable = Commutable;
689 let Inst{19-16} = Rn;
690 let Inst{15-12} = 0b0000;
691 let Inst{11-4} = 0b00000000;
694 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
695 opc, "\t$Rn, $shift",
696 [(opnode GPR:$Rn, so_reg:$shift)]> {
701 let Inst{19-16} = Rn;
702 let Inst{15-12} = 0b0000;
703 let Inst{11-0} = shift;
708 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
709 /// register and one whose operand is a register rotated by 8/16/24.
710 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
711 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
712 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
713 IIC_iEXTr, opc, "\t$Rd, $Rm",
714 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
715 Requires<[IsARM, HasV6]> {
718 let Inst{19-16} = 0b1111;
719 let Inst{15-12} = Rd;
720 let Inst{11-10} = 0b00;
723 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
724 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
725 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
726 Requires<[IsARM, HasV6]> {
730 let Inst{19-16} = 0b1111;
731 let Inst{15-12} = Rd;
732 let Inst{11-10} = rot;
737 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
738 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
739 IIC_iEXTr, opc, "\t$Rd, $Rm",
740 [/* For disassembly only; pattern left blank */]>,
741 Requires<[IsARM, HasV6]> {
742 let Inst{19-16} = 0b1111;
743 let Inst{11-10} = 0b00;
745 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
746 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
747 [/* For disassembly only; pattern left blank */]>,
748 Requires<[IsARM, HasV6]> {
750 let Inst{19-16} = 0b1111;
751 let Inst{11-10} = rot;
755 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
756 /// register and one whose operand is a register rotated by 8/16/24.
757 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
758 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
759 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
760 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
761 Requires<[IsARM, HasV6]> {
765 let Inst{19-16} = Rn;
766 let Inst{15-12} = Rd;
767 let Inst{11-10} = 0b00;
768 let Inst{9-4} = 0b000111;
771 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
773 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
774 [(set GPR:$Rd, (opnode GPR:$Rn,
775 (rotr GPR:$Rm, rot_imm:$rot)))]>,
776 Requires<[IsARM, HasV6]> {
781 let Inst{19-16} = Rn;
782 let Inst{15-12} = Rd;
783 let Inst{11-10} = rot;
784 let Inst{9-4} = 0b000111;
789 // For disassembly only.
790 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
791 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
792 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
793 [/* For disassembly only; pattern left blank */]>,
794 Requires<[IsARM, HasV6]> {
795 let Inst{11-10} = 0b00;
797 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
799 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
800 [/* For disassembly only; pattern left blank */]>,
801 Requires<[IsARM, HasV6]> {
804 let Inst{19-16} = Rn;
805 let Inst{11-10} = rot;
809 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
810 let Uses = [CPSR] in {
811 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
812 bit Commutable = 0> {
813 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
814 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
815 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
821 let Inst{15-12} = Rd;
822 let Inst{19-16} = Rn;
823 let Inst{11-0} = imm;
825 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
826 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
827 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
832 let Inst{11-4} = 0b00000000;
834 let isCommutable = Commutable;
836 let Inst{15-12} = Rd;
837 let Inst{19-16} = Rn;
839 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
840 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
841 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
847 let Inst{11-0} = shift;
848 let Inst{15-12} = Rd;
849 let Inst{19-16} = Rn;
852 // Carry setting variants
853 let Defs = [CPSR] in {
854 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
855 bit Commutable = 0> {
856 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
857 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
858 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
863 let Inst{15-12} = Rd;
864 let Inst{19-16} = Rn;
865 let Inst{11-0} = imm;
869 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
870 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
871 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
876 let Inst{11-4} = 0b00000000;
877 let isCommutable = Commutable;
879 let Inst{15-12} = Rd;
880 let Inst{19-16} = Rn;
884 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
885 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
886 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
891 let Inst{11-0} = shift;
892 let Inst{15-12} = Rd;
893 let Inst{19-16} = Rn;
901 let canFoldAsLoad = 1, isReMaterializable = 1 in {
902 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
903 InstrItinClass iir, PatFrag opnode> {
904 // Note: We use the complex addrmode_imm12 rather than just an input
905 // GPR and a constrained immediate so that we can use this to match
906 // frame index references and avoid matching constant pool references.
907 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
908 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
909 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
912 let Inst{23} = addr{12}; // U (add = ('U' == 1))
913 let Inst{19-16} = addr{16-13}; // Rn
914 let Inst{15-12} = Rt;
915 let Inst{11-0} = addr{11-0}; // imm12
917 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
918 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
919 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
922 let Inst{23} = shift{12}; // U (add = ('U' == 1))
923 let Inst{19-16} = shift{16-13}; // Rn
924 let Inst{15-12} = Rt;
925 let Inst{11-0} = shift{11-0};
930 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
931 InstrItinClass iir, PatFrag opnode> {
932 // Note: We use the complex addrmode_imm12 rather than just an input
933 // GPR and a constrained immediate so that we can use this to match
934 // frame index references and avoid matching constant pool references.
935 def i12 : AI2ldst<0b010, 0, isByte, (outs),
936 (ins GPR:$Rt, addrmode_imm12:$addr),
937 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
938 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
941 let Inst{23} = addr{12}; // U (add = ('U' == 1))
942 let Inst{19-16} = addr{16-13}; // Rn
943 let Inst{15-12} = Rt;
944 let Inst{11-0} = addr{11-0}; // imm12
946 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
947 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
948 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
951 let Inst{23} = shift{12}; // U (add = ('U' == 1))
952 let Inst{19-16} = shift{16-13}; // Rn
953 let Inst{15-12} = Rt;
954 let Inst{11-0} = shift{11-0};
957 //===----------------------------------------------------------------------===//
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
962 // Miscellaneous Instructions.
965 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
966 /// the function. The first operand is the ID# for this instruction, the second
967 /// is the index into the MachineConstantPool that this is, the third is the
968 /// size in bytes of this constant pool entry.
969 let neverHasSideEffects = 1, isNotDuplicable = 1 in
970 def CONSTPOOL_ENTRY :
971 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
972 i32imm:$size), NoItinerary, []>;
974 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
975 // from removing one half of the matched pairs. That breaks PEI, which assumes
976 // these will always be in pairs, and asserts if it finds otherwise. Better way?
977 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
979 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
980 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
982 def ADJCALLSTACKDOWN :
983 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
984 [(ARMcallseq_start timm:$amt)]>;
987 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
988 [/* For disassembly only; pattern left blank */]>,
989 Requires<[IsARM, HasV6T2]> {
990 let Inst{27-16} = 0b001100100000;
991 let Inst{15-8} = 0b11110000;
992 let Inst{7-0} = 0b00000000;
995 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
996 [/* For disassembly only; pattern left blank */]>,
997 Requires<[IsARM, HasV6T2]> {
998 let Inst{27-16} = 0b001100100000;
999 let Inst{15-8} = 0b11110000;
1000 let Inst{7-0} = 0b00000001;
1003 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1004 [/* For disassembly only; pattern left blank */]>,
1005 Requires<[IsARM, HasV6T2]> {
1006 let Inst{27-16} = 0b001100100000;
1007 let Inst{15-8} = 0b11110000;
1008 let Inst{7-0} = 0b00000010;
1011 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1012 [/* For disassembly only; pattern left blank */]>,
1013 Requires<[IsARM, HasV6T2]> {
1014 let Inst{27-16} = 0b001100100000;
1015 let Inst{15-8} = 0b11110000;
1016 let Inst{7-0} = 0b00000011;
1019 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1021 [/* For disassembly only; pattern left blank */]>,
1022 Requires<[IsARM, HasV6]> {
1027 let Inst{15-12} = Rd;
1028 let Inst{19-16} = Rn;
1029 let Inst{27-20} = 0b01101000;
1030 let Inst{7-4} = 0b1011;
1031 let Inst{11-8} = 0b1111;
1034 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1035 [/* For disassembly only; pattern left blank */]>,
1036 Requires<[IsARM, HasV6T2]> {
1037 let Inst{27-16} = 0b001100100000;
1038 let Inst{15-8} = 0b11110000;
1039 let Inst{7-0} = 0b00000100;
1042 // The i32imm operand $val can be used by a debugger to store more information
1043 // about the breakpoint.
1044 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1045 [/* For disassembly only; pattern left blank */]>,
1048 let Inst{3-0} = val{3-0};
1049 let Inst{19-8} = val{15-4};
1050 let Inst{27-20} = 0b00010010;
1051 let Inst{7-4} = 0b0111;
1054 // Change Processor State is a system instruction -- for disassembly only.
1055 // The singleton $opt operand contains the following information:
1056 // opt{4-0} = mode from Inst{4-0}
1057 // opt{5} = changemode from Inst{17}
1058 // opt{8-6} = AIF from Inst{8-6}
1059 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1060 // FIXME: Integrated assembler will need these split out.
1061 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1062 [/* For disassembly only; pattern left blank */]>,
1064 let Inst{31-28} = 0b1111;
1065 let Inst{27-20} = 0b00010000;
1070 // Preload signals the memory system of possible future data/instruction access.
1071 // These are for disassembly only.
1072 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1074 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1075 !strconcat(opc, "\t$addr"),
1076 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1079 let Inst{31-26} = 0b111101;
1080 let Inst{25} = 0; // 0 for immediate form
1081 let Inst{24} = data;
1082 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1083 let Inst{22} = read;
1084 let Inst{21-20} = 0b01;
1085 let Inst{19-16} = addr{16-13}; // Rn
1086 let Inst{15-12} = Rt;
1087 let Inst{11-0} = addr{11-0}; // imm12
1090 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1091 !strconcat(opc, "\t$shift"),
1092 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1095 let Inst{31-26} = 0b111101;
1096 let Inst{25} = 1; // 1 for register form
1097 let Inst{24} = data;
1098 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1099 let Inst{22} = read;
1100 let Inst{21-20} = 0b01;
1101 let Inst{19-16} = shift{16-13}; // Rn
1102 let Inst{11-0} = shift{11-0};
1106 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1107 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1108 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1110 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1112 [/* For disassembly only; pattern left blank */]>,
1115 let Inst{31-10} = 0b1111000100000001000000;
1120 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1121 [/* For disassembly only; pattern left blank */]>,
1122 Requires<[IsARM, HasV7]> {
1124 let Inst{27-4} = 0b001100100000111100001111;
1125 let Inst{3-0} = opt;
1128 // A5.4 Permanently UNDEFINED instructions.
1129 let isBarrier = 1, isTerminator = 1 in
1130 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1133 let Inst = 0xe7ffdefe;
1136 // Address computation and loads and stores in PIC mode.
1137 let isNotDuplicable = 1 in {
1138 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1140 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1142 let AddedComplexity = 10 in {
1143 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1145 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1147 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1149 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1151 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1153 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1155 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1157 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1159 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1161 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1163 let AddedComplexity = 10 in {
1164 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1165 IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1167 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1168 IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1170 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1171 IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1173 } // isNotDuplicable = 1
1176 // LEApcrel - Load a pc-relative address into a register without offending the
1178 let neverHasSideEffects = 1 in {
1179 let isReMaterializable = 1 in
1180 // FIXME: We want one cannonical LEApcrel instruction and to express one or
1181 // both of these as pseudo-instructions that get expanded to it.
1182 def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1184 "adr$p\t$Rd, #$label", []>;
1186 } // neverHasSideEffects
1187 def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
1188 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1190 "adr$p\t$Rd, #${label}_${id}", []> {
1193 let Inst{31-28} = p;
1194 let Inst{27-25} = 0b001;
1196 let Inst{19-16} = 0b1111;
1197 let Inst{15-12} = Rd;
1198 // FIXME: Add label encoding/fixup
1201 //===----------------------------------------------------------------------===//
1202 // Control Flow Instructions.
1205 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1207 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1208 "bx", "\tlr", [(ARMretflag)]>,
1209 Requires<[IsARM, HasV4T]> {
1210 let Inst{27-0} = 0b0001001011111111111100011110;
1214 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1215 "mov", "\tpc, lr", [(ARMretflag)]>,
1216 Requires<[IsARM, NoV4T]> {
1217 let Inst{27-0} = 0b0001101000001111000000001110;
1221 // Indirect branches
1222 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1224 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1225 [(brind GPR:$dst)]>,
1226 Requires<[IsARM, HasV4T]> {
1228 let Inst{31-4} = 0b1110000100101111111111110001;
1229 let Inst{3-0} = dst;
1233 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1234 [(brind GPR:$dst)]>,
1235 Requires<[IsARM, NoV4T]> {
1237 let Inst{31-4} = 0b1110000110100000111100000000;
1238 let Inst{3-0} = dst;
1242 // On non-Darwin platforms R9 is callee-saved.
1244 Defs = [R0, R1, R2, R3, R12, LR,
1245 D0, D1, D2, D3, D4, D5, D6, D7,
1246 D16, D17, D18, D19, D20, D21, D22, D23,
1247 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1248 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1249 IIC_Br, "bl\t$func",
1250 [(ARMcall tglobaladdr:$func)]>,
1251 Requires<[IsARM, IsNotDarwin]> {
1252 let Inst{31-28} = 0b1110;
1254 let Inst{23-0} = func;
1257 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1258 IIC_Br, "bl", "\t$func",
1259 [(ARMcall_pred tglobaladdr:$func)]>,
1260 Requires<[IsARM, IsNotDarwin]> {
1262 let Inst{23-0} = func;
1266 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1267 IIC_Br, "blx\t$func",
1268 [(ARMcall GPR:$func)]>,
1269 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1271 let Inst{31-4} = 0b1110000100101111111111110011;
1272 let Inst{3-0} = func;
1276 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1277 // FIXME: x2 insn patterns like this need to be pseudo instructions.
1278 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1279 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1280 [(ARMcall_nolink tGPR:$func)]>,
1281 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1283 let Inst{27-4} = 0b000100101111111111110001;
1284 let Inst{3-0} = func;
1288 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1289 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1290 [(ARMcall_nolink tGPR:$func)]>,
1291 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1293 let Inst{27-4} = 0b000110100000111100000000;
1294 let Inst{3-0} = func;
1298 // On Darwin R9 is call-clobbered.
1300 Defs = [R0, R1, R2, R3, R9, R12, LR,
1301 D0, D1, D2, D3, D4, D5, D6, D7,
1302 D16, D17, D18, D19, D20, D21, D22, D23,
1303 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1304 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1305 IIC_Br, "bl\t$func",
1306 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1307 let Inst{31-28} = 0b1110;
1309 let Inst{23-0} = func;
1312 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1313 IIC_Br, "bl", "\t$func",
1314 [(ARMcall_pred tglobaladdr:$func)]>,
1315 Requires<[IsARM, IsDarwin]> {
1317 let Inst{23-0} = func;
1321 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1322 IIC_Br, "blx\t$func",
1323 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1325 let Inst{31-4} = 0b1110000100101111111111110011;
1326 let Inst{3-0} = func;
1330 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1331 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1332 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1333 [(ARMcall_nolink tGPR:$func)]>,
1334 Requires<[IsARM, HasV4T, IsDarwin]> {
1336 let Inst{27-4} = 0b000100101111111111110001;
1337 let Inst{3-0} = func;
1341 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1342 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1343 [(ARMcall_nolink tGPR:$func)]>,
1344 Requires<[IsARM, NoV4T, IsDarwin]> {
1346 let Inst{27-4} = 0b000110100000111100000000;
1347 let Inst{3-0} = func;
1353 // FIXME: These should probably be xformed into the non-TC versions of the
1354 // instructions as part of MC lowering.
1355 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1357 let Defs = [R0, R1, R2, R3, R9, R12,
1358 D0, D1, D2, D3, D4, D5, D6, D7,
1359 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1360 D27, D28, D29, D30, D31, PC],
1362 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1364 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1366 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1368 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1370 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1371 IIC_Br, "b\t$dst @ TAILCALL",
1372 []>, Requires<[IsDarwin]>;
1374 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1375 IIC_Br, "b.w\t$dst @ TAILCALL",
1376 []>, Requires<[IsDarwin]>;
1378 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1379 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1380 []>, Requires<[IsDarwin]> {
1382 let Inst{31-4} = 0b1110000100101111111111110001;
1383 let Inst{3-0} = dst;
1387 // Non-Darwin versions (the difference is R9).
1388 let Defs = [R0, R1, R2, R3, R12,
1389 D0, D1, D2, D3, D4, D5, D6, D7,
1390 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1391 D27, D28, D29, D30, D31, PC],
1393 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1395 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1397 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1399 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1401 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1402 IIC_Br, "b\t$dst @ TAILCALL",
1403 []>, Requires<[IsARM, IsNotDarwin]>;
1405 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1406 IIC_Br, "b.w\t$dst @ TAILCALL",
1407 []>, Requires<[IsThumb, IsNotDarwin]>;
1409 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1410 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1411 []>, Requires<[IsNotDarwin]> {
1413 let Inst{31-4} = 0b1110000100101111111111110001;
1414 let Inst{3-0} = dst;
1419 let isBranch = 1, isTerminator = 1 in {
1420 // B is "predicable" since it can be xformed into a Bcc.
1421 let isBarrier = 1 in {
1422 let isPredicable = 1 in
1423 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1424 "b\t$target", [(br bb:$target)]> {
1426 let Inst{31-28} = 0b1110;
1427 let Inst{23-0} = target;
1430 let isNotDuplicable = 1, isIndirectBranch = 1,
1431 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1432 isCodeGenOnly = 1 in {
1433 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1434 IIC_Br, "mov\tpc, $target$jt",
1435 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1436 let Inst{11-4} = 0b00000000;
1437 let Inst{15-12} = 0b1111;
1438 let Inst{20} = 0; // S Bit
1439 let Inst{24-21} = 0b1101;
1440 let Inst{27-25} = 0b000;
1442 def BR_JTm : JTI<(outs),
1443 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1444 IIC_Br, "ldr\tpc, $target$jt",
1445 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1447 let Inst{15-12} = 0b1111;
1448 let Inst{20} = 1; // L bit
1449 let Inst{21} = 0; // W bit
1450 let Inst{22} = 0; // B bit
1451 let Inst{24} = 1; // P bit
1452 let Inst{27-25} = 0b011;
1454 def BR_JTadd : ARMPseudoInst<(outs),
1455 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1457 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1459 } // isNotDuplicable = 1, isIndirectBranch = 1
1462 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1463 // a two-value operand where a dag node expects two operands. :(
1464 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1465 IIC_Br, "b", "\t$target",
1466 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1468 let Inst{23-0} = target;
1472 // Branch and Exchange Jazelle -- for disassembly only
1473 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1474 [/* For disassembly only; pattern left blank */]> {
1475 let Inst{23-20} = 0b0010;
1476 //let Inst{19-8} = 0xfff;
1477 let Inst{7-4} = 0b0010;
1480 // Secure Monitor Call is a system instruction -- for disassembly only
1481 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1482 [/* For disassembly only; pattern left blank */]> {
1484 let Inst{23-4} = 0b01100000000000000111;
1485 let Inst{3-0} = opt;
1488 // Supervisor Call (Software Interrupt) -- for disassembly only
1490 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1491 [/* For disassembly only; pattern left blank */]> {
1493 let Inst{23-0} = svc;
1497 // Store Return State is a system instruction -- for disassembly only
1498 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1499 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1500 NoItinerary, "srs${amode}\tsp!, $mode",
1501 [/* For disassembly only; pattern left blank */]> {
1502 let Inst{31-28} = 0b1111;
1503 let Inst{22-20} = 0b110; // W = 1
1506 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1507 NoItinerary, "srs${amode}\tsp, $mode",
1508 [/* For disassembly only; pattern left blank */]> {
1509 let Inst{31-28} = 0b1111;
1510 let Inst{22-20} = 0b100; // W = 0
1513 // Return From Exception is a system instruction -- for disassembly only
1514 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1515 NoItinerary, "rfe${amode}\t$base!",
1516 [/* For disassembly only; pattern left blank */]> {
1517 let Inst{31-28} = 0b1111;
1518 let Inst{22-20} = 0b011; // W = 1
1521 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1522 NoItinerary, "rfe${amode}\t$base",
1523 [/* For disassembly only; pattern left blank */]> {
1524 let Inst{31-28} = 0b1111;
1525 let Inst{22-20} = 0b001; // W = 0
1527 } // isCodeGenOnly = 1
1529 //===----------------------------------------------------------------------===//
1530 // Load / store Instructions.
1536 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1537 UnOpFrag<(load node:$Src)>>;
1538 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1539 UnOpFrag<(zextloadi8 node:$Src)>>;
1540 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1541 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1542 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1543 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1545 // Special LDR for loads from non-pc-relative constpools.
1546 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1547 isReMaterializable = 1 in
1548 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1549 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1553 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1554 let Inst{19-16} = 0b1111;
1555 let Inst{15-12} = Rt;
1556 let Inst{11-0} = addr{11-0}; // imm12
1559 // Loads with zero extension
1560 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1561 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1562 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1564 // Loads with sign extension
1565 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1566 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1567 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1569 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1570 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1571 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1573 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1574 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1575 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1576 // how to represent that such that tblgen is happy and we don't
1577 // mark this codegen only?
1579 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1580 (ins addrmode3:$addr), LdMiscFrm,
1581 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1582 []>, Requires<[IsARM, HasV5TE]>;
1586 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1587 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1588 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1589 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1591 // {13} 1 == Rm, 0 == imm12
1595 let Inst{25} = addr{13};
1596 let Inst{23} = addr{12};
1597 let Inst{19-16} = addr{17-14};
1598 let Inst{11-0} = addr{11-0};
1600 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1601 (ins GPR:$Rn, am2offset:$offset),
1602 IndexModePost, LdFrm, itin,
1603 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1604 // {13} 1 == Rm, 0 == imm12
1609 let Inst{25} = offset{13};
1610 let Inst{23} = offset{12};
1611 let Inst{19-16} = Rn;
1612 let Inst{11-0} = offset{11-0};
1616 let mayLoad = 1, neverHasSideEffects = 1 in {
1617 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1618 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1621 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1622 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1623 (ins addrmode3:$addr), IndexModePre,
1625 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1627 let Inst{23} = addr{8}; // U bit
1628 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1629 let Inst{19-16} = addr{12-9}; // Rn
1630 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1631 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1633 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1634 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1636 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1639 let Inst{23} = offset{8}; // U bit
1640 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1641 let Inst{19-16} = Rn;
1642 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1643 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1647 let mayLoad = 1, neverHasSideEffects = 1 in {
1648 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1649 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1650 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1651 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1652 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1653 } // mayLoad = 1, neverHasSideEffects = 1
1655 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1656 let mayLoad = 1, neverHasSideEffects = 1 in {
1657 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1658 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1659 LdFrm, IIC_iLoad_ru,
1660 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1661 let Inst{21} = 1; // overwrite
1663 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1664 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1665 LdFrm, IIC_iLoad_bh_ru,
1666 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1667 let Inst{21} = 1; // overwrite
1669 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1670 (ins GPR:$base, am3offset:$offset), IndexModePost,
1671 LdMiscFrm, IIC_iLoad_bh_ru,
1672 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1673 let Inst{21} = 1; // overwrite
1675 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1676 (ins GPR:$base, am3offset:$offset), IndexModePost,
1677 LdMiscFrm, IIC_iLoad_bh_ru,
1678 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1679 let Inst{21} = 1; // overwrite
1681 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1682 (ins GPR:$base, am3offset:$offset), IndexModePost,
1683 LdMiscFrm, IIC_iLoad_bh_ru,
1684 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1685 let Inst{21} = 1; // overwrite
1691 // Stores with truncate
1692 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1693 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1694 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1697 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1698 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1699 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1700 StMiscFrm, IIC_iStore_d_r,
1701 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1704 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1705 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1706 IndexModePre, StFrm, IIC_iStore_ru,
1707 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1709 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1711 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1712 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1713 IndexModePost, StFrm, IIC_iStore_ru,
1714 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1716 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1718 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1719 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1720 IndexModePre, StFrm, IIC_iStore_bh_ru,
1721 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1722 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1723 GPR:$Rn, am2offset:$offset))]>;
1724 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1725 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1726 IndexModePost, StFrm, IIC_iStore_bh_ru,
1727 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1728 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1729 GPR:$Rn, am2offset:$offset))]>;
1731 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1732 (ins GPR:$src, GPR:$base,am3offset:$offset),
1733 StMiscFrm, IIC_iStore_ru,
1734 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1736 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1738 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1739 (ins GPR:$src, GPR:$base,am3offset:$offset),
1740 StMiscFrm, IIC_iStore_bh_ru,
1741 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1742 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1743 GPR:$base, am3offset:$offset))]>;
1745 // For disassembly only
1746 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1747 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1748 StMiscFrm, IIC_iStore_d_ru,
1749 "strd", "\t$src1, $src2, [$base, $offset]!",
1750 "$base = $base_wb", []>;
1752 // For disassembly only
1753 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1754 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1755 StMiscFrm, IIC_iStore_d_ru,
1756 "strd", "\t$src1, $src2, [$base], $offset",
1757 "$base = $base_wb", []>;
1759 // STRT, STRBT, and STRHT are for disassembly only.
1761 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1762 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1763 IndexModeNone, StFrm, IIC_iStore_ru,
1764 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1765 [/* For disassembly only; pattern left blank */]> {
1766 let Inst{21} = 1; // overwrite
1769 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1770 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1771 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1772 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1773 [/* For disassembly only; pattern left blank */]> {
1774 let Inst{21} = 1; // overwrite
1777 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1778 (ins GPR:$src, GPR:$base,am3offset:$offset),
1779 StMiscFrm, IIC_iStore_bh_ru,
1780 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1781 [/* For disassembly only; pattern left blank */]> {
1782 let Inst{21} = 1; // overwrite
1785 //===----------------------------------------------------------------------===//
1786 // Load / store multiple Instructions.
1789 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1790 InstrItinClass itin, InstrItinClass itin_upd> {
1792 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1793 IndexModeNone, f, itin,
1794 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1795 let Inst{24-23} = 0b01; // Increment After
1796 let Inst{21} = 0; // No writeback
1797 let Inst{20} = L_bit;
1800 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1801 IndexModeUpd, f, itin_upd,
1802 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1803 let Inst{24-23} = 0b01; // Increment After
1804 let Inst{21} = 1; // Writeback
1805 let Inst{20} = L_bit;
1808 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1809 IndexModeNone, f, itin,
1810 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1811 let Inst{24-23} = 0b00; // Decrement After
1812 let Inst{21} = 0; // No writeback
1813 let Inst{20} = L_bit;
1816 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1817 IndexModeUpd, f, itin_upd,
1818 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1819 let Inst{24-23} = 0b00; // Decrement After
1820 let Inst{21} = 1; // Writeback
1821 let Inst{20} = L_bit;
1824 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1825 IndexModeNone, f, itin,
1826 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1827 let Inst{24-23} = 0b10; // Decrement Before
1828 let Inst{21} = 0; // No writeback
1829 let Inst{20} = L_bit;
1832 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1833 IndexModeUpd, f, itin_upd,
1834 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1835 let Inst{24-23} = 0b10; // Decrement Before
1836 let Inst{21} = 1; // Writeback
1837 let Inst{20} = L_bit;
1840 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1841 IndexModeNone, f, itin,
1842 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1843 let Inst{24-23} = 0b11; // Increment Before
1844 let Inst{21} = 0; // No writeback
1845 let Inst{20} = L_bit;
1848 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1849 IndexModeUpd, f, itin_upd,
1850 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1851 let Inst{24-23} = 0b11; // Increment Before
1852 let Inst{21} = 1; // Writeback
1853 let Inst{20} = L_bit;
1857 let neverHasSideEffects = 1 in {
1859 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1860 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1862 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1863 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1865 } // neverHasSideEffects
1867 // Load / Store Multiple Mnemnoic Aliases
1868 def : MnemonicAlias<"ldm", "ldmia">;
1869 def : MnemonicAlias<"stm", "stmia">;
1871 // FIXME: remove when we have a way to marking a MI with these properties.
1872 // FIXME: Should pc be an implicit operand like PICADD, etc?
1873 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1874 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1875 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1876 reglist:$regs, variable_ops),
1877 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1878 "ldmia${p}\t$Rn!, $regs",
1880 let Inst{24-23} = 0b01; // Increment After
1881 let Inst{21} = 1; // Writeback
1882 let Inst{20} = 1; // Load
1885 //===----------------------------------------------------------------------===//
1886 // Move Instructions.
1889 let neverHasSideEffects = 1 in
1890 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1891 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1895 let Inst{11-4} = 0b00000000;
1898 let Inst{15-12} = Rd;
1901 // A version for the smaller set of tail call registers.
1902 let neverHasSideEffects = 1 in
1903 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1904 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1908 let Inst{11-4} = 0b00000000;
1911 let Inst{15-12} = Rd;
1914 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1915 DPSoRegFrm, IIC_iMOVsr,
1916 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1920 let Inst{15-12} = Rd;
1921 let Inst{11-0} = src;
1925 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1926 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1927 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1931 let Inst{15-12} = Rd;
1932 let Inst{19-16} = 0b0000;
1933 let Inst{11-0} = imm;
1936 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1937 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1939 "movw", "\t$Rd, $imm",
1940 [(set GPR:$Rd, imm0_65535:$imm)]>,
1941 Requires<[IsARM, HasV6T2]>, UnaryDP {
1944 let Inst{15-12} = Rd;
1945 let Inst{11-0} = imm{11-0};
1946 let Inst{19-16} = imm{15-12};
1951 let Constraints = "$src = $Rd" in
1952 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1954 "movt", "\t$Rd, $imm",
1956 (or (and GPR:$src, 0xffff),
1957 lo16AllZero:$imm))]>, UnaryDP,
1958 Requires<[IsARM, HasV6T2]> {
1961 let Inst{15-12} = Rd;
1962 let Inst{11-0} = imm{11-0};
1963 let Inst{19-16} = imm{15-12};
1968 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1969 Requires<[IsARM, HasV6T2]>;
1971 let Uses = [CPSR] in
1972 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1973 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1976 // These aren't really mov instructions, but we have to define them this way
1977 // due to flag operands.
1979 let Defs = [CPSR] in {
1980 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1981 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1983 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1984 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1988 //===----------------------------------------------------------------------===//
1989 // Extend Instructions.
1994 defm SXTB : AI_ext_rrot<0b01101010,
1995 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1996 defm SXTH : AI_ext_rrot<0b01101011,
1997 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1999 defm SXTAB : AI_exta_rrot<0b01101010,
2000 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2001 defm SXTAH : AI_exta_rrot<0b01101011,
2002 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2004 // For disassembly only
2005 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2007 // For disassembly only
2008 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2012 let AddedComplexity = 16 in {
2013 defm UXTB : AI_ext_rrot<0b01101110,
2014 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2015 defm UXTH : AI_ext_rrot<0b01101111,
2016 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2017 defm UXTB16 : AI_ext_rrot<0b01101100,
2018 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2020 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2021 // The transformation should probably be done as a combiner action
2022 // instead so we can include a check for masking back in the upper
2023 // eight bits of the source into the lower eight bits of the result.
2024 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2025 // (UXTB16r_rot GPR:$Src, 24)>;
2026 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2027 (UXTB16r_rot GPR:$Src, 8)>;
2029 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2030 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2031 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2032 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2035 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2036 // For disassembly only
2037 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2040 def SBFX : I<(outs GPR:$Rd),
2041 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2042 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2043 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2044 Requires<[IsARM, HasV6T2]> {
2049 let Inst{27-21} = 0b0111101;
2050 let Inst{6-4} = 0b101;
2051 let Inst{20-16} = width;
2052 let Inst{15-12} = Rd;
2053 let Inst{11-7} = lsb;
2057 def UBFX : I<(outs GPR:$Rd),
2058 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2059 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2060 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2061 Requires<[IsARM, HasV6T2]> {
2066 let Inst{27-21} = 0b0111111;
2067 let Inst{6-4} = 0b101;
2068 let Inst{20-16} = width;
2069 let Inst{15-12} = Rd;
2070 let Inst{11-7} = lsb;
2074 //===----------------------------------------------------------------------===//
2075 // Arithmetic Instructions.
2078 defm ADD : AsI1_bin_irs<0b0100, "add",
2079 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2080 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2081 defm SUB : AsI1_bin_irs<0b0010, "sub",
2082 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2083 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2085 // ADD and SUB with 's' bit set.
2086 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2087 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2088 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2089 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2090 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2091 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2093 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2094 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2095 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2096 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2097 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2098 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2099 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2100 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2102 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2103 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2104 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2109 let Inst{15-12} = Rd;
2110 let Inst{19-16} = Rn;
2111 let Inst{11-0} = imm;
2114 // The reg/reg form is only defined for the disassembler; for codegen it is
2115 // equivalent to SUBrr.
2116 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2117 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2118 [/* For disassembly only; pattern left blank */]> {
2122 let Inst{11-4} = 0b00000000;
2125 let Inst{15-12} = Rd;
2126 let Inst{19-16} = Rn;
2129 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2130 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2131 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2136 let Inst{11-0} = shift;
2137 let Inst{15-12} = Rd;
2138 let Inst{19-16} = Rn;
2141 // RSB with 's' bit set.
2142 let Defs = [CPSR] in {
2143 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2144 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2145 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2151 let Inst{15-12} = Rd;
2152 let Inst{19-16} = Rn;
2153 let Inst{11-0} = imm;
2155 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2156 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2157 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2163 let Inst{11-0} = shift;
2164 let Inst{15-12} = Rd;
2165 let Inst{19-16} = Rn;
2169 let Uses = [CPSR] in {
2170 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2171 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2172 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2178 let Inst{15-12} = Rd;
2179 let Inst{19-16} = Rn;
2180 let Inst{11-0} = imm;
2182 // The reg/reg form is only defined for the disassembler; for codegen it is
2183 // equivalent to SUBrr.
2184 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2185 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2186 [/* For disassembly only; pattern left blank */]> {
2190 let Inst{11-4} = 0b00000000;
2193 let Inst{15-12} = Rd;
2194 let Inst{19-16} = Rn;
2196 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2197 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2198 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2204 let Inst{11-0} = shift;
2205 let Inst{15-12} = Rd;
2206 let Inst{19-16} = Rn;
2210 // FIXME: Allow these to be predicated.
2211 let Defs = [CPSR], Uses = [CPSR] in {
2212 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2213 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2214 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2221 let Inst{15-12} = Rd;
2222 let Inst{19-16} = Rn;
2223 let Inst{11-0} = imm;
2225 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2226 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2227 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2234 let Inst{11-0} = shift;
2235 let Inst{15-12} = Rd;
2236 let Inst{19-16} = Rn;
2240 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2241 // The assume-no-carry-in form uses the negation of the input since add/sub
2242 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2243 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2245 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2246 (SUBri GPR:$src, so_imm_neg:$imm)>;
2247 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2248 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2249 // The with-carry-in form matches bitwise not instead of the negation.
2250 // Effectively, the inverse interpretation of the carry flag already accounts
2251 // for part of the negation.
2252 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2253 (SBCri GPR:$src, so_imm_not:$imm)>;
2255 // Note: These are implemented in C++ code, because they have to generate
2256 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2258 // (mul X, 2^n+1) -> (add (X << n), X)
2259 // (mul X, 2^n-1) -> (rsb X, (X << n))
2261 // ARM Arithmetic Instruction -- for disassembly only
2262 // GPR:$dst = GPR:$a op GPR:$b
2263 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2264 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2265 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2266 opc, "\t$Rd, $Rn, $Rm", pattern> {
2270 let Inst{27-20} = op27_20;
2271 let Inst{11-4} = op11_4;
2272 let Inst{19-16} = Rn;
2273 let Inst{15-12} = Rd;
2277 // Saturating add/subtract -- for disassembly only
2279 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2280 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2281 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2282 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2283 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2284 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2286 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2287 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2288 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2289 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2290 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2291 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2292 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2293 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2294 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2295 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2296 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2297 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2299 // Signed/Unsigned add/subtract -- for disassembly only
2301 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2302 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2303 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2304 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2305 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2306 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2307 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2308 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2309 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2310 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2311 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2312 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2314 // Signed/Unsigned halving add/subtract -- for disassembly only
2316 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2317 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2318 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2319 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2320 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2321 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2322 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2323 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2324 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2325 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2326 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2327 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2329 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2331 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2332 MulFrm /* for convenience */, NoItinerary, "usad8",
2333 "\t$Rd, $Rn, $Rm", []>,
2334 Requires<[IsARM, HasV6]> {
2338 let Inst{27-20} = 0b01111000;
2339 let Inst{15-12} = 0b1111;
2340 let Inst{7-4} = 0b0001;
2341 let Inst{19-16} = Rd;
2342 let Inst{11-8} = Rm;
2345 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2346 MulFrm /* for convenience */, NoItinerary, "usada8",
2347 "\t$Rd, $Rn, $Rm, $Ra", []>,
2348 Requires<[IsARM, HasV6]> {
2353 let Inst{27-20} = 0b01111000;
2354 let Inst{7-4} = 0b0001;
2355 let Inst{19-16} = Rd;
2356 let Inst{15-12} = Ra;
2357 let Inst{11-8} = Rm;
2361 // Signed/Unsigned saturate -- for disassembly only
2363 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2364 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2365 [/* For disassembly only; pattern left blank */]> {
2370 let Inst{27-21} = 0b0110101;
2371 let Inst{5-4} = 0b01;
2372 let Inst{20-16} = sat_imm;
2373 let Inst{15-12} = Rd;
2374 let Inst{11-7} = sh{7-3};
2375 let Inst{6} = sh{0};
2379 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2380 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2381 [/* For disassembly only; pattern left blank */]> {
2385 let Inst{27-20} = 0b01101010;
2386 let Inst{11-4} = 0b11110011;
2387 let Inst{15-12} = Rd;
2388 let Inst{19-16} = sat_imm;
2392 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2393 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2394 [/* For disassembly only; pattern left blank */]> {
2399 let Inst{27-21} = 0b0110111;
2400 let Inst{5-4} = 0b01;
2401 let Inst{15-12} = Rd;
2402 let Inst{11-7} = sh{7-3};
2403 let Inst{6} = sh{0};
2404 let Inst{20-16} = sat_imm;
2408 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2409 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2410 [/* For disassembly only; pattern left blank */]> {
2414 let Inst{27-20} = 0b01101110;
2415 let Inst{11-4} = 0b11110011;
2416 let Inst{15-12} = Rd;
2417 let Inst{19-16} = sat_imm;
2421 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2422 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2424 //===----------------------------------------------------------------------===//
2425 // Bitwise Instructions.
2428 defm AND : AsI1_bin_irs<0b0000, "and",
2429 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2430 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2431 defm ORR : AsI1_bin_irs<0b1100, "orr",
2432 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2433 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2434 defm EOR : AsI1_bin_irs<0b0001, "eor",
2435 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2436 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2437 defm BIC : AsI1_bin_irs<0b1110, "bic",
2438 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2439 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2441 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2442 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2443 "bfc", "\t$Rd, $imm", "$src = $Rd",
2444 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2445 Requires<[IsARM, HasV6T2]> {
2448 let Inst{27-21} = 0b0111110;
2449 let Inst{6-0} = 0b0011111;
2450 let Inst{15-12} = Rd;
2451 let Inst{11-7} = imm{4-0}; // lsb
2452 let Inst{20-16} = imm{9-5}; // width
2455 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2456 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2457 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2458 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2459 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2460 bf_inv_mask_imm:$imm))]>,
2461 Requires<[IsARM, HasV6T2]> {
2465 let Inst{27-21} = 0b0111110;
2466 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2467 let Inst{15-12} = Rd;
2468 let Inst{11-7} = imm{4-0}; // lsb
2469 let Inst{20-16} = imm{9-5}; // width
2473 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2474 "mvn", "\t$Rd, $Rm",
2475 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2479 let Inst{19-16} = 0b0000;
2480 let Inst{11-4} = 0b00000000;
2481 let Inst{15-12} = Rd;
2484 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2485 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2486 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2490 let Inst{19-16} = 0b0000;
2491 let Inst{15-12} = Rd;
2492 let Inst{11-0} = shift;
2494 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2495 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2496 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2497 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2501 let Inst{19-16} = 0b0000;
2502 let Inst{15-12} = Rd;
2503 let Inst{11-0} = imm;
2506 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2507 (BICri GPR:$src, so_imm_not:$imm)>;
2509 //===----------------------------------------------------------------------===//
2510 // Multiply Instructions.
2512 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2513 string opc, string asm, list<dag> pattern>
2514 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2518 let Inst{19-16} = Rd;
2519 let Inst{11-8} = Rm;
2522 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2523 string opc, string asm, list<dag> pattern>
2524 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2529 let Inst{19-16} = RdHi;
2530 let Inst{15-12} = RdLo;
2531 let Inst{11-8} = Rm;
2535 let isCommutable = 1 in
2536 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2537 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2538 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2540 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2541 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2542 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2544 let Inst{15-12} = Ra;
2547 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2548 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2549 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2550 Requires<[IsARM, HasV6T2]> {
2555 let Inst{19-16} = Rd;
2556 let Inst{15-12} = Ra;
2557 let Inst{11-8} = Rm;
2561 // Extra precision multiplies with low / high results
2563 let neverHasSideEffects = 1 in {
2564 let isCommutable = 1 in {
2565 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2566 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2567 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2569 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2570 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2571 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2574 // Multiply + accumulate
2575 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2576 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2577 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2579 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2580 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2581 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2583 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2584 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2585 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2586 Requires<[IsARM, HasV6]> {
2591 let Inst{19-16} = RdLo;
2592 let Inst{15-12} = RdHi;
2593 let Inst{11-8} = Rm;
2596 } // neverHasSideEffects
2598 // Most significant word multiply
2599 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2600 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2601 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2602 Requires<[IsARM, HasV6]> {
2603 let Inst{15-12} = 0b1111;
2606 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2607 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2608 [/* For disassembly only; pattern left blank */]>,
2609 Requires<[IsARM, HasV6]> {
2610 let Inst{15-12} = 0b1111;
2613 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2614 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2615 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2616 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2617 Requires<[IsARM, HasV6]>;
2619 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2620 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2621 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2622 [/* For disassembly only; pattern left blank */]>,
2623 Requires<[IsARM, HasV6]>;
2625 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2626 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2627 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2628 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2629 Requires<[IsARM, HasV6]>;
2631 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2632 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2633 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2634 [/* For disassembly only; pattern left blank */]>,
2635 Requires<[IsARM, HasV6]>;
2637 multiclass AI_smul<string opc, PatFrag opnode> {
2638 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2639 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2640 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2641 (sext_inreg GPR:$Rm, i16)))]>,
2642 Requires<[IsARM, HasV5TE]>;
2644 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2645 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2646 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2647 (sra GPR:$Rm, (i32 16))))]>,
2648 Requires<[IsARM, HasV5TE]>;
2650 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2651 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2652 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2653 (sext_inreg GPR:$Rm, i16)))]>,
2654 Requires<[IsARM, HasV5TE]>;
2656 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2657 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2658 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2659 (sra GPR:$Rm, (i32 16))))]>,
2660 Requires<[IsARM, HasV5TE]>;
2662 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2663 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2664 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2665 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2666 Requires<[IsARM, HasV5TE]>;
2668 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2669 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2670 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2671 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2672 Requires<[IsARM, HasV5TE]>;
2676 multiclass AI_smla<string opc, PatFrag opnode> {
2677 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2678 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2679 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2680 [(set GPR:$Rd, (add GPR:$Ra,
2681 (opnode (sext_inreg GPR:$Rn, i16),
2682 (sext_inreg GPR:$Rm, i16))))]>,
2683 Requires<[IsARM, HasV5TE]>;
2685 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2686 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2687 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2688 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2689 (sra GPR:$Rm, (i32 16)))))]>,
2690 Requires<[IsARM, HasV5TE]>;
2692 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2693 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2694 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2695 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2696 (sext_inreg GPR:$Rm, i16))))]>,
2697 Requires<[IsARM, HasV5TE]>;
2699 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2700 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2701 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2702 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2703 (sra GPR:$Rm, (i32 16)))))]>,
2704 Requires<[IsARM, HasV5TE]>;
2706 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2707 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2708 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2709 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2710 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2711 Requires<[IsARM, HasV5TE]>;
2713 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2714 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2715 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2716 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2717 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2718 Requires<[IsARM, HasV5TE]>;
2721 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2722 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2724 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2725 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2726 (ins GPR:$Rn, GPR:$Rm),
2727 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2728 [/* For disassembly only; pattern left blank */]>,
2729 Requires<[IsARM, HasV5TE]>;
2731 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2732 (ins GPR:$Rn, GPR:$Rm),
2733 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2734 [/* For disassembly only; pattern left blank */]>,
2735 Requires<[IsARM, HasV5TE]>;
2737 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2738 (ins GPR:$Rn, GPR:$Rm),
2739 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2740 [/* For disassembly only; pattern left blank */]>,
2741 Requires<[IsARM, HasV5TE]>;
2743 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2744 (ins GPR:$Rn, GPR:$Rm),
2745 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2746 [/* For disassembly only; pattern left blank */]>,
2747 Requires<[IsARM, HasV5TE]>;
2749 // Helper class for AI_smld -- for disassembly only
2750 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2751 InstrItinClass itin, string opc, string asm>
2752 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2759 let Inst{21-20} = 0b00;
2760 let Inst{22} = long;
2761 let Inst{27-23} = 0b01110;
2762 let Inst{11-8} = Rm;
2765 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2766 InstrItinClass itin, string opc, string asm>
2767 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2769 let Inst{15-12} = 0b1111;
2770 let Inst{19-16} = Rd;
2772 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2773 InstrItinClass itin, string opc, string asm>
2774 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2776 let Inst{15-12} = Ra;
2778 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2779 InstrItinClass itin, string opc, string asm>
2780 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2783 let Inst{19-16} = RdHi;
2784 let Inst{15-12} = RdLo;
2787 multiclass AI_smld<bit sub, string opc> {
2789 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2790 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2792 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2793 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2795 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2796 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2797 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2799 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2800 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2801 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2805 defm SMLA : AI_smld<0, "smla">;
2806 defm SMLS : AI_smld<1, "smls">;
2808 multiclass AI_sdml<bit sub, string opc> {
2810 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2811 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2812 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2813 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2816 defm SMUA : AI_sdml<0, "smua">;
2817 defm SMUS : AI_sdml<1, "smus">;
2819 //===----------------------------------------------------------------------===//
2820 // Misc. Arithmetic Instructions.
2823 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2824 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2825 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2827 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2828 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2829 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2830 Requires<[IsARM, HasV6T2]>;
2832 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2833 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2834 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2836 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2837 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2839 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2840 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2841 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2842 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2843 Requires<[IsARM, HasV6]>;
2845 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2846 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2849 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2850 (shl GPR:$Rm, (i32 8))), i16))]>,
2851 Requires<[IsARM, HasV6]>;
2853 def lsl_shift_imm : SDNodeXForm<imm, [{
2854 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2855 return CurDAG->getTargetConstant(Sh, MVT::i32);
2858 def lsl_amt : PatLeaf<(i32 imm), [{
2859 return (N->getZExtValue() < 32);
2862 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2863 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2864 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2865 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2866 (and (shl GPR:$Rm, lsl_amt:$sh),
2868 Requires<[IsARM, HasV6]>;
2870 // Alternate cases for PKHBT where identities eliminate some nodes.
2871 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2872 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2873 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2874 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2876 def asr_shift_imm : SDNodeXForm<imm, [{
2877 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2878 return CurDAG->getTargetConstant(Sh, MVT::i32);
2881 def asr_amt : PatLeaf<(i32 imm), [{
2882 return (N->getZExtValue() <= 32);
2885 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2886 // will match the pattern below.
2887 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2888 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2889 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2890 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2891 (and (sra GPR:$Rm, asr_amt:$sh),
2893 Requires<[IsARM, HasV6]>;
2895 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2896 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2897 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2898 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2899 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2900 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2901 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2903 //===----------------------------------------------------------------------===//
2904 // Comparison Instructions...
2907 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2908 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2909 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2911 // FIXME: We have to be careful when using the CMN instruction and comparison
2912 // with 0. One would expect these two pieces of code should give identical
2928 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2929 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2930 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2931 // value of r0 and the carry bit (because the "carry bit" parameter to
2932 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2933 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2934 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2935 // parameter to AddWithCarry is defined as 0).
2937 // When x is 0 and unsigned:
2941 // ~x + 1 = 0x1 0000 0000
2942 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2944 // Therefore, we should disable CMN when comparing against zero, until we can
2945 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2946 // when it's a comparison which doesn't look at the 'carry' flag).
2948 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2950 // This is related to <rdar://problem/7569620>.
2952 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2953 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2955 // Note that TST/TEQ don't set all the same flags that CMP does!
2956 defm TST : AI1_cmp_irs<0b1000, "tst",
2957 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2958 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2959 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2960 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2961 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2963 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2964 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2965 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2966 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2967 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2968 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2970 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2971 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2973 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2974 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2976 // Pseudo i64 compares for some floating point compares.
2977 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2979 def BCCi64 : PseudoInst<(outs),
2980 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2982 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2984 def BCCZi64 : PseudoInst<(outs),
2985 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2986 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2987 } // usesCustomInserter
2990 // Conditional moves
2991 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2992 // a two-value operand where a dag node expects two operands. :(
2993 // FIXME: These should all be pseudo-instructions that get expanded to
2994 // the normal MOV instructions. That would fix the dependency on
2995 // special casing them in tblgen.
2996 let neverHasSideEffects = 1 in {
2997 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2998 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2999 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3000 RegConstraint<"$false = $Rd">, UnaryDP {
3005 let Inst{15-12} = Rd;
3006 let Inst{11-4} = 0b00000000;
3010 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3011 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3012 "mov", "\t$Rd, $shift",
3013 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3014 RegConstraint<"$false = $Rd">, UnaryDP {
3019 let Inst{19-16} = 0;
3020 let Inst{15-12} = Rd;
3021 let Inst{11-0} = shift;
3024 let isMoveImm = 1 in
3025 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3027 "movw", "\t$Rd, $imm",
3029 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3035 let Inst{19-16} = imm{15-12};
3036 let Inst{15-12} = Rd;
3037 let Inst{11-0} = imm{11-0};
3040 let isMoveImm = 1 in
3041 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3042 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3043 "mov", "\t$Rd, $imm",
3044 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3045 RegConstraint<"$false = $Rd">, UnaryDP {
3050 let Inst{19-16} = 0b0000;
3051 let Inst{15-12} = Rd;
3052 let Inst{11-0} = imm;
3055 // Two instruction predicate mov immediate.
3056 let isMoveImm = 1 in
3057 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3058 (ins GPR:$false, i32imm:$src, pred:$p),
3059 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3061 let isMoveImm = 1 in
3062 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3063 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3064 "mvn", "\t$Rd, $imm",
3065 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3066 RegConstraint<"$false = $Rd">, UnaryDP {
3071 let Inst{19-16} = 0b0000;
3072 let Inst{15-12} = Rd;
3073 let Inst{11-0} = imm;
3075 } // neverHasSideEffects
3077 //===----------------------------------------------------------------------===//
3078 // Atomic operations intrinsics
3081 def memb_opt : Operand<i32> {
3082 let PrintMethod = "printMemBOption";
3085 // memory barriers protect the atomic sequences
3086 let hasSideEffects = 1 in {
3087 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3088 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3089 Requires<[IsARM, HasDB]> {
3091 let Inst{31-4} = 0xf57ff05;
3092 let Inst{3-0} = opt;
3095 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3096 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3097 [(ARMMemBarrierMCR GPR:$zero)]>,
3098 Requires<[IsARM, HasV6]> {
3099 // FIXME: add encoding
3103 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3105 [/* For disassembly only; pattern left blank */]>,
3106 Requires<[IsARM, HasDB]> {
3108 let Inst{31-4} = 0xf57ff04;
3109 let Inst{3-0} = opt;
3112 // ISB has only full system option -- for disassembly only
3113 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3114 Requires<[IsARM, HasDB]> {
3115 let Inst{31-4} = 0xf57ff06;
3116 let Inst{3-0} = 0b1111;
3119 let usesCustomInserter = 1 in {
3120 let Uses = [CPSR] in {
3121 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3123 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3124 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3126 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3127 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3129 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3130 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3132 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3133 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3135 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3136 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3138 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3139 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3141 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3142 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3144 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3145 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3147 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3148 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3150 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3151 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3153 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3154 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3156 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3157 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3159 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3160 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3162 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3163 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3165 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3166 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3168 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3169 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3171 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3172 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3173 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3174 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3176 def ATOMIC_SWAP_I8 : PseudoInst<
3177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3178 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3179 def ATOMIC_SWAP_I16 : PseudoInst<
3180 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3181 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3182 def ATOMIC_SWAP_I32 : PseudoInst<
3183 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3184 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3186 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3188 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3189 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3191 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3192 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3194 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3198 let mayLoad = 1 in {
3199 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3200 "ldrexb", "\t$Rt, [$Rn]",
3202 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3203 "ldrexh", "\t$Rt, [$Rn]",
3205 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3206 "ldrex", "\t$Rt, [$Rn]",
3208 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3210 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3214 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3215 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3217 "strexb", "\t$Rd, $src, [$Rn]",
3219 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3221 "strexh", "\t$Rd, $Rt, [$Rn]",
3223 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3225 "strex", "\t$Rd, $Rt, [$Rn]",
3227 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3228 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3230 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3234 // Clear-Exclusive is for disassembly only.
3235 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3236 [/* For disassembly only; pattern left blank */]>,
3237 Requires<[IsARM, HasV7]> {
3238 let Inst{31-0} = 0b11110101011111111111000000011111;
3241 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3242 let mayLoad = 1 in {
3243 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3244 [/* For disassembly only; pattern left blank */]>;
3245 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3246 [/* For disassembly only; pattern left blank */]>;
3249 //===----------------------------------------------------------------------===//
3253 // __aeabi_read_tp preserves the registers r1-r3.
3254 // FIXME: This needs to be a pseudo of some sort so that we can get the
3255 // encoding right, complete with fixup for the aeabi_read_tp function.
3257 Defs = [R0, R12, LR, CPSR] in {
3258 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3259 "bl\t__aeabi_read_tp",
3260 [(set R0, ARMthread_pointer)]>;
3263 //===----------------------------------------------------------------------===//
3264 // SJLJ Exception handling intrinsics
3265 // eh_sjlj_setjmp() is an instruction sequence to store the return
3266 // address and save #0 in R0 for the non-longjmp case.
3267 // Since by its nature we may be coming from some other function to get
3268 // here, and we're using the stack frame for the containing function to
3269 // save/restore registers, we can't keep anything live in regs across
3270 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3271 // when we get here from a longjmp(). We force everthing out of registers
3272 // except for our own input by listing the relevant registers in Defs. By
3273 // doing so, we also cause the prologue/epilogue code to actively preserve
3274 // all of the callee-saved resgisters, which is exactly what we want.
3275 // A constant value is passed in $val, and we use the location as a scratch.
3277 // These are pseudo-instructions and are lowered to individual MC-insts, so
3278 // no encoding information is necessary.
3280 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3281 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3282 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3283 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3284 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3285 AddrModeNone, SizeSpecial, IndexModeNone,
3286 Pseudo, NoItinerary, "", "",
3287 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3288 Requires<[IsARM, HasVFP2]>;
3292 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3293 hasSideEffects = 1, isBarrier = 1 in {
3294 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3295 AddrModeNone, SizeSpecial, IndexModeNone,
3296 Pseudo, NoItinerary, "", "",
3297 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3298 Requires<[IsARM, NoVFP]>;
3301 // FIXME: Non-Darwin version(s)
3302 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3303 Defs = [ R7, LR, SP ] in {
3304 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3305 AddrModeNone, SizeSpecial, IndexModeNone,
3306 Pseudo, NoItinerary, "", "",
3307 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3308 Requires<[IsARM, IsDarwin]>;
3311 // eh.sjlj.dispatchsetup pseudo-instruction.
3312 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3313 // handled when the pseudo is expanded (which happens before any passes
3314 // that need the instruction size).
3315 let isBarrier = 1, hasSideEffects = 1 in
3316 def Int_eh_sjlj_dispatchsetup :
3317 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3318 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3319 Requires<[IsDarwin]>;
3321 //===----------------------------------------------------------------------===//
3322 // Non-Instruction Patterns
3325 // Large immediate handling.
3327 // 32-bit immediate using two piece so_imms or movw + movt.
3328 // This is a single pseudo instruction, the benefit is that it can be remat'd
3329 // as a single unit instead of having to handle reg inputs.
3330 // FIXME: Remove this when we can do generalized remat.
3331 let isReMaterializable = 1, isMoveImm = 1 in
3332 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3333 [(set GPR:$dst, (arm_i32imm:$src))]>,
3336 // ConstantPool, GlobalAddress, and JumpTable
3337 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3338 Requires<[IsARM, DontUseMovt]>;
3339 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3340 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3341 Requires<[IsARM, UseMovt]>;
3342 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3343 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3345 // TODO: add,sub,and, 3-instr forms?
3348 def : ARMPat<(ARMtcret tcGPR:$dst),
3349 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3351 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3352 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3354 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3355 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3357 def : ARMPat<(ARMtcret tcGPR:$dst),
3358 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3360 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3361 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3363 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3364 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3367 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3368 Requires<[IsARM, IsNotDarwin]>;
3369 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3370 Requires<[IsARM, IsDarwin]>;
3372 // zextload i1 -> zextload i8
3373 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3374 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3376 // extload -> zextload
3377 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3378 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3379 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3380 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3382 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3384 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3385 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3388 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3389 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3390 (SMULBB GPR:$a, GPR:$b)>;
3391 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3392 (SMULBB GPR:$a, GPR:$b)>;
3393 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3394 (sra GPR:$b, (i32 16))),
3395 (SMULBT GPR:$a, GPR:$b)>;
3396 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3397 (SMULBT GPR:$a, GPR:$b)>;
3398 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3399 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3400 (SMULTB GPR:$a, GPR:$b)>;
3401 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3402 (SMULTB GPR:$a, GPR:$b)>;
3403 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3405 (SMULWB GPR:$a, GPR:$b)>;
3406 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3407 (SMULWB GPR:$a, GPR:$b)>;
3409 def : ARMV5TEPat<(add GPR:$acc,
3410 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3411 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3412 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3413 def : ARMV5TEPat<(add GPR:$acc,
3414 (mul sext_16_node:$a, sext_16_node:$b)),
3415 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3416 def : ARMV5TEPat<(add GPR:$acc,
3417 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3418 (sra GPR:$b, (i32 16)))),
3419 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3420 def : ARMV5TEPat<(add GPR:$acc,
3421 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3422 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3423 def : ARMV5TEPat<(add GPR:$acc,
3424 (mul (sra GPR:$a, (i32 16)),
3425 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3426 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3427 def : ARMV5TEPat<(add GPR:$acc,
3428 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3429 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3430 def : ARMV5TEPat<(add GPR:$acc,
3431 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3433 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3434 def : ARMV5TEPat<(add GPR:$acc,
3435 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3436 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3438 //===----------------------------------------------------------------------===//
3442 include "ARMInstrThumb.td"
3444 //===----------------------------------------------------------------------===//
3448 include "ARMInstrThumb2.td"
3450 //===----------------------------------------------------------------------===//
3451 // Floating Point Support
3454 include "ARMInstrVFP.td"
3456 //===----------------------------------------------------------------------===//
3457 // Advanced SIMD (NEON) Support
3460 include "ARMInstrNEON.td"
3462 //===----------------------------------------------------------------------===//
3463 // Coprocessor Instructions. For disassembly only.
3466 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3467 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3468 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3469 [/* For disassembly only; pattern left blank */]> {
3473 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3474 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3475 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3476 [/* For disassembly only; pattern left blank */]> {
3477 let Inst{31-28} = 0b1111;
3481 class ACI<dag oops, dag iops, string opc, string asm>
3482 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3483 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3484 let Inst{27-25} = 0b110;
3487 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3489 def _OFFSET : ACI<(outs),
3490 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3491 opc, "\tp$cop, cr$CRd, $addr"> {
3492 let Inst{31-28} = op31_28;
3493 let Inst{24} = 1; // P = 1
3494 let Inst{21} = 0; // W = 0
3495 let Inst{22} = 0; // D = 0
3496 let Inst{20} = load;
3499 def _PRE : ACI<(outs),
3500 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3501 opc, "\tp$cop, cr$CRd, $addr!"> {
3502 let Inst{31-28} = op31_28;
3503 let Inst{24} = 1; // P = 1
3504 let Inst{21} = 1; // W = 1
3505 let Inst{22} = 0; // D = 0
3506 let Inst{20} = load;
3509 def _POST : ACI<(outs),
3510 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3511 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3512 let Inst{31-28} = op31_28;
3513 let Inst{24} = 0; // P = 0
3514 let Inst{21} = 1; // W = 1
3515 let Inst{22} = 0; // D = 0
3516 let Inst{20} = load;
3519 def _OPTION : ACI<(outs),
3520 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3521 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3522 let Inst{31-28} = op31_28;
3523 let Inst{24} = 0; // P = 0
3524 let Inst{23} = 1; // U = 1
3525 let Inst{21} = 0; // W = 0
3526 let Inst{22} = 0; // D = 0
3527 let Inst{20} = load;
3530 def L_OFFSET : ACI<(outs),
3531 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3532 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3533 let Inst{31-28} = op31_28;
3534 let Inst{24} = 1; // P = 1
3535 let Inst{21} = 0; // W = 0
3536 let Inst{22} = 1; // D = 1
3537 let Inst{20} = load;
3540 def L_PRE : ACI<(outs),
3541 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3542 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3543 let Inst{31-28} = op31_28;
3544 let Inst{24} = 1; // P = 1
3545 let Inst{21} = 1; // W = 1
3546 let Inst{22} = 1; // D = 1
3547 let Inst{20} = load;
3550 def L_POST : ACI<(outs),
3551 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3552 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3553 let Inst{31-28} = op31_28;
3554 let Inst{24} = 0; // P = 0
3555 let Inst{21} = 1; // W = 1
3556 let Inst{22} = 1; // D = 1
3557 let Inst{20} = load;
3560 def L_OPTION : ACI<(outs),
3561 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3562 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3563 let Inst{31-28} = op31_28;
3564 let Inst{24} = 0; // P = 0
3565 let Inst{23} = 1; // U = 1
3566 let Inst{21} = 0; // W = 0
3567 let Inst{22} = 1; // D = 1
3568 let Inst{20} = load;
3572 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3573 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3574 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3575 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3577 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3578 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3579 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3580 [/* For disassembly only; pattern left blank */]> {
3585 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3586 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3587 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3588 [/* For disassembly only; pattern left blank */]> {
3589 let Inst{31-28} = 0b1111;
3594 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3595 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3596 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3597 [/* For disassembly only; pattern left blank */]> {
3602 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3603 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3604 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3605 [/* For disassembly only; pattern left blank */]> {
3606 let Inst{31-28} = 0b1111;
3611 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3612 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3613 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3614 [/* For disassembly only; pattern left blank */]> {
3615 let Inst{23-20} = 0b0100;
3618 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3619 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3620 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3621 [/* For disassembly only; pattern left blank */]> {
3622 let Inst{31-28} = 0b1111;
3623 let Inst{23-20} = 0b0100;
3626 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3627 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3628 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3629 [/* For disassembly only; pattern left blank */]> {
3630 let Inst{23-20} = 0b0101;
3633 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3634 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3635 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3636 [/* For disassembly only; pattern left blank */]> {
3637 let Inst{31-28} = 0b1111;
3638 let Inst{23-20} = 0b0101;
3641 //===----------------------------------------------------------------------===//
3642 // Move between special register and ARM core register -- for disassembly only
3645 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3646 [/* For disassembly only; pattern left blank */]> {
3647 let Inst{23-20} = 0b0000;
3648 let Inst{7-4} = 0b0000;
3651 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3652 [/* For disassembly only; pattern left blank */]> {
3653 let Inst{23-20} = 0b0100;
3654 let Inst{7-4} = 0b0000;
3657 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3658 "msr", "\tcpsr$mask, $src",
3659 [/* For disassembly only; pattern left blank */]> {
3660 let Inst{23-20} = 0b0010;
3661 let Inst{7-4} = 0b0000;
3664 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3665 "msr", "\tcpsr$mask, $a",
3666 [/* For disassembly only; pattern left blank */]> {
3667 let Inst{23-20} = 0b0010;
3668 let Inst{7-4} = 0b0000;
3671 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3672 "msr", "\tspsr$mask, $src",
3673 [/* For disassembly only; pattern left blank */]> {
3674 let Inst{23-20} = 0b0110;
3675 let Inst{7-4} = 0b0000;
3678 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3679 "msr", "\tspsr$mask, $a",
3680 [/* For disassembly only; pattern left blank */]> {
3681 let Inst{23-20} = 0b0110;
3682 let Inst{7-4} = 0b0000;