1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 // An 'and' node with a single use.
273 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
274 return N->hasOneUse();
277 // An 'xor' node with a single use.
278 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
279 return N->hasOneUse();
282 //===----------------------------------------------------------------------===//
283 // Operand Definitions.
287 def brtarget : Operand<OtherVT> {
288 let EncoderMethod = "getBranchTargetOpValue";
292 def bltarget : Operand<i32> {
293 // Encoded the same as branch targets.
294 let EncoderMethod = "getBranchTargetOpValue";
297 // A list of registers separated by comma. Used by load/store multiple.
298 def RegListAsmOperand : AsmOperandClass {
299 let Name = "RegList";
300 let SuperClasses = [];
303 def DPRRegListAsmOperand : AsmOperandClass {
304 let Name = "DPRRegList";
305 let SuperClasses = [];
308 def SPRRegListAsmOperand : AsmOperandClass {
309 let Name = "SPRRegList";
310 let SuperClasses = [];
313 def reglist : Operand<i32> {
314 let EncoderMethod = "getRegisterListOpValue";
315 let ParserMatchClass = RegListAsmOperand;
316 let PrintMethod = "printRegisterList";
319 def dpr_reglist : Operand<i32> {
320 let EncoderMethod = "getRegisterListOpValue";
321 let ParserMatchClass = DPRRegListAsmOperand;
322 let PrintMethod = "printRegisterList";
325 def spr_reglist : Operand<i32> {
326 let EncoderMethod = "getRegisterListOpValue";
327 let ParserMatchClass = SPRRegListAsmOperand;
328 let PrintMethod = "printRegisterList";
331 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
332 def cpinst_operand : Operand<i32> {
333 let PrintMethod = "printCPInstOperand";
336 def jtblock_operand : Operand<i32> {
337 let PrintMethod = "printJTBlockOperand";
339 def jt2block_operand : Operand<i32> {
340 let PrintMethod = "printJT2BlockOperand";
344 def pclabel : Operand<i32> {
345 let PrintMethod = "printPCLabel";
348 def neon_vcvt_imm32 : Operand<i32> {
349 let EncoderMethod = "getNEONVcvtImm32OpValue";
352 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
353 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
354 int32_t v = (int32_t)N->getZExtValue();
355 return v == 8 || v == 16 || v == 24; }]> {
356 let EncoderMethod = "getRotImmOpValue";
359 // shift_imm: An integer that encodes a shift amount and the type of shift
360 // (currently either asr or lsl) using the same encoding used for the
361 // immediates in so_reg operands.
362 def shift_imm : Operand<i32> {
363 let PrintMethod = "printShiftImmOperand";
366 // shifter_operand operands: so_reg and so_imm.
367 def so_reg : Operand<i32>, // reg reg imm
368 ComplexPattern<i32, 3, "SelectShifterOperandReg",
369 [shl,srl,sra,rotr]> {
370 let EncoderMethod = "getSORegOpValue";
371 let PrintMethod = "printSORegOperand";
372 let MIOperandInfo = (ops GPR, GPR, i32imm);
374 def shift_so_reg : Operand<i32>, // reg reg imm
375 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
376 [shl,srl,sra,rotr]> {
377 let EncoderMethod = "getSORegOpValue";
378 let PrintMethod = "printSORegOperand";
379 let MIOperandInfo = (ops GPR, GPR, i32imm);
382 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
383 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
384 // represented in the imm field in the same 12-bit form that they are encoded
385 // into so_imm instructions: the 8-bit immediate is the least significant bits
386 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
387 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
388 let EncoderMethod = "getSOImmOpValue";
389 let PrintMethod = "printSOImmOperand";
392 // Break so_imm's up into two pieces. This handles immediates with up to 16
393 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
394 // get the first/second pieces.
395 def so_imm2part : PatLeaf<(imm), [{
396 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
399 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
401 def arm_i32imm : PatLeaf<(imm), [{
402 if (Subtarget->hasV6T2Ops())
404 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
407 def so_imm2part_1 : SDNodeXForm<imm, [{
408 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
409 return CurDAG->getTargetConstant(V, MVT::i32);
412 def so_imm2part_2 : SDNodeXForm<imm, [{
413 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
414 return CurDAG->getTargetConstant(V, MVT::i32);
417 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
418 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
420 let PrintMethod = "printSOImm2PartOperand";
423 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
424 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
425 return CurDAG->getTargetConstant(V, MVT::i32);
428 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
429 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
430 return CurDAG->getTargetConstant(V, MVT::i32);
433 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
434 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
435 return (int32_t)N->getZExtValue() < 32;
438 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
439 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
440 return (int32_t)N->getZExtValue() < 32;
442 let EncoderMethod = "getImmMinusOneOpValue";
445 // For movt/movw - sets the MC Encoder method.
446 // The imm is split into imm{15-12}, imm{11-0}
448 def movt_imm : Operand<i32> {
449 let EncoderMethod = "getMovtImmOpValue";
452 // Define ARM specific addressing modes.
455 // addrmode_imm12 := reg +/- imm12
457 def addrmode_imm12 : Operand<i32>,
458 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
459 // 12-bit immediate operand. Note that instructions using this encode
460 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
461 // immediate values are as normal.
463 let EncoderMethod = "getAddrModeImm12OpValue";
464 let PrintMethod = "printAddrModeImm12Operand";
465 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
467 // ldst_so_reg := reg +/- reg shop imm
469 def ldst_so_reg : Operand<i32>,
470 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
471 let EncoderMethod = "getLdStSORegOpValue";
472 // FIXME: Simplify the printer
473 let PrintMethod = "printAddrMode2Operand";
474 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
477 // addrmode2 := reg +/- imm12
478 // := reg +/- reg shop imm
480 def addrmode2 : Operand<i32>,
481 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
482 string EncoderMethod = "getAddrMode2OpValue";
483 let PrintMethod = "printAddrMode2Operand";
484 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
487 def am2offset : Operand<i32>,
488 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
489 [], [SDNPWantRoot]> {
490 string EncoderMethod = "getAddrMode2OffsetOpValue";
491 let PrintMethod = "printAddrMode2OffsetOperand";
492 let MIOperandInfo = (ops GPR, i32imm);
495 // addrmode3 := reg +/- reg
496 // addrmode3 := reg +/- imm8
498 def addrmode3 : Operand<i32>,
499 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
500 let EncoderMethod = "getAddrMode3OpValue";
501 let PrintMethod = "printAddrMode3Operand";
502 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
505 def am3offset : Operand<i32>,
506 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
507 [], [SDNPWantRoot]> {
508 let EncoderMethod = "getAddrMode3OffsetOpValue";
509 let PrintMethod = "printAddrMode3OffsetOperand";
510 let MIOperandInfo = (ops GPR, i32imm);
513 // ldstm_mode := {ia, ib, da, db}
515 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
516 let EncoderMethod = "getLdStmModeOpValue";
517 let PrintMethod = "printLdStmModeOperand";
520 def MemMode5AsmOperand : AsmOperandClass {
521 let Name = "MemMode5";
522 let SuperClasses = [];
525 // addrmode5 := reg +/- imm8*4
527 def addrmode5 : Operand<i32>,
528 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
529 let PrintMethod = "printAddrMode5Operand";
530 let MIOperandInfo = (ops GPR:$base, i32imm);
531 let ParserMatchClass = MemMode5AsmOperand;
532 let EncoderMethod = "getAddrMode5OpValue";
535 // addrmode6 := reg with optional writeback
537 def addrmode6 : Operand<i32>,
538 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
539 let PrintMethod = "printAddrMode6Operand";
540 let MIOperandInfo = (ops GPR:$addr, i32imm);
541 let EncoderMethod = "getAddrMode6AddressOpValue";
544 def am6offset : Operand<i32> {
545 let PrintMethod = "printAddrMode6OffsetOperand";
546 let MIOperandInfo = (ops GPR);
547 let EncoderMethod = "getAddrMode6OffsetOpValue";
550 // addrmodepc := pc + reg
552 def addrmodepc : Operand<i32>,
553 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
554 let PrintMethod = "printAddrModePCOperand";
555 let MIOperandInfo = (ops GPR, i32imm);
558 def nohash_imm : Operand<i32> {
559 let PrintMethod = "printNoHashImmediate";
562 //===----------------------------------------------------------------------===//
564 include "ARMInstrFormats.td"
566 //===----------------------------------------------------------------------===//
567 // Multiclass helpers...
570 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
571 /// binop that produces a value.
572 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
573 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
574 PatFrag opnode, bit Commutable = 0> {
575 // The register-immediate version is re-materializable. This is useful
576 // in particular for taking the address of a local.
577 let isReMaterializable = 1 in {
578 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
579 iii, opc, "\t$Rd, $Rn, $imm",
580 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
585 let Inst{19-16} = Rn;
586 let Inst{15-12} = Rd;
587 let Inst{11-0} = imm;
590 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
591 iir, opc, "\t$Rd, $Rn, $Rm",
592 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
597 let isCommutable = Commutable;
598 let Inst{19-16} = Rn;
599 let Inst{15-12} = Rd;
600 let Inst{11-4} = 0b00000000;
603 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
604 iis, opc, "\t$Rd, $Rn, $shift",
605 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
610 let Inst{19-16} = Rn;
611 let Inst{15-12} = Rd;
612 let Inst{11-0} = shift;
616 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
617 /// instruction modifies the CPSR register.
618 let Defs = [CPSR] in {
619 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
620 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
621 PatFrag opnode, bit Commutable = 0> {
622 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
623 iii, opc, "\t$Rd, $Rn, $imm",
624 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
630 let Inst{19-16} = Rn;
631 let Inst{15-12} = Rd;
632 let Inst{11-0} = imm;
634 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
635 iir, opc, "\t$Rd, $Rn, $Rm",
636 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
640 let isCommutable = Commutable;
643 let Inst{19-16} = Rn;
644 let Inst{15-12} = Rd;
645 let Inst{11-4} = 0b00000000;
648 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
649 iis, opc, "\t$Rd, $Rn, $shift",
650 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
656 let Inst{19-16} = Rn;
657 let Inst{15-12} = Rd;
658 let Inst{11-0} = shift;
663 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
664 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
665 /// a explicit result, only implicitly set CPSR.
666 let isCompare = 1, Defs = [CPSR] in {
667 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
668 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
669 PatFrag opnode, bit Commutable = 0> {
670 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
672 [(opnode GPR:$Rn, so_imm:$imm)]> {
677 let Inst{19-16} = Rn;
678 let Inst{15-12} = 0b0000;
679 let Inst{11-0} = imm;
681 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
683 [(opnode GPR:$Rn, GPR:$Rm)]> {
686 let isCommutable = Commutable;
689 let Inst{19-16} = Rn;
690 let Inst{15-12} = 0b0000;
691 let Inst{11-4} = 0b00000000;
694 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
695 opc, "\t$Rn, $shift",
696 [(opnode GPR:$Rn, so_reg:$shift)]> {
701 let Inst{19-16} = Rn;
702 let Inst{15-12} = 0b0000;
703 let Inst{11-0} = shift;
708 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
709 /// register and one whose operand is a register rotated by 8/16/24.
710 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
711 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
712 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
713 IIC_iEXTr, opc, "\t$Rd, $Rm",
714 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
715 Requires<[IsARM, HasV6]> {
718 let Inst{19-16} = 0b1111;
719 let Inst{15-12} = Rd;
720 let Inst{11-10} = 0b00;
723 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
724 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
725 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
726 Requires<[IsARM, HasV6]> {
730 let Inst{19-16} = 0b1111;
731 let Inst{15-12} = Rd;
732 let Inst{11-10} = rot;
737 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
738 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
739 IIC_iEXTr, opc, "\t$Rd, $Rm",
740 [/* For disassembly only; pattern left blank */]>,
741 Requires<[IsARM, HasV6]> {
742 let Inst{19-16} = 0b1111;
743 let Inst{11-10} = 0b00;
745 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
746 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
747 [/* For disassembly only; pattern left blank */]>,
748 Requires<[IsARM, HasV6]> {
750 let Inst{19-16} = 0b1111;
751 let Inst{11-10} = rot;
755 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
756 /// register and one whose operand is a register rotated by 8/16/24.
757 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
758 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
759 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
760 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
761 Requires<[IsARM, HasV6]> {
765 let Inst{19-16} = Rn;
766 let Inst{15-12} = Rd;
767 let Inst{11-10} = 0b00;
768 let Inst{9-4} = 0b000111;
771 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
773 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
774 [(set GPR:$Rd, (opnode GPR:$Rn,
775 (rotr GPR:$Rm, rot_imm:$rot)))]>,
776 Requires<[IsARM, HasV6]> {
781 let Inst{19-16} = Rn;
782 let Inst{15-12} = Rd;
783 let Inst{11-10} = rot;
784 let Inst{9-4} = 0b000111;
789 // For disassembly only.
790 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
791 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
792 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
793 [/* For disassembly only; pattern left blank */]>,
794 Requires<[IsARM, HasV6]> {
795 let Inst{11-10} = 0b00;
797 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
799 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
800 [/* For disassembly only; pattern left blank */]>,
801 Requires<[IsARM, HasV6]> {
804 let Inst{19-16} = Rn;
805 let Inst{11-10} = rot;
809 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
810 let Uses = [CPSR] in {
811 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
812 bit Commutable = 0> {
813 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
814 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
815 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
821 let Inst{15-12} = Rd;
822 let Inst{19-16} = Rn;
823 let Inst{11-0} = imm;
825 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
826 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
827 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
832 let Inst{11-4} = 0b00000000;
834 let isCommutable = Commutable;
836 let Inst{15-12} = Rd;
837 let Inst{19-16} = Rn;
839 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
840 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
841 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
847 let Inst{11-0} = shift;
848 let Inst{15-12} = Rd;
849 let Inst{19-16} = Rn;
852 // Carry setting variants
853 let Defs = [CPSR] in {
854 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
855 bit Commutable = 0> {
856 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
857 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
858 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
863 let Inst{15-12} = Rd;
864 let Inst{19-16} = Rn;
865 let Inst{11-0} = imm;
869 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
870 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
871 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
876 let Inst{11-4} = 0b00000000;
877 let isCommutable = Commutable;
879 let Inst{15-12} = Rd;
880 let Inst{19-16} = Rn;
884 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
885 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
886 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
891 let Inst{11-0} = shift;
892 let Inst{15-12} = Rd;
893 let Inst{19-16} = Rn;
901 let canFoldAsLoad = 1, isReMaterializable = 1 in {
902 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
903 InstrItinClass iir, PatFrag opnode> {
904 // Note: We use the complex addrmode_imm12 rather than just an input
905 // GPR and a constrained immediate so that we can use this to match
906 // frame index references and avoid matching constant pool references.
907 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
908 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
909 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
912 let Inst{23} = addr{12}; // U (add = ('U' == 1))
913 let Inst{19-16} = addr{16-13}; // Rn
914 let Inst{15-12} = Rt;
915 let Inst{11-0} = addr{11-0}; // imm12
917 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
918 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
919 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
922 let Inst{23} = shift{12}; // U (add = ('U' == 1))
923 let Inst{19-16} = shift{16-13}; // Rn
924 let Inst{15-12} = Rt;
925 let Inst{11-0} = shift{11-0};
930 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
931 InstrItinClass iir, PatFrag opnode> {
932 // Note: We use the complex addrmode_imm12 rather than just an input
933 // GPR and a constrained immediate so that we can use this to match
934 // frame index references and avoid matching constant pool references.
935 def i12 : AI2ldst<0b010, 0, isByte, (outs),
936 (ins GPR:$Rt, addrmode_imm12:$addr),
937 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
938 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
941 let Inst{23} = addr{12}; // U (add = ('U' == 1))
942 let Inst{19-16} = addr{16-13}; // Rn
943 let Inst{15-12} = Rt;
944 let Inst{11-0} = addr{11-0}; // imm12
946 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
947 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
948 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
951 let Inst{23} = shift{12}; // U (add = ('U' == 1))
952 let Inst{19-16} = shift{16-13}; // Rn
953 let Inst{15-12} = Rt;
954 let Inst{11-0} = shift{11-0};
957 //===----------------------------------------------------------------------===//
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
962 // Miscellaneous Instructions.
965 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
966 /// the function. The first operand is the ID# for this instruction, the second
967 /// is the index into the MachineConstantPool that this is, the third is the
968 /// size in bytes of this constant pool entry.
969 let neverHasSideEffects = 1, isNotDuplicable = 1 in
970 def CONSTPOOL_ENTRY :
971 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
972 i32imm:$size), NoItinerary, []>;
974 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
975 // from removing one half of the matched pairs. That breaks PEI, which assumes
976 // these will always be in pairs, and asserts if it finds otherwise. Better way?
977 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
979 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
980 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
982 def ADJCALLSTACKDOWN :
983 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
984 [(ARMcallseq_start timm:$amt)]>;
987 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
988 [/* For disassembly only; pattern left blank */]>,
989 Requires<[IsARM, HasV6T2]> {
990 let Inst{27-16} = 0b001100100000;
991 let Inst{15-8} = 0b11110000;
992 let Inst{7-0} = 0b00000000;
995 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
996 [/* For disassembly only; pattern left blank */]>,
997 Requires<[IsARM, HasV6T2]> {
998 let Inst{27-16} = 0b001100100000;
999 let Inst{15-8} = 0b11110000;
1000 let Inst{7-0} = 0b00000001;
1003 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1004 [/* For disassembly only; pattern left blank */]>,
1005 Requires<[IsARM, HasV6T2]> {
1006 let Inst{27-16} = 0b001100100000;
1007 let Inst{15-8} = 0b11110000;
1008 let Inst{7-0} = 0b00000010;
1011 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1012 [/* For disassembly only; pattern left blank */]>,
1013 Requires<[IsARM, HasV6T2]> {
1014 let Inst{27-16} = 0b001100100000;
1015 let Inst{15-8} = 0b11110000;
1016 let Inst{7-0} = 0b00000011;
1019 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1021 [/* For disassembly only; pattern left blank */]>,
1022 Requires<[IsARM, HasV6]> {
1027 let Inst{15-12} = Rd;
1028 let Inst{19-16} = Rn;
1029 let Inst{27-20} = 0b01101000;
1030 let Inst{7-4} = 0b1011;
1031 let Inst{11-8} = 0b1111;
1034 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1035 [/* For disassembly only; pattern left blank */]>,
1036 Requires<[IsARM, HasV6T2]> {
1037 let Inst{27-16} = 0b001100100000;
1038 let Inst{15-8} = 0b11110000;
1039 let Inst{7-0} = 0b00000100;
1042 // The i32imm operand $val can be used by a debugger to store more information
1043 // about the breakpoint.
1044 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1045 [/* For disassembly only; pattern left blank */]>,
1048 let Inst{3-0} = val{3-0};
1049 let Inst{19-8} = val{15-4};
1050 let Inst{27-20} = 0b00010010;
1051 let Inst{7-4} = 0b0111;
1054 // Change Processor State is a system instruction -- for disassembly only.
1055 // The singleton $opt operand contains the following information:
1056 // opt{4-0} = mode from Inst{4-0}
1057 // opt{5} = changemode from Inst{17}
1058 // opt{8-6} = AIF from Inst{8-6}
1059 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1060 // FIXME: Integrated assembler will need these split out.
1061 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1062 [/* For disassembly only; pattern left blank */]>,
1064 let Inst{31-28} = 0b1111;
1065 let Inst{27-20} = 0b00010000;
1070 // Preload signals the memory system of possible future data/instruction access.
1071 // These are for disassembly only.
1072 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1074 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1075 !strconcat(opc, "\t$addr"),
1076 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1079 let Inst{31-26} = 0b111101;
1080 let Inst{25} = 0; // 0 for immediate form
1081 let Inst{24} = data;
1082 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1083 let Inst{22} = read;
1084 let Inst{21-20} = 0b01;
1085 let Inst{19-16} = addr{16-13}; // Rn
1086 let Inst{15-12} = Rt;
1087 let Inst{11-0} = addr{11-0}; // imm12
1090 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1091 !strconcat(opc, "\t$shift"),
1092 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1095 let Inst{31-26} = 0b111101;
1096 let Inst{25} = 1; // 1 for register form
1097 let Inst{24} = data;
1098 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1099 let Inst{22} = read;
1100 let Inst{21-20} = 0b01;
1101 let Inst{19-16} = shift{16-13}; // Rn
1102 let Inst{11-0} = shift{11-0};
1106 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1107 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1108 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1110 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1112 [/* For disassembly only; pattern left blank */]>,
1115 let Inst{31-10} = 0b1111000100000001000000;
1120 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1121 [/* For disassembly only; pattern left blank */]>,
1122 Requires<[IsARM, HasV7]> {
1124 let Inst{27-4} = 0b001100100000111100001111;
1125 let Inst{3-0} = opt;
1128 // A5.4 Permanently UNDEFINED instructions.
1129 let isBarrier = 1, isTerminator = 1 in
1130 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1133 let Inst = 0xe7ffdefe;
1136 // Address computation and loads and stores in PIC mode.
1137 let isNotDuplicable = 1 in {
1138 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1140 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1142 let AddedComplexity = 10 in {
1143 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1145 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1147 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1149 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1151 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1153 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1155 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1157 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1159 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1161 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1163 let AddedComplexity = 10 in {
1164 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1165 IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1167 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1168 IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1170 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1171 IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1173 } // isNotDuplicable = 1
1176 // LEApcrel - Load a pc-relative address into a register without offending the
1178 let neverHasSideEffects = 1 in {
1179 let isReMaterializable = 1 in
1180 // FIXME: We want one cannonical LEApcrel instruction and to express one or
1181 // both of these as pseudo-instructions that get expanded to it.
1182 def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1184 "adr$p\t$Rd, #$label", []>;
1186 } // neverHasSideEffects
1187 def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
1188 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1190 "adr$p\t$Rd, #${label}_${id}", []> {
1193 let Inst{31-28} = p;
1194 let Inst{27-25} = 0b001;
1196 let Inst{19-16} = 0b1111;
1197 let Inst{15-12} = Rd;
1198 // FIXME: Add label encoding/fixup
1201 //===----------------------------------------------------------------------===//
1202 // Control Flow Instructions.
1205 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1207 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1208 "bx", "\tlr", [(ARMretflag)]>,
1209 Requires<[IsARM, HasV4T]> {
1210 let Inst{27-0} = 0b0001001011111111111100011110;
1214 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1215 "mov", "\tpc, lr", [(ARMretflag)]>,
1216 Requires<[IsARM, NoV4T]> {
1217 let Inst{27-0} = 0b0001101000001111000000001110;
1221 // Indirect branches
1222 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1224 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1225 [(brind GPR:$dst)]>,
1226 Requires<[IsARM, HasV4T]> {
1228 let Inst{31-4} = 0b1110000100101111111111110001;
1229 let Inst{3-0} = dst;
1233 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1234 [(brind GPR:$dst)]>,
1235 Requires<[IsARM, NoV4T]> {
1237 let Inst{31-4} = 0b1110000110100000111100000000;
1238 let Inst{3-0} = dst;
1242 // On non-Darwin platforms R9 is callee-saved.
1244 Defs = [R0, R1, R2, R3, R12, LR,
1245 D0, D1, D2, D3, D4, D5, D6, D7,
1246 D16, D17, D18, D19, D20, D21, D22, D23,
1247 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1248 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1249 IIC_Br, "bl\t$func",
1250 [(ARMcall tglobaladdr:$func)]>,
1251 Requires<[IsARM, IsNotDarwin]> {
1252 let Inst{31-28} = 0b1110;
1254 let Inst{23-0} = func;
1257 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1258 IIC_Br, "bl", "\t$func",
1259 [(ARMcall_pred tglobaladdr:$func)]>,
1260 Requires<[IsARM, IsNotDarwin]> {
1262 let Inst{23-0} = func;
1266 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1267 IIC_Br, "blx\t$func",
1268 [(ARMcall GPR:$func)]>,
1269 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1271 let Inst{31-4} = 0b1110000100101111111111110011;
1272 let Inst{3-0} = func;
1276 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1277 // FIXME: x2 insn patterns like this need to be pseudo instructions.
1278 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1279 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1280 [(ARMcall_nolink tGPR:$func)]>,
1281 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1283 let Inst{27-4} = 0b000100101111111111110001;
1284 let Inst{3-0} = func;
1288 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1289 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1290 [(ARMcall_nolink tGPR:$func)]>,
1291 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1293 let Inst{27-4} = 0b000110100000111100000000;
1294 let Inst{3-0} = func;
1298 // On Darwin R9 is call-clobbered.
1300 Defs = [R0, R1, R2, R3, R9, R12, LR,
1301 D0, D1, D2, D3, D4, D5, D6, D7,
1302 D16, D17, D18, D19, D20, D21, D22, D23,
1303 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1304 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1305 IIC_Br, "bl\t$func",
1306 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1307 let Inst{31-28} = 0b1110;
1309 let Inst{23-0} = func;
1312 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1313 IIC_Br, "bl", "\t$func",
1314 [(ARMcall_pred tglobaladdr:$func)]>,
1315 Requires<[IsARM, IsDarwin]> {
1317 let Inst{23-0} = func;
1321 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1322 IIC_Br, "blx\t$func",
1323 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1325 let Inst{31-4} = 0b1110000100101111111111110011;
1326 let Inst{3-0} = func;
1330 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1331 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1332 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1333 [(ARMcall_nolink tGPR:$func)]>,
1334 Requires<[IsARM, HasV4T, IsDarwin]> {
1336 let Inst{27-4} = 0b000100101111111111110001;
1337 let Inst{3-0} = func;
1341 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1342 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1343 [(ARMcall_nolink tGPR:$func)]>,
1344 Requires<[IsARM, NoV4T, IsDarwin]> {
1346 let Inst{27-4} = 0b000110100000111100000000;
1347 let Inst{3-0} = func;
1353 // FIXME: These should probably be xformed into the non-TC versions of the
1354 // instructions as part of MC lowering.
1355 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1357 let Defs = [R0, R1, R2, R3, R9, R12,
1358 D0, D1, D2, D3, D4, D5, D6, D7,
1359 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1360 D27, D28, D29, D30, D31, PC],
1362 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1364 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1366 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1368 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1370 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1371 IIC_Br, "b\t$dst @ TAILCALL",
1372 []>, Requires<[IsDarwin]>;
1374 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1375 IIC_Br, "b.w\t$dst @ TAILCALL",
1376 []>, Requires<[IsDarwin]>;
1378 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1379 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1380 []>, Requires<[IsDarwin]> {
1382 let Inst{31-4} = 0b1110000100101111111111110001;
1383 let Inst{3-0} = dst;
1387 // Non-Darwin versions (the difference is R9).
1388 let Defs = [R0, R1, R2, R3, R12,
1389 D0, D1, D2, D3, D4, D5, D6, D7,
1390 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1391 D27, D28, D29, D30, D31, PC],
1393 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1395 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1397 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1399 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1401 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1402 IIC_Br, "b\t$dst @ TAILCALL",
1403 []>, Requires<[IsARM, IsNotDarwin]>;
1405 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1406 IIC_Br, "b.w\t$dst @ TAILCALL",
1407 []>, Requires<[IsThumb, IsNotDarwin]>;
1409 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1410 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1411 []>, Requires<[IsNotDarwin]> {
1413 let Inst{31-4} = 0b1110000100101111111111110001;
1414 let Inst{3-0} = dst;
1419 let isBranch = 1, isTerminator = 1 in {
1420 // B is "predicable" since it can be xformed into a Bcc.
1421 let isBarrier = 1 in {
1422 let isPredicable = 1 in
1423 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1424 "b\t$target", [(br bb:$target)]> {
1426 let Inst{31-28} = 0b1110;
1427 let Inst{23-0} = target;
1430 let isNotDuplicable = 1, isIndirectBranch = 1,
1431 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1432 isCodeGenOnly = 1 in {
1433 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1434 IIC_Br, "mov\tpc, $target$jt",
1435 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1436 let Inst{11-4} = 0b00000000;
1437 let Inst{15-12} = 0b1111;
1438 let Inst{20} = 0; // S Bit
1439 let Inst{24-21} = 0b1101;
1440 let Inst{27-25} = 0b000;
1442 def BR_JTm : JTI<(outs),
1443 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1444 IIC_Br, "ldr\tpc, $target$jt",
1445 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1447 let Inst{15-12} = 0b1111;
1448 let Inst{20} = 1; // L bit
1449 let Inst{21} = 0; // W bit
1450 let Inst{22} = 0; // B bit
1451 let Inst{24} = 1; // P bit
1452 let Inst{27-25} = 0b011;
1454 def BR_JTadd : ARMPseudoInst<(outs),
1455 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1457 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1459 let SZ = SizeSpecial;
1461 } // isNotDuplicable = 1, isIndirectBranch = 1
1464 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1465 // a two-value operand where a dag node expects two operands. :(
1466 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1467 IIC_Br, "b", "\t$target",
1468 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1470 let Inst{23-0} = target;
1474 // Branch and Exchange Jazelle -- for disassembly only
1475 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1476 [/* For disassembly only; pattern left blank */]> {
1477 let Inst{23-20} = 0b0010;
1478 //let Inst{19-8} = 0xfff;
1479 let Inst{7-4} = 0b0010;
1482 // Secure Monitor Call is a system instruction -- for disassembly only
1483 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1484 [/* For disassembly only; pattern left blank */]> {
1486 let Inst{23-4} = 0b01100000000000000111;
1487 let Inst{3-0} = opt;
1490 // Supervisor Call (Software Interrupt) -- for disassembly only
1492 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1493 [/* For disassembly only; pattern left blank */]> {
1495 let Inst{23-0} = svc;
1499 // Store Return State is a system instruction -- for disassembly only
1500 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1501 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1502 NoItinerary, "srs${amode}\tsp!, $mode",
1503 [/* For disassembly only; pattern left blank */]> {
1504 let Inst{31-28} = 0b1111;
1505 let Inst{22-20} = 0b110; // W = 1
1508 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1509 NoItinerary, "srs${amode}\tsp, $mode",
1510 [/* For disassembly only; pattern left blank */]> {
1511 let Inst{31-28} = 0b1111;
1512 let Inst{22-20} = 0b100; // W = 0
1515 // Return From Exception is a system instruction -- for disassembly only
1516 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1517 NoItinerary, "rfe${amode}\t$base!",
1518 [/* For disassembly only; pattern left blank */]> {
1519 let Inst{31-28} = 0b1111;
1520 let Inst{22-20} = 0b011; // W = 1
1523 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1524 NoItinerary, "rfe${amode}\t$base",
1525 [/* For disassembly only; pattern left blank */]> {
1526 let Inst{31-28} = 0b1111;
1527 let Inst{22-20} = 0b001; // W = 0
1529 } // isCodeGenOnly = 1
1531 //===----------------------------------------------------------------------===//
1532 // Load / store Instructions.
1538 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1539 UnOpFrag<(load node:$Src)>>;
1540 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1541 UnOpFrag<(zextloadi8 node:$Src)>>;
1542 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1543 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1544 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1545 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1547 // Special LDR for loads from non-pc-relative constpools.
1548 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1549 isReMaterializable = 1 in
1550 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1551 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1555 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1556 let Inst{19-16} = 0b1111;
1557 let Inst{15-12} = Rt;
1558 let Inst{11-0} = addr{11-0}; // imm12
1561 // Loads with zero extension
1562 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1563 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1564 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1566 // Loads with sign extension
1567 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1568 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1569 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1571 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1572 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1573 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1575 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1576 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1577 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1578 // how to represent that such that tblgen is happy and we don't
1579 // mark this codegen only?
1581 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1582 (ins addrmode3:$addr), LdMiscFrm,
1583 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1584 []>, Requires<[IsARM, HasV5TE]>;
1588 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1589 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1590 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1591 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1593 // {13} 1 == Rm, 0 == imm12
1597 let Inst{25} = addr{13};
1598 let Inst{23} = addr{12};
1599 let Inst{19-16} = addr{17-14};
1600 let Inst{11-0} = addr{11-0};
1602 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1603 (ins GPR:$Rn, am2offset:$offset),
1604 IndexModePost, LdFrm, itin,
1605 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1606 // {13} 1 == Rm, 0 == imm12
1611 let Inst{25} = offset{13};
1612 let Inst{23} = offset{12};
1613 let Inst{19-16} = Rn;
1614 let Inst{11-0} = offset{11-0};
1618 let mayLoad = 1, neverHasSideEffects = 1 in {
1619 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1620 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1623 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1624 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1625 (ins addrmode3:$addr), IndexModePre,
1627 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1629 let Inst{23} = addr{8}; // U bit
1630 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1631 let Inst{19-16} = addr{12-9}; // Rn
1632 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1633 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1635 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1636 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1638 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1641 let Inst{23} = offset{8}; // U bit
1642 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1643 let Inst{19-16} = Rn;
1644 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1645 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1649 let mayLoad = 1, neverHasSideEffects = 1 in {
1650 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1651 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1652 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1653 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1654 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1655 } // mayLoad = 1, neverHasSideEffects = 1
1657 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1658 let mayLoad = 1, neverHasSideEffects = 1 in {
1659 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1660 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1661 LdFrm, IIC_iLoad_ru,
1662 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1663 let Inst{21} = 1; // overwrite
1665 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1666 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1667 LdFrm, IIC_iLoad_bh_ru,
1668 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1669 let Inst{21} = 1; // overwrite
1671 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1672 (ins GPR:$base, am3offset:$offset), IndexModePost,
1673 LdMiscFrm, IIC_iLoad_bh_ru,
1674 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1675 let Inst{21} = 1; // overwrite
1677 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1678 (ins GPR:$base, am3offset:$offset), IndexModePost,
1679 LdMiscFrm, IIC_iLoad_bh_ru,
1680 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1681 let Inst{21} = 1; // overwrite
1683 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1684 (ins GPR:$base, am3offset:$offset), IndexModePost,
1685 LdMiscFrm, IIC_iLoad_bh_ru,
1686 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1687 let Inst{21} = 1; // overwrite
1693 // Stores with truncate
1694 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1695 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1696 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1699 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1700 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1701 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1702 StMiscFrm, IIC_iStore_d_r,
1703 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1706 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1707 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1708 IndexModePre, StFrm, IIC_iStore_ru,
1709 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1711 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1713 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1714 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1715 IndexModePost, StFrm, IIC_iStore_ru,
1716 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1718 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1720 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1721 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1722 IndexModePre, StFrm, IIC_iStore_bh_ru,
1723 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1724 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1725 GPR:$Rn, am2offset:$offset))]>;
1726 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1727 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1728 IndexModePost, StFrm, IIC_iStore_bh_ru,
1729 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1730 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1731 GPR:$Rn, am2offset:$offset))]>;
1733 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1734 (ins GPR:$src, GPR:$base,am3offset:$offset),
1735 StMiscFrm, IIC_iStore_ru,
1736 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1738 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1740 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1741 (ins GPR:$src, GPR:$base,am3offset:$offset),
1742 StMiscFrm, IIC_iStore_bh_ru,
1743 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1744 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1745 GPR:$base, am3offset:$offset))]>;
1747 // For disassembly only
1748 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1749 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1750 StMiscFrm, IIC_iStore_d_ru,
1751 "strd", "\t$src1, $src2, [$base, $offset]!",
1752 "$base = $base_wb", []>;
1754 // For disassembly only
1755 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1756 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1757 StMiscFrm, IIC_iStore_d_ru,
1758 "strd", "\t$src1, $src2, [$base], $offset",
1759 "$base = $base_wb", []>;
1761 // STRT, STRBT, and STRHT are for disassembly only.
1763 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1764 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1765 IndexModeNone, StFrm, IIC_iStore_ru,
1766 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1767 [/* For disassembly only; pattern left blank */]> {
1768 let Inst{21} = 1; // overwrite
1771 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1772 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1773 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1774 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1775 [/* For disassembly only; pattern left blank */]> {
1776 let Inst{21} = 1; // overwrite
1779 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1780 (ins GPR:$src, GPR:$base,am3offset:$offset),
1781 StMiscFrm, IIC_iStore_bh_ru,
1782 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1783 [/* For disassembly only; pattern left blank */]> {
1784 let Inst{21} = 1; // overwrite
1787 //===----------------------------------------------------------------------===//
1788 // Load / store multiple Instructions.
1791 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1792 InstrItinClass itin, InstrItinClass itin_upd> {
1794 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1795 IndexModeNone, f, itin,
1796 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1797 let Inst{24-23} = 0b01; // Increment After
1798 let Inst{21} = 0; // No writeback
1799 let Inst{20} = L_bit;
1802 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1803 IndexModeUpd, f, itin_upd,
1804 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1805 let Inst{24-23} = 0b01; // Increment After
1806 let Inst{21} = 1; // Writeback
1807 let Inst{20} = L_bit;
1810 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1811 IndexModeNone, f, itin,
1812 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1813 let Inst{24-23} = 0b00; // Decrement After
1814 let Inst{21} = 0; // No writeback
1815 let Inst{20} = L_bit;
1818 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1819 IndexModeUpd, f, itin_upd,
1820 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1821 let Inst{24-23} = 0b00; // Decrement After
1822 let Inst{21} = 1; // Writeback
1823 let Inst{20} = L_bit;
1826 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1827 IndexModeNone, f, itin,
1828 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1829 let Inst{24-23} = 0b10; // Decrement Before
1830 let Inst{21} = 0; // No writeback
1831 let Inst{20} = L_bit;
1834 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1835 IndexModeUpd, f, itin_upd,
1836 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1837 let Inst{24-23} = 0b10; // Decrement Before
1838 let Inst{21} = 1; // Writeback
1839 let Inst{20} = L_bit;
1842 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1843 IndexModeNone, f, itin,
1844 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1845 let Inst{24-23} = 0b11; // Increment Before
1846 let Inst{21} = 0; // No writeback
1847 let Inst{20} = L_bit;
1850 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1851 IndexModeUpd, f, itin_upd,
1852 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1853 let Inst{24-23} = 0b11; // Increment Before
1854 let Inst{21} = 1; // Writeback
1855 let Inst{20} = L_bit;
1859 let neverHasSideEffects = 1 in {
1861 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1862 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1864 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1865 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1867 } // neverHasSideEffects
1869 // Load / Store Multiple Mnemnoic Aliases
1870 def : MnemonicAlias<"ldm", "ldmia">;
1871 def : MnemonicAlias<"stm", "stmia">;
1873 // FIXME: remove when we have a way to marking a MI with these properties.
1874 // FIXME: Should pc be an implicit operand like PICADD, etc?
1875 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1876 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1877 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1878 reglist:$regs, variable_ops),
1879 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1880 "ldmia${p}\t$Rn!, $regs",
1882 let Inst{24-23} = 0b01; // Increment After
1883 let Inst{21} = 1; // Writeback
1884 let Inst{20} = 1; // Load
1887 //===----------------------------------------------------------------------===//
1888 // Move Instructions.
1891 let neverHasSideEffects = 1 in
1892 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1893 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1897 let Inst{11-4} = 0b00000000;
1900 let Inst{15-12} = Rd;
1903 // A version for the smaller set of tail call registers.
1904 let neverHasSideEffects = 1 in
1905 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1906 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1910 let Inst{11-4} = 0b00000000;
1913 let Inst{15-12} = Rd;
1916 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1917 DPSoRegFrm, IIC_iMOVsr,
1918 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1922 let Inst{15-12} = Rd;
1923 let Inst{11-0} = src;
1927 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1928 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1929 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1933 let Inst{15-12} = Rd;
1934 let Inst{19-16} = 0b0000;
1935 let Inst{11-0} = imm;
1938 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1939 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1941 "movw", "\t$Rd, $imm",
1942 [(set GPR:$Rd, imm0_65535:$imm)]>,
1943 Requires<[IsARM, HasV6T2]>, UnaryDP {
1946 let Inst{15-12} = Rd;
1947 let Inst{11-0} = imm{11-0};
1948 let Inst{19-16} = imm{15-12};
1953 let Constraints = "$src = $Rd" in
1954 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1956 "movt", "\t$Rd, $imm",
1958 (or (and GPR:$src, 0xffff),
1959 lo16AllZero:$imm))]>, UnaryDP,
1960 Requires<[IsARM, HasV6T2]> {
1963 let Inst{15-12} = Rd;
1964 let Inst{11-0} = imm{11-0};
1965 let Inst{19-16} = imm{15-12};
1970 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1971 Requires<[IsARM, HasV6T2]>;
1973 let Uses = [CPSR] in
1974 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1975 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1978 // These aren't really mov instructions, but we have to define them this way
1979 // due to flag operands.
1981 let Defs = [CPSR] in {
1982 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1983 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1985 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1986 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1990 //===----------------------------------------------------------------------===//
1991 // Extend Instructions.
1996 defm SXTB : AI_ext_rrot<0b01101010,
1997 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1998 defm SXTH : AI_ext_rrot<0b01101011,
1999 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2001 defm SXTAB : AI_exta_rrot<0b01101010,
2002 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2003 defm SXTAH : AI_exta_rrot<0b01101011,
2004 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2006 // For disassembly only
2007 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2009 // For disassembly only
2010 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2014 let AddedComplexity = 16 in {
2015 defm UXTB : AI_ext_rrot<0b01101110,
2016 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2017 defm UXTH : AI_ext_rrot<0b01101111,
2018 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2019 defm UXTB16 : AI_ext_rrot<0b01101100,
2020 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2022 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2023 // The transformation should probably be done as a combiner action
2024 // instead so we can include a check for masking back in the upper
2025 // eight bits of the source into the lower eight bits of the result.
2026 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2027 // (UXTB16r_rot GPR:$Src, 24)>;
2028 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2029 (UXTB16r_rot GPR:$Src, 8)>;
2031 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2032 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2033 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2034 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2037 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2038 // For disassembly only
2039 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2042 def SBFX : I<(outs GPR:$Rd),
2043 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2044 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2045 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2046 Requires<[IsARM, HasV6T2]> {
2051 let Inst{27-21} = 0b0111101;
2052 let Inst{6-4} = 0b101;
2053 let Inst{20-16} = width;
2054 let Inst{15-12} = Rd;
2055 let Inst{11-7} = lsb;
2059 def UBFX : I<(outs GPR:$Rd),
2060 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2061 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2062 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2063 Requires<[IsARM, HasV6T2]> {
2068 let Inst{27-21} = 0b0111111;
2069 let Inst{6-4} = 0b101;
2070 let Inst{20-16} = width;
2071 let Inst{15-12} = Rd;
2072 let Inst{11-7} = lsb;
2076 //===----------------------------------------------------------------------===//
2077 // Arithmetic Instructions.
2080 defm ADD : AsI1_bin_irs<0b0100, "add",
2081 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2082 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2083 defm SUB : AsI1_bin_irs<0b0010, "sub",
2084 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2085 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2087 // ADD and SUB with 's' bit set.
2088 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2089 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2090 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2091 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2092 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2093 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2095 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2096 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2097 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2098 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2099 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2100 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2101 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2102 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2104 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2105 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2106 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2111 let Inst{15-12} = Rd;
2112 let Inst{19-16} = Rn;
2113 let Inst{11-0} = imm;
2116 // The reg/reg form is only defined for the disassembler; for codegen it is
2117 // equivalent to SUBrr.
2118 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2119 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2120 [/* For disassembly only; pattern left blank */]> {
2124 let Inst{11-4} = 0b00000000;
2127 let Inst{15-12} = Rd;
2128 let Inst{19-16} = Rn;
2131 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2132 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2133 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2138 let Inst{11-0} = shift;
2139 let Inst{15-12} = Rd;
2140 let Inst{19-16} = Rn;
2143 // RSB with 's' bit set.
2144 let Defs = [CPSR] in {
2145 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2146 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2147 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2153 let Inst{15-12} = Rd;
2154 let Inst{19-16} = Rn;
2155 let Inst{11-0} = imm;
2157 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2158 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2159 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2165 let Inst{11-0} = shift;
2166 let Inst{15-12} = Rd;
2167 let Inst{19-16} = Rn;
2171 let Uses = [CPSR] in {
2172 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2173 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2174 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2180 let Inst{15-12} = Rd;
2181 let Inst{19-16} = Rn;
2182 let Inst{11-0} = imm;
2184 // The reg/reg form is only defined for the disassembler; for codegen it is
2185 // equivalent to SUBrr.
2186 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2187 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2188 [/* For disassembly only; pattern left blank */]> {
2192 let Inst{11-4} = 0b00000000;
2195 let Inst{15-12} = Rd;
2196 let Inst{19-16} = Rn;
2198 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2199 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2200 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2206 let Inst{11-0} = shift;
2207 let Inst{15-12} = Rd;
2208 let Inst{19-16} = Rn;
2212 // FIXME: Allow these to be predicated.
2213 let Defs = [CPSR], Uses = [CPSR] in {
2214 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2215 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2216 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2223 let Inst{15-12} = Rd;
2224 let Inst{19-16} = Rn;
2225 let Inst{11-0} = imm;
2227 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2228 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2229 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2236 let Inst{11-0} = shift;
2237 let Inst{15-12} = Rd;
2238 let Inst{19-16} = Rn;
2242 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2243 // The assume-no-carry-in form uses the negation of the input since add/sub
2244 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2245 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2247 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2248 (SUBri GPR:$src, so_imm_neg:$imm)>;
2249 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2250 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2251 // The with-carry-in form matches bitwise not instead of the negation.
2252 // Effectively, the inverse interpretation of the carry flag already accounts
2253 // for part of the negation.
2254 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2255 (SBCri GPR:$src, so_imm_not:$imm)>;
2257 // Note: These are implemented in C++ code, because they have to generate
2258 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2260 // (mul X, 2^n+1) -> (add (X << n), X)
2261 // (mul X, 2^n-1) -> (rsb X, (X << n))
2263 // ARM Arithmetic Instruction -- for disassembly only
2264 // GPR:$dst = GPR:$a op GPR:$b
2265 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2266 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2267 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2268 opc, "\t$Rd, $Rn, $Rm", pattern> {
2272 let Inst{27-20} = op27_20;
2273 let Inst{11-4} = op11_4;
2274 let Inst{19-16} = Rn;
2275 let Inst{15-12} = Rd;
2279 // Saturating add/subtract -- for disassembly only
2281 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2282 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2283 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2284 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2285 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2286 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2288 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2289 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2290 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2291 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2292 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2293 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2294 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2295 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2296 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2297 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2298 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2299 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2301 // Signed/Unsigned add/subtract -- for disassembly only
2303 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2304 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2305 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2306 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2307 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2308 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2309 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2310 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2311 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2312 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2313 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2314 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2316 // Signed/Unsigned halving add/subtract -- for disassembly only
2318 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2319 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2320 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2321 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2322 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2323 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2324 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2325 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2326 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2327 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2328 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2329 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2331 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2333 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2334 MulFrm /* for convenience */, NoItinerary, "usad8",
2335 "\t$Rd, $Rn, $Rm", []>,
2336 Requires<[IsARM, HasV6]> {
2340 let Inst{27-20} = 0b01111000;
2341 let Inst{15-12} = 0b1111;
2342 let Inst{7-4} = 0b0001;
2343 let Inst{19-16} = Rd;
2344 let Inst{11-8} = Rm;
2347 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2348 MulFrm /* for convenience */, NoItinerary, "usada8",
2349 "\t$Rd, $Rn, $Rm, $Ra", []>,
2350 Requires<[IsARM, HasV6]> {
2355 let Inst{27-20} = 0b01111000;
2356 let Inst{7-4} = 0b0001;
2357 let Inst{19-16} = Rd;
2358 let Inst{15-12} = Ra;
2359 let Inst{11-8} = Rm;
2363 // Signed/Unsigned saturate -- for disassembly only
2365 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2366 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2367 [/* For disassembly only; pattern left blank */]> {
2372 let Inst{27-21} = 0b0110101;
2373 let Inst{5-4} = 0b01;
2374 let Inst{20-16} = sat_imm;
2375 let Inst{15-12} = Rd;
2376 let Inst{11-7} = sh{7-3};
2377 let Inst{6} = sh{0};
2381 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2382 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2383 [/* For disassembly only; pattern left blank */]> {
2387 let Inst{27-20} = 0b01101010;
2388 let Inst{11-4} = 0b11110011;
2389 let Inst{15-12} = Rd;
2390 let Inst{19-16} = sat_imm;
2394 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2395 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2396 [/* For disassembly only; pattern left blank */]> {
2401 let Inst{27-21} = 0b0110111;
2402 let Inst{5-4} = 0b01;
2403 let Inst{15-12} = Rd;
2404 let Inst{11-7} = sh{7-3};
2405 let Inst{6} = sh{0};
2406 let Inst{20-16} = sat_imm;
2410 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2411 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2412 [/* For disassembly only; pattern left blank */]> {
2416 let Inst{27-20} = 0b01101110;
2417 let Inst{11-4} = 0b11110011;
2418 let Inst{15-12} = Rd;
2419 let Inst{19-16} = sat_imm;
2423 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2424 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2426 //===----------------------------------------------------------------------===//
2427 // Bitwise Instructions.
2430 defm AND : AsI1_bin_irs<0b0000, "and",
2431 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2432 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2433 defm ORR : AsI1_bin_irs<0b1100, "orr",
2434 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2435 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2436 defm EOR : AsI1_bin_irs<0b0001, "eor",
2437 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2438 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2439 defm BIC : AsI1_bin_irs<0b1110, "bic",
2440 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2441 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2443 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2444 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2445 "bfc", "\t$Rd, $imm", "$src = $Rd",
2446 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2447 Requires<[IsARM, HasV6T2]> {
2450 let Inst{27-21} = 0b0111110;
2451 let Inst{6-0} = 0b0011111;
2452 let Inst{15-12} = Rd;
2453 let Inst{11-7} = imm{4-0}; // lsb
2454 let Inst{20-16} = imm{9-5}; // width
2457 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2458 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2459 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2460 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2461 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2462 bf_inv_mask_imm:$imm))]>,
2463 Requires<[IsARM, HasV6T2]> {
2467 let Inst{27-21} = 0b0111110;
2468 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2469 let Inst{15-12} = Rd;
2470 let Inst{11-7} = imm{4-0}; // lsb
2471 let Inst{20-16} = imm{9-5}; // width
2475 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2476 "mvn", "\t$Rd, $Rm",
2477 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2481 let Inst{19-16} = 0b0000;
2482 let Inst{11-4} = 0b00000000;
2483 let Inst{15-12} = Rd;
2486 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2487 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2488 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2492 let Inst{19-16} = 0b0000;
2493 let Inst{15-12} = Rd;
2494 let Inst{11-0} = shift;
2496 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2497 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2498 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2499 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2503 let Inst{19-16} = 0b0000;
2504 let Inst{15-12} = Rd;
2505 let Inst{11-0} = imm;
2508 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2509 (BICri GPR:$src, so_imm_not:$imm)>;
2511 //===----------------------------------------------------------------------===//
2512 // Multiply Instructions.
2514 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2515 string opc, string asm, list<dag> pattern>
2516 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2520 let Inst{19-16} = Rd;
2521 let Inst{11-8} = Rm;
2524 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2525 string opc, string asm, list<dag> pattern>
2526 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2531 let Inst{19-16} = RdHi;
2532 let Inst{15-12} = RdLo;
2533 let Inst{11-8} = Rm;
2537 let isCommutable = 1 in
2538 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2539 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2540 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2542 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2543 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2544 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2546 let Inst{15-12} = Ra;
2549 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2550 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2551 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2552 Requires<[IsARM, HasV6T2]> {
2557 let Inst{19-16} = Rd;
2558 let Inst{15-12} = Ra;
2559 let Inst{11-8} = Rm;
2563 // Extra precision multiplies with low / high results
2565 let neverHasSideEffects = 1 in {
2566 let isCommutable = 1 in {
2567 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2568 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2569 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2571 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2572 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2573 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2576 // Multiply + accumulate
2577 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2578 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2579 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2581 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2582 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2583 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2585 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2586 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2587 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2588 Requires<[IsARM, HasV6]> {
2593 let Inst{19-16} = RdLo;
2594 let Inst{15-12} = RdHi;
2595 let Inst{11-8} = Rm;
2598 } // neverHasSideEffects
2600 // Most significant word multiply
2601 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2602 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2603 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2604 Requires<[IsARM, HasV6]> {
2605 let Inst{15-12} = 0b1111;
2608 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2609 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2610 [/* For disassembly only; pattern left blank */]>,
2611 Requires<[IsARM, HasV6]> {
2612 let Inst{15-12} = 0b1111;
2615 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2616 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2617 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2618 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2619 Requires<[IsARM, HasV6]>;
2621 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2622 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2623 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2624 [/* For disassembly only; pattern left blank */]>,
2625 Requires<[IsARM, HasV6]>;
2627 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2628 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2629 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2630 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2631 Requires<[IsARM, HasV6]>;
2633 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2634 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2635 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2636 [/* For disassembly only; pattern left blank */]>,
2637 Requires<[IsARM, HasV6]>;
2639 multiclass AI_smul<string opc, PatFrag opnode> {
2640 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2641 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2642 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2643 (sext_inreg GPR:$Rm, i16)))]>,
2644 Requires<[IsARM, HasV5TE]>;
2646 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2647 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2648 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2649 (sra GPR:$Rm, (i32 16))))]>,
2650 Requires<[IsARM, HasV5TE]>;
2652 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2653 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2654 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2655 (sext_inreg GPR:$Rm, i16)))]>,
2656 Requires<[IsARM, HasV5TE]>;
2658 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2659 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2660 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2661 (sra GPR:$Rm, (i32 16))))]>,
2662 Requires<[IsARM, HasV5TE]>;
2664 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2665 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2666 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2667 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2668 Requires<[IsARM, HasV5TE]>;
2670 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2671 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2672 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2673 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2674 Requires<[IsARM, HasV5TE]>;
2678 multiclass AI_smla<string opc, PatFrag opnode> {
2679 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2680 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2681 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2682 [(set GPR:$Rd, (add GPR:$Ra,
2683 (opnode (sext_inreg GPR:$Rn, i16),
2684 (sext_inreg GPR:$Rm, i16))))]>,
2685 Requires<[IsARM, HasV5TE]>;
2687 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2688 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2689 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2690 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2691 (sra GPR:$Rm, (i32 16)))))]>,
2692 Requires<[IsARM, HasV5TE]>;
2694 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2695 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2696 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2697 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2698 (sext_inreg GPR:$Rm, i16))))]>,
2699 Requires<[IsARM, HasV5TE]>;
2701 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2702 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2703 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2704 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2705 (sra GPR:$Rm, (i32 16)))))]>,
2706 Requires<[IsARM, HasV5TE]>;
2708 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2709 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2710 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2711 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2712 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2713 Requires<[IsARM, HasV5TE]>;
2715 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2716 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2717 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2718 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2719 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2720 Requires<[IsARM, HasV5TE]>;
2723 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2724 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2726 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2727 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2728 (ins GPR:$Rn, GPR:$Rm),
2729 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2730 [/* For disassembly only; pattern left blank */]>,
2731 Requires<[IsARM, HasV5TE]>;
2733 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2734 (ins GPR:$Rn, GPR:$Rm),
2735 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2736 [/* For disassembly only; pattern left blank */]>,
2737 Requires<[IsARM, HasV5TE]>;
2739 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2740 (ins GPR:$Rn, GPR:$Rm),
2741 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2742 [/* For disassembly only; pattern left blank */]>,
2743 Requires<[IsARM, HasV5TE]>;
2745 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2746 (ins GPR:$Rn, GPR:$Rm),
2747 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2748 [/* For disassembly only; pattern left blank */]>,
2749 Requires<[IsARM, HasV5TE]>;
2751 // Helper class for AI_smld -- for disassembly only
2752 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2753 InstrItinClass itin, string opc, string asm>
2754 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2761 let Inst{21-20} = 0b00;
2762 let Inst{22} = long;
2763 let Inst{27-23} = 0b01110;
2764 let Inst{11-8} = Rm;
2767 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2768 InstrItinClass itin, string opc, string asm>
2769 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2771 let Inst{15-12} = 0b1111;
2772 let Inst{19-16} = Rd;
2774 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2775 InstrItinClass itin, string opc, string asm>
2776 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2778 let Inst{15-12} = Ra;
2780 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2781 InstrItinClass itin, string opc, string asm>
2782 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2785 let Inst{19-16} = RdHi;
2786 let Inst{15-12} = RdLo;
2789 multiclass AI_smld<bit sub, string opc> {
2791 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2792 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2794 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2795 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2797 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2798 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2799 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2801 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2802 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2803 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2807 defm SMLA : AI_smld<0, "smla">;
2808 defm SMLS : AI_smld<1, "smls">;
2810 multiclass AI_sdml<bit sub, string opc> {
2812 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2813 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2814 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2815 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2818 defm SMUA : AI_sdml<0, "smua">;
2819 defm SMUS : AI_sdml<1, "smus">;
2821 //===----------------------------------------------------------------------===//
2822 // Misc. Arithmetic Instructions.
2825 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2826 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2827 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2829 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2830 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2831 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2832 Requires<[IsARM, HasV6T2]>;
2834 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2835 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2836 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2838 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2839 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2841 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2842 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2843 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2844 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2845 Requires<[IsARM, HasV6]>;
2847 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2848 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2851 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2852 (shl GPR:$Rm, (i32 8))), i16))]>,
2853 Requires<[IsARM, HasV6]>;
2855 def lsl_shift_imm : SDNodeXForm<imm, [{
2856 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2857 return CurDAG->getTargetConstant(Sh, MVT::i32);
2860 def lsl_amt : PatLeaf<(i32 imm), [{
2861 return (N->getZExtValue() < 32);
2864 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2865 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2866 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2867 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2868 (and (shl GPR:$Rm, lsl_amt:$sh),
2870 Requires<[IsARM, HasV6]>;
2872 // Alternate cases for PKHBT where identities eliminate some nodes.
2873 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2874 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2875 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2876 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2878 def asr_shift_imm : SDNodeXForm<imm, [{
2879 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2880 return CurDAG->getTargetConstant(Sh, MVT::i32);
2883 def asr_amt : PatLeaf<(i32 imm), [{
2884 return (N->getZExtValue() <= 32);
2887 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2888 // will match the pattern below.
2889 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2890 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2891 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2892 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2893 (and (sra GPR:$Rm, asr_amt:$sh),
2895 Requires<[IsARM, HasV6]>;
2897 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2898 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2899 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2900 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2901 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2902 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2903 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2905 //===----------------------------------------------------------------------===//
2906 // Comparison Instructions...
2909 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2910 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2911 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2913 // FIXME: We have to be careful when using the CMN instruction and comparison
2914 // with 0. One would expect these two pieces of code should give identical
2930 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2931 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2932 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2933 // value of r0 and the carry bit (because the "carry bit" parameter to
2934 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2935 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2936 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2937 // parameter to AddWithCarry is defined as 0).
2939 // When x is 0 and unsigned:
2943 // ~x + 1 = 0x1 0000 0000
2944 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2946 // Therefore, we should disable CMN when comparing against zero, until we can
2947 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2948 // when it's a comparison which doesn't look at the 'carry' flag).
2950 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2952 // This is related to <rdar://problem/7569620>.
2954 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2955 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2957 // Note that TST/TEQ don't set all the same flags that CMP does!
2958 defm TST : AI1_cmp_irs<0b1000, "tst",
2959 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2960 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2961 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2962 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2963 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2965 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2966 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2967 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2968 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2969 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2970 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2972 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2973 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2975 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2976 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2978 // Pseudo i64 compares for some floating point compares.
2979 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2981 def BCCi64 : PseudoInst<(outs),
2982 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2984 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2986 def BCCZi64 : PseudoInst<(outs),
2987 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2988 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2989 } // usesCustomInserter
2992 // Conditional moves
2993 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2994 // a two-value operand where a dag node expects two operands. :(
2995 // FIXME: These should all be pseudo-instructions that get expanded to
2996 // the normal MOV instructions. That would fix the dependency on
2997 // special casing them in tblgen.
2998 let neverHasSideEffects = 1 in {
2999 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
3000 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
3001 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3002 RegConstraint<"$false = $Rd">, UnaryDP {
3007 let Inst{15-12} = Rd;
3008 let Inst{11-4} = 0b00000000;
3012 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3013 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3014 "mov", "\t$Rd, $shift",
3015 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3016 RegConstraint<"$false = $Rd">, UnaryDP {
3021 let Inst{19-16} = 0;
3022 let Inst{15-12} = Rd;
3023 let Inst{11-0} = shift;
3026 let isMoveImm = 1 in
3027 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3029 "movw", "\t$Rd, $imm",
3031 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3037 let Inst{19-16} = imm{15-12};
3038 let Inst{15-12} = Rd;
3039 let Inst{11-0} = imm{11-0};
3042 let isMoveImm = 1 in
3043 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3044 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3045 "mov", "\t$Rd, $imm",
3046 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3047 RegConstraint<"$false = $Rd">, UnaryDP {
3052 let Inst{19-16} = 0b0000;
3053 let Inst{15-12} = Rd;
3054 let Inst{11-0} = imm;
3057 // Two instruction predicate mov immediate.
3058 let isMoveImm = 1 in
3059 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3060 (ins GPR:$false, i32imm:$src, pred:$p),
3061 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3063 let isMoveImm = 1 in
3064 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3065 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3066 "mvn", "\t$Rd, $imm",
3067 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3068 RegConstraint<"$false = $Rd">, UnaryDP {
3073 let Inst{19-16} = 0b0000;
3074 let Inst{15-12} = Rd;
3075 let Inst{11-0} = imm;
3077 } // neverHasSideEffects
3079 //===----------------------------------------------------------------------===//
3080 // Atomic operations intrinsics
3083 def memb_opt : Operand<i32> {
3084 let PrintMethod = "printMemBOption";
3087 // memory barriers protect the atomic sequences
3088 let hasSideEffects = 1 in {
3089 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3090 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3091 Requires<[IsARM, HasDB]> {
3093 let Inst{31-4} = 0xf57ff05;
3094 let Inst{3-0} = opt;
3097 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3098 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3099 [(ARMMemBarrierMCR GPR:$zero)]>,
3100 Requires<[IsARM, HasV6]> {
3101 // FIXME: add encoding
3105 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3107 [/* For disassembly only; pattern left blank */]>,
3108 Requires<[IsARM, HasDB]> {
3110 let Inst{31-4} = 0xf57ff04;
3111 let Inst{3-0} = opt;
3114 // ISB has only full system option -- for disassembly only
3115 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3116 Requires<[IsARM, HasDB]> {
3117 let Inst{31-4} = 0xf57ff06;
3118 let Inst{3-0} = 0b1111;
3121 let usesCustomInserter = 1 in {
3122 let Uses = [CPSR] in {
3123 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3125 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3126 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3128 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3129 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3131 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3132 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3134 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3135 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3137 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3138 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3140 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3141 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3143 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3144 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3146 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3147 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3149 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3150 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3152 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3153 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3155 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3156 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3158 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3159 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3161 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3162 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3164 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3165 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3167 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3168 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3170 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3171 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3173 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3174 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3176 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3178 def ATOMIC_SWAP_I8 : PseudoInst<
3179 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3180 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3181 def ATOMIC_SWAP_I16 : PseudoInst<
3182 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3183 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3184 def ATOMIC_SWAP_I32 : PseudoInst<
3185 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3186 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3188 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3189 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3190 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3191 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3192 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3193 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3194 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3195 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3196 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3200 let mayLoad = 1 in {
3201 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3202 "ldrexb", "\t$Rt, [$Rn]",
3204 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3205 "ldrexh", "\t$Rt, [$Rn]",
3207 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3208 "ldrex", "\t$Rt, [$Rn]",
3210 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3212 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3216 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3217 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3219 "strexb", "\t$Rd, $src, [$Rn]",
3221 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3223 "strexh", "\t$Rd, $Rt, [$Rn]",
3225 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3227 "strex", "\t$Rd, $Rt, [$Rn]",
3229 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3230 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3232 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3236 // Clear-Exclusive is for disassembly only.
3237 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3238 [/* For disassembly only; pattern left blank */]>,
3239 Requires<[IsARM, HasV7]> {
3240 let Inst{31-0} = 0b11110101011111111111000000011111;
3243 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3244 let mayLoad = 1 in {
3245 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3246 [/* For disassembly only; pattern left blank */]>;
3247 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3248 [/* For disassembly only; pattern left blank */]>;
3251 //===----------------------------------------------------------------------===//
3255 // __aeabi_read_tp preserves the registers r1-r3.
3256 // FIXME: This needs to be a pseudo of some sort so that we can get the
3257 // encoding right, complete with fixup for the aeabi_read_tp function.
3259 Defs = [R0, R12, LR, CPSR] in {
3260 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3261 "bl\t__aeabi_read_tp",
3262 [(set R0, ARMthread_pointer)]>;
3265 //===----------------------------------------------------------------------===//
3266 // SJLJ Exception handling intrinsics
3267 // eh_sjlj_setjmp() is an instruction sequence to store the return
3268 // address and save #0 in R0 for the non-longjmp case.
3269 // Since by its nature we may be coming from some other function to get
3270 // here, and we're using the stack frame for the containing function to
3271 // save/restore registers, we can't keep anything live in regs across
3272 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3273 // when we get here from a longjmp(). We force everthing out of registers
3274 // except for our own input by listing the relevant registers in Defs. By
3275 // doing so, we also cause the prologue/epilogue code to actively preserve
3276 // all of the callee-saved resgisters, which is exactly what we want.
3277 // A constant value is passed in $val, and we use the location as a scratch.
3279 // These are pseudo-instructions and are lowered to individual MC-insts, so
3280 // no encoding information is necessary.
3282 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3283 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3284 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3285 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3286 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3287 AddrModeNone, SizeSpecial, IndexModeNone,
3288 Pseudo, NoItinerary, "", "",
3289 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3290 Requires<[IsARM, HasVFP2]>;
3294 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3295 hasSideEffects = 1, isBarrier = 1 in {
3296 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3297 AddrModeNone, SizeSpecial, IndexModeNone,
3298 Pseudo, NoItinerary, "", "",
3299 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3300 Requires<[IsARM, NoVFP]>;
3303 // FIXME: Non-Darwin version(s)
3304 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3305 Defs = [ R7, LR, SP ] in {
3306 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3307 AddrModeNone, SizeSpecial, IndexModeNone,
3308 Pseudo, NoItinerary, "", "",
3309 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3310 Requires<[IsARM, IsDarwin]>;
3313 // eh.sjlj.dispatchsetup pseudo-instruction.
3314 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3315 // handled when the pseudo is expanded (which happens before any passes
3316 // that need the instruction size).
3317 let isBarrier = 1, hasSideEffects = 1 in
3318 def Int_eh_sjlj_dispatchsetup :
3319 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3320 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3321 Requires<[IsDarwin]>;
3323 //===----------------------------------------------------------------------===//
3324 // Non-Instruction Patterns
3327 // Large immediate handling.
3329 // 32-bit immediate using two piece so_imms or movw + movt.
3330 // This is a single pseudo instruction, the benefit is that it can be remat'd
3331 // as a single unit instead of having to handle reg inputs.
3332 // FIXME: Remove this when we can do generalized remat.
3333 let isReMaterializable = 1, isMoveImm = 1 in
3334 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3335 [(set GPR:$dst, (arm_i32imm:$src))]>,
3338 // ConstantPool, GlobalAddress, and JumpTable
3339 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3340 Requires<[IsARM, DontUseMovt]>;
3341 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3342 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3343 Requires<[IsARM, UseMovt]>;
3344 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3345 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3347 // TODO: add,sub,and, 3-instr forms?
3350 def : ARMPat<(ARMtcret tcGPR:$dst),
3351 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3353 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3354 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3356 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3357 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3359 def : ARMPat<(ARMtcret tcGPR:$dst),
3360 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3362 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3363 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3365 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3366 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3369 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3370 Requires<[IsARM, IsNotDarwin]>;
3371 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3372 Requires<[IsARM, IsDarwin]>;
3374 // zextload i1 -> zextload i8
3375 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3376 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3378 // extload -> zextload
3379 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3380 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3381 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3382 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3384 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3386 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3387 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3390 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3391 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3392 (SMULBB GPR:$a, GPR:$b)>;
3393 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3394 (SMULBB GPR:$a, GPR:$b)>;
3395 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3396 (sra GPR:$b, (i32 16))),
3397 (SMULBT GPR:$a, GPR:$b)>;
3398 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3399 (SMULBT GPR:$a, GPR:$b)>;
3400 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3401 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3402 (SMULTB GPR:$a, GPR:$b)>;
3403 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3404 (SMULTB GPR:$a, GPR:$b)>;
3405 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3407 (SMULWB GPR:$a, GPR:$b)>;
3408 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3409 (SMULWB GPR:$a, GPR:$b)>;
3411 def : ARMV5TEPat<(add GPR:$acc,
3412 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3413 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3414 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3415 def : ARMV5TEPat<(add GPR:$acc,
3416 (mul sext_16_node:$a, sext_16_node:$b)),
3417 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3418 def : ARMV5TEPat<(add GPR:$acc,
3419 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3420 (sra GPR:$b, (i32 16)))),
3421 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3422 def : ARMV5TEPat<(add GPR:$acc,
3423 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3424 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3425 def : ARMV5TEPat<(add GPR:$acc,
3426 (mul (sra GPR:$a, (i32 16)),
3427 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3428 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3429 def : ARMV5TEPat<(add GPR:$acc,
3430 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3431 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3432 def : ARMV5TEPat<(add GPR:$acc,
3433 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3435 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3436 def : ARMV5TEPat<(add GPR:$acc,
3437 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3438 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3440 //===----------------------------------------------------------------------===//
3444 include "ARMInstrThumb.td"
3446 //===----------------------------------------------------------------------===//
3450 include "ARMInstrThumb2.td"
3452 //===----------------------------------------------------------------------===//
3453 // Floating Point Support
3456 include "ARMInstrVFP.td"
3458 //===----------------------------------------------------------------------===//
3459 // Advanced SIMD (NEON) Support
3462 include "ARMInstrNEON.td"
3464 //===----------------------------------------------------------------------===//
3465 // Coprocessor Instructions. For disassembly only.
3468 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3469 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3470 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3471 [/* For disassembly only; pattern left blank */]> {
3475 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3476 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3477 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3478 [/* For disassembly only; pattern left blank */]> {
3479 let Inst{31-28} = 0b1111;
3483 class ACI<dag oops, dag iops, string opc, string asm>
3484 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3485 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3486 let Inst{27-25} = 0b110;
3489 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3491 def _OFFSET : ACI<(outs),
3492 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3493 opc, "\tp$cop, cr$CRd, $addr"> {
3494 let Inst{31-28} = op31_28;
3495 let Inst{24} = 1; // P = 1
3496 let Inst{21} = 0; // W = 0
3497 let Inst{22} = 0; // D = 0
3498 let Inst{20} = load;
3501 def _PRE : ACI<(outs),
3502 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3503 opc, "\tp$cop, cr$CRd, $addr!"> {
3504 let Inst{31-28} = op31_28;
3505 let Inst{24} = 1; // P = 1
3506 let Inst{21} = 1; // W = 1
3507 let Inst{22} = 0; // D = 0
3508 let Inst{20} = load;
3511 def _POST : ACI<(outs),
3512 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3513 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3514 let Inst{31-28} = op31_28;
3515 let Inst{24} = 0; // P = 0
3516 let Inst{21} = 1; // W = 1
3517 let Inst{22} = 0; // D = 0
3518 let Inst{20} = load;
3521 def _OPTION : ACI<(outs),
3522 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3523 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3524 let Inst{31-28} = op31_28;
3525 let Inst{24} = 0; // P = 0
3526 let Inst{23} = 1; // U = 1
3527 let Inst{21} = 0; // W = 0
3528 let Inst{22} = 0; // D = 0
3529 let Inst{20} = load;
3532 def L_OFFSET : ACI<(outs),
3533 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3534 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3535 let Inst{31-28} = op31_28;
3536 let Inst{24} = 1; // P = 1
3537 let Inst{21} = 0; // W = 0
3538 let Inst{22} = 1; // D = 1
3539 let Inst{20} = load;
3542 def L_PRE : ACI<(outs),
3543 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3544 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3545 let Inst{31-28} = op31_28;
3546 let Inst{24} = 1; // P = 1
3547 let Inst{21} = 1; // W = 1
3548 let Inst{22} = 1; // D = 1
3549 let Inst{20} = load;
3552 def L_POST : ACI<(outs),
3553 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3554 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3555 let Inst{31-28} = op31_28;
3556 let Inst{24} = 0; // P = 0
3557 let Inst{21} = 1; // W = 1
3558 let Inst{22} = 1; // D = 1
3559 let Inst{20} = load;
3562 def L_OPTION : ACI<(outs),
3563 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3564 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3565 let Inst{31-28} = op31_28;
3566 let Inst{24} = 0; // P = 0
3567 let Inst{23} = 1; // U = 1
3568 let Inst{21} = 0; // W = 0
3569 let Inst{22} = 1; // D = 1
3570 let Inst{20} = load;
3574 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3575 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3576 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3577 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3579 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3580 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3581 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3582 [/* For disassembly only; pattern left blank */]> {
3587 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3588 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3589 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3590 [/* For disassembly only; pattern left blank */]> {
3591 let Inst{31-28} = 0b1111;
3596 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3597 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3598 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3599 [/* For disassembly only; pattern left blank */]> {
3604 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3605 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3606 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3607 [/* For disassembly only; pattern left blank */]> {
3608 let Inst{31-28} = 0b1111;
3613 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3614 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3615 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3616 [/* For disassembly only; pattern left blank */]> {
3617 let Inst{23-20} = 0b0100;
3620 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3621 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3622 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3623 [/* For disassembly only; pattern left blank */]> {
3624 let Inst{31-28} = 0b1111;
3625 let Inst{23-20} = 0b0100;
3628 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3629 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3630 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3631 [/* For disassembly only; pattern left blank */]> {
3632 let Inst{23-20} = 0b0101;
3635 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3636 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3637 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3638 [/* For disassembly only; pattern left blank */]> {
3639 let Inst{31-28} = 0b1111;
3640 let Inst{23-20} = 0b0101;
3643 //===----------------------------------------------------------------------===//
3644 // Move between special register and ARM core register -- for disassembly only
3647 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3648 [/* For disassembly only; pattern left blank */]> {
3649 let Inst{23-20} = 0b0000;
3650 let Inst{7-4} = 0b0000;
3653 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3654 [/* For disassembly only; pattern left blank */]> {
3655 let Inst{23-20} = 0b0100;
3656 let Inst{7-4} = 0b0000;
3659 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3660 "msr", "\tcpsr$mask, $src",
3661 [/* For disassembly only; pattern left blank */]> {
3662 let Inst{23-20} = 0b0010;
3663 let Inst{7-4} = 0b0000;
3666 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3667 "msr", "\tcpsr$mask, $a",
3668 [/* For disassembly only; pattern left blank */]> {
3669 let Inst{23-20} = 0b0010;
3670 let Inst{7-4} = 0b0000;
3673 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3674 "msr", "\tspsr$mask, $src",
3675 [/* For disassembly only; pattern left blank */]> {
3676 let Inst{23-20} = 0b0110;
3677 let Inst{7-4} = 0b0000;
3680 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3681 "msr", "\tspsr$mask, $a",
3682 [/* For disassembly only; pattern left blank */]> {
3683 let Inst{23-20} = 0b0110;
3684 let Inst{7-4} = 0b0000;