1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
99 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
100 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
102 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
103 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
104 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
105 [SDNPHasChain, SDNPSideEffect,
106 SDNPOptInGlue, SDNPOutGlue]>;
107 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
109 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
110 SDNPMayStore, SDNPMayLoad]>;
112 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
118 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
119 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
124 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
129 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
130 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
132 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
134 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
137 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
140 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
143 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
146 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
147 [SDNPOutGlue, SDNPCommutative]>;
149 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
151 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
153 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
155 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
157 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
158 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
159 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
161 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
162 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
163 SDT_ARMEH_SJLJ_Setjmp,
164 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
166 SDT_ARMEH_SJLJ_Longjmp,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
170 [SDNPHasChain, SDNPSideEffect]>;
171 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
172 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
174 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
176 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
179 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
181 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
182 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
184 //===----------------------------------------------------------------------===//
185 // ARM Instruction Predicate Definitions.
187 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
188 AssemblerPredicate<"HasV4TOps", "armv4t">;
189 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
190 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
191 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
196 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
199 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
203 AssemblerPredicate<"HasV7Ops", "armv7">;
204 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"HasV8Ops", "armv8">;
206 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
208 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
209 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
210 AssemblerPredicate<"FeatureVFP2", "VFP2">;
211 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
212 AssemblerPredicate<"FeatureVFP3", "VFP3">;
213 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
214 AssemblerPredicate<"FeatureVFP4", "VFP4">;
215 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
216 AssemblerPredicate<"!FeatureVFPOnlySP",
217 "double precision VFP">;
218 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
220 def HasNEON : Predicate<"Subtarget->hasNEON()">,
221 AssemblerPredicate<"FeatureNEON", "NEON">;
222 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
223 AssemblerPredicate<"FeatureCrypto", "crypto">;
224 def HasCRC : Predicate<"Subtarget->hasCRC()">,
225 AssemblerPredicate<"FeatureCRC", "crc">;
226 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
227 AssemblerPredicate<"FeatureFP16","half-float">;
228 def HasDivide : Predicate<"Subtarget->hasDivide()">,
229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
230 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
232 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
233 AssemblerPredicate<"FeatureT2XtPk",
235 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
236 AssemblerPredicate<"FeatureDSPThumb2",
238 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
239 AssemblerPredicate<"FeatureDB",
241 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
242 AssemblerPredicate<"FeatureMP",
244 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
245 AssemblerPredicate<"FeatureTrustZone",
247 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
248 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
249 def IsThumb : Predicate<"Subtarget->isThumb()">,
250 AssemblerPredicate<"ModeThumb", "thumb">;
251 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
252 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
253 AssemblerPredicate<"ModeThumb,FeatureThumb2",
255 def IsMClass : Predicate<"Subtarget->isMClass()">,
256 AssemblerPredicate<"FeatureMClass", "armv*m">;
257 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
258 AssemblerPredicate<"!FeatureMClass",
260 def IsARM : Predicate<"!Subtarget->isThumb()">,
261 AssemblerPredicate<"!ModeThumb", "arm-mode">;
262 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
263 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
264 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
265 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
266 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
267 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
269 // FIXME: Eventually this will be just "hasV6T2Ops".
270 def UseMovt : Predicate<"Subtarget->useMovt()">;
271 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
272 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
273 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
275 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
276 // But only select them if more precision in FP computation is allowed.
277 // Do not use them for Darwin platforms.
278 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
279 " FPOpFusion::Fast) && "
280 "!Subtarget->isTargetDarwin()">;
281 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
282 " FPOpFusion::Fast &&"
283 " Subtarget->hasVFP4()) || "
284 "Subtarget->isTargetDarwin()">;
286 // VGETLNi32 is microcoded on Swift - prefer VMOV.
287 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
288 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
290 // VDUP.32 is microcoded on Swift - prefer VMOV.
291 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
292 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
294 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
295 // this allows more effective execution domain optimization. See
296 // setExecutionDomain().
297 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
298 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
300 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
301 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
303 //===----------------------------------------------------------------------===//
304 // ARM Flag Definitions.
306 class RegConstraint<string C> {
307 string Constraints = C;
310 //===----------------------------------------------------------------------===//
311 // ARM specific transformation functions and pattern fragments.
314 // imm_neg_XFORM - Return the negation of an i32 immediate value.
315 def imm_neg_XFORM : SDNodeXForm<imm, [{
316 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
319 // imm_not_XFORM - Return the complement of a i32 immediate value.
320 def imm_not_XFORM : SDNodeXForm<imm, [{
321 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
324 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
325 def imm16_31 : ImmLeaf<i32, [{
326 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
329 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
330 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
331 unsigned Value = -(unsigned)N->getZExtValue();
332 return Value && ARM_AM::getSOImmVal(Value) != -1;
334 let ParserMatchClass = so_imm_neg_asmoperand;
337 // Note: this pattern doesn't require an encoder method and such, as it's
338 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
339 // is handled by the destination instructions, which use so_imm.
340 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
341 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
342 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
344 let ParserMatchClass = so_imm_not_asmoperand;
347 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
348 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
349 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
352 /// Split a 32-bit immediate into two 16 bit parts.
353 def hi16 : SDNodeXForm<imm, [{
354 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
357 def lo16AllZero : PatLeaf<(i32 imm), [{
358 // Returns true if all low 16-bits are 0.
359 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
362 class BinOpWithFlagFrag<dag res> :
363 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
364 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
365 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
367 // An 'and' node with a single use.
368 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
369 return N->hasOneUse();
372 // An 'xor' node with a single use.
373 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
374 return N->hasOneUse();
377 // An 'fmul' node with a single use.
378 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
379 return N->hasOneUse();
382 // An 'fadd' node which checks for single non-hazardous use.
383 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
384 return hasNoVMLxHazardUse(N);
387 // An 'fsub' node which checks for single non-hazardous use.
388 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
389 return hasNoVMLxHazardUse(N);
392 //===----------------------------------------------------------------------===//
393 // Operand Definitions.
396 // Immediate operands with a shared generic asm render method.
397 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
400 // FIXME: rename brtarget to t2_brtarget
401 def brtarget : Operand<OtherVT> {
402 let EncoderMethod = "getBranchTargetOpValue";
403 let OperandType = "OPERAND_PCREL";
404 let DecoderMethod = "DecodeT2BROperand";
407 // FIXME: get rid of this one?
408 def uncondbrtarget : Operand<OtherVT> {
409 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
410 let OperandType = "OPERAND_PCREL";
413 // Branch target for ARM. Handles conditional/unconditional
414 def br_target : Operand<OtherVT> {
415 let EncoderMethod = "getARMBranchTargetOpValue";
416 let OperandType = "OPERAND_PCREL";
420 // FIXME: rename bltarget to t2_bl_target?
421 def bltarget : Operand<i32> {
422 // Encoded the same as branch targets.
423 let EncoderMethod = "getBranchTargetOpValue";
424 let OperandType = "OPERAND_PCREL";
427 // Call target for ARM. Handles conditional/unconditional
428 // FIXME: rename bl_target to t2_bltarget?
429 def bl_target : Operand<i32> {
430 let EncoderMethod = "getARMBLTargetOpValue";
431 let OperandType = "OPERAND_PCREL";
434 def blx_target : Operand<i32> {
435 let EncoderMethod = "getARMBLXTargetOpValue";
436 let OperandType = "OPERAND_PCREL";
439 // A list of registers separated by comma. Used by load/store multiple.
440 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
441 def reglist : Operand<i32> {
442 let EncoderMethod = "getRegisterListOpValue";
443 let ParserMatchClass = RegListAsmOperand;
444 let PrintMethod = "printRegisterList";
445 let DecoderMethod = "DecodeRegListOperand";
448 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
450 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
451 def dpr_reglist : Operand<i32> {
452 let EncoderMethod = "getRegisterListOpValue";
453 let ParserMatchClass = DPRRegListAsmOperand;
454 let PrintMethod = "printRegisterList";
455 let DecoderMethod = "DecodeDPRRegListOperand";
458 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
459 def spr_reglist : Operand<i32> {
460 let EncoderMethod = "getRegisterListOpValue";
461 let ParserMatchClass = SPRRegListAsmOperand;
462 let PrintMethod = "printRegisterList";
463 let DecoderMethod = "DecodeSPRRegListOperand";
466 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
467 def cpinst_operand : Operand<i32> {
468 let PrintMethod = "printCPInstOperand";
472 def pclabel : Operand<i32> {
473 let PrintMethod = "printPCLabel";
476 // ADR instruction labels.
477 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
478 def adrlabel : Operand<i32> {
479 let EncoderMethod = "getAdrLabelOpValue";
480 let ParserMatchClass = AdrLabelAsmOperand;
481 let PrintMethod = "printAdrLabelOperand<0>";
484 def neon_vcvt_imm32 : Operand<i32> {
485 let EncoderMethod = "getNEONVcvtImm32OpValue";
486 let DecoderMethod = "DecodeVCVTImmOperand";
489 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
490 def rot_imm_XFORM: SDNodeXForm<imm, [{
491 switch (N->getZExtValue()){
493 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
494 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
495 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
496 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
499 def RotImmAsmOperand : AsmOperandClass {
501 let ParserMethod = "parseRotImm";
503 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
504 int32_t v = N->getZExtValue();
505 return v == 8 || v == 16 || v == 24; }],
507 let PrintMethod = "printRotImmOperand";
508 let ParserMatchClass = RotImmAsmOperand;
511 // shift_imm: An integer that encodes a shift amount and the type of shift
512 // (asr or lsl). The 6-bit immediate encodes as:
515 // {4-0} imm5 shift amount.
516 // asr #32 encoded as imm5 == 0.
517 def ShifterImmAsmOperand : AsmOperandClass {
518 let Name = "ShifterImm";
519 let ParserMethod = "parseShifterImm";
521 def shift_imm : Operand<i32> {
522 let PrintMethod = "printShiftImmOperand";
523 let ParserMatchClass = ShifterImmAsmOperand;
526 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
527 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
528 def so_reg_reg : Operand<i32>, // reg reg imm
529 ComplexPattern<i32, 3, "SelectRegShifterOperand",
530 [shl, srl, sra, rotr]> {
531 let EncoderMethod = "getSORegRegOpValue";
532 let PrintMethod = "printSORegRegOperand";
533 let DecoderMethod = "DecodeSORegRegOperand";
534 let ParserMatchClass = ShiftedRegAsmOperand;
535 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
538 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
539 def so_reg_imm : Operand<i32>, // reg imm
540 ComplexPattern<i32, 2, "SelectImmShifterOperand",
541 [shl, srl, sra, rotr]> {
542 let EncoderMethod = "getSORegImmOpValue";
543 let PrintMethod = "printSORegImmOperand";
544 let DecoderMethod = "DecodeSORegImmOperand";
545 let ParserMatchClass = ShiftedImmAsmOperand;
546 let MIOperandInfo = (ops GPR, i32imm);
549 // FIXME: Does this need to be distinct from so_reg?
550 def shift_so_reg_reg : Operand<i32>, // reg reg imm
551 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
552 [shl,srl,sra,rotr]> {
553 let EncoderMethod = "getSORegRegOpValue";
554 let PrintMethod = "printSORegRegOperand";
555 let DecoderMethod = "DecodeSORegRegOperand";
556 let ParserMatchClass = ShiftedRegAsmOperand;
557 let MIOperandInfo = (ops GPR, GPR, i32imm);
560 // FIXME: Does this need to be distinct from so_reg?
561 def shift_so_reg_imm : Operand<i32>, // reg reg imm
562 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
563 [shl,srl,sra,rotr]> {
564 let EncoderMethod = "getSORegImmOpValue";
565 let PrintMethod = "printSORegImmOperand";
566 let DecoderMethod = "DecodeSORegImmOperand";
567 let ParserMatchClass = ShiftedImmAsmOperand;
568 let MIOperandInfo = (ops GPR, i32imm);
572 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
573 // 8-bit immediate rotated by an arbitrary number of bits.
574 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
575 def so_imm : Operand<i32>, ImmLeaf<i32, [{
576 return ARM_AM::getSOImmVal(Imm) != -1;
578 let EncoderMethod = "getSOImmOpValue";
579 let ParserMatchClass = SOImmAsmOperand;
580 let DecoderMethod = "DecodeSOImmOperand";
583 // Break so_imm's up into two pieces. This handles immediates with up to 16
584 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
585 // get the first/second pieces.
586 def so_imm2part : PatLeaf<(imm), [{
587 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
590 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
592 def arm_i32imm : PatLeaf<(imm), [{
593 if (Subtarget->hasV6T2Ops())
595 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
598 /// imm0_1 predicate - Immediate in the range [0,1].
599 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
600 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
602 /// imm0_3 predicate - Immediate in the range [0,3].
603 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
604 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
606 /// imm0_7 predicate - Immediate in the range [0,7].
607 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
608 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
609 return Imm >= 0 && Imm < 8;
611 let ParserMatchClass = Imm0_7AsmOperand;
614 /// imm8 predicate - Immediate is exactly 8.
615 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
616 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
617 let ParserMatchClass = Imm8AsmOperand;
620 /// imm16 predicate - Immediate is exactly 16.
621 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
622 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
623 let ParserMatchClass = Imm16AsmOperand;
626 /// imm32 predicate - Immediate is exactly 32.
627 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
628 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
629 let ParserMatchClass = Imm32AsmOperand;
632 /// imm1_7 predicate - Immediate in the range [1,7].
633 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
634 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
635 let ParserMatchClass = Imm1_7AsmOperand;
638 /// imm1_15 predicate - Immediate in the range [1,15].
639 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
640 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
641 let ParserMatchClass = Imm1_15AsmOperand;
644 /// imm1_31 predicate - Immediate in the range [1,31].
645 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
646 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
647 let ParserMatchClass = Imm1_31AsmOperand;
650 /// imm0_15 predicate - Immediate in the range [0,15].
651 def Imm0_15AsmOperand: ImmAsmOperand {
652 let Name = "Imm0_15";
653 let DiagnosticType = "ImmRange0_15";
655 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
656 return Imm >= 0 && Imm < 16;
658 let ParserMatchClass = Imm0_15AsmOperand;
661 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
662 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
663 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
664 return Imm >= 0 && Imm < 32;
666 let ParserMatchClass = Imm0_31AsmOperand;
669 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
670 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
671 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
672 return Imm >= 0 && Imm < 32;
674 let ParserMatchClass = Imm0_32AsmOperand;
677 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
678 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
679 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
680 return Imm >= 0 && Imm < 64;
682 let ParserMatchClass = Imm0_63AsmOperand;
685 /// imm0_239 predicate - Immediate in the range [0,239].
686 def Imm0_239AsmOperand : ImmAsmOperand {
687 let Name = "Imm0_239";
688 let DiagnosticType = "ImmRange0_239";
690 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
691 let ParserMatchClass = Imm0_239AsmOperand;
694 /// imm0_255 predicate - Immediate in the range [0,255].
695 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
696 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
697 let ParserMatchClass = Imm0_255AsmOperand;
700 /// imm0_65535 - An immediate is in the range [0.65535].
701 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
702 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
703 return Imm >= 0 && Imm < 65536;
705 let ParserMatchClass = Imm0_65535AsmOperand;
708 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
709 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
710 return -Imm >= 0 && -Imm < 65536;
713 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
714 // a relocatable expression.
716 // FIXME: This really needs a Thumb version separate from the ARM version.
717 // While the range is the same, and can thus use the same match class,
718 // the encoding is different so it should have a different encoder method.
719 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
720 def imm0_65535_expr : Operand<i32> {
721 let EncoderMethod = "getHiLo16ImmOpValue";
722 let ParserMatchClass = Imm0_65535ExprAsmOperand;
725 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
726 def imm256_65535_expr : Operand<i32> {
727 let ParserMatchClass = Imm256_65535ExprAsmOperand;
730 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
731 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
732 def imm24b : Operand<i32>, ImmLeaf<i32, [{
733 return Imm >= 0 && Imm <= 0xffffff;
735 let ParserMatchClass = Imm24bitAsmOperand;
739 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
741 def BitfieldAsmOperand : AsmOperandClass {
742 let Name = "Bitfield";
743 let ParserMethod = "parseBitfield";
746 def bf_inv_mask_imm : Operand<i32>,
748 return ARM::isBitFieldInvertedMask(N->getZExtValue());
750 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
751 let PrintMethod = "printBitfieldInvMaskImmOperand";
752 let DecoderMethod = "DecodeBitfieldMaskOperand";
753 let ParserMatchClass = BitfieldAsmOperand;
756 def imm1_32_XFORM: SDNodeXForm<imm, [{
757 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
759 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
760 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
761 uint64_t Imm = N->getZExtValue();
762 return Imm > 0 && Imm <= 32;
765 let PrintMethod = "printImmPlusOneOperand";
766 let ParserMatchClass = Imm1_32AsmOperand;
769 def imm1_16_XFORM: SDNodeXForm<imm, [{
770 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
772 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
773 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
775 let PrintMethod = "printImmPlusOneOperand";
776 let ParserMatchClass = Imm1_16AsmOperand;
779 // Define ARM specific addressing modes.
780 // addrmode_imm12 := reg +/- imm12
782 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
783 class AddrMode_Imm12 : Operand<i32>,
784 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
785 // 12-bit immediate operand. Note that instructions using this encode
786 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
787 // immediate values are as normal.
789 let EncoderMethod = "getAddrModeImm12OpValue";
790 let DecoderMethod = "DecodeAddrModeImm12Operand";
791 let ParserMatchClass = MemImm12OffsetAsmOperand;
792 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
795 def addrmode_imm12 : AddrMode_Imm12 {
796 let PrintMethod = "printAddrModeImm12Operand<false>";
799 def addrmode_imm12_pre : AddrMode_Imm12 {
800 let PrintMethod = "printAddrModeImm12Operand<true>";
803 // ldst_so_reg := reg +/- reg shop imm
805 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
806 def ldst_so_reg : Operand<i32>,
807 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
808 let EncoderMethod = "getLdStSORegOpValue";
809 // FIXME: Simplify the printer
810 let PrintMethod = "printAddrMode2Operand";
811 let DecoderMethod = "DecodeSORegMemOperand";
812 let ParserMatchClass = MemRegOffsetAsmOperand;
813 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
816 // postidx_imm8 := +/- [0,255]
819 // {8} 1 is imm8 is non-negative. 0 otherwise.
820 // {7-0} [0,255] imm8 value.
821 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
822 def postidx_imm8 : Operand<i32> {
823 let PrintMethod = "printPostIdxImm8Operand";
824 let ParserMatchClass = PostIdxImm8AsmOperand;
825 let MIOperandInfo = (ops i32imm);
828 // postidx_imm8s4 := +/- [0,1020]
831 // {8} 1 is imm8 is non-negative. 0 otherwise.
832 // {7-0} [0,255] imm8 value, scaled by 4.
833 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
834 def postidx_imm8s4 : Operand<i32> {
835 let PrintMethod = "printPostIdxImm8s4Operand";
836 let ParserMatchClass = PostIdxImm8s4AsmOperand;
837 let MIOperandInfo = (ops i32imm);
841 // postidx_reg := +/- reg
843 def PostIdxRegAsmOperand : AsmOperandClass {
844 let Name = "PostIdxReg";
845 let ParserMethod = "parsePostIdxReg";
847 def postidx_reg : Operand<i32> {
848 let EncoderMethod = "getPostIdxRegOpValue";
849 let DecoderMethod = "DecodePostIdxReg";
850 let PrintMethod = "printPostIdxRegOperand";
851 let ParserMatchClass = PostIdxRegAsmOperand;
852 let MIOperandInfo = (ops GPRnopc, i32imm);
856 // addrmode2 := reg +/- imm12
857 // := reg +/- reg shop imm
859 // FIXME: addrmode2 should be refactored the rest of the way to always
860 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
861 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
862 def addrmode2 : Operand<i32>,
863 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
864 let EncoderMethod = "getAddrMode2OpValue";
865 let PrintMethod = "printAddrMode2Operand";
866 let ParserMatchClass = AddrMode2AsmOperand;
867 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
870 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
871 let Name = "PostIdxRegShifted";
872 let ParserMethod = "parsePostIdxReg";
874 def am2offset_reg : Operand<i32>,
875 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
876 [], [SDNPWantRoot]> {
877 let EncoderMethod = "getAddrMode2OffsetOpValue";
878 let PrintMethod = "printAddrMode2OffsetOperand";
879 // When using this for assembly, it's always as a post-index offset.
880 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
881 let MIOperandInfo = (ops GPRnopc, i32imm);
884 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
885 // the GPR is purely vestigal at this point.
886 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
887 def am2offset_imm : Operand<i32>,
888 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
889 [], [SDNPWantRoot]> {
890 let EncoderMethod = "getAddrMode2OffsetOpValue";
891 let PrintMethod = "printAddrMode2OffsetOperand";
892 let ParserMatchClass = AM2OffsetImmAsmOperand;
893 let MIOperandInfo = (ops GPRnopc, i32imm);
897 // addrmode3 := reg +/- reg
898 // addrmode3 := reg +/- imm8
900 // FIXME: split into imm vs. reg versions.
901 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
902 class AddrMode3 : Operand<i32>,
903 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
904 let EncoderMethod = "getAddrMode3OpValue";
905 let ParserMatchClass = AddrMode3AsmOperand;
906 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
909 def addrmode3 : AddrMode3
911 let PrintMethod = "printAddrMode3Operand<false>";
914 def addrmode3_pre : AddrMode3
916 let PrintMethod = "printAddrMode3Operand<true>";
919 // FIXME: split into imm vs. reg versions.
920 // FIXME: parser method to handle +/- register.
921 def AM3OffsetAsmOperand : AsmOperandClass {
922 let Name = "AM3Offset";
923 let ParserMethod = "parseAM3Offset";
925 def am3offset : Operand<i32>,
926 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
927 [], [SDNPWantRoot]> {
928 let EncoderMethod = "getAddrMode3OffsetOpValue";
929 let PrintMethod = "printAddrMode3OffsetOperand";
930 let ParserMatchClass = AM3OffsetAsmOperand;
931 let MIOperandInfo = (ops GPR, i32imm);
934 // ldstm_mode := {ia, ib, da, db}
936 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
937 let EncoderMethod = "getLdStmModeOpValue";
938 let PrintMethod = "printLdStmModeOperand";
941 // addrmode5 := reg +/- imm8*4
943 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
944 class AddrMode5 : Operand<i32>,
945 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
946 let EncoderMethod = "getAddrMode5OpValue";
947 let DecoderMethod = "DecodeAddrMode5Operand";
948 let ParserMatchClass = AddrMode5AsmOperand;
949 let MIOperandInfo = (ops GPR:$base, i32imm);
952 def addrmode5 : AddrMode5 {
953 let PrintMethod = "printAddrMode5Operand<false>";
956 def addrmode5_pre : AddrMode5 {
957 let PrintMethod = "printAddrMode5Operand<true>";
960 // addrmode6 := reg with optional alignment
962 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
963 def addrmode6 : Operand<i32>,
964 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
965 let PrintMethod = "printAddrMode6Operand";
966 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
967 let EncoderMethod = "getAddrMode6AddressOpValue";
968 let DecoderMethod = "DecodeAddrMode6Operand";
969 let ParserMatchClass = AddrMode6AsmOperand;
972 def am6offset : Operand<i32>,
973 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
974 [], [SDNPWantRoot]> {
975 let PrintMethod = "printAddrMode6OffsetOperand";
976 let MIOperandInfo = (ops GPR);
977 let EncoderMethod = "getAddrMode6OffsetOpValue";
978 let DecoderMethod = "DecodeGPRRegisterClass";
981 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
982 // (single element from one lane) for size 32.
983 def addrmode6oneL32 : Operand<i32>,
984 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
985 let PrintMethod = "printAddrMode6Operand";
986 let MIOperandInfo = (ops GPR:$addr, i32imm);
987 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
990 // Special version of addrmode6 to handle alignment encoding for VLD-dup
991 // instructions, specifically VLD4-dup.
992 def addrmode6dup : Operand<i32>,
993 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
994 let PrintMethod = "printAddrMode6Operand";
995 let MIOperandInfo = (ops GPR:$addr, i32imm);
996 let EncoderMethod = "getAddrMode6DupAddressOpValue";
997 // FIXME: This is close, but not quite right. The alignment specifier is
999 let ParserMatchClass = AddrMode6AsmOperand;
1002 // addrmodepc := pc + reg
1004 def addrmodepc : Operand<i32>,
1005 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1006 let PrintMethod = "printAddrModePCOperand";
1007 let MIOperandInfo = (ops GPR, i32imm);
1010 // addr_offset_none := reg
1012 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1013 def addr_offset_none : Operand<i32>,
1014 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1015 let PrintMethod = "printAddrMode7Operand";
1016 let DecoderMethod = "DecodeAddrMode7Operand";
1017 let ParserMatchClass = MemNoOffsetAsmOperand;
1018 let MIOperandInfo = (ops GPR:$base);
1021 def nohash_imm : Operand<i32> {
1022 let PrintMethod = "printNoHashImmediate";
1025 def CoprocNumAsmOperand : AsmOperandClass {
1026 let Name = "CoprocNum";
1027 let ParserMethod = "parseCoprocNumOperand";
1029 def p_imm : Operand<i32> {
1030 let PrintMethod = "printPImmediate";
1031 let ParserMatchClass = CoprocNumAsmOperand;
1032 let DecoderMethod = "DecodeCoprocessor";
1035 def CoprocRegAsmOperand : AsmOperandClass {
1036 let Name = "CoprocReg";
1037 let ParserMethod = "parseCoprocRegOperand";
1039 def c_imm : Operand<i32> {
1040 let PrintMethod = "printCImmediate";
1041 let ParserMatchClass = CoprocRegAsmOperand;
1043 def CoprocOptionAsmOperand : AsmOperandClass {
1044 let Name = "CoprocOption";
1045 let ParserMethod = "parseCoprocOptionOperand";
1047 def coproc_option_imm : Operand<i32> {
1048 let PrintMethod = "printCoprocOptionImm";
1049 let ParserMatchClass = CoprocOptionAsmOperand;
1052 //===----------------------------------------------------------------------===//
1054 include "ARMInstrFormats.td"
1056 //===----------------------------------------------------------------------===//
1057 // Multiclass helpers...
1060 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1061 /// binop that produces a value.
1062 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1063 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1064 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1065 PatFrag opnode, bit Commutable = 0> {
1066 // The register-immediate version is re-materializable. This is useful
1067 // in particular for taking the address of a local.
1068 let isReMaterializable = 1 in {
1069 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1070 iii, opc, "\t$Rd, $Rn, $imm",
1071 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1072 Sched<[WriteALU, ReadALU]> {
1077 let Inst{19-16} = Rn;
1078 let Inst{15-12} = Rd;
1079 let Inst{11-0} = imm;
1082 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1083 iir, opc, "\t$Rd, $Rn, $Rm",
1084 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1085 Sched<[WriteALU, ReadALU, ReadALU]> {
1090 let isCommutable = Commutable;
1091 let Inst{19-16} = Rn;
1092 let Inst{15-12} = Rd;
1093 let Inst{11-4} = 0b00000000;
1097 def rsi : AsI1<opcod, (outs GPR:$Rd),
1098 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1099 iis, opc, "\t$Rd, $Rn, $shift",
1100 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1101 Sched<[WriteALUsi, ReadALU]> {
1106 let Inst{19-16} = Rn;
1107 let Inst{15-12} = Rd;
1108 let Inst{11-5} = shift{11-5};
1110 let Inst{3-0} = shift{3-0};
1113 def rsr : AsI1<opcod, (outs GPR:$Rd),
1114 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1115 iis, opc, "\t$Rd, $Rn, $shift",
1116 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1117 Sched<[WriteALUsr, ReadALUsr]> {
1122 let Inst{19-16} = Rn;
1123 let Inst{15-12} = Rd;
1124 let Inst{11-8} = shift{11-8};
1126 let Inst{6-5} = shift{6-5};
1128 let Inst{3-0} = shift{3-0};
1132 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1133 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1134 /// it is equivalent to the AsI1_bin_irs counterpart.
1135 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1136 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1137 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1138 PatFrag opnode, bit Commutable = 0> {
1139 // The register-immediate version is re-materializable. This is useful
1140 // in particular for taking the address of a local.
1141 let isReMaterializable = 1 in {
1142 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1143 iii, opc, "\t$Rd, $Rn, $imm",
1144 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1145 Sched<[WriteALU, ReadALU]> {
1150 let Inst{19-16} = Rn;
1151 let Inst{15-12} = Rd;
1152 let Inst{11-0} = imm;
1155 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1156 iir, opc, "\t$Rd, $Rn, $Rm",
1157 [/* pattern left blank */]>,
1158 Sched<[WriteALU, ReadALU, ReadALU]> {
1162 let Inst{11-4} = 0b00000000;
1165 let Inst{15-12} = Rd;
1166 let Inst{19-16} = Rn;
1169 def rsi : AsI1<opcod, (outs GPR:$Rd),
1170 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1171 iis, opc, "\t$Rd, $Rn, $shift",
1172 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1173 Sched<[WriteALUsi, ReadALU]> {
1178 let Inst{19-16} = Rn;
1179 let Inst{15-12} = Rd;
1180 let Inst{11-5} = shift{11-5};
1182 let Inst{3-0} = shift{3-0};
1185 def rsr : AsI1<opcod, (outs GPR:$Rd),
1186 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1187 iis, opc, "\t$Rd, $Rn, $shift",
1188 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1189 Sched<[WriteALUsr, ReadALUsr]> {
1194 let Inst{19-16} = Rn;
1195 let Inst{15-12} = Rd;
1196 let Inst{11-8} = shift{11-8};
1198 let Inst{6-5} = shift{6-5};
1200 let Inst{3-0} = shift{3-0};
1204 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1206 /// These opcodes will be converted to the real non-S opcodes by
1207 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1208 let hasPostISelHook = 1, Defs = [CPSR] in {
1209 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1210 InstrItinClass iis, PatFrag opnode,
1211 bit Commutable = 0> {
1212 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1214 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1215 Sched<[WriteALU, ReadALU]>;
1217 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1219 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1220 Sched<[WriteALU, ReadALU, ReadALU]> {
1221 let isCommutable = Commutable;
1223 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1224 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1226 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1227 so_reg_imm:$shift))]>,
1228 Sched<[WriteALUsi, ReadALU]>;
1230 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1231 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1233 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1234 so_reg_reg:$shift))]>,
1235 Sched<[WriteALUSsr, ReadALUsr]>;
1239 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1240 /// operands are reversed.
1241 let hasPostISelHook = 1, Defs = [CPSR] in {
1242 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1243 InstrItinClass iis, PatFrag opnode,
1244 bit Commutable = 0> {
1245 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1247 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1248 Sched<[WriteALU, ReadALU]>;
1250 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1251 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1253 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1255 Sched<[WriteALUsi, ReadALU]>;
1257 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1258 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1260 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1262 Sched<[WriteALUSsr, ReadALUsr]>;
1266 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1267 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1268 /// a explicit result, only implicitly set CPSR.
1269 let isCompare = 1, Defs = [CPSR] in {
1270 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1271 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1272 PatFrag opnode, bit Commutable = 0> {
1273 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1275 [(opnode GPR:$Rn, so_imm:$imm)]>,
1276 Sched<[WriteCMP, ReadALU]> {
1281 let Inst{19-16} = Rn;
1282 let Inst{15-12} = 0b0000;
1283 let Inst{11-0} = imm;
1285 let Unpredictable{15-12} = 0b1111;
1287 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1289 [(opnode GPR:$Rn, GPR:$Rm)]>,
1290 Sched<[WriteCMP, ReadALU, ReadALU]> {
1293 let isCommutable = Commutable;
1296 let Inst{19-16} = Rn;
1297 let Inst{15-12} = 0b0000;
1298 let Inst{11-4} = 0b00000000;
1301 let Unpredictable{15-12} = 0b1111;
1303 def rsi : AI1<opcod, (outs),
1304 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1305 opc, "\t$Rn, $shift",
1306 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1307 Sched<[WriteCMPsi, ReadALU]> {
1312 let Inst{19-16} = Rn;
1313 let Inst{15-12} = 0b0000;
1314 let Inst{11-5} = shift{11-5};
1316 let Inst{3-0} = shift{3-0};
1318 let Unpredictable{15-12} = 0b1111;
1320 def rsr : AI1<opcod, (outs),
1321 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1322 opc, "\t$Rn, $shift",
1323 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1324 Sched<[WriteCMPsr, ReadALU]> {
1329 let Inst{19-16} = Rn;
1330 let Inst{15-12} = 0b0000;
1331 let Inst{11-8} = shift{11-8};
1333 let Inst{6-5} = shift{6-5};
1335 let Inst{3-0} = shift{3-0};
1337 let Unpredictable{15-12} = 0b1111;
1343 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1344 /// register and one whose operand is a register rotated by 8/16/24.
1345 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1346 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1347 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1348 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1349 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1350 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1354 let Inst{19-16} = 0b1111;
1355 let Inst{15-12} = Rd;
1356 let Inst{11-10} = rot;
1360 class AI_ext_rrot_np<bits<8> opcod, string opc>
1361 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1362 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1363 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1365 let Inst{19-16} = 0b1111;
1366 let Inst{11-10} = rot;
1369 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1370 /// register and one whose operand is a register rotated by 8/16/24.
1371 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1372 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1373 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1374 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1375 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1376 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1381 let Inst{19-16} = Rn;
1382 let Inst{15-12} = Rd;
1383 let Inst{11-10} = rot;
1384 let Inst{9-4} = 0b000111;
1388 class AI_exta_rrot_np<bits<8> opcod, string opc>
1389 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1390 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1391 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1394 let Inst{19-16} = Rn;
1395 let Inst{11-10} = rot;
1398 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1399 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1400 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1401 bit Commutable = 0> {
1402 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1403 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1404 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1405 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1407 Sched<[WriteALU, ReadALU]> {
1412 let Inst{15-12} = Rd;
1413 let Inst{19-16} = Rn;
1414 let Inst{11-0} = imm;
1416 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1417 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1418 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1420 Sched<[WriteALU, ReadALU, ReadALU]> {
1424 let Inst{11-4} = 0b00000000;
1426 let isCommutable = Commutable;
1428 let Inst{15-12} = Rd;
1429 let Inst{19-16} = Rn;
1431 def rsi : AsI1<opcod, (outs GPR:$Rd),
1432 (ins GPR:$Rn, so_reg_imm:$shift),
1433 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1434 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1436 Sched<[WriteALUsi, ReadALU]> {
1441 let Inst{19-16} = Rn;
1442 let Inst{15-12} = Rd;
1443 let Inst{11-5} = shift{11-5};
1445 let Inst{3-0} = shift{3-0};
1447 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1448 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1449 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1450 [(set GPRnopc:$Rd, CPSR,
1451 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1453 Sched<[WriteALUsr, ReadALUsr]> {
1458 let Inst{19-16} = Rn;
1459 let Inst{15-12} = Rd;
1460 let Inst{11-8} = shift{11-8};
1462 let Inst{6-5} = shift{6-5};
1464 let Inst{3-0} = shift{3-0};
1469 /// AI1_rsc_irs - Define instructions and patterns for rsc
1470 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1471 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1472 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1473 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1474 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1475 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1477 Sched<[WriteALU, ReadALU]> {
1482 let Inst{15-12} = Rd;
1483 let Inst{19-16} = Rn;
1484 let Inst{11-0} = imm;
1486 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1487 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1488 [/* pattern left blank */]>,
1489 Sched<[WriteALU, ReadALU, ReadALU]> {
1493 let Inst{11-4} = 0b00000000;
1496 let Inst{15-12} = Rd;
1497 let Inst{19-16} = Rn;
1499 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1500 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1501 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1503 Sched<[WriteALUsi, ReadALU]> {
1508 let Inst{19-16} = Rn;
1509 let Inst{15-12} = Rd;
1510 let Inst{11-5} = shift{11-5};
1512 let Inst{3-0} = shift{3-0};
1514 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1515 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1516 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1518 Sched<[WriteALUsr, ReadALUsr]> {
1523 let Inst{19-16} = Rn;
1524 let Inst{15-12} = Rd;
1525 let Inst{11-8} = shift{11-8};
1527 let Inst{6-5} = shift{6-5};
1529 let Inst{3-0} = shift{3-0};
1534 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1535 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1536 InstrItinClass iir, PatFrag opnode> {
1537 // Note: We use the complex addrmode_imm12 rather than just an input
1538 // GPR and a constrained immediate so that we can use this to match
1539 // frame index references and avoid matching constant pool references.
1540 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1541 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1542 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1545 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1546 let Inst{19-16} = addr{16-13}; // Rn
1547 let Inst{15-12} = Rt;
1548 let Inst{11-0} = addr{11-0}; // imm12
1550 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1551 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1552 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1555 let shift{4} = 0; // Inst{4} = 0
1556 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1557 let Inst{19-16} = shift{16-13}; // Rn
1558 let Inst{15-12} = Rt;
1559 let Inst{11-0} = shift{11-0};
1564 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1565 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1566 InstrItinClass iir, PatFrag opnode> {
1567 // Note: We use the complex addrmode_imm12 rather than just an input
1568 // GPR and a constrained immediate so that we can use this to match
1569 // frame index references and avoid matching constant pool references.
1570 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1571 (ins addrmode_imm12:$addr),
1572 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1573 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1576 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1577 let Inst{19-16} = addr{16-13}; // Rn
1578 let Inst{15-12} = Rt;
1579 let Inst{11-0} = addr{11-0}; // imm12
1581 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1582 (ins ldst_so_reg:$shift),
1583 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1584 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1587 let shift{4} = 0; // Inst{4} = 0
1588 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1589 let Inst{19-16} = shift{16-13}; // Rn
1590 let Inst{15-12} = Rt;
1591 let Inst{11-0} = shift{11-0};
1597 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1598 InstrItinClass iir, PatFrag opnode> {
1599 // Note: We use the complex addrmode_imm12 rather than just an input
1600 // GPR and a constrained immediate so that we can use this to match
1601 // frame index references and avoid matching constant pool references.
1602 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1603 (ins GPR:$Rt, addrmode_imm12:$addr),
1604 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1605 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1608 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1609 let Inst{19-16} = addr{16-13}; // Rn
1610 let Inst{15-12} = Rt;
1611 let Inst{11-0} = addr{11-0}; // imm12
1613 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1614 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1615 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1618 let shift{4} = 0; // Inst{4} = 0
1619 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1620 let Inst{19-16} = shift{16-13}; // Rn
1621 let Inst{15-12} = Rt;
1622 let Inst{11-0} = shift{11-0};
1626 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1627 InstrItinClass iir, PatFrag opnode> {
1628 // Note: We use the complex addrmode_imm12 rather than just an input
1629 // GPR and a constrained immediate so that we can use this to match
1630 // frame index references and avoid matching constant pool references.
1631 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1632 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1633 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1634 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1637 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1638 let Inst{19-16} = addr{16-13}; // Rn
1639 let Inst{15-12} = Rt;
1640 let Inst{11-0} = addr{11-0}; // imm12
1642 def rs : AI2ldst<0b011, 0, isByte, (outs),
1643 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1644 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1645 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1648 let shift{4} = 0; // Inst{4} = 0
1649 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1650 let Inst{19-16} = shift{16-13}; // Rn
1651 let Inst{15-12} = Rt;
1652 let Inst{11-0} = shift{11-0};
1657 //===----------------------------------------------------------------------===//
1659 //===----------------------------------------------------------------------===//
1661 //===----------------------------------------------------------------------===//
1662 // Miscellaneous Instructions.
1665 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1666 /// the function. The first operand is the ID# for this instruction, the second
1667 /// is the index into the MachineConstantPool that this is, the third is the
1668 /// size in bytes of this constant pool entry.
1669 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1670 def CONSTPOOL_ENTRY :
1671 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1672 i32imm:$size), NoItinerary, []>;
1674 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1675 // from removing one half of the matched pairs. That breaks PEI, which assumes
1676 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1677 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1678 def ADJCALLSTACKUP :
1679 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1680 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1682 def ADJCALLSTACKDOWN :
1683 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1684 [(ARMcallseq_start timm:$amt)]>;
1687 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1688 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1690 let Inst{27-8} = 0b00110010000011110000;
1691 let Inst{7-0} = imm;
1694 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1695 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1696 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1697 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1698 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1699 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1701 def : Pat<(int_arm_sevl), (HINT 5)>;
1703 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1704 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1709 let Inst{15-12} = Rd;
1710 let Inst{19-16} = Rn;
1711 let Inst{27-20} = 0b01101000;
1712 let Inst{7-4} = 0b1011;
1713 let Inst{11-8} = 0b1111;
1714 let Unpredictable{11-8} = 0b1111;
1717 // The 16-bit operand $val can be used by a debugger to store more information
1718 // about the breakpoint.
1719 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1720 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1722 let Inst{3-0} = val{3-0};
1723 let Inst{19-8} = val{15-4};
1724 let Inst{27-20} = 0b00010010;
1725 let Inst{31-28} = 0xe; // AL
1726 let Inst{7-4} = 0b0111;
1729 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1730 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1732 let Inst{3-0} = val{3-0};
1733 let Inst{19-8} = val{15-4};
1734 let Inst{27-20} = 0b00010000;
1735 let Inst{31-28} = 0xe; // AL
1736 let Inst{7-4} = 0b0111;
1739 // Change Processor State
1740 // FIXME: We should use InstAlias to handle the optional operands.
1741 class CPS<dag iops, string asm_ops>
1742 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1743 []>, Requires<[IsARM]> {
1749 let Inst{31-28} = 0b1111;
1750 let Inst{27-20} = 0b00010000;
1751 let Inst{19-18} = imod;
1752 let Inst{17} = M; // Enabled if mode is set;
1753 let Inst{16-9} = 0b00000000;
1754 let Inst{8-6} = iflags;
1756 let Inst{4-0} = mode;
1759 let DecoderMethod = "DecodeCPSInstruction" in {
1761 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1762 "$imod\t$iflags, $mode">;
1763 let mode = 0, M = 0 in
1764 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1766 let imod = 0, iflags = 0, M = 1 in
1767 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1770 // Preload signals the memory system of possible future data/instruction access.
1771 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1773 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1774 !strconcat(opc, "\t$addr"),
1775 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1776 Sched<[WritePreLd]> {
1779 let Inst{31-26} = 0b111101;
1780 let Inst{25} = 0; // 0 for immediate form
1781 let Inst{24} = data;
1782 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1783 let Inst{22} = read;
1784 let Inst{21-20} = 0b01;
1785 let Inst{19-16} = addr{16-13}; // Rn
1786 let Inst{15-12} = 0b1111;
1787 let Inst{11-0} = addr{11-0}; // imm12
1790 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1791 !strconcat(opc, "\t$shift"),
1792 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1793 Sched<[WritePreLd]> {
1795 let Inst{31-26} = 0b111101;
1796 let Inst{25} = 1; // 1 for register form
1797 let Inst{24} = data;
1798 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1799 let Inst{22} = read;
1800 let Inst{21-20} = 0b01;
1801 let Inst{19-16} = shift{16-13}; // Rn
1802 let Inst{15-12} = 0b1111;
1803 let Inst{11-0} = shift{11-0};
1808 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1809 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1810 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1812 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1813 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1815 let Inst{31-10} = 0b1111000100000001000000;
1820 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1821 []>, Requires<[IsARM, HasV7]> {
1823 let Inst{27-4} = 0b001100100000111100001111;
1824 let Inst{3-0} = opt;
1828 * A5.4 Permanently UNDEFINED instructions.
1830 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1831 * Other UDF encodings generate SIGILL.
1833 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1835 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1837 * 1101 1110 iiii iiii
1838 * It uses the following encoding:
1839 * 1110 0111 1111 1110 1101 1110 1111 0000
1840 * - In ARM: UDF #60896;
1841 * - In Thumb: UDF #254 followed by a branch-to-self.
1843 let isBarrier = 1, isTerminator = 1 in
1844 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1846 Requires<[IsARM,UseNaClTrap]> {
1847 let Inst = 0xe7fedef0;
1849 let isBarrier = 1, isTerminator = 1 in
1850 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1852 Requires<[IsARM,DontUseNaClTrap]> {
1853 let Inst = 0xe7ffdefe;
1856 // Address computation and loads and stores in PIC mode.
1857 let isNotDuplicable = 1 in {
1858 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1860 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1861 Sched<[WriteALU, ReadALU]>;
1863 let AddedComplexity = 10 in {
1864 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1866 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1868 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1870 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1872 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1874 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1876 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1878 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1880 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1882 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1884 let AddedComplexity = 10 in {
1885 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1886 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1888 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1889 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1890 addrmodepc:$addr)]>;
1892 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1893 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1895 } // isNotDuplicable = 1
1898 // LEApcrel - Load a pc-relative address into a register without offending the
1900 let neverHasSideEffects = 1, isReMaterializable = 1 in
1901 // The 'adr' mnemonic encodes differently if the label is before or after
1902 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1903 // know until then which form of the instruction will be used.
1904 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1905 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1906 Sched<[WriteALU, ReadALU]> {
1909 let Inst{27-25} = 0b001;
1911 let Inst{23-22} = label{13-12};
1914 let Inst{19-16} = 0b1111;
1915 let Inst{15-12} = Rd;
1916 let Inst{11-0} = label{11-0};
1919 let hasSideEffects = 1 in {
1920 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1921 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1923 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1924 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1925 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1928 //===----------------------------------------------------------------------===//
1929 // Control Flow Instructions.
1932 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1934 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1935 "bx", "\tlr", [(ARMretflag)]>,
1936 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1937 let Inst{27-0} = 0b0001001011111111111100011110;
1941 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1942 "mov", "\tpc, lr", [(ARMretflag)]>,
1943 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1944 let Inst{27-0} = 0b0001101000001111000000001110;
1947 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
1948 // the user-space one).
1949 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
1951 [(ARMintretflag imm:$offset)]>;
1954 // Indirect branches
1955 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1957 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1958 [(brind GPR:$dst)]>,
1959 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1961 let Inst{31-4} = 0b1110000100101111111111110001;
1962 let Inst{3-0} = dst;
1965 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1966 "bx", "\t$dst", [/* pattern left blank */]>,
1967 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1969 let Inst{27-4} = 0b000100101111111111110001;
1970 let Inst{3-0} = dst;
1974 // SP is marked as a use to prevent stack-pointer assignments that appear
1975 // immediately before calls from potentially appearing dead.
1977 // FIXME: Do we really need a non-predicated version? If so, it should
1978 // at least be a pseudo instruction expanding to the predicated version
1979 // at MC lowering time.
1980 Defs = [LR], Uses = [SP] in {
1981 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1982 IIC_Br, "bl\t$func",
1983 [(ARMcall tglobaladdr:$func)]>,
1984 Requires<[IsARM]>, Sched<[WriteBrL]> {
1985 let Inst{31-28} = 0b1110;
1987 let Inst{23-0} = func;
1988 let DecoderMethod = "DecodeBranchImmInstruction";
1991 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1992 IIC_Br, "bl", "\t$func",
1993 [(ARMcall_pred tglobaladdr:$func)]>,
1994 Requires<[IsARM]>, Sched<[WriteBrL]> {
1996 let Inst{23-0} = func;
1997 let DecoderMethod = "DecodeBranchImmInstruction";
2001 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2002 IIC_Br, "blx\t$func",
2003 [(ARMcall GPR:$func)]>,
2004 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2006 let Inst{31-4} = 0b1110000100101111111111110011;
2007 let Inst{3-0} = func;
2010 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2011 IIC_Br, "blx", "\t$func",
2012 [(ARMcall_pred GPR:$func)]>,
2013 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2015 let Inst{27-4} = 0b000100101111111111110011;
2016 let Inst{3-0} = func;
2020 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2021 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2022 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2023 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2026 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2027 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2028 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2030 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2031 // return stack predictor.
2032 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2033 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2034 Requires<[IsARM]>, Sched<[WriteBr]>;
2037 let isBranch = 1, isTerminator = 1 in {
2038 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2039 // a two-value operand where a dag node expects two operands. :(
2040 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2041 IIC_Br, "b", "\t$target",
2042 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2045 let Inst{23-0} = target;
2046 let DecoderMethod = "DecodeBranchImmInstruction";
2049 let isBarrier = 1 in {
2050 // B is "predicable" since it's just a Bcc with an 'always' condition.
2051 let isPredicable = 1 in
2052 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2053 // should be sufficient.
2054 // FIXME: Is B really a Barrier? That doesn't seem right.
2055 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2056 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2059 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2060 def BR_JTr : ARMPseudoInst<(outs),
2061 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2063 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2065 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2066 // into i12 and rs suffixed versions.
2067 def BR_JTm : ARMPseudoInst<(outs),
2068 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2070 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2071 imm:$id)]>, Sched<[WriteBrTbl]>;
2072 def BR_JTadd : ARMPseudoInst<(outs),
2073 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2075 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2076 imm:$id)]>, Sched<[WriteBrTbl]>;
2077 } // isNotDuplicable = 1, isIndirectBranch = 1
2083 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2084 "blx\t$target", []>,
2085 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2086 let Inst{31-25} = 0b1111101;
2088 let Inst{23-0} = target{24-1};
2089 let Inst{24} = target{0};
2092 // Branch and Exchange Jazelle
2093 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2094 [/* pattern left blank */]>, Sched<[WriteBr]> {
2096 let Inst{23-20} = 0b0010;
2097 let Inst{19-8} = 0xfff;
2098 let Inst{7-4} = 0b0010;
2099 let Inst{3-0} = func;
2104 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2105 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2108 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2111 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2113 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2114 Requires<[IsARM]>, Sched<[WriteBr]>;
2116 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2118 (BX GPR:$dst)>, Sched<[WriteBr]>,
2122 // Secure Monitor Call is a system instruction.
2123 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2124 []>, Requires<[IsARM, HasTrustZone]> {
2126 let Inst{23-4} = 0b01100000000000000111;
2127 let Inst{3-0} = opt;
2130 // Supervisor Call (Software Interrupt)
2131 let isCall = 1, Uses = [SP] in {
2132 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2135 let Inst{23-0} = svc;
2139 // Store Return State
2140 class SRSI<bit wb, string asm>
2141 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2142 NoItinerary, asm, "", []> {
2144 let Inst{31-28} = 0b1111;
2145 let Inst{27-25} = 0b100;
2149 let Inst{19-16} = 0b1101; // SP
2150 let Inst{15-5} = 0b00000101000;
2151 let Inst{4-0} = mode;
2154 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2155 let Inst{24-23} = 0;
2157 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2158 let Inst{24-23} = 0;
2160 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2161 let Inst{24-23} = 0b10;
2163 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2164 let Inst{24-23} = 0b10;
2166 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2167 let Inst{24-23} = 0b01;
2169 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2170 let Inst{24-23} = 0b01;
2172 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2173 let Inst{24-23} = 0b11;
2175 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2176 let Inst{24-23} = 0b11;
2179 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2180 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2182 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2183 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2185 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2186 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2188 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2189 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2191 // Return From Exception
2192 class RFEI<bit wb, string asm>
2193 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2194 NoItinerary, asm, "", []> {
2196 let Inst{31-28} = 0b1111;
2197 let Inst{27-25} = 0b100;
2201 let Inst{19-16} = Rn;
2202 let Inst{15-0} = 0xa00;
2205 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2206 let Inst{24-23} = 0;
2208 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2209 let Inst{24-23} = 0;
2211 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2212 let Inst{24-23} = 0b10;
2214 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2215 let Inst{24-23} = 0b10;
2217 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2218 let Inst{24-23} = 0b01;
2220 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2221 let Inst{24-23} = 0b01;
2223 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2224 let Inst{24-23} = 0b11;
2226 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2227 let Inst{24-23} = 0b11;
2230 //===----------------------------------------------------------------------===//
2231 // Load / Store Instructions.
2237 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2238 UnOpFrag<(load node:$Src)>>;
2239 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2240 UnOpFrag<(zextloadi8 node:$Src)>>;
2241 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2242 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2243 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2244 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2246 // Special LDR for loads from non-pc-relative constpools.
2247 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2248 isReMaterializable = 1, isCodeGenOnly = 1 in
2249 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2250 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2254 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2255 let Inst{19-16} = 0b1111;
2256 let Inst{15-12} = Rt;
2257 let Inst{11-0} = addr{11-0}; // imm12
2260 // Loads with zero extension
2261 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2262 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2263 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2265 // Loads with sign extension
2266 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2267 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2268 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2270 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2271 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2272 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2274 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2276 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2277 (ins addrmode3:$addr), LdMiscFrm,
2278 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2279 []>, Requires<[IsARM, HasV5TE]>;
2282 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2283 NoItinerary, "lda", "\t$Rt, $addr", []>;
2284 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2285 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2286 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2287 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2290 multiclass AI2_ldridx<bit isByte, string opc,
2291 InstrItinClass iii, InstrItinClass iir> {
2292 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2293 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2294 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2297 let Inst{23} = addr{12};
2298 let Inst{19-16} = addr{16-13};
2299 let Inst{11-0} = addr{11-0};
2300 let DecoderMethod = "DecodeLDRPreImm";
2303 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2304 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2305 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2308 let Inst{23} = addr{12};
2309 let Inst{19-16} = addr{16-13};
2310 let Inst{11-0} = addr{11-0};
2312 let DecoderMethod = "DecodeLDRPreReg";
2315 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2316 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2317 IndexModePost, LdFrm, iir,
2318 opc, "\t$Rt, $addr, $offset",
2319 "$addr.base = $Rn_wb", []> {
2325 let Inst{23} = offset{12};
2326 let Inst{19-16} = addr;
2327 let Inst{11-0} = offset{11-0};
2330 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2333 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2334 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2335 IndexModePost, LdFrm, iii,
2336 opc, "\t$Rt, $addr, $offset",
2337 "$addr.base = $Rn_wb", []> {
2343 let Inst{23} = offset{12};
2344 let Inst{19-16} = addr;
2345 let Inst{11-0} = offset{11-0};
2347 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2352 let mayLoad = 1, neverHasSideEffects = 1 in {
2353 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2354 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2355 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2356 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2359 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2360 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2361 (ins addrmode3_pre:$addr), IndexModePre,
2363 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2365 let Inst{23} = addr{8}; // U bit
2366 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2367 let Inst{19-16} = addr{12-9}; // Rn
2368 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2369 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2370 let DecoderMethod = "DecodeAddrMode3Instruction";
2372 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2373 (ins addr_offset_none:$addr, am3offset:$offset),
2374 IndexModePost, LdMiscFrm, itin,
2375 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2379 let Inst{23} = offset{8}; // U bit
2380 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2381 let Inst{19-16} = addr;
2382 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2383 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2384 let DecoderMethod = "DecodeAddrMode3Instruction";
2388 let mayLoad = 1, neverHasSideEffects = 1 in {
2389 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2390 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2391 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2392 let hasExtraDefRegAllocReq = 1 in {
2393 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2394 (ins addrmode3_pre:$addr), IndexModePre,
2395 LdMiscFrm, IIC_iLoad_d_ru,
2396 "ldrd", "\t$Rt, $Rt2, $addr!",
2397 "$addr.base = $Rn_wb", []> {
2399 let Inst{23} = addr{8}; // U bit
2400 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2401 let Inst{19-16} = addr{12-9}; // Rn
2402 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2403 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2404 let DecoderMethod = "DecodeAddrMode3Instruction";
2406 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2407 (ins addr_offset_none:$addr, am3offset:$offset),
2408 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2409 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2410 "$addr.base = $Rn_wb", []> {
2413 let Inst{23} = offset{8}; // U bit
2414 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2415 let Inst{19-16} = addr;
2416 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2417 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2418 let DecoderMethod = "DecodeAddrMode3Instruction";
2420 } // hasExtraDefRegAllocReq = 1
2421 } // mayLoad = 1, neverHasSideEffects = 1
2423 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2424 let mayLoad = 1, neverHasSideEffects = 1 in {
2425 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2426 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2427 IndexModePost, LdFrm, IIC_iLoad_ru,
2428 "ldrt", "\t$Rt, $addr, $offset",
2429 "$addr.base = $Rn_wb", []> {
2435 let Inst{23} = offset{12};
2436 let Inst{21} = 1; // overwrite
2437 let Inst{19-16} = addr;
2438 let Inst{11-5} = offset{11-5};
2440 let Inst{3-0} = offset{3-0};
2441 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2444 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2445 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2446 IndexModePost, LdFrm, IIC_iLoad_ru,
2447 "ldrt", "\t$Rt, $addr, $offset",
2448 "$addr.base = $Rn_wb", []> {
2454 let Inst{23} = offset{12};
2455 let Inst{21} = 1; // overwrite
2456 let Inst{19-16} = addr;
2457 let Inst{11-0} = offset{11-0};
2458 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2461 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2462 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2463 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2464 "ldrbt", "\t$Rt, $addr, $offset",
2465 "$addr.base = $Rn_wb", []> {
2471 let Inst{23} = offset{12};
2472 let Inst{21} = 1; // overwrite
2473 let Inst{19-16} = addr;
2474 let Inst{11-5} = offset{11-5};
2476 let Inst{3-0} = offset{3-0};
2477 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2480 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2481 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2482 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2483 "ldrbt", "\t$Rt, $addr, $offset",
2484 "$addr.base = $Rn_wb", []> {
2490 let Inst{23} = offset{12};
2491 let Inst{21} = 1; // overwrite
2492 let Inst{19-16} = addr;
2493 let Inst{11-0} = offset{11-0};
2494 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2497 multiclass AI3ldrT<bits<4> op, string opc> {
2498 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2499 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2500 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2501 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2503 let Inst{23} = offset{8};
2505 let Inst{11-8} = offset{7-4};
2506 let Inst{3-0} = offset{3-0};
2508 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2509 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2510 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2511 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2513 let Inst{23} = Rm{4};
2516 let Unpredictable{11-8} = 0b1111;
2517 let Inst{3-0} = Rm{3-0};
2518 let DecoderMethod = "DecodeLDR";
2522 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2523 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2524 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2529 // Stores with truncate
2530 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2531 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2532 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2535 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2536 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2537 StMiscFrm, IIC_iStore_d_r,
2538 "strd", "\t$Rt, $src2, $addr", []>,
2539 Requires<[IsARM, HasV5TE]> {
2544 multiclass AI2_stridx<bit isByte, string opc,
2545 InstrItinClass iii, InstrItinClass iir> {
2546 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2547 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2549 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2552 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2553 let Inst{19-16} = addr{16-13}; // Rn
2554 let Inst{11-0} = addr{11-0}; // imm12
2555 let DecoderMethod = "DecodeSTRPreImm";
2558 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2559 (ins GPR:$Rt, ldst_so_reg:$addr),
2560 IndexModePre, StFrm, iir,
2561 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2564 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2565 let Inst{19-16} = addr{16-13}; // Rn
2566 let Inst{11-0} = addr{11-0};
2567 let Inst{4} = 0; // Inst{4} = 0
2568 let DecoderMethod = "DecodeSTRPreReg";
2570 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2571 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2572 IndexModePost, StFrm, iir,
2573 opc, "\t$Rt, $addr, $offset",
2574 "$addr.base = $Rn_wb", []> {
2580 let Inst{23} = offset{12};
2581 let Inst{19-16} = addr;
2582 let Inst{11-0} = offset{11-0};
2585 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2588 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2589 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2590 IndexModePost, StFrm, iii,
2591 opc, "\t$Rt, $addr, $offset",
2592 "$addr.base = $Rn_wb", []> {
2598 let Inst{23} = offset{12};
2599 let Inst{19-16} = addr;
2600 let Inst{11-0} = offset{11-0};
2602 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2606 let mayStore = 1, neverHasSideEffects = 1 in {
2607 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2608 // IIC_iStore_siu depending on whether it the offset register is shifted.
2609 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2610 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2613 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2614 am2offset_reg:$offset),
2615 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2616 am2offset_reg:$offset)>;
2617 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2618 am2offset_imm:$offset),
2619 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2620 am2offset_imm:$offset)>;
2621 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2622 am2offset_reg:$offset),
2623 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2624 am2offset_reg:$offset)>;
2625 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2626 am2offset_imm:$offset),
2627 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2628 am2offset_imm:$offset)>;
2630 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2631 // put the patterns on the instruction definitions directly as ISel wants
2632 // the address base and offset to be separate operands, not a single
2633 // complex operand like we represent the instructions themselves. The
2634 // pseudos map between the two.
2635 let usesCustomInserter = 1,
2636 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2637 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2638 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2641 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2642 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2643 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2646 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2647 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2648 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2651 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2652 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2653 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2656 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2657 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2658 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2661 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2666 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2667 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2668 StMiscFrm, IIC_iStore_bh_ru,
2669 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2671 let Inst{23} = addr{8}; // U bit
2672 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2673 let Inst{19-16} = addr{12-9}; // Rn
2674 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2675 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2676 let DecoderMethod = "DecodeAddrMode3Instruction";
2679 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2680 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2681 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2682 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2683 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2684 addr_offset_none:$addr,
2685 am3offset:$offset))]> {
2688 let Inst{23} = offset{8}; // U bit
2689 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2690 let Inst{19-16} = addr;
2691 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2692 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2693 let DecoderMethod = "DecodeAddrMode3Instruction";
2696 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2697 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2698 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2699 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2700 "strd", "\t$Rt, $Rt2, $addr!",
2701 "$addr.base = $Rn_wb", []> {
2703 let Inst{23} = addr{8}; // U bit
2704 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2705 let Inst{19-16} = addr{12-9}; // Rn
2706 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2707 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2708 let DecoderMethod = "DecodeAddrMode3Instruction";
2711 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2712 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2714 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2715 "strd", "\t$Rt, $Rt2, $addr, $offset",
2716 "$addr.base = $Rn_wb", []> {
2719 let Inst{23} = offset{8}; // U bit
2720 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2721 let Inst{19-16} = addr;
2722 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2723 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2724 let DecoderMethod = "DecodeAddrMode3Instruction";
2726 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2728 // STRT, STRBT, and STRHT
2730 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2731 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2732 IndexModePost, StFrm, IIC_iStore_bh_ru,
2733 "strbt", "\t$Rt, $addr, $offset",
2734 "$addr.base = $Rn_wb", []> {
2740 let Inst{23} = offset{12};
2741 let Inst{21} = 1; // overwrite
2742 let Inst{19-16} = addr;
2743 let Inst{11-5} = offset{11-5};
2745 let Inst{3-0} = offset{3-0};
2746 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2749 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2750 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2751 IndexModePost, StFrm, IIC_iStore_bh_ru,
2752 "strbt", "\t$Rt, $addr, $offset",
2753 "$addr.base = $Rn_wb", []> {
2759 let Inst{23} = offset{12};
2760 let Inst{21} = 1; // overwrite
2761 let Inst{19-16} = addr;
2762 let Inst{11-0} = offset{11-0};
2763 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2766 let mayStore = 1, neverHasSideEffects = 1 in {
2767 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2768 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2769 IndexModePost, StFrm, IIC_iStore_ru,
2770 "strt", "\t$Rt, $addr, $offset",
2771 "$addr.base = $Rn_wb", []> {
2777 let Inst{23} = offset{12};
2778 let Inst{21} = 1; // overwrite
2779 let Inst{19-16} = addr;
2780 let Inst{11-5} = offset{11-5};
2782 let Inst{3-0} = offset{3-0};
2783 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2786 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2787 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2788 IndexModePost, StFrm, IIC_iStore_ru,
2789 "strt", "\t$Rt, $addr, $offset",
2790 "$addr.base = $Rn_wb", []> {
2796 let Inst{23} = offset{12};
2797 let Inst{21} = 1; // overwrite
2798 let Inst{19-16} = addr;
2799 let Inst{11-0} = offset{11-0};
2800 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2805 multiclass AI3strT<bits<4> op, string opc> {
2806 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2807 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2808 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2809 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2811 let Inst{23} = offset{8};
2813 let Inst{11-8} = offset{7-4};
2814 let Inst{3-0} = offset{3-0};
2816 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2817 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2818 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2819 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2821 let Inst{23} = Rm{4};
2824 let Inst{3-0} = Rm{3-0};
2829 defm STRHT : AI3strT<0b1011, "strht">;
2831 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2832 NoItinerary, "stl", "\t$Rt, $addr", []>;
2833 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2834 NoItinerary, "stlb", "\t$Rt, $addr", []>;
2835 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2836 NoItinerary, "stlh", "\t$Rt, $addr", []>;
2838 //===----------------------------------------------------------------------===//
2839 // Load / store multiple Instructions.
2842 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2843 InstrItinClass itin, InstrItinClass itin_upd> {
2844 // IA is the default, so no need for an explicit suffix on the
2845 // mnemonic here. Without it is the canonical spelling.
2847 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2848 IndexModeNone, f, itin,
2849 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2850 let Inst{24-23} = 0b01; // Increment After
2851 let Inst{22} = P_bit;
2852 let Inst{21} = 0; // No writeback
2853 let Inst{20} = L_bit;
2856 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2857 IndexModeUpd, f, itin_upd,
2858 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2859 let Inst{24-23} = 0b01; // Increment After
2860 let Inst{22} = P_bit;
2861 let Inst{21} = 1; // Writeback
2862 let Inst{20} = L_bit;
2864 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2867 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2868 IndexModeNone, f, itin,
2869 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2870 let Inst{24-23} = 0b00; // Decrement After
2871 let Inst{22} = P_bit;
2872 let Inst{21} = 0; // No writeback
2873 let Inst{20} = L_bit;
2876 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2877 IndexModeUpd, f, itin_upd,
2878 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2879 let Inst{24-23} = 0b00; // Decrement After
2880 let Inst{22} = P_bit;
2881 let Inst{21} = 1; // Writeback
2882 let Inst{20} = L_bit;
2884 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2887 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2888 IndexModeNone, f, itin,
2889 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2890 let Inst{24-23} = 0b10; // Decrement Before
2891 let Inst{22} = P_bit;
2892 let Inst{21} = 0; // No writeback
2893 let Inst{20} = L_bit;
2896 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2897 IndexModeUpd, f, itin_upd,
2898 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2899 let Inst{24-23} = 0b10; // Decrement Before
2900 let Inst{22} = P_bit;
2901 let Inst{21} = 1; // Writeback
2902 let Inst{20} = L_bit;
2904 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2907 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2908 IndexModeNone, f, itin,
2909 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2910 let Inst{24-23} = 0b11; // Increment Before
2911 let Inst{22} = P_bit;
2912 let Inst{21} = 0; // No writeback
2913 let Inst{20} = L_bit;
2916 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2917 IndexModeUpd, f, itin_upd,
2918 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2919 let Inst{24-23} = 0b11; // Increment Before
2920 let Inst{22} = P_bit;
2921 let Inst{21} = 1; // Writeback
2922 let Inst{20} = L_bit;
2924 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2928 let neverHasSideEffects = 1 in {
2930 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2931 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2934 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2935 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2938 } // neverHasSideEffects
2940 // FIXME: remove when we have a way to marking a MI with these properties.
2941 // FIXME: Should pc be an implicit operand like PICADD, etc?
2942 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2943 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2944 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2945 reglist:$regs, variable_ops),
2946 4, IIC_iLoad_mBr, [],
2947 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2948 RegConstraint<"$Rn = $wb">;
2950 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2951 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2954 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2955 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2960 //===----------------------------------------------------------------------===//
2961 // Move Instructions.
2964 let neverHasSideEffects = 1 in
2965 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2966 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2970 let Inst{19-16} = 0b0000;
2971 let Inst{11-4} = 0b00000000;
2974 let Inst{15-12} = Rd;
2977 // A version for the smaller set of tail call registers.
2978 let neverHasSideEffects = 1 in
2979 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2980 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2984 let Inst{11-4} = 0b00000000;
2987 let Inst{15-12} = Rd;
2990 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2991 DPSoRegRegFrm, IIC_iMOVsr,
2992 "mov", "\t$Rd, $src",
2993 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
2997 let Inst{15-12} = Rd;
2998 let Inst{19-16} = 0b0000;
2999 let Inst{11-8} = src{11-8};
3001 let Inst{6-5} = src{6-5};
3003 let Inst{3-0} = src{3-0};
3007 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3008 DPSoRegImmFrm, IIC_iMOVsr,
3009 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3010 UnaryDP, Sched<[WriteALU]> {
3013 let Inst{15-12} = Rd;
3014 let Inst{19-16} = 0b0000;
3015 let Inst{11-5} = src{11-5};
3017 let Inst{3-0} = src{3-0};
3021 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3022 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3023 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3028 let Inst{15-12} = Rd;
3029 let Inst{19-16} = 0b0000;
3030 let Inst{11-0} = imm;
3033 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3034 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3036 "movw", "\t$Rd, $imm",
3037 [(set GPR:$Rd, imm0_65535:$imm)]>,
3038 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3041 let Inst{15-12} = Rd;
3042 let Inst{11-0} = imm{11-0};
3043 let Inst{19-16} = imm{15-12};
3046 let DecoderMethod = "DecodeArmMOVTWInstruction";
3049 def : InstAlias<"mov${p} $Rd, $imm",
3050 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3053 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3054 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3057 let Constraints = "$src = $Rd" in {
3058 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3059 (ins GPR:$src, imm0_65535_expr:$imm),
3061 "movt", "\t$Rd, $imm",
3063 (or (and GPR:$src, 0xffff),
3064 lo16AllZero:$imm))]>, UnaryDP,
3065 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3068 let Inst{15-12} = Rd;
3069 let Inst{11-0} = imm{11-0};
3070 let Inst{19-16} = imm{15-12};
3073 let DecoderMethod = "DecodeArmMOVTWInstruction";
3076 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3077 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3082 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3083 Requires<[IsARM, HasV6T2]>;
3085 let Uses = [CPSR] in
3086 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3087 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3088 Requires<[IsARM]>, Sched<[WriteALU]>;
3090 // These aren't really mov instructions, but we have to define them this way
3091 // due to flag operands.
3093 let Defs = [CPSR] in {
3094 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3095 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3096 Sched<[WriteALU]>, Requires<[IsARM]>;
3097 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3098 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3099 Sched<[WriteALU]>, Requires<[IsARM]>;
3102 //===----------------------------------------------------------------------===//
3103 // Extend Instructions.
3108 def SXTB : AI_ext_rrot<0b01101010,
3109 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3110 def SXTH : AI_ext_rrot<0b01101011,
3111 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3113 def SXTAB : AI_exta_rrot<0b01101010,
3114 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3115 def SXTAH : AI_exta_rrot<0b01101011,
3116 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3118 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3120 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3124 let AddedComplexity = 16 in {
3125 def UXTB : AI_ext_rrot<0b01101110,
3126 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3127 def UXTH : AI_ext_rrot<0b01101111,
3128 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3129 def UXTB16 : AI_ext_rrot<0b01101100,
3130 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3132 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3133 // The transformation should probably be done as a combiner action
3134 // instead so we can include a check for masking back in the upper
3135 // eight bits of the source into the lower eight bits of the result.
3136 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3137 // (UXTB16r_rot GPR:$Src, 3)>;
3138 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3139 (UXTB16 GPR:$Src, 1)>;
3141 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3142 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3143 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3144 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3147 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3148 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3151 def SBFX : I<(outs GPRnopc:$Rd),
3152 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3153 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3154 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3155 Requires<[IsARM, HasV6T2]> {
3160 let Inst{27-21} = 0b0111101;
3161 let Inst{6-4} = 0b101;
3162 let Inst{20-16} = width;
3163 let Inst{15-12} = Rd;
3164 let Inst{11-7} = lsb;
3168 def UBFX : I<(outs GPR:$Rd),
3169 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3170 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3171 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3172 Requires<[IsARM, HasV6T2]> {
3177 let Inst{27-21} = 0b0111111;
3178 let Inst{6-4} = 0b101;
3179 let Inst{20-16} = width;
3180 let Inst{15-12} = Rd;
3181 let Inst{11-7} = lsb;
3185 //===----------------------------------------------------------------------===//
3186 // Arithmetic Instructions.
3189 defm ADD : AsI1_bin_irs<0b0100, "add",
3190 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3191 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3192 defm SUB : AsI1_bin_irs<0b0010, "sub",
3193 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3194 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3196 // ADD and SUB with 's' bit set.
3198 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3199 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3200 // AdjustInstrPostInstrSelection where we determine whether or not to
3201 // set the "s" bit based on CPSR liveness.
3203 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3204 // support for an optional CPSR definition that corresponds to the DAG
3205 // node's second value. We can then eliminate the implicit def of CPSR.
3206 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3207 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3208 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3209 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3211 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3212 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3213 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3214 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3216 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3217 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3218 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3220 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3221 // CPSR and the implicit def of CPSR is not needed.
3222 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3223 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3225 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3226 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3228 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3229 // The assume-no-carry-in form uses the negation of the input since add/sub
3230 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3231 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3233 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3234 (SUBri GPR:$src, so_imm_neg:$imm)>;
3235 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3236 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3238 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3239 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3240 Requires<[IsARM, HasV6T2]>;
3241 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3242 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3243 Requires<[IsARM, HasV6T2]>;
3245 // The with-carry-in form matches bitwise not instead of the negation.
3246 // Effectively, the inverse interpretation of the carry flag already accounts
3247 // for part of the negation.
3248 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3249 (SBCri GPR:$src, so_imm_not:$imm)>;
3250 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3251 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3253 // Note: These are implemented in C++ code, because they have to generate
3254 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3256 // (mul X, 2^n+1) -> (add (X << n), X)
3257 // (mul X, 2^n-1) -> (rsb X, (X << n))
3259 // ARM Arithmetic Instruction
3260 // GPR:$dst = GPR:$a op GPR:$b
3261 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3262 list<dag> pattern = [],
3263 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3264 string asm = "\t$Rd, $Rn, $Rm">
3265 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3266 Sched<[WriteALU, ReadALU, ReadALU]> {
3270 let Inst{27-20} = op27_20;
3271 let Inst{11-4} = op11_4;
3272 let Inst{19-16} = Rn;
3273 let Inst{15-12} = Rd;
3276 let Unpredictable{11-8} = 0b1111;
3279 // Saturating add/subtract
3281 let DecoderMethod = "DecodeQADDInstruction" in
3282 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3283 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3284 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3286 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3287 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3288 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3289 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3290 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3292 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3293 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3296 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3297 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3298 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3299 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3300 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3301 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3302 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3303 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3304 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3305 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3306 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3307 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3309 // Signed/Unsigned add/subtract
3311 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3312 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3313 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3314 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3315 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3316 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3317 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3318 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3319 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3320 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3321 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3322 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3324 // Signed/Unsigned halving add/subtract
3326 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3327 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3328 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3329 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3330 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3331 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3332 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3333 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3334 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3335 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3336 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3337 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3339 // Unsigned Sum of Absolute Differences [and Accumulate].
3341 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3342 MulFrm /* for convenience */, NoItinerary, "usad8",
3343 "\t$Rd, $Rn, $Rm", []>,
3344 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3348 let Inst{27-20} = 0b01111000;
3349 let Inst{15-12} = 0b1111;
3350 let Inst{7-4} = 0b0001;
3351 let Inst{19-16} = Rd;
3352 let Inst{11-8} = Rm;
3355 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3356 MulFrm /* for convenience */, NoItinerary, "usada8",
3357 "\t$Rd, $Rn, $Rm, $Ra", []>,
3358 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3363 let Inst{27-20} = 0b01111000;
3364 let Inst{7-4} = 0b0001;
3365 let Inst{19-16} = Rd;
3366 let Inst{15-12} = Ra;
3367 let Inst{11-8} = Rm;
3371 // Signed/Unsigned saturate
3373 def SSAT : AI<(outs GPRnopc:$Rd),
3374 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3375 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3380 let Inst{27-21} = 0b0110101;
3381 let Inst{5-4} = 0b01;
3382 let Inst{20-16} = sat_imm;
3383 let Inst{15-12} = Rd;
3384 let Inst{11-7} = sh{4-0};
3385 let Inst{6} = sh{5};
3389 def SSAT16 : AI<(outs GPRnopc:$Rd),
3390 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3391 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3395 let Inst{27-20} = 0b01101010;
3396 let Inst{11-4} = 0b11110011;
3397 let Inst{15-12} = Rd;
3398 let Inst{19-16} = sat_imm;
3402 def USAT : AI<(outs GPRnopc:$Rd),
3403 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3404 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3409 let Inst{27-21} = 0b0110111;
3410 let Inst{5-4} = 0b01;
3411 let Inst{15-12} = Rd;
3412 let Inst{11-7} = sh{4-0};
3413 let Inst{6} = sh{5};
3414 let Inst{20-16} = sat_imm;
3418 def USAT16 : AI<(outs GPRnopc:$Rd),
3419 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3420 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3424 let Inst{27-20} = 0b01101110;
3425 let Inst{11-4} = 0b11110011;
3426 let Inst{15-12} = Rd;
3427 let Inst{19-16} = sat_imm;
3431 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3432 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3433 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3434 (USAT imm:$pos, GPRnopc:$a, 0)>;
3436 //===----------------------------------------------------------------------===//
3437 // Bitwise Instructions.
3440 defm AND : AsI1_bin_irs<0b0000, "and",
3441 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3442 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3443 defm ORR : AsI1_bin_irs<0b1100, "orr",
3444 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3445 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3446 defm EOR : AsI1_bin_irs<0b0001, "eor",
3447 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3448 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3449 defm BIC : AsI1_bin_irs<0b1110, "bic",
3450 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3451 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3453 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3454 // like in the actual instruction encoding. The complexity of mapping the mask
3455 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3456 // instruction description.
3457 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3458 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3459 "bfc", "\t$Rd, $imm", "$src = $Rd",
3460 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3461 Requires<[IsARM, HasV6T2]> {
3464 let Inst{27-21} = 0b0111110;
3465 let Inst{6-0} = 0b0011111;
3466 let Inst{15-12} = Rd;
3467 let Inst{11-7} = imm{4-0}; // lsb
3468 let Inst{20-16} = imm{9-5}; // msb
3471 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3472 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3473 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3474 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3475 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3476 bf_inv_mask_imm:$imm))]>,
3477 Requires<[IsARM, HasV6T2]> {
3481 let Inst{27-21} = 0b0111110;
3482 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3483 let Inst{15-12} = Rd;
3484 let Inst{11-7} = imm{4-0}; // lsb
3485 let Inst{20-16} = imm{9-5}; // width
3489 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3490 "mvn", "\t$Rd, $Rm",
3491 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3495 let Inst{19-16} = 0b0000;
3496 let Inst{11-4} = 0b00000000;
3497 let Inst{15-12} = Rd;
3500 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3501 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3502 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3507 let Inst{19-16} = 0b0000;
3508 let Inst{15-12} = Rd;
3509 let Inst{11-5} = shift{11-5};
3511 let Inst{3-0} = shift{3-0};
3513 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3514 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3515 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3520 let Inst{19-16} = 0b0000;
3521 let Inst{15-12} = Rd;
3522 let Inst{11-8} = shift{11-8};
3524 let Inst{6-5} = shift{6-5};
3526 let Inst{3-0} = shift{3-0};
3528 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3529 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3530 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3531 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3535 let Inst{19-16} = 0b0000;
3536 let Inst{15-12} = Rd;
3537 let Inst{11-0} = imm;
3540 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3541 (BICri GPR:$src, so_imm_not:$imm)>;
3543 //===----------------------------------------------------------------------===//
3544 // Multiply Instructions.
3546 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3547 string opc, string asm, list<dag> pattern>
3548 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3552 let Inst{19-16} = Rd;
3553 let Inst{11-8} = Rm;
3556 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3557 string opc, string asm, list<dag> pattern>
3558 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3563 let Inst{19-16} = RdHi;
3564 let Inst{15-12} = RdLo;
3565 let Inst{11-8} = Rm;
3568 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3569 string opc, string asm, list<dag> pattern>
3570 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3575 let Inst{19-16} = RdHi;
3576 let Inst{15-12} = RdLo;
3577 let Inst{11-8} = Rm;
3581 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3582 // property. Remove them when it's possible to add those properties
3583 // on an individual MachineInstr, not just an instruction description.
3584 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3585 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3586 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3587 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3588 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3589 Requires<[IsARM, HasV6]> {
3590 let Inst{15-12} = 0b0000;
3591 let Unpredictable{15-12} = 0b1111;
3594 let Constraints = "@earlyclobber $Rd" in
3595 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3596 pred:$p, cc_out:$s),
3598 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3599 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3600 Requires<[IsARM, NoV6, UseMulOps]>;
3603 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3604 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3605 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3606 Requires<[IsARM, HasV6, UseMulOps]> {
3608 let Inst{15-12} = Ra;
3611 let Constraints = "@earlyclobber $Rd" in
3612 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3613 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3615 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3616 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3617 Requires<[IsARM, NoV6]>;
3619 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3620 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3621 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3622 Requires<[IsARM, HasV6T2, UseMulOps]> {
3627 let Inst{19-16} = Rd;
3628 let Inst{15-12} = Ra;
3629 let Inst{11-8} = Rm;
3633 // Extra precision multiplies with low / high results
3634 let neverHasSideEffects = 1 in {
3635 let isCommutable = 1 in {
3636 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3637 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3638 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3639 Requires<[IsARM, HasV6]>;
3641 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3642 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3643 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3644 Requires<[IsARM, HasV6]>;
3646 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3647 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3648 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3650 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3651 Requires<[IsARM, NoV6]>;
3653 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3654 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3656 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3657 Requires<[IsARM, NoV6]>;
3661 // Multiply + accumulate
3662 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3663 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3664 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3665 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3666 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3667 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3668 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3669 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3671 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3672 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3673 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3674 Requires<[IsARM, HasV6]> {
3679 let Inst{19-16} = RdHi;
3680 let Inst{15-12} = RdLo;
3681 let Inst{11-8} = Rm;
3685 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3686 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3687 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3689 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3690 pred:$p, cc_out:$s)>,
3691 Requires<[IsARM, NoV6]>;
3692 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3693 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3695 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3696 pred:$p, cc_out:$s)>,
3697 Requires<[IsARM, NoV6]>;
3700 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3701 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3702 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3704 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3705 Requires<[IsARM, NoV6]>;
3708 } // neverHasSideEffects
3710 // Most significant word multiply
3711 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3712 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3713 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3714 Requires<[IsARM, HasV6]> {
3715 let Inst{15-12} = 0b1111;
3718 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3719 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3720 Requires<[IsARM, HasV6]> {
3721 let Inst{15-12} = 0b1111;
3724 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3725 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3726 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3727 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3728 Requires<[IsARM, HasV6, UseMulOps]>;
3730 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3731 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3732 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3733 Requires<[IsARM, HasV6]>;
3735 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3736 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3737 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3738 Requires<[IsARM, HasV6, UseMulOps]>;
3740 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3741 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3742 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3743 Requires<[IsARM, HasV6]>;
3745 multiclass AI_smul<string opc, PatFrag opnode> {
3746 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3747 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3748 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3749 (sext_inreg GPR:$Rm, i16)))]>,
3750 Requires<[IsARM, HasV5TE]>;
3752 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3753 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3754 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3755 (sra GPR:$Rm, (i32 16))))]>,
3756 Requires<[IsARM, HasV5TE]>;
3758 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3759 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3760 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3761 (sext_inreg GPR:$Rm, i16)))]>,
3762 Requires<[IsARM, HasV5TE]>;
3764 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3765 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3766 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3767 (sra GPR:$Rm, (i32 16))))]>,
3768 Requires<[IsARM, HasV5TE]>;
3770 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3771 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3772 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3773 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3774 Requires<[IsARM, HasV5TE]>;
3776 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3777 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3778 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3779 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3780 Requires<[IsARM, HasV5TE]>;
3784 multiclass AI_smla<string opc, PatFrag opnode> {
3785 let DecoderMethod = "DecodeSMLAInstruction" in {
3786 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3787 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3788 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3789 [(set GPRnopc:$Rd, (add GPR:$Ra,
3790 (opnode (sext_inreg GPRnopc:$Rn, i16),
3791 (sext_inreg GPRnopc:$Rm, i16))))]>,
3792 Requires<[IsARM, HasV5TE, UseMulOps]>;
3794 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3795 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3796 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3798 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3799 (sra GPRnopc:$Rm, (i32 16)))))]>,
3800 Requires<[IsARM, HasV5TE, UseMulOps]>;
3802 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3803 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3804 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3806 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3807 (sext_inreg GPRnopc:$Rm, i16))))]>,
3808 Requires<[IsARM, HasV5TE, UseMulOps]>;
3810 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3811 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3812 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3814 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3815 (sra GPRnopc:$Rm, (i32 16)))))]>,
3816 Requires<[IsARM, HasV5TE, UseMulOps]>;
3818 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3819 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3820 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3822 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3823 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3824 Requires<[IsARM, HasV5TE, UseMulOps]>;
3826 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3827 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3828 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3830 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3831 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3832 Requires<[IsARM, HasV5TE, UseMulOps]>;
3836 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3837 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3839 // Halfword multiply accumulate long: SMLAL<x><y>.
3840 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3841 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3842 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3843 Requires<[IsARM, HasV5TE]>;
3845 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3846 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3847 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3848 Requires<[IsARM, HasV5TE]>;
3850 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3851 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3852 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3853 Requires<[IsARM, HasV5TE]>;
3855 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3856 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3857 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3858 Requires<[IsARM, HasV5TE]>;
3860 // Helper class for AI_smld.
3861 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3862 InstrItinClass itin, string opc, string asm>
3863 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3866 let Inst{27-23} = 0b01110;
3867 let Inst{22} = long;
3868 let Inst{21-20} = 0b00;
3869 let Inst{11-8} = Rm;
3876 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3877 InstrItinClass itin, string opc, string asm>
3878 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3880 let Inst{15-12} = 0b1111;
3881 let Inst{19-16} = Rd;
3883 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3884 InstrItinClass itin, string opc, string asm>
3885 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3888 let Inst{19-16} = Rd;
3889 let Inst{15-12} = Ra;
3891 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3892 InstrItinClass itin, string opc, string asm>
3893 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3896 let Inst{19-16} = RdHi;
3897 let Inst{15-12} = RdLo;
3900 multiclass AI_smld<bit sub, string opc> {
3902 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3903 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3904 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3906 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3907 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3908 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3910 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3911 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3912 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3914 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3915 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3916 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3920 defm SMLA : AI_smld<0, "smla">;
3921 defm SMLS : AI_smld<1, "smls">;
3923 multiclass AI_sdml<bit sub, string opc> {
3925 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3926 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3927 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3928 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3931 defm SMUA : AI_sdml<0, "smua">;
3932 defm SMUS : AI_sdml<1, "smus">;
3934 //===----------------------------------------------------------------------===//
3935 // Division Instructions (ARMv7-A with virtualization extension)
3937 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3938 "sdiv", "\t$Rd, $Rn, $Rm",
3939 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3940 Requires<[IsARM, HasDivideInARM]>;
3942 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3943 "udiv", "\t$Rd, $Rn, $Rm",
3944 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3945 Requires<[IsARM, HasDivideInARM]>;
3947 //===----------------------------------------------------------------------===//
3948 // Misc. Arithmetic Instructions.
3951 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3952 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3953 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3956 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3957 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3958 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3959 Requires<[IsARM, HasV6T2]>,
3962 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3963 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3964 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3967 let AddedComplexity = 5 in
3968 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3969 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3970 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3971 Requires<[IsARM, HasV6]>,
3974 let AddedComplexity = 5 in
3975 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3976 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3977 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3978 Requires<[IsARM, HasV6]>,
3981 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3982 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3985 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3986 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3987 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3988 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3989 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3991 Requires<[IsARM, HasV6]>,
3992 Sched<[WriteALUsi, ReadALU]>;
3994 // Alternate cases for PKHBT where identities eliminate some nodes.
3995 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3996 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3997 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3998 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4000 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4001 // will match the pattern below.
4002 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4003 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4004 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4005 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4006 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4008 Requires<[IsARM, HasV6]>,
4009 Sched<[WriteALUsi, ReadALU]>;
4011 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4012 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4013 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4014 // pkhtb src1, src2, asr (17..31).
4015 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4016 (srl GPRnopc:$src2, imm16:$sh)),
4017 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4018 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4019 (sra GPRnopc:$src2, imm16_31:$sh)),
4020 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4021 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4022 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4023 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4025 //===----------------------------------------------------------------------===//
4029 // + CRC32{B,H,W} 0x04C11DB7
4030 // + CRC32C{B,H,W} 0x1EDC6F41
4033 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4034 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4035 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4036 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4037 Requires<[IsARM, HasV8, HasCRC]> {
4042 let Inst{31-28} = 0b1110;
4043 let Inst{27-23} = 0b00010;
4044 let Inst{22-21} = sz;
4046 let Inst{19-16} = Rn;
4047 let Inst{15-12} = Rd;
4048 let Inst{11-10} = 0b00;
4051 let Inst{7-4} = 0b0100;
4054 let Unpredictable{11-8} = 0b1101;
4057 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4058 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4059 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4060 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4061 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4062 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4064 //===----------------------------------------------------------------------===//
4065 // Comparison Instructions...
4068 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4069 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4070 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4072 // ARMcmpZ can re-use the above instruction definitions.
4073 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4074 (CMPri GPR:$src, so_imm:$imm)>;
4075 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4076 (CMPrr GPR:$src, GPR:$rhs)>;
4077 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4078 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4079 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4080 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4082 // CMN register-integer
4083 let isCompare = 1, Defs = [CPSR] in {
4084 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4085 "cmn", "\t$Rn, $imm",
4086 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4087 Sched<[WriteCMP, ReadALU]> {
4092 let Inst{19-16} = Rn;
4093 let Inst{15-12} = 0b0000;
4094 let Inst{11-0} = imm;
4096 let Unpredictable{15-12} = 0b1111;
4099 // CMN register-register/shift
4100 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4101 "cmn", "\t$Rn, $Rm",
4102 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4103 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4106 let isCommutable = 1;
4109 let Inst{19-16} = Rn;
4110 let Inst{15-12} = 0b0000;
4111 let Inst{11-4} = 0b00000000;
4114 let Unpredictable{15-12} = 0b1111;
4117 def CMNzrsi : AI1<0b1011, (outs),
4118 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4119 "cmn", "\t$Rn, $shift",
4120 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4121 GPR:$Rn, so_reg_imm:$shift)]>,
4122 Sched<[WriteCMPsi, ReadALU]> {
4127 let Inst{19-16} = Rn;
4128 let Inst{15-12} = 0b0000;
4129 let Inst{11-5} = shift{11-5};
4131 let Inst{3-0} = shift{3-0};
4133 let Unpredictable{15-12} = 0b1111;
4136 def CMNzrsr : AI1<0b1011, (outs),
4137 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4138 "cmn", "\t$Rn, $shift",
4139 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4140 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4141 Sched<[WriteCMPsr, ReadALU]> {
4146 let Inst{19-16} = Rn;
4147 let Inst{15-12} = 0b0000;
4148 let Inst{11-8} = shift{11-8};
4150 let Inst{6-5} = shift{6-5};
4152 let Inst{3-0} = shift{3-0};
4154 let Unpredictable{15-12} = 0b1111;
4159 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4160 (CMNri GPR:$src, so_imm_neg:$imm)>;
4162 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4163 (CMNri GPR:$src, so_imm_neg:$imm)>;
4165 // Note that TST/TEQ don't set all the same flags that CMP does!
4166 defm TST : AI1_cmp_irs<0b1000, "tst",
4167 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4168 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4169 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4170 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4171 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4173 // Pseudo i64 compares for some floating point compares.
4174 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4176 def BCCi64 : PseudoInst<(outs),
4177 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4179 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4182 def BCCZi64 : PseudoInst<(outs),
4183 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4184 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4186 } // usesCustomInserter
4189 // Conditional moves
4190 let neverHasSideEffects = 1 in {
4192 let isCommutable = 1, isSelect = 1 in
4193 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4194 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4196 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4198 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4200 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4201 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4204 (ARMcmov GPR:$false, so_reg_imm:$shift,
4206 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4207 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4208 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4210 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4212 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4215 let isMoveImm = 1 in
4217 : ARMPseudoInst<(outs GPR:$Rd),
4218 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4220 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4222 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4225 let isMoveImm = 1 in
4226 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4227 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4229 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4231 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4233 // Two instruction predicate mov immediate.
4234 let isMoveImm = 1 in
4236 : ARMPseudoInst<(outs GPR:$Rd),
4237 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4239 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4241 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4243 let isMoveImm = 1 in
4244 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4245 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4247 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4249 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4251 } // neverHasSideEffects
4254 //===----------------------------------------------------------------------===//
4255 // Atomic operations intrinsics
4258 def MemBarrierOptOperand : AsmOperandClass {
4259 let Name = "MemBarrierOpt";
4260 let ParserMethod = "parseMemBarrierOptOperand";
4262 def memb_opt : Operand<i32> {
4263 let PrintMethod = "printMemBOption";
4264 let ParserMatchClass = MemBarrierOptOperand;
4265 let DecoderMethod = "DecodeMemBarrierOption";
4268 def InstSyncBarrierOptOperand : AsmOperandClass {
4269 let Name = "InstSyncBarrierOpt";
4270 let ParserMethod = "parseInstSyncBarrierOptOperand";
4272 def instsyncb_opt : Operand<i32> {
4273 let PrintMethod = "printInstSyncBOption";
4274 let ParserMatchClass = InstSyncBarrierOptOperand;
4275 let DecoderMethod = "DecodeInstSyncBarrierOption";
4278 // memory barriers protect the atomic sequences
4279 let hasSideEffects = 1 in {
4280 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4281 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4282 Requires<[IsARM, HasDB]> {
4284 let Inst{31-4} = 0xf57ff05;
4285 let Inst{3-0} = opt;
4289 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4290 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4291 Requires<[IsARM, HasDB]> {
4293 let Inst{31-4} = 0xf57ff04;
4294 let Inst{3-0} = opt;
4297 // ISB has only full system option
4298 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4299 "isb", "\t$opt", []>,
4300 Requires<[IsARM, HasDB]> {
4302 let Inst{31-4} = 0xf57ff06;
4303 let Inst{3-0} = opt;
4306 let usesCustomInserter = 1, Defs = [CPSR] in {
4308 // Pseudo instruction that combines movs + predicated rsbmi
4309 // to implement integer ABS
4310 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4312 // Atomic pseudo-insts which will be lowered to ldrex/strex loops.
4313 // (64-bit pseudos use a hand-written selection code).
4314 let mayLoad = 1, mayStore = 1 in {
4315 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4317 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4319 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4321 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4323 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4325 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4327 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4329 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4331 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4333 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4335 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4337 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4339 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4341 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4343 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4345 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4347 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4349 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4351 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4353 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4355 def ATOMIC_SWAP_I8 : PseudoInst<
4357 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4359 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4361 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4363 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4365 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4367 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4369 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4371 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4373 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4375 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4377 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4379 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4381 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4383 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4385 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4387 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4389 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4391 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4393 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4395 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4397 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4399 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4401 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4403 def ATOMIC_SWAP_I16 : PseudoInst<
4405 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4407 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4409 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4411 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4413 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4415 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4417 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4419 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4421 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4423 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4425 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4427 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4429 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4431 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4433 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4435 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4437 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4439 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4441 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4443 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4445 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4447 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4449 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4451 def ATOMIC_SWAP_I32 : PseudoInst<
4453 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4455 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4457 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4459 def ATOMIC_LOAD_ADD_I64 : PseudoInst<
4460 (outs GPR:$dst1, GPR:$dst2),
4461 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4463 def ATOMIC_LOAD_SUB_I64 : PseudoInst<
4464 (outs GPR:$dst1, GPR:$dst2),
4465 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4467 def ATOMIC_LOAD_AND_I64 : PseudoInst<
4468 (outs GPR:$dst1, GPR:$dst2),
4469 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4471 def ATOMIC_LOAD_OR_I64 : PseudoInst<
4472 (outs GPR:$dst1, GPR:$dst2),
4473 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4475 def ATOMIC_LOAD_XOR_I64 : PseudoInst<
4476 (outs GPR:$dst1, GPR:$dst2),
4477 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4479 def ATOMIC_LOAD_NAND_I64 : PseudoInst<
4480 (outs GPR:$dst1, GPR:$dst2),
4481 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4483 def ATOMIC_LOAD_MIN_I64 : PseudoInst<
4484 (outs GPR:$dst1, GPR:$dst2),
4485 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4487 def ATOMIC_LOAD_MAX_I64 : PseudoInst<
4488 (outs GPR:$dst1, GPR:$dst2),
4489 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4491 def ATOMIC_LOAD_UMIN_I64 : PseudoInst<
4492 (outs GPR:$dst1, GPR:$dst2),
4493 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4495 def ATOMIC_LOAD_UMAX_I64 : PseudoInst<
4496 (outs GPR:$dst1, GPR:$dst2),
4497 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4499 def ATOMIC_SWAP_I64 : PseudoInst<
4500 (outs GPR:$dst1, GPR:$dst2),
4501 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4503 def ATOMIC_CMP_SWAP_I64 : PseudoInst<
4504 (outs GPR:$dst1, GPR:$dst2),
4505 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
4506 GPR:$set1, GPR:$set2, i32imm:$ordering),
4510 def ATOMIC_LOAD_I64 : PseudoInst<
4511 (outs GPR:$dst1, GPR:$dst2),
4512 (ins GPR:$addr, i32imm:$ordering),
4515 def ATOMIC_STORE_I64 : PseudoInst<
4516 (outs GPR:$dst1, GPR:$dst2),
4517 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4521 let usesCustomInserter = 1 in {
4522 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4523 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4525 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4528 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4529 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4532 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4533 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4536 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4537 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4540 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4541 (int_arm_strex node:$val, node:$ptr), [{
4542 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4545 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4546 (int_arm_strex node:$val, node:$ptr), [{
4547 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4550 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4551 (int_arm_strex node:$val, node:$ptr), [{
4552 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4555 let mayLoad = 1 in {
4556 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4557 NoItinerary, "ldrexb", "\t$Rt, $addr",
4558 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4559 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4560 NoItinerary, "ldrexh", "\t$Rt, $addr",
4561 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4562 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4563 NoItinerary, "ldrex", "\t$Rt, $addr",
4564 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4565 let hasExtraDefRegAllocReq = 1 in
4566 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4567 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4568 let DecoderMethod = "DecodeDoubleRegLoad";
4571 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4572 NoItinerary, "ldaexb", "\t$Rt, $addr", []>;
4573 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4574 NoItinerary, "ldaexh", "\t$Rt, $addr", []>;
4575 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4576 NoItinerary, "ldaex", "\t$Rt, $addr", []>;
4577 let hasExtraDefRegAllocReq = 1 in
4578 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4579 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4580 let DecoderMethod = "DecodeDoubleRegLoad";
4584 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4585 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4586 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4587 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4588 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4589 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4590 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4591 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4592 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4593 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4594 let hasExtraSrcRegAllocReq = 1 in
4595 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4596 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4597 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4598 let DecoderMethod = "DecodeDoubleRegStore";
4600 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4601 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4603 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4604 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4606 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4607 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4609 let hasExtraSrcRegAllocReq = 1 in
4610 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4611 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4612 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4613 let DecoderMethod = "DecodeDoubleRegStore";
4617 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4619 Requires<[IsARM, HasV7]> {
4620 let Inst{31-0} = 0b11110101011111111111000000011111;
4623 def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
4624 (LDREXB addr_offset_none:$addr)>;
4625 def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
4626 (LDREXH addr_offset_none:$addr)>;
4627 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4628 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4629 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4630 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4632 class acquiring_load<PatFrag base>
4633 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4634 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4635 return Ordering == Acquire || Ordering == SequentiallyConsistent;
4638 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4639 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4640 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4642 class releasing_store<PatFrag base>
4643 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4644 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4645 return Ordering == Release || Ordering == SequentiallyConsistent;
4648 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4649 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4650 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4652 let AddedComplexity = 8 in {
4653 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4654 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4655 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4656 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4657 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4658 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4661 // SWP/SWPB are deprecated in V6/V7.
4662 let mayLoad = 1, mayStore = 1 in {
4663 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4664 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4666 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4667 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4671 //===----------------------------------------------------------------------===//
4672 // Coprocessor Instructions.
4675 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4676 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4677 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4678 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4679 imm:$CRm, imm:$opc2)]> {
4687 let Inst{3-0} = CRm;
4689 let Inst{7-5} = opc2;
4690 let Inst{11-8} = cop;
4691 let Inst{15-12} = CRd;
4692 let Inst{19-16} = CRn;
4693 let Inst{23-20} = opc1;
4696 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4697 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4698 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4699 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4700 imm:$CRm, imm:$opc2)]> {
4701 let Inst{31-28} = 0b1111;
4709 let Inst{3-0} = CRm;
4711 let Inst{7-5} = opc2;
4712 let Inst{11-8} = cop;
4713 let Inst{15-12} = CRd;
4714 let Inst{19-16} = CRn;
4715 let Inst{23-20} = opc1;
4718 class ACI<dag oops, dag iops, string opc, string asm,
4719 IndexMode im = IndexModeNone>
4720 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4722 let Inst{27-25} = 0b110;
4724 class ACInoP<dag oops, dag iops, string opc, string asm,
4725 IndexMode im = IndexModeNone>
4726 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4728 let Inst{31-28} = 0b1111;
4729 let Inst{27-25} = 0b110;
4731 multiclass LdStCop<bit load, bit Dbit, string asm> {
4732 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4733 asm, "\t$cop, $CRd, $addr"> {
4737 let Inst{24} = 1; // P = 1
4738 let Inst{23} = addr{8};
4739 let Inst{22} = Dbit;
4740 let Inst{21} = 0; // W = 0
4741 let Inst{20} = load;
4742 let Inst{19-16} = addr{12-9};
4743 let Inst{15-12} = CRd;
4744 let Inst{11-8} = cop;
4745 let Inst{7-0} = addr{7-0};
4746 let DecoderMethod = "DecodeCopMemInstruction";
4748 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4749 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4753 let Inst{24} = 1; // P = 1
4754 let Inst{23} = addr{8};
4755 let Inst{22} = Dbit;
4756 let Inst{21} = 1; // W = 1
4757 let Inst{20} = load;
4758 let Inst{19-16} = addr{12-9};
4759 let Inst{15-12} = CRd;
4760 let Inst{11-8} = cop;
4761 let Inst{7-0} = addr{7-0};
4762 let DecoderMethod = "DecodeCopMemInstruction";
4764 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4765 postidx_imm8s4:$offset),
4766 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4771 let Inst{24} = 0; // P = 0
4772 let Inst{23} = offset{8};
4773 let Inst{22} = Dbit;
4774 let Inst{21} = 1; // W = 1
4775 let Inst{20} = load;
4776 let Inst{19-16} = addr;
4777 let Inst{15-12} = CRd;
4778 let Inst{11-8} = cop;
4779 let Inst{7-0} = offset{7-0};
4780 let DecoderMethod = "DecodeCopMemInstruction";
4782 def _OPTION : ACI<(outs),
4783 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4784 coproc_option_imm:$option),
4785 asm, "\t$cop, $CRd, $addr, $option"> {
4790 let Inst{24} = 0; // P = 0
4791 let Inst{23} = 1; // U = 1
4792 let Inst{22} = Dbit;
4793 let Inst{21} = 0; // W = 0
4794 let Inst{20} = load;
4795 let Inst{19-16} = addr;
4796 let Inst{15-12} = CRd;
4797 let Inst{11-8} = cop;
4798 let Inst{7-0} = option;
4799 let DecoderMethod = "DecodeCopMemInstruction";
4802 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4803 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4804 asm, "\t$cop, $CRd, $addr"> {
4808 let Inst{24} = 1; // P = 1
4809 let Inst{23} = addr{8};
4810 let Inst{22} = Dbit;
4811 let Inst{21} = 0; // W = 0
4812 let Inst{20} = load;
4813 let Inst{19-16} = addr{12-9};
4814 let Inst{15-12} = CRd;
4815 let Inst{11-8} = cop;
4816 let Inst{7-0} = addr{7-0};
4817 let DecoderMethod = "DecodeCopMemInstruction";
4819 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4820 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4824 let Inst{24} = 1; // P = 1
4825 let Inst{23} = addr{8};
4826 let Inst{22} = Dbit;
4827 let Inst{21} = 1; // W = 1
4828 let Inst{20} = load;
4829 let Inst{19-16} = addr{12-9};
4830 let Inst{15-12} = CRd;
4831 let Inst{11-8} = cop;
4832 let Inst{7-0} = addr{7-0};
4833 let DecoderMethod = "DecodeCopMemInstruction";
4835 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4836 postidx_imm8s4:$offset),
4837 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4842 let Inst{24} = 0; // P = 0
4843 let Inst{23} = offset{8};
4844 let Inst{22} = Dbit;
4845 let Inst{21} = 1; // W = 1
4846 let Inst{20} = load;
4847 let Inst{19-16} = addr;
4848 let Inst{15-12} = CRd;
4849 let Inst{11-8} = cop;
4850 let Inst{7-0} = offset{7-0};
4851 let DecoderMethod = "DecodeCopMemInstruction";
4853 def _OPTION : ACInoP<(outs),
4854 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4855 coproc_option_imm:$option),
4856 asm, "\t$cop, $CRd, $addr, $option"> {
4861 let Inst{24} = 0; // P = 0
4862 let Inst{23} = 1; // U = 1
4863 let Inst{22} = Dbit;
4864 let Inst{21} = 0; // W = 0
4865 let Inst{20} = load;
4866 let Inst{19-16} = addr;
4867 let Inst{15-12} = CRd;
4868 let Inst{11-8} = cop;
4869 let Inst{7-0} = option;
4870 let DecoderMethod = "DecodeCopMemInstruction";
4874 defm LDC : LdStCop <1, 0, "ldc">;
4875 defm LDCL : LdStCop <1, 1, "ldcl">;
4876 defm STC : LdStCop <0, 0, "stc">;
4877 defm STCL : LdStCop <0, 1, "stcl">;
4878 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4879 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4880 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4881 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4883 //===----------------------------------------------------------------------===//
4884 // Move between coprocessor and ARM core register.
4887 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4889 : ABI<0b1110, oops, iops, NoItinerary, opc,
4890 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4891 let Inst{20} = direction;
4901 let Inst{15-12} = Rt;
4902 let Inst{11-8} = cop;
4903 let Inst{23-21} = opc1;
4904 let Inst{7-5} = opc2;
4905 let Inst{3-0} = CRm;
4906 let Inst{19-16} = CRn;
4909 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4911 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4912 c_imm:$CRm, imm0_7:$opc2),
4913 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4914 imm:$CRm, imm:$opc2)]>,
4915 ComplexDeprecationPredicate<"MCR">;
4916 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4917 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4918 c_imm:$CRm, 0, pred:$p)>;
4919 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4920 (outs GPRwithAPSR:$Rt),
4921 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4923 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4924 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4925 c_imm:$CRm, 0, pred:$p)>;
4927 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4928 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4930 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4932 : ABXI<0b1110, oops, iops, NoItinerary,
4933 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4934 let Inst{31-24} = 0b11111110;
4935 let Inst{20} = direction;
4945 let Inst{15-12} = Rt;
4946 let Inst{11-8} = cop;
4947 let Inst{23-21} = opc1;
4948 let Inst{7-5} = opc2;
4949 let Inst{3-0} = CRm;
4950 let Inst{19-16} = CRn;
4953 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4955 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4956 c_imm:$CRm, imm0_7:$opc2),
4957 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4958 imm:$CRm, imm:$opc2)]>;
4959 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4960 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4962 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4963 (outs GPRwithAPSR:$Rt),
4964 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4966 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4967 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4970 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4971 imm:$CRm, imm:$opc2),
4972 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4974 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4975 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4976 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4977 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4978 let Inst{23-21} = 0b010;
4979 let Inst{20} = direction;
4987 let Inst{15-12} = Rt;
4988 let Inst{19-16} = Rt2;
4989 let Inst{11-8} = cop;
4990 let Inst{7-4} = opc1;
4991 let Inst{3-0} = CRm;
4994 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4995 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4996 GPRnopc:$Rt2, imm:$CRm)]>;
4997 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4999 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5000 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5001 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5002 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
5003 let Inst{31-28} = 0b1111;
5004 let Inst{23-21} = 0b010;
5005 let Inst{20} = direction;
5013 let Inst{15-12} = Rt;
5014 let Inst{19-16} = Rt2;
5015 let Inst{11-8} = cop;
5016 let Inst{7-4} = opc1;
5017 let Inst{3-0} = CRm;
5019 let DecoderMethod = "DecodeMRRC2";
5022 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5023 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5024 GPRnopc:$Rt2, imm:$CRm)]>;
5025 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5027 //===----------------------------------------------------------------------===//
5028 // Move between special register and ARM core register
5031 // Move to ARM core register from Special Register
5032 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5033 "mrs", "\t$Rd, apsr", []> {
5035 let Inst{23-16} = 0b00001111;
5036 let Unpredictable{19-17} = 0b111;
5038 let Inst{15-12} = Rd;
5040 let Inst{11-0} = 0b000000000000;
5041 let Unpredictable{11-0} = 0b110100001111;
5044 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5047 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5048 // section B9.3.9, with the R bit set to 1.
5049 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5050 "mrs", "\t$Rd, spsr", []> {
5052 let Inst{23-16} = 0b01001111;
5053 let Unpredictable{19-16} = 0b1111;
5055 let Inst{15-12} = Rd;
5057 let Inst{11-0} = 0b000000000000;
5058 let Unpredictable{11-0} = 0b110100001111;
5061 // Move from ARM core register to Special Register
5063 // No need to have both system and application versions, the encodings are the
5064 // same and the assembly parser has no way to distinguish between them. The mask
5065 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
5066 // the mask with the fields to be accessed in the special register.
5067 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5068 "msr", "\t$mask, $Rn", []> {
5073 let Inst{22} = mask{4}; // R bit
5074 let Inst{21-20} = 0b10;
5075 let Inst{19-16} = mask{3-0};
5076 let Inst{15-12} = 0b1111;
5077 let Inst{11-4} = 0b00000000;
5081 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
5082 "msr", "\t$mask, $a", []> {
5087 let Inst{22} = mask{4}; // R bit
5088 let Inst{21-20} = 0b10;
5089 let Inst{19-16} = mask{3-0};
5090 let Inst{15-12} = 0b1111;
5094 //===----------------------------------------------------------------------===//
5098 // __aeabi_read_tp preserves the registers r1-r3.
5099 // This is a pseudo inst so that we can get the encoding right,
5100 // complete with fixup for the aeabi_read_tp function.
5102 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5103 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
5104 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5107 //===----------------------------------------------------------------------===//
5108 // SJLJ Exception handling intrinsics
5109 // eh_sjlj_setjmp() is an instruction sequence to store the return
5110 // address and save #0 in R0 for the non-longjmp case.
5111 // Since by its nature we may be coming from some other function to get
5112 // here, and we're using the stack frame for the containing function to
5113 // save/restore registers, we can't keep anything live in regs across
5114 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5115 // when we get here from a longjmp(). We force everything out of registers
5116 // except for our own input by listing the relevant registers in Defs. By
5117 // doing so, we also cause the prologue/epilogue code to actively preserve
5118 // all of the callee-saved resgisters, which is exactly what we want.
5119 // A constant value is passed in $val, and we use the location as a scratch.
5121 // These are pseudo-instructions and are lowered to individual MC-insts, so
5122 // no encoding information is necessary.
5124 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5125 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5126 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5127 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5129 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5130 Requires<[IsARM, HasVFP2]>;
5134 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5135 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5136 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5138 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5139 Requires<[IsARM, NoVFP]>;
5142 // FIXME: Non-IOS version(s)
5143 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5144 Defs = [ R7, LR, SP ] in {
5145 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5147 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5148 Requires<[IsARM, IsIOS]>;
5151 // eh.sjlj.dispatchsetup pseudo-instruction.
5152 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5153 // the pseudo is expanded (which happens before any passes that need the
5154 // instruction size).
5155 let isBarrier = 1 in
5156 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5159 //===----------------------------------------------------------------------===//
5160 // Non-Instruction Patterns
5163 // ARMv4 indirect branch using (MOVr PC, dst)
5164 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5165 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5166 4, IIC_Br, [(brind GPR:$dst)],
5167 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5168 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5170 // Large immediate handling.
5172 // 32-bit immediate using two piece so_imms or movw + movt.
5173 // This is a single pseudo instruction, the benefit is that it can be remat'd
5174 // as a single unit instead of having to handle reg inputs.
5175 // FIXME: Remove this when we can do generalized remat.
5176 let isReMaterializable = 1, isMoveImm = 1 in
5177 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5178 [(set GPR:$dst, (arm_i32imm:$src))]>,
5181 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5182 // It also makes it possible to rematerialize the instructions.
5183 // FIXME: Remove this when we can do generalized remat and when machine licm
5184 // can properly the instructions.
5185 let isReMaterializable = 1 in {
5186 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5188 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5189 Requires<[IsARM, UseMovt]>;
5191 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5193 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
5194 Requires<[IsARM, UseMovt]>;
5196 let AddedComplexity = 10 in
5197 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5199 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5200 Requires<[IsARM, UseMovt]>;
5201 } // isReMaterializable
5203 // ConstantPool, GlobalAddress, and JumpTable
5204 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
5205 Requires<[IsARM, DontUseMovt]>;
5206 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5207 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5208 Requires<[IsARM, UseMovt]>;
5209 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5210 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5212 // TODO: add,sub,and, 3-instr forms?
5214 // Tail calls. These patterns also apply to Thumb mode.
5215 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5216 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5217 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5220 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5221 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5222 (BMOVPCB_CALL texternalsym:$func)>;
5224 // zextload i1 -> zextload i8
5225 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5226 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5228 // extload -> zextload
5229 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5230 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5231 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5232 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5234 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5236 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5237 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5240 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5241 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5242 (SMULBB GPR:$a, GPR:$b)>;
5243 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5244 (SMULBB GPR:$a, GPR:$b)>;
5245 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5246 (sra GPR:$b, (i32 16))),
5247 (SMULBT GPR:$a, GPR:$b)>;
5248 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5249 (SMULBT GPR:$a, GPR:$b)>;
5250 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5251 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5252 (SMULTB GPR:$a, GPR:$b)>;
5253 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5254 (SMULTB GPR:$a, GPR:$b)>;
5255 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5257 (SMULWB GPR:$a, GPR:$b)>;
5258 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5259 (SMULWB GPR:$a, GPR:$b)>;
5261 def : ARMV5MOPat<(add GPR:$acc,
5262 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5263 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5264 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5265 def : ARMV5MOPat<(add GPR:$acc,
5266 (mul sext_16_node:$a, sext_16_node:$b)),
5267 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5268 def : ARMV5MOPat<(add GPR:$acc,
5269 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5270 (sra GPR:$b, (i32 16)))),
5271 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5272 def : ARMV5MOPat<(add GPR:$acc,
5273 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5274 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5275 def : ARMV5MOPat<(add GPR:$acc,
5276 (mul (sra GPR:$a, (i32 16)),
5277 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5278 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5279 def : ARMV5MOPat<(add GPR:$acc,
5280 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5281 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5282 def : ARMV5MOPat<(add GPR:$acc,
5283 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5285 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5286 def : ARMV5MOPat<(add GPR:$acc,
5287 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5288 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5291 // Pre-v7 uses MCR for synchronization barriers.
5292 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5293 Requires<[IsARM, HasV6]>;
5295 // SXT/UXT with no rotate
5296 let AddedComplexity = 16 in {
5297 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5298 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5299 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5300 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5301 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5302 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5303 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5306 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5307 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5309 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5310 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5311 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5312 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5314 // Atomic load/store patterns
5315 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5316 (LDRBrs ldst_so_reg:$src)>;
5317 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5318 (LDRBi12 addrmode_imm12:$src)>;
5319 def : ARMPat<(atomic_load_16 addrmode3:$src),
5320 (LDRH addrmode3:$src)>;
5321 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5322 (LDRrs ldst_so_reg:$src)>;
5323 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5324 (LDRi12 addrmode_imm12:$src)>;
5325 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5326 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5327 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5328 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5329 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5330 (STRH GPR:$val, addrmode3:$ptr)>;
5331 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5332 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5333 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5334 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5337 //===----------------------------------------------------------------------===//
5341 include "ARMInstrThumb.td"
5343 //===----------------------------------------------------------------------===//
5347 include "ARMInstrThumb2.td"
5349 //===----------------------------------------------------------------------===//
5350 // Floating Point Support
5353 include "ARMInstrVFP.td"
5355 //===----------------------------------------------------------------------===//
5356 // Advanced SIMD (NEON) Support
5359 include "ARMInstrNEON.td"
5361 //===----------------------------------------------------------------------===//
5362 // Assembler aliases
5366 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5367 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5368 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5370 // System instructions
5371 def : MnemonicAlias<"swi", "svc">;
5373 // Load / Store Multiple
5374 def : MnemonicAlias<"ldmfd", "ldm">;
5375 def : MnemonicAlias<"ldmia", "ldm">;
5376 def : MnemonicAlias<"ldmea", "ldmdb">;
5377 def : MnemonicAlias<"stmfd", "stmdb">;
5378 def : MnemonicAlias<"stmia", "stm">;
5379 def : MnemonicAlias<"stmea", "stm">;
5381 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5382 // shift amount is zero (i.e., unspecified).
5383 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5384 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5385 Requires<[IsARM, HasV6]>;
5386 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5387 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5388 Requires<[IsARM, HasV6]>;
5390 // PUSH/POP aliases for STM/LDM
5391 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5392 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5394 // SSAT/USAT optional shift operand.
5395 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5396 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5397 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5398 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5401 // Extend instruction optional rotate operand.
5402 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5403 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5404 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5405 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5406 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5407 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5408 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5409 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5410 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5411 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5412 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5413 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5415 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5416 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5417 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5418 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5419 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5420 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5421 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5422 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5423 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5424 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5425 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5426 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5430 def : MnemonicAlias<"rfefa", "rfeda">;
5431 def : MnemonicAlias<"rfeea", "rfedb">;
5432 def : MnemonicAlias<"rfefd", "rfeia">;
5433 def : MnemonicAlias<"rfeed", "rfeib">;
5434 def : MnemonicAlias<"rfe", "rfeia">;
5437 def : MnemonicAlias<"srsfa", "srsib">;
5438 def : MnemonicAlias<"srsea", "srsia">;
5439 def : MnemonicAlias<"srsfd", "srsdb">;
5440 def : MnemonicAlias<"srsed", "srsda">;
5441 def : MnemonicAlias<"srs", "srsia">;
5444 def : MnemonicAlias<"qsubaddx", "qsax">;
5446 def : MnemonicAlias<"saddsubx", "sasx">;
5447 // SHASX == SHADDSUBX
5448 def : MnemonicAlias<"shaddsubx", "shasx">;
5449 // SHSAX == SHSUBADDX
5450 def : MnemonicAlias<"shsubaddx", "shsax">;
5452 def : MnemonicAlias<"ssubaddx", "ssax">;
5454 def : MnemonicAlias<"uaddsubx", "uasx">;
5455 // UHASX == UHADDSUBX
5456 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5457 // UHSAX == UHSUBADDX
5458 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5459 // UQASX == UQADDSUBX
5460 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5461 // UQSAX == UQSUBADDX
5462 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5464 def : MnemonicAlias<"usubaddx", "usax">;
5466 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5468 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5469 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5470 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5471 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5472 // Same for AND <--> BIC
5473 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5474 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5475 pred:$p, cc_out:$s)>;
5476 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5477 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5478 pred:$p, cc_out:$s)>;
5479 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5480 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5481 pred:$p, cc_out:$s)>;
5482 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5483 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5484 pred:$p, cc_out:$s)>;
5486 // Likewise, "add Rd, so_imm_neg" -> sub
5487 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5488 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5489 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5490 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5491 // Same for CMP <--> CMN via so_imm_neg
5492 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5493 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5494 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5495 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5497 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5498 // LSR, ROR, and RRX instructions.
5499 // FIXME: We need C++ parser hooks to map the alias to the MOV
5500 // encoding. It seems we should be able to do that sort of thing
5501 // in tblgen, but it could get ugly.
5502 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5503 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5504 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5506 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5507 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5509 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5510 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5512 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5513 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5516 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5517 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5518 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5519 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5520 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5522 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5523 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5525 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5526 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5528 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5529 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5533 // "neg" is and alias for "rsb rd, rn, #0"
5534 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5535 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5537 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5538 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5539 Requires<[IsARM, NoV6]>;
5541 // UMULL/SMULL are available on all arches, but the instruction definitions
5542 // need difference constraints pre-v6. Use these aliases for the assembly
5543 // parsing on pre-v6.
5544 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5545 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5546 Requires<[IsARM, NoV6]>;
5547 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5548 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5549 Requires<[IsARM, NoV6]>;
5551 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5553 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5554 ComplexDeprecationPredicate<"IT">;