1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 2,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
39 def SDT_ARMBr2JT : SDTypeProfile<0, 3,
40 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
43 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
45 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
46 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
47 SDTCisVT<5, OtherVT>]>;
49 def SDT_ARMAnd : SDTypeProfile<1, 2,
50 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
53 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
55 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
56 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
58 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
59 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
61 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
73 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
74 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
76 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
79 SDTCisInt<0>, SDTCisVT<1, i32>]>;
81 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
82 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
89 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
90 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
91 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
92 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
93 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
96 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
97 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
98 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>;
100 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
101 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
102 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
103 [SDNPHasChain, SDNPSideEffect,
104 SDNPOptInGlue, SDNPOutGlue]>;
105 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
107 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
108 SDNPMayStore, SDNPMayLoad]>;
110 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
111 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
113 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
121 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
124 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
127 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
130 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
132 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
135 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
138 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
141 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
144 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
145 [SDNPOutGlue, SDNPCommutative]>;
147 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
149 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
150 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
153 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
155 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
156 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
157 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
159 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
160 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
161 SDT_ARMEH_SJLJ_Setjmp,
162 [SDNPHasChain, SDNPSideEffect]>;
163 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
164 SDT_ARMEH_SJLJ_Longjmp,
165 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
177 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
179 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
180 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
182 //===----------------------------------------------------------------------===//
183 // ARM Instruction Predicate Definitions.
185 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
186 AssemblerPredicate<"HasV4TOps", "armv4t">;
187 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
188 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
189 AssemblerPredicate<"HasV5TOps", "armv5t">;
190 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
191 AssemblerPredicate<"HasV5TEOps", "armv5te">;
192 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
193 AssemblerPredicate<"HasV6Ops", "armv6">;
194 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
195 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
196 AssemblerPredicate<"HasV6MOps",
197 "armv6m or armv6t2">;
198 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
199 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
200 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
201 def HasV6K : Predicate<"Subtarget->hasV6KOps()">,
202 AssemblerPredicate<"HasV6KOps", "armv6k">;
203 def NoV6K : Predicate<"!Subtarget->hasV6KOps()">;
204 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
205 AssemblerPredicate<"HasV7Ops", "armv7">;
206 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"HasV8Ops", "armv8">;
208 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
209 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
210 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
211 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
212 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
213 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
214 AssemblerPredicate<"FeatureVFP2", "VFP2">;
215 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
216 AssemblerPredicate<"FeatureVFP3", "VFP3">;
217 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
218 AssemblerPredicate<"FeatureVFP4", "VFP4">;
219 def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">,
220 AssemblerPredicate<"!FeatureVFPOnlySP",
221 "double precision VFP">;
222 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
223 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
224 def HasNEON : Predicate<"Subtarget->hasNEON()">,
225 AssemblerPredicate<"FeatureNEON", "NEON">;
226 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
227 AssemblerPredicate<"FeatureCrypto", "crypto">;
228 def HasCRC : Predicate<"Subtarget->hasCRC()">,
229 AssemblerPredicate<"FeatureCRC", "crc">;
230 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
231 AssemblerPredicate<"FeatureFP16","half-float">;
232 def HasDivide : Predicate<"Subtarget->hasDivide()">,
233 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
234 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
235 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
236 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
237 AssemblerPredicate<"FeatureT2XtPk",
239 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
240 AssemblerPredicate<"FeatureDSPThumb2",
242 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
243 AssemblerPredicate<"FeatureDB",
245 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
246 AssemblerPredicate<"FeatureMP",
248 def HasVirtualization: Predicate<"false">,
249 AssemblerPredicate<"FeatureVirtualization",
250 "virtualization-extensions">;
251 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
252 AssemblerPredicate<"FeatureTrustZone",
254 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
255 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
256 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
257 def IsThumb : Predicate<"Subtarget->isThumb()">,
258 AssemblerPredicate<"ModeThumb", "thumb">;
259 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
260 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
261 AssemblerPredicate<"ModeThumb,FeatureThumb2",
263 def IsMClass : Predicate<"Subtarget->isMClass()">,
264 AssemblerPredicate<"FeatureMClass", "armv*m">;
265 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
266 AssemblerPredicate<"!FeatureMClass",
268 def IsARM : Predicate<"!Subtarget->isThumb()">,
269 AssemblerPredicate<"!ModeThumb", "arm-mode">;
270 def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
271 def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
272 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
273 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
274 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
275 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
277 // FIXME: Eventually this will be just "hasV6T2Ops".
278 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">;
279 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">;
280 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
281 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
283 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
284 // But only select them if more precision in FP computation is allowed.
285 // Do not use them for Darwin platforms.
286 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
287 " FPOpFusion::Fast && "
288 " Subtarget->hasVFP4()) && "
289 "!Subtarget->isTargetDarwin()">;
290 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
291 " FPOpFusion::Fast &&"
292 " Subtarget->hasVFP4()) || "
293 "Subtarget->isTargetDarwin()">;
295 // VGETLNi32 is microcoded on Swift - prefer VMOV.
296 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
297 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
299 // VDUP.32 is microcoded on Swift - prefer VMOV.
300 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
301 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
303 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
304 // this allows more effective execution domain optimization. See
305 // setExecutionDomain().
306 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
307 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
309 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
310 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
312 //===----------------------------------------------------------------------===//
313 // ARM Flag Definitions.
315 class RegConstraint<string C> {
316 string Constraints = C;
319 //===----------------------------------------------------------------------===//
320 // ARM specific transformation functions and pattern fragments.
323 // imm_neg_XFORM - Return the negation of an i32 immediate value.
324 def imm_neg_XFORM : SDNodeXForm<imm, [{
325 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
328 // imm_not_XFORM - Return the complement of a i32 immediate value.
329 def imm_not_XFORM : SDNodeXForm<imm, [{
330 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
333 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
334 def imm16_31 : ImmLeaf<i32, [{
335 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
338 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
339 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
340 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
343 /// Split a 32-bit immediate into two 16 bit parts.
344 def hi16 : SDNodeXForm<imm, [{
345 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
349 def lo16AllZero : PatLeaf<(i32 imm), [{
350 // Returns true if all low 16-bits are 0.
351 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
354 class BinOpWithFlagFrag<dag res> :
355 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
356 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
357 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
359 // An 'and' node with a single use.
360 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
361 return N->hasOneUse();
364 // An 'xor' node with a single use.
365 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
366 return N->hasOneUse();
369 // An 'fmul' node with a single use.
370 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
371 return N->hasOneUse();
374 // An 'fadd' node which checks for single non-hazardous use.
375 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
376 return hasNoVMLxHazardUse(N);
379 // An 'fsub' node which checks for single non-hazardous use.
380 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
381 return hasNoVMLxHazardUse(N);
384 //===----------------------------------------------------------------------===//
385 // Operand Definitions.
388 // Immediate operands with a shared generic asm render method.
389 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
391 // Operands that are part of a memory addressing mode.
392 class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; }
395 // FIXME: rename brtarget to t2_brtarget
396 def brtarget : Operand<OtherVT> {
397 let EncoderMethod = "getBranchTargetOpValue";
398 let OperandType = "OPERAND_PCREL";
399 let DecoderMethod = "DecodeT2BROperand";
402 // FIXME: get rid of this one?
403 def uncondbrtarget : Operand<OtherVT> {
404 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
405 let OperandType = "OPERAND_PCREL";
408 // Branch target for ARM. Handles conditional/unconditional
409 def br_target : Operand<OtherVT> {
410 let EncoderMethod = "getARMBranchTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
415 // FIXME: rename bltarget to t2_bl_target?
416 def bltarget : Operand<i32> {
417 // Encoded the same as branch targets.
418 let EncoderMethod = "getBranchTargetOpValue";
419 let OperandType = "OPERAND_PCREL";
422 // Call target for ARM. Handles conditional/unconditional
423 // FIXME: rename bl_target to t2_bltarget?
424 def bl_target : Operand<i32> {
425 let EncoderMethod = "getARMBLTargetOpValue";
426 let OperandType = "OPERAND_PCREL";
429 def blx_target : Operand<i32> {
430 let EncoderMethod = "getARMBLXTargetOpValue";
431 let OperandType = "OPERAND_PCREL";
434 // A list of registers separated by comma. Used by load/store multiple.
435 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
436 def reglist : Operand<i32> {
437 let EncoderMethod = "getRegisterListOpValue";
438 let ParserMatchClass = RegListAsmOperand;
439 let PrintMethod = "printRegisterList";
440 let DecoderMethod = "DecodeRegListOperand";
443 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
445 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
446 def dpr_reglist : Operand<i32> {
447 let EncoderMethod = "getRegisterListOpValue";
448 let ParserMatchClass = DPRRegListAsmOperand;
449 let PrintMethod = "printRegisterList";
450 let DecoderMethod = "DecodeDPRRegListOperand";
453 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
454 def spr_reglist : Operand<i32> {
455 let EncoderMethod = "getRegisterListOpValue";
456 let ParserMatchClass = SPRRegListAsmOperand;
457 let PrintMethod = "printRegisterList";
458 let DecoderMethod = "DecodeSPRRegListOperand";
461 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
462 def cpinst_operand : Operand<i32> {
463 let PrintMethod = "printCPInstOperand";
467 def pclabel : Operand<i32> {
468 let PrintMethod = "printPCLabel";
471 // ADR instruction labels.
472 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
473 def adrlabel : Operand<i32> {
474 let EncoderMethod = "getAdrLabelOpValue";
475 let ParserMatchClass = AdrLabelAsmOperand;
476 let PrintMethod = "printAdrLabelOperand<0>";
479 def neon_vcvt_imm32 : Operand<i32> {
480 let EncoderMethod = "getNEONVcvtImm32OpValue";
481 let DecoderMethod = "DecodeVCVTImmOperand";
484 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
485 def rot_imm_XFORM: SDNodeXForm<imm, [{
486 switch (N->getZExtValue()){
487 default: llvm_unreachable(nullptr);
488 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
489 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32);
490 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32);
491 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32);
494 def RotImmAsmOperand : AsmOperandClass {
496 let ParserMethod = "parseRotImm";
498 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
499 int32_t v = N->getZExtValue();
500 return v == 8 || v == 16 || v == 24; }],
502 let PrintMethod = "printRotImmOperand";
503 let ParserMatchClass = RotImmAsmOperand;
506 // shift_imm: An integer that encodes a shift amount and the type of shift
507 // (asr or lsl). The 6-bit immediate encodes as:
510 // {4-0} imm5 shift amount.
511 // asr #32 encoded as imm5 == 0.
512 def ShifterImmAsmOperand : AsmOperandClass {
513 let Name = "ShifterImm";
514 let ParserMethod = "parseShifterImm";
516 def shift_imm : Operand<i32> {
517 let PrintMethod = "printShiftImmOperand";
518 let ParserMatchClass = ShifterImmAsmOperand;
521 // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm.
522 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
523 def so_reg_reg : Operand<i32>, // reg reg imm
524 ComplexPattern<i32, 3, "SelectRegShifterOperand",
525 [shl, srl, sra, rotr]> {
526 let EncoderMethod = "getSORegRegOpValue";
527 let PrintMethod = "printSORegRegOperand";
528 let DecoderMethod = "DecodeSORegRegOperand";
529 let ParserMatchClass = ShiftedRegAsmOperand;
530 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
533 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
534 def so_reg_imm : Operand<i32>, // reg imm
535 ComplexPattern<i32, 2, "SelectImmShifterOperand",
536 [shl, srl, sra, rotr]> {
537 let EncoderMethod = "getSORegImmOpValue";
538 let PrintMethod = "printSORegImmOperand";
539 let DecoderMethod = "DecodeSORegImmOperand";
540 let ParserMatchClass = ShiftedImmAsmOperand;
541 let MIOperandInfo = (ops GPR, i32imm);
544 // FIXME: Does this need to be distinct from so_reg?
545 def shift_so_reg_reg : Operand<i32>, // reg reg imm
546 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
547 [shl,srl,sra,rotr]> {
548 let EncoderMethod = "getSORegRegOpValue";
549 let PrintMethod = "printSORegRegOperand";
550 let DecoderMethod = "DecodeSORegRegOperand";
551 let ParserMatchClass = ShiftedRegAsmOperand;
552 let MIOperandInfo = (ops GPR, GPR, i32imm);
555 // FIXME: Does this need to be distinct from so_reg?
556 def shift_so_reg_imm : Operand<i32>, // reg reg imm
557 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
558 [shl,srl,sra,rotr]> {
559 let EncoderMethod = "getSORegImmOpValue";
560 let PrintMethod = "printSORegImmOperand";
561 let DecoderMethod = "DecodeSORegImmOperand";
562 let ParserMatchClass = ShiftedImmAsmOperand;
563 let MIOperandInfo = (ops GPR, i32imm);
566 // mod_imm: match a 32-bit immediate operand, which can be encoded into
567 // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM
568 // - "Modified Immediate Constants"). Within the MC layer we keep this
569 // immediate in its encoded form.
570 def ModImmAsmOperand: AsmOperandClass {
572 let ParserMethod = "parseModImm";
574 def mod_imm : Operand<i32>, ImmLeaf<i32, [{
575 return ARM_AM::getSOImmVal(Imm) != -1;
577 let EncoderMethod = "getModImmOpValue";
578 let PrintMethod = "printModImmOperand";
579 let ParserMatchClass = ModImmAsmOperand;
582 // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder
583 // method and such, as they are only used on aliases (Pat<> and InstAlias<>).
584 // The actual parsing, encoding, decoding are handled by the destination
585 // instructions, which use mod_imm.
587 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
588 def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{
589 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
591 let ParserMatchClass = ModImmNotAsmOperand;
594 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
595 def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
596 unsigned Value = -(unsigned)N->getZExtValue();
597 return Value && ARM_AM::getSOImmVal(Value) != -1;
599 let ParserMatchClass = ModImmNegAsmOperand;
602 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
603 def arm_i32imm : PatLeaf<(imm), [{
604 if (Subtarget->useMovt(*MF))
606 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
609 /// imm0_1 predicate - Immediate in the range [0,1].
610 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
611 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
613 /// imm0_3 predicate - Immediate in the range [0,3].
614 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
615 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
617 /// imm0_7 predicate - Immediate in the range [0,7].
618 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
619 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
620 return Imm >= 0 && Imm < 8;
622 let ParserMatchClass = Imm0_7AsmOperand;
625 /// imm8 predicate - Immediate is exactly 8.
626 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
627 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
628 let ParserMatchClass = Imm8AsmOperand;
631 /// imm16 predicate - Immediate is exactly 16.
632 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
633 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
634 let ParserMatchClass = Imm16AsmOperand;
637 /// imm32 predicate - Immediate is exactly 32.
638 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
639 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
640 let ParserMatchClass = Imm32AsmOperand;
643 def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>;
645 /// imm1_7 predicate - Immediate in the range [1,7].
646 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
647 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
648 let ParserMatchClass = Imm1_7AsmOperand;
651 /// imm1_15 predicate - Immediate in the range [1,15].
652 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
653 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
654 let ParserMatchClass = Imm1_15AsmOperand;
657 /// imm1_31 predicate - Immediate in the range [1,31].
658 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
659 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
660 let ParserMatchClass = Imm1_31AsmOperand;
663 /// imm0_15 predicate - Immediate in the range [0,15].
664 def Imm0_15AsmOperand: ImmAsmOperand {
665 let Name = "Imm0_15";
666 let DiagnosticType = "ImmRange0_15";
668 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 16;
671 let ParserMatchClass = Imm0_15AsmOperand;
674 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
675 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
676 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
677 return Imm >= 0 && Imm < 32;
679 let ParserMatchClass = Imm0_31AsmOperand;
682 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
683 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
684 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
685 return Imm >= 0 && Imm < 32;
687 let ParserMatchClass = Imm0_32AsmOperand;
690 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
691 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
692 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
693 return Imm >= 0 && Imm < 64;
695 let ParserMatchClass = Imm0_63AsmOperand;
698 /// imm0_239 predicate - Immediate in the range [0,239].
699 def Imm0_239AsmOperand : ImmAsmOperand {
700 let Name = "Imm0_239";
701 let DiagnosticType = "ImmRange0_239";
703 def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> {
704 let ParserMatchClass = Imm0_239AsmOperand;
707 /// imm0_255 predicate - Immediate in the range [0,255].
708 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
709 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
710 let ParserMatchClass = Imm0_255AsmOperand;
713 /// imm0_65535 - An immediate is in the range [0.65535].
714 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
715 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
716 return Imm >= 0 && Imm < 65536;
718 let ParserMatchClass = Imm0_65535AsmOperand;
721 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
722 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
723 return -Imm >= 0 && -Imm < 65536;
726 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
727 // a relocatable expression.
729 // FIXME: This really needs a Thumb version separate from the ARM version.
730 // While the range is the same, and can thus use the same match class,
731 // the encoding is different so it should have a different encoder method.
732 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
733 def imm0_65535_expr : Operand<i32> {
734 let EncoderMethod = "getHiLo16ImmOpValue";
735 let ParserMatchClass = Imm0_65535ExprAsmOperand;
738 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
739 def imm256_65535_expr : Operand<i32> {
740 let ParserMatchClass = Imm256_65535ExprAsmOperand;
743 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
744 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
745 def imm24b : Operand<i32>, ImmLeaf<i32, [{
746 return Imm >= 0 && Imm <= 0xffffff;
748 let ParserMatchClass = Imm24bitAsmOperand;
752 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
754 def BitfieldAsmOperand : AsmOperandClass {
755 let Name = "Bitfield";
756 let ParserMethod = "parseBitfield";
759 def bf_inv_mask_imm : Operand<i32>,
761 return ARM::isBitFieldInvertedMask(N->getZExtValue());
763 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
764 let PrintMethod = "printBitfieldInvMaskImmOperand";
765 let DecoderMethod = "DecodeBitfieldMaskOperand";
766 let ParserMatchClass = BitfieldAsmOperand;
769 def imm1_32_XFORM: SDNodeXForm<imm, [{
770 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
773 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
774 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
775 uint64_t Imm = N->getZExtValue();
776 return Imm > 0 && Imm <= 32;
779 let PrintMethod = "printImmPlusOneOperand";
780 let ParserMatchClass = Imm1_32AsmOperand;
783 def imm1_16_XFORM: SDNodeXForm<imm, [{
784 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
787 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
788 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
790 let PrintMethod = "printImmPlusOneOperand";
791 let ParserMatchClass = Imm1_16AsmOperand;
794 // Define ARM specific addressing modes.
795 // addrmode_imm12 := reg +/- imm12
797 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
798 class AddrMode_Imm12 : MemOperand,
799 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
800 // 12-bit immediate operand. Note that instructions using this encode
801 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
802 // immediate values are as normal.
804 let EncoderMethod = "getAddrModeImm12OpValue";
805 let DecoderMethod = "DecodeAddrModeImm12Operand";
806 let ParserMatchClass = MemImm12OffsetAsmOperand;
807 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
810 def addrmode_imm12 : AddrMode_Imm12 {
811 let PrintMethod = "printAddrModeImm12Operand<false>";
814 def addrmode_imm12_pre : AddrMode_Imm12 {
815 let PrintMethod = "printAddrModeImm12Operand<true>";
818 // ldst_so_reg := reg +/- reg shop imm
820 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
821 def ldst_so_reg : MemOperand,
822 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
823 let EncoderMethod = "getLdStSORegOpValue";
824 // FIXME: Simplify the printer
825 let PrintMethod = "printAddrMode2Operand";
826 let DecoderMethod = "DecodeSORegMemOperand";
827 let ParserMatchClass = MemRegOffsetAsmOperand;
828 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
831 // postidx_imm8 := +/- [0,255]
834 // {8} 1 is imm8 is non-negative. 0 otherwise.
835 // {7-0} [0,255] imm8 value.
836 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
837 def postidx_imm8 : MemOperand {
838 let PrintMethod = "printPostIdxImm8Operand";
839 let ParserMatchClass = PostIdxImm8AsmOperand;
840 let MIOperandInfo = (ops i32imm);
843 // postidx_imm8s4 := +/- [0,1020]
846 // {8} 1 is imm8 is non-negative. 0 otherwise.
847 // {7-0} [0,255] imm8 value, scaled by 4.
848 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
849 def postidx_imm8s4 : MemOperand {
850 let PrintMethod = "printPostIdxImm8s4Operand";
851 let ParserMatchClass = PostIdxImm8s4AsmOperand;
852 let MIOperandInfo = (ops i32imm);
856 // postidx_reg := +/- reg
858 def PostIdxRegAsmOperand : AsmOperandClass {
859 let Name = "PostIdxReg";
860 let ParserMethod = "parsePostIdxReg";
862 def postidx_reg : MemOperand {
863 let EncoderMethod = "getPostIdxRegOpValue";
864 let DecoderMethod = "DecodePostIdxReg";
865 let PrintMethod = "printPostIdxRegOperand";
866 let ParserMatchClass = PostIdxRegAsmOperand;
867 let MIOperandInfo = (ops GPRnopc, i32imm);
871 // addrmode2 := reg +/- imm12
872 // := reg +/- reg shop imm
874 // FIXME: addrmode2 should be refactored the rest of the way to always
875 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
876 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
877 def addrmode2 : MemOperand,
878 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
879 let EncoderMethod = "getAddrMode2OpValue";
880 let PrintMethod = "printAddrMode2Operand";
881 let ParserMatchClass = AddrMode2AsmOperand;
882 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
885 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
886 let Name = "PostIdxRegShifted";
887 let ParserMethod = "parsePostIdxReg";
889 def am2offset_reg : MemOperand,
890 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
891 [], [SDNPWantRoot]> {
892 let EncoderMethod = "getAddrMode2OffsetOpValue";
893 let PrintMethod = "printAddrMode2OffsetOperand";
894 // When using this for assembly, it's always as a post-index offset.
895 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
896 let MIOperandInfo = (ops GPRnopc, i32imm);
899 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
900 // the GPR is purely vestigal at this point.
901 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
902 def am2offset_imm : MemOperand,
903 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
904 [], [SDNPWantRoot]> {
905 let EncoderMethod = "getAddrMode2OffsetOpValue";
906 let PrintMethod = "printAddrMode2OffsetOperand";
907 let ParserMatchClass = AM2OffsetImmAsmOperand;
908 let MIOperandInfo = (ops GPRnopc, i32imm);
912 // addrmode3 := reg +/- reg
913 // addrmode3 := reg +/- imm8
915 // FIXME: split into imm vs. reg versions.
916 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
917 class AddrMode3 : MemOperand,
918 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
919 let EncoderMethod = "getAddrMode3OpValue";
920 let ParserMatchClass = AddrMode3AsmOperand;
921 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
924 def addrmode3 : AddrMode3
926 let PrintMethod = "printAddrMode3Operand<false>";
929 def addrmode3_pre : AddrMode3
931 let PrintMethod = "printAddrMode3Operand<true>";
934 // FIXME: split into imm vs. reg versions.
935 // FIXME: parser method to handle +/- register.
936 def AM3OffsetAsmOperand : AsmOperandClass {
937 let Name = "AM3Offset";
938 let ParserMethod = "parseAM3Offset";
940 def am3offset : MemOperand,
941 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
942 [], [SDNPWantRoot]> {
943 let EncoderMethod = "getAddrMode3OffsetOpValue";
944 let PrintMethod = "printAddrMode3OffsetOperand";
945 let ParserMatchClass = AM3OffsetAsmOperand;
946 let MIOperandInfo = (ops GPR, i32imm);
949 // ldstm_mode := {ia, ib, da, db}
951 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
952 let EncoderMethod = "getLdStmModeOpValue";
953 let PrintMethod = "printLdStmModeOperand";
956 // addrmode5 := reg +/- imm8*4
958 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
959 class AddrMode5 : MemOperand,
960 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
961 let EncoderMethod = "getAddrMode5OpValue";
962 let DecoderMethod = "DecodeAddrMode5Operand";
963 let ParserMatchClass = AddrMode5AsmOperand;
964 let MIOperandInfo = (ops GPR:$base, i32imm);
967 def addrmode5 : AddrMode5 {
968 let PrintMethod = "printAddrMode5Operand<false>";
971 def addrmode5_pre : AddrMode5 {
972 let PrintMethod = "printAddrMode5Operand<true>";
975 // addrmode6 := reg with optional alignment
977 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
978 def addrmode6 : MemOperand,
979 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
980 let PrintMethod = "printAddrMode6Operand";
981 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
982 let EncoderMethod = "getAddrMode6AddressOpValue";
983 let DecoderMethod = "DecodeAddrMode6Operand";
984 let ParserMatchClass = AddrMode6AsmOperand;
987 def am6offset : MemOperand,
988 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
989 [], [SDNPWantRoot]> {
990 let PrintMethod = "printAddrMode6OffsetOperand";
991 let MIOperandInfo = (ops GPR);
992 let EncoderMethod = "getAddrMode6OffsetOpValue";
993 let DecoderMethod = "DecodeGPRRegisterClass";
996 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
997 // (single element from one lane) for size 32.
998 def addrmode6oneL32 : MemOperand,
999 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1000 let PrintMethod = "printAddrMode6Operand";
1001 let MIOperandInfo = (ops GPR:$addr, i32imm);
1002 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
1005 // Base class for addrmode6 with specific alignment restrictions.
1006 class AddrMode6Align : MemOperand,
1007 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1008 let PrintMethod = "printAddrMode6Operand";
1009 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1010 let EncoderMethod = "getAddrMode6AddressOpValue";
1011 let DecoderMethod = "DecodeAddrMode6Operand";
1014 // Special version of addrmode6 to handle no allowed alignment encoding for
1015 // VLD/VST instructions and checking the alignment is not specified.
1016 def AddrMode6AlignNoneAsmOperand : AsmOperandClass {
1017 let Name = "AlignedMemoryNone";
1018 let DiagnosticType = "AlignedMemoryRequiresNone";
1020 def addrmode6alignNone : AddrMode6Align {
1021 // The alignment specifier can only be omitted.
1022 let ParserMatchClass = AddrMode6AlignNoneAsmOperand;
1025 // Special version of addrmode6 to handle 16-bit alignment encoding for
1026 // VLD/VST instructions and checking the alignment value.
1027 def AddrMode6Align16AsmOperand : AsmOperandClass {
1028 let Name = "AlignedMemory16";
1029 let DiagnosticType = "AlignedMemoryRequires16";
1031 def addrmode6align16 : AddrMode6Align {
1032 // The alignment specifier can only be 16 or omitted.
1033 let ParserMatchClass = AddrMode6Align16AsmOperand;
1036 // Special version of addrmode6 to handle 32-bit alignment encoding for
1037 // VLD/VST instructions and checking the alignment value.
1038 def AddrMode6Align32AsmOperand : AsmOperandClass {
1039 let Name = "AlignedMemory32";
1040 let DiagnosticType = "AlignedMemoryRequires32";
1042 def addrmode6align32 : AddrMode6Align {
1043 // The alignment specifier can only be 32 or omitted.
1044 let ParserMatchClass = AddrMode6Align32AsmOperand;
1047 // Special version of addrmode6 to handle 64-bit alignment encoding for
1048 // VLD/VST instructions and checking the alignment value.
1049 def AddrMode6Align64AsmOperand : AsmOperandClass {
1050 let Name = "AlignedMemory64";
1051 let DiagnosticType = "AlignedMemoryRequires64";
1053 def addrmode6align64 : AddrMode6Align {
1054 // The alignment specifier can only be 64 or omitted.
1055 let ParserMatchClass = AddrMode6Align64AsmOperand;
1058 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1059 // for VLD/VST instructions and checking the alignment value.
1060 def AddrMode6Align64or128AsmOperand : AsmOperandClass {
1061 let Name = "AlignedMemory64or128";
1062 let DiagnosticType = "AlignedMemoryRequires64or128";
1064 def addrmode6align64or128 : AddrMode6Align {
1065 // The alignment specifier can only be 64, 128 or omitted.
1066 let ParserMatchClass = AddrMode6Align64or128AsmOperand;
1069 // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment
1070 // encoding for VLD/VST instructions and checking the alignment value.
1071 def AddrMode6Align64or128or256AsmOperand : AsmOperandClass {
1072 let Name = "AlignedMemory64or128or256";
1073 let DiagnosticType = "AlignedMemoryRequires64or128or256";
1075 def addrmode6align64or128or256 : AddrMode6Align {
1076 // The alignment specifier can only be 64, 128, 256 or omitted.
1077 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand;
1080 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1081 // instructions, specifically VLD4-dup.
1082 def addrmode6dup : MemOperand,
1083 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1084 let PrintMethod = "printAddrMode6Operand";
1085 let MIOperandInfo = (ops GPR:$addr, i32imm);
1086 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1087 // FIXME: This is close, but not quite right. The alignment specifier is
1089 let ParserMatchClass = AddrMode6AsmOperand;
1092 // Base class for addrmode6dup with specific alignment restrictions.
1093 class AddrMode6DupAlign : MemOperand,
1094 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
1095 let PrintMethod = "printAddrMode6Operand";
1096 let MIOperandInfo = (ops GPR:$addr, i32imm);
1097 let EncoderMethod = "getAddrMode6DupAddressOpValue";
1100 // Special version of addrmode6 to handle no allowed alignment encoding for
1101 // VLD-dup instruction and checking the alignment is not specified.
1102 def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass {
1103 let Name = "DupAlignedMemoryNone";
1104 let DiagnosticType = "DupAlignedMemoryRequiresNone";
1106 def addrmode6dupalignNone : AddrMode6DupAlign {
1107 // The alignment specifier can only be omitted.
1108 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand;
1111 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1112 // instruction and checking the alignment value.
1113 def AddrMode6dupAlign16AsmOperand : AsmOperandClass {
1114 let Name = "DupAlignedMemory16";
1115 let DiagnosticType = "DupAlignedMemoryRequires16";
1117 def addrmode6dupalign16 : AddrMode6DupAlign {
1118 // The alignment specifier can only be 16 or omitted.
1119 let ParserMatchClass = AddrMode6dupAlign16AsmOperand;
1122 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
1123 // instruction and checking the alignment value.
1124 def AddrMode6dupAlign32AsmOperand : AsmOperandClass {
1125 let Name = "DupAlignedMemory32";
1126 let DiagnosticType = "DupAlignedMemoryRequires32";
1128 def addrmode6dupalign32 : AddrMode6DupAlign {
1129 // The alignment specifier can only be 32 or omitted.
1130 let ParserMatchClass = AddrMode6dupAlign32AsmOperand;
1133 // Special version of addrmode6 to handle 64-bit alignment encoding for VLD
1134 // instructions and checking the alignment value.
1135 def AddrMode6dupAlign64AsmOperand : AsmOperandClass {
1136 let Name = "DupAlignedMemory64";
1137 let DiagnosticType = "DupAlignedMemoryRequires64";
1139 def addrmode6dupalign64 : AddrMode6DupAlign {
1140 // The alignment specifier can only be 64 or omitted.
1141 let ParserMatchClass = AddrMode6dupAlign64AsmOperand;
1144 // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding
1145 // for VLD instructions and checking the alignment value.
1146 def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass {
1147 let Name = "DupAlignedMemory64or128";
1148 let DiagnosticType = "DupAlignedMemoryRequires64or128";
1150 def addrmode6dupalign64or128 : AddrMode6DupAlign {
1151 // The alignment specifier can only be 64, 128 or omitted.
1152 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand;
1155 // addrmodepc := pc + reg
1157 def addrmodepc : MemOperand,
1158 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
1159 let PrintMethod = "printAddrModePCOperand";
1160 let MIOperandInfo = (ops GPR, i32imm);
1163 // addr_offset_none := reg
1165 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1166 def addr_offset_none : MemOperand,
1167 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1168 let PrintMethod = "printAddrMode7Operand";
1169 let DecoderMethod = "DecodeAddrMode7Operand";
1170 let ParserMatchClass = MemNoOffsetAsmOperand;
1171 let MIOperandInfo = (ops GPR:$base);
1174 def nohash_imm : Operand<i32> {
1175 let PrintMethod = "printNoHashImmediate";
1178 def CoprocNumAsmOperand : AsmOperandClass {
1179 let Name = "CoprocNum";
1180 let ParserMethod = "parseCoprocNumOperand";
1182 def p_imm : Operand<i32> {
1183 let PrintMethod = "printPImmediate";
1184 let ParserMatchClass = CoprocNumAsmOperand;
1185 let DecoderMethod = "DecodeCoprocessor";
1188 def CoprocRegAsmOperand : AsmOperandClass {
1189 let Name = "CoprocReg";
1190 let ParserMethod = "parseCoprocRegOperand";
1192 def c_imm : Operand<i32> {
1193 let PrintMethod = "printCImmediate";
1194 let ParserMatchClass = CoprocRegAsmOperand;
1196 def CoprocOptionAsmOperand : AsmOperandClass {
1197 let Name = "CoprocOption";
1198 let ParserMethod = "parseCoprocOptionOperand";
1200 def coproc_option_imm : Operand<i32> {
1201 let PrintMethod = "printCoprocOptionImm";
1202 let ParserMatchClass = CoprocOptionAsmOperand;
1205 //===----------------------------------------------------------------------===//
1207 include "ARMInstrFormats.td"
1209 //===----------------------------------------------------------------------===//
1210 // Multiclass helpers...
1213 /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a
1214 /// binop that produces a value.
1215 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1216 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1217 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1218 PatFrag opnode, bit Commutable = 0> {
1219 // The register-immediate version is re-materializable. This is useful
1220 // in particular for taking the address of a local.
1221 let isReMaterializable = 1 in {
1222 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1223 iii, opc, "\t$Rd, $Rn, $imm",
1224 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1225 Sched<[WriteALU, ReadALU]> {
1230 let Inst{19-16} = Rn;
1231 let Inst{15-12} = Rd;
1232 let Inst{11-0} = imm;
1235 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1236 iir, opc, "\t$Rd, $Rn, $Rm",
1237 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1238 Sched<[WriteALU, ReadALU, ReadALU]> {
1243 let isCommutable = Commutable;
1244 let Inst{19-16} = Rn;
1245 let Inst{15-12} = Rd;
1246 let Inst{11-4} = 0b00000000;
1250 def rsi : AsI1<opcod, (outs GPR:$Rd),
1251 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1252 iis, opc, "\t$Rd, $Rn, $shift",
1253 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1254 Sched<[WriteALUsi, ReadALU]> {
1259 let Inst{19-16} = Rn;
1260 let Inst{15-12} = Rd;
1261 let Inst{11-5} = shift{11-5};
1263 let Inst{3-0} = shift{3-0};
1266 def rsr : AsI1<opcod, (outs GPR:$Rd),
1267 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1268 iis, opc, "\t$Rd, $Rn, $shift",
1269 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1270 Sched<[WriteALUsr, ReadALUsr]> {
1275 let Inst{19-16} = Rn;
1276 let Inst{15-12} = Rd;
1277 let Inst{11-8} = shift{11-8};
1279 let Inst{6-5} = shift{6-5};
1281 let Inst{3-0} = shift{3-0};
1285 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1286 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1287 /// it is equivalent to the AsI1_bin_irs counterpart.
1288 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1289 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1290 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1291 PatFrag opnode, bit Commutable = 0> {
1292 // The register-immediate version is re-materializable. This is useful
1293 // in particular for taking the address of a local.
1294 let isReMaterializable = 1 in {
1295 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1296 iii, opc, "\t$Rd, $Rn, $imm",
1297 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1298 Sched<[WriteALU, ReadALU]> {
1303 let Inst{19-16} = Rn;
1304 let Inst{15-12} = Rd;
1305 let Inst{11-0} = imm;
1308 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1309 iir, opc, "\t$Rd, $Rn, $Rm",
1310 [/* pattern left blank */]>,
1311 Sched<[WriteALU, ReadALU, ReadALU]> {
1315 let Inst{11-4} = 0b00000000;
1318 let Inst{15-12} = Rd;
1319 let Inst{19-16} = Rn;
1322 def rsi : AsI1<opcod, (outs GPR:$Rd),
1323 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1324 iis, opc, "\t$Rd, $Rn, $shift",
1325 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1326 Sched<[WriteALUsi, ReadALU]> {
1331 let Inst{19-16} = Rn;
1332 let Inst{15-12} = Rd;
1333 let Inst{11-5} = shift{11-5};
1335 let Inst{3-0} = shift{3-0};
1338 def rsr : AsI1<opcod, (outs GPR:$Rd),
1339 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1340 iis, opc, "\t$Rd, $Rn, $shift",
1341 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1342 Sched<[WriteALUsr, ReadALUsr]> {
1347 let Inst{19-16} = Rn;
1348 let Inst{15-12} = Rd;
1349 let Inst{11-8} = shift{11-8};
1351 let Inst{6-5} = shift{6-5};
1353 let Inst{3-0} = shift{3-0};
1357 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1359 /// These opcodes will be converted to the real non-S opcodes by
1360 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1361 let hasPostISelHook = 1, Defs = [CPSR] in {
1362 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1363 InstrItinClass iis, PatFrag opnode,
1364 bit Commutable = 0> {
1365 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1367 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1368 Sched<[WriteALU, ReadALU]>;
1370 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1372 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1373 Sched<[WriteALU, ReadALU, ReadALU]> {
1374 let isCommutable = Commutable;
1376 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1377 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1379 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1380 so_reg_imm:$shift))]>,
1381 Sched<[WriteALUsi, ReadALU]>;
1383 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1384 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1386 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1387 so_reg_reg:$shift))]>,
1388 Sched<[WriteALUSsr, ReadALUsr]>;
1392 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1393 /// operands are reversed.
1394 let hasPostISelHook = 1, Defs = [CPSR] in {
1395 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1396 InstrItinClass iis, PatFrag opnode,
1397 bit Commutable = 0> {
1398 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1400 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1401 Sched<[WriteALU, ReadALU]>;
1403 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1404 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1406 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1408 Sched<[WriteALUsi, ReadALU]>;
1410 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1411 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1413 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1415 Sched<[WriteALUSsr, ReadALUsr]>;
1419 /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test
1420 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1421 /// a explicit result, only implicitly set CPSR.
1422 let isCompare = 1, Defs = [CPSR] in {
1423 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1424 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1425 PatFrag opnode, bit Commutable = 0,
1426 string rrDecoderMethod = ""> {
1427 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1429 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1430 Sched<[WriteCMP, ReadALU]> {
1435 let Inst{19-16} = Rn;
1436 let Inst{15-12} = 0b0000;
1437 let Inst{11-0} = imm;
1439 let Unpredictable{15-12} = 0b1111;
1441 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1443 [(opnode GPR:$Rn, GPR:$Rm)]>,
1444 Sched<[WriteCMP, ReadALU, ReadALU]> {
1447 let isCommutable = Commutable;
1450 let Inst{19-16} = Rn;
1451 let Inst{15-12} = 0b0000;
1452 let Inst{11-4} = 0b00000000;
1454 let DecoderMethod = rrDecoderMethod;
1456 let Unpredictable{15-12} = 0b1111;
1458 def rsi : AI1<opcod, (outs),
1459 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1460 opc, "\t$Rn, $shift",
1461 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1462 Sched<[WriteCMPsi, ReadALU]> {
1467 let Inst{19-16} = Rn;
1468 let Inst{15-12} = 0b0000;
1469 let Inst{11-5} = shift{11-5};
1471 let Inst{3-0} = shift{3-0};
1473 let Unpredictable{15-12} = 0b1111;
1475 def rsr : AI1<opcod, (outs),
1476 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1477 opc, "\t$Rn, $shift",
1478 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1479 Sched<[WriteCMPsr, ReadALU]> {
1484 let Inst{19-16} = Rn;
1485 let Inst{15-12} = 0b0000;
1486 let Inst{11-8} = shift{11-8};
1488 let Inst{6-5} = shift{6-5};
1490 let Inst{3-0} = shift{3-0};
1492 let Unpredictable{15-12} = 0b1111;
1498 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1499 /// register and one whose operand is a register rotated by 8/16/24.
1500 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1501 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1502 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1503 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1504 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1505 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1509 let Inst{19-16} = 0b1111;
1510 let Inst{15-12} = Rd;
1511 let Inst{11-10} = rot;
1515 class AI_ext_rrot_np<bits<8> opcod, string opc>
1516 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1517 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1518 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1520 let Inst{19-16} = 0b1111;
1521 let Inst{11-10} = rot;
1524 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1525 /// register and one whose operand is a register rotated by 8/16/24.
1526 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1527 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1528 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1529 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1530 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1531 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1536 let Inst{19-16} = Rn;
1537 let Inst{15-12} = Rd;
1538 let Inst{11-10} = rot;
1539 let Inst{9-4} = 0b000111;
1543 class AI_exta_rrot_np<bits<8> opcod, string opc>
1544 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1545 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1546 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1549 let Inst{19-16} = Rn;
1550 let Inst{11-10} = rot;
1553 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1554 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1555 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1556 bit Commutable = 0> {
1557 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1558 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1559 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1560 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1562 Sched<[WriteALU, ReadALU]> {
1567 let Inst{15-12} = Rd;
1568 let Inst{19-16} = Rn;
1569 let Inst{11-0} = imm;
1571 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1572 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1573 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1575 Sched<[WriteALU, ReadALU, ReadALU]> {
1579 let Inst{11-4} = 0b00000000;
1581 let isCommutable = Commutable;
1583 let Inst{15-12} = Rd;
1584 let Inst{19-16} = Rn;
1586 def rsi : AsI1<opcod, (outs GPR:$Rd),
1587 (ins GPR:$Rn, so_reg_imm:$shift),
1588 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1589 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1591 Sched<[WriteALUsi, ReadALU]> {
1596 let Inst{19-16} = Rn;
1597 let Inst{15-12} = Rd;
1598 let Inst{11-5} = shift{11-5};
1600 let Inst{3-0} = shift{3-0};
1602 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1603 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1604 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1605 [(set GPRnopc:$Rd, CPSR,
1606 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1608 Sched<[WriteALUsr, ReadALUsr]> {
1613 let Inst{19-16} = Rn;
1614 let Inst{15-12} = Rd;
1615 let Inst{11-8} = shift{11-8};
1617 let Inst{6-5} = shift{6-5};
1619 let Inst{3-0} = shift{3-0};
1624 /// AI1_rsc_irs - Define instructions and patterns for rsc
1625 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1626 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1627 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1628 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1629 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1630 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1632 Sched<[WriteALU, ReadALU]> {
1637 let Inst{15-12} = Rd;
1638 let Inst{19-16} = Rn;
1639 let Inst{11-0} = imm;
1641 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1642 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1643 [/* pattern left blank */]>,
1644 Sched<[WriteALU, ReadALU, ReadALU]> {
1648 let Inst{11-4} = 0b00000000;
1651 let Inst{15-12} = Rd;
1652 let Inst{19-16} = Rn;
1654 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1655 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1656 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1658 Sched<[WriteALUsi, ReadALU]> {
1663 let Inst{19-16} = Rn;
1664 let Inst{15-12} = Rd;
1665 let Inst{11-5} = shift{11-5};
1667 let Inst{3-0} = shift{3-0};
1669 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1670 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1671 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1673 Sched<[WriteALUsr, ReadALUsr]> {
1678 let Inst{19-16} = Rn;
1679 let Inst{15-12} = Rd;
1680 let Inst{11-8} = shift{11-8};
1682 let Inst{6-5} = shift{6-5};
1684 let Inst{3-0} = shift{3-0};
1689 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1690 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1691 InstrItinClass iir, PatFrag opnode> {
1692 // Note: We use the complex addrmode_imm12 rather than just an input
1693 // GPR and a constrained immediate so that we can use this to match
1694 // frame index references and avoid matching constant pool references.
1695 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1696 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1697 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1700 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1701 let Inst{19-16} = addr{16-13}; // Rn
1702 let Inst{15-12} = Rt;
1703 let Inst{11-0} = addr{11-0}; // imm12
1705 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1706 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1707 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1710 let shift{4} = 0; // Inst{4} = 0
1711 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1712 let Inst{19-16} = shift{16-13}; // Rn
1713 let Inst{15-12} = Rt;
1714 let Inst{11-0} = shift{11-0};
1719 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1720 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1721 InstrItinClass iir, PatFrag opnode> {
1722 // Note: We use the complex addrmode_imm12 rather than just an input
1723 // GPR and a constrained immediate so that we can use this to match
1724 // frame index references and avoid matching constant pool references.
1725 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1726 (ins addrmode_imm12:$addr),
1727 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1728 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1731 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1732 let Inst{19-16} = addr{16-13}; // Rn
1733 let Inst{15-12} = Rt;
1734 let Inst{11-0} = addr{11-0}; // imm12
1736 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1737 (ins ldst_so_reg:$shift),
1738 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1739 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1742 let shift{4} = 0; // Inst{4} = 0
1743 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1744 let Inst{19-16} = shift{16-13}; // Rn
1745 let Inst{15-12} = Rt;
1746 let Inst{11-0} = shift{11-0};
1752 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1753 InstrItinClass iir, PatFrag opnode> {
1754 // Note: We use the complex addrmode_imm12 rather than just an input
1755 // GPR and a constrained immediate so that we can use this to match
1756 // frame index references and avoid matching constant pool references.
1757 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1758 (ins GPR:$Rt, addrmode_imm12:$addr),
1759 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1760 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1763 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1764 let Inst{19-16} = addr{16-13}; // Rn
1765 let Inst{15-12} = Rt;
1766 let Inst{11-0} = addr{11-0}; // imm12
1768 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1769 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1770 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1773 let shift{4} = 0; // Inst{4} = 0
1774 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1775 let Inst{19-16} = shift{16-13}; // Rn
1776 let Inst{15-12} = Rt;
1777 let Inst{11-0} = shift{11-0};
1781 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1782 InstrItinClass iir, PatFrag opnode> {
1783 // Note: We use the complex addrmode_imm12 rather than just an input
1784 // GPR and a constrained immediate so that we can use this to match
1785 // frame index references and avoid matching constant pool references.
1786 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1787 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1788 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1789 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1792 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1793 let Inst{19-16} = addr{16-13}; // Rn
1794 let Inst{15-12} = Rt;
1795 let Inst{11-0} = addr{11-0}; // imm12
1797 def rs : AI2ldst<0b011, 0, isByte, (outs),
1798 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1799 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1800 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1803 let shift{4} = 0; // Inst{4} = 0
1804 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1805 let Inst{19-16} = shift{16-13}; // Rn
1806 let Inst{15-12} = Rt;
1807 let Inst{11-0} = shift{11-0};
1812 //===----------------------------------------------------------------------===//
1814 //===----------------------------------------------------------------------===//
1816 //===----------------------------------------------------------------------===//
1817 // Miscellaneous Instructions.
1820 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1821 /// the function. The first operand is the ID# for this instruction, the second
1822 /// is the index into the MachineConstantPool that this is, the third is the
1823 /// size in bytes of this constant pool entry.
1824 let hasSideEffects = 0, isNotDuplicable = 1 in
1825 def CONSTPOOL_ENTRY :
1826 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1827 i32imm:$size), NoItinerary, []>;
1829 /// A jumptable consisting of direct 32-bit addresses of the destination basic
1830 /// blocks (either absolute, or relative to the start of the jump-table in PIC
1831 /// mode). Used mostly in ARM and Thumb-1 modes.
1832 def JUMPTABLE_ADDRS :
1833 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1834 i32imm:$size), NoItinerary, []>;
1836 /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables
1837 /// that cannot be optimised to use TBB or TBH.
1838 def JUMPTABLE_INSTS :
1839 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1840 i32imm:$size), NoItinerary, []>;
1842 /// A jumptable consisting of 8-bit unsigned integers representing offsets from
1843 /// a TBB instruction.
1845 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1846 i32imm:$size), NoItinerary, []>;
1848 /// A jumptable consisting of 16-bit unsigned integers representing offsets from
1849 /// a TBH instruction.
1851 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1852 i32imm:$size), NoItinerary, []>;
1855 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1856 // from removing one half of the matched pairs. That breaks PEI, which assumes
1857 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1858 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1859 def ADJCALLSTACKUP :
1860 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1861 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1863 def ADJCALLSTACKDOWN :
1864 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1865 [(ARMcallseq_start timm:$amt)]>;
1868 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
1869 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
1870 Requires<[IsARM, HasV6]> {
1872 let Inst{27-8} = 0b00110010000011110000;
1873 let Inst{7-0} = imm;
1876 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
1877 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
1878 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
1879 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
1880 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
1881 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1883 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1884 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1889 let Inst{15-12} = Rd;
1890 let Inst{19-16} = Rn;
1891 let Inst{27-20} = 0b01101000;
1892 let Inst{7-4} = 0b1011;
1893 let Inst{11-8} = 0b1111;
1894 let Unpredictable{11-8} = 0b1111;
1897 // The 16-bit operand $val can be used by a debugger to store more information
1898 // about the breakpoint.
1899 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1900 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1902 let Inst{3-0} = val{3-0};
1903 let Inst{19-8} = val{15-4};
1904 let Inst{27-20} = 0b00010010;
1905 let Inst{31-28} = 0xe; // AL
1906 let Inst{7-4} = 0b0111;
1908 // default immediate for breakpoint mnemonic
1909 def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
1911 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1912 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1914 let Inst{3-0} = val{3-0};
1915 let Inst{19-8} = val{15-4};
1916 let Inst{27-20} = 0b00010000;
1917 let Inst{31-28} = 0xe; // AL
1918 let Inst{7-4} = 0b0111;
1921 // Change Processor State
1922 // FIXME: We should use InstAlias to handle the optional operands.
1923 class CPS<dag iops, string asm_ops>
1924 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1925 []>, Requires<[IsARM]> {
1931 let Inst{31-28} = 0b1111;
1932 let Inst{27-20} = 0b00010000;
1933 let Inst{19-18} = imod;
1934 let Inst{17} = M; // Enabled if mode is set;
1935 let Inst{16-9} = 0b00000000;
1936 let Inst{8-6} = iflags;
1938 let Inst{4-0} = mode;
1941 let DecoderMethod = "DecodeCPSInstruction" in {
1943 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1944 "$imod\t$iflags, $mode">;
1945 let mode = 0, M = 0 in
1946 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1948 let imod = 0, iflags = 0, M = 1 in
1949 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1952 // Preload signals the memory system of possible future data/instruction access.
1953 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1955 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm,
1956 IIC_Preload, !strconcat(opc, "\t$addr"),
1957 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1958 Sched<[WritePreLd]> {
1961 let Inst{31-26} = 0b111101;
1962 let Inst{25} = 0; // 0 for immediate form
1963 let Inst{24} = data;
1964 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1965 let Inst{22} = read;
1966 let Inst{21-20} = 0b01;
1967 let Inst{19-16} = addr{16-13}; // Rn
1968 let Inst{15-12} = 0b1111;
1969 let Inst{11-0} = addr{11-0}; // imm12
1972 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1973 !strconcat(opc, "\t$shift"),
1974 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1975 Sched<[WritePreLd]> {
1977 let Inst{31-26} = 0b111101;
1978 let Inst{25} = 1; // 1 for register form
1979 let Inst{24} = data;
1980 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1981 let Inst{22} = read;
1982 let Inst{21-20} = 0b01;
1983 let Inst{19-16} = shift{16-13}; // Rn
1984 let Inst{15-12} = 0b1111;
1985 let Inst{11-0} = shift{11-0};
1990 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1991 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1992 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1994 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1995 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1997 let Inst{31-10} = 0b1111000100000001000000;
2002 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
2003 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> {
2005 let Inst{27-4} = 0b001100100000111100001111;
2006 let Inst{3-0} = opt;
2009 // A8.8.247 UDF - Undefined (Encoding A1)
2010 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
2011 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
2013 let Inst{31-28} = 0b1110; // AL
2014 let Inst{27-25} = 0b011;
2015 let Inst{24-20} = 0b11111;
2016 let Inst{19-8} = imm16{15-4};
2017 let Inst{7-4} = 0b1111;
2018 let Inst{3-0} = imm16{3-0};
2022 * A5.4 Permanently UNDEFINED instructions.
2024 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
2025 * Other UDF encodings generate SIGILL.
2027 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
2029 * 1110 0111 1111 iiii iiii iiii 1111 iiii
2031 * 1101 1110 iiii iiii
2032 * It uses the following encoding:
2033 * 1110 0111 1111 1110 1101 1110 1111 0000
2034 * - In ARM: UDF #60896;
2035 * - In Thumb: UDF #254 followed by a branch-to-self.
2037 let isBarrier = 1, isTerminator = 1 in
2038 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
2040 Requires<[IsARM,UseNaClTrap]> {
2041 let Inst = 0xe7fedef0;
2043 let isBarrier = 1, isTerminator = 1 in
2044 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
2046 Requires<[IsARM,DontUseNaClTrap]> {
2047 let Inst = 0xe7ffdefe;
2050 // Address computation and loads and stores in PIC mode.
2051 let isNotDuplicable = 1 in {
2052 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2054 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2055 Sched<[WriteALU, ReadALU]>;
2057 let AddedComplexity = 10 in {
2058 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2060 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2062 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2064 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2066 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2068 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2070 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2072 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2074 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2076 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2078 let AddedComplexity = 10 in {
2079 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2080 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2082 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2083 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2084 addrmodepc:$addr)]>;
2086 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2087 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2089 } // isNotDuplicable = 1
2092 // LEApcrel - Load a pc-relative address into a register without offending the
2094 let hasSideEffects = 0, isReMaterializable = 1 in
2095 // The 'adr' mnemonic encodes differently if the label is before or after
2096 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
2097 // know until then which form of the instruction will be used.
2098 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2099 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
2100 Sched<[WriteALU, ReadALU]> {
2103 let Inst{27-25} = 0b001;
2105 let Inst{23-22} = label{13-12};
2108 let Inst{19-16} = 0b1111;
2109 let Inst{15-12} = Rd;
2110 let Inst{11-0} = label{11-0};
2113 let hasSideEffects = 1 in {
2114 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2115 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2117 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2118 (ins i32imm:$label, pred:$p),
2119 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2122 //===----------------------------------------------------------------------===//
2123 // Control Flow Instructions.
2126 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
2128 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2129 "bx", "\tlr", [(ARMretflag)]>,
2130 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2131 let Inst{27-0} = 0b0001001011111111111100011110;
2135 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
2136 "mov", "\tpc, lr", [(ARMretflag)]>,
2137 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2138 let Inst{27-0} = 0b0001101000001111000000001110;
2141 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
2142 // the user-space one).
2143 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
2145 [(ARMintretflag imm:$offset)]>;
2148 // Indirect branches
2149 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
2151 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2152 [(brind GPR:$dst)]>,
2153 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2155 let Inst{31-4} = 0b1110000100101111111111110001;
2156 let Inst{3-0} = dst;
2159 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2160 "bx", "\t$dst", [/* pattern left blank */]>,
2161 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2163 let Inst{27-4} = 0b000100101111111111110001;
2164 let Inst{3-0} = dst;
2168 // SP is marked as a use to prevent stack-pointer assignments that appear
2169 // immediately before calls from potentially appearing dead.
2171 // FIXME: Do we really need a non-predicated version? If so, it should
2172 // at least be a pseudo instruction expanding to the predicated version
2173 // at MC lowering time.
2174 Defs = [LR], Uses = [SP] in {
2175 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2176 IIC_Br, "bl\t$func",
2177 [(ARMcall tglobaladdr:$func)]>,
2178 Requires<[IsARM]>, Sched<[WriteBrL]> {
2179 let Inst{31-28} = 0b1110;
2181 let Inst{23-0} = func;
2182 let DecoderMethod = "DecodeBranchImmInstruction";
2185 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2186 IIC_Br, "bl", "\t$func",
2187 [(ARMcall_pred tglobaladdr:$func)]>,
2188 Requires<[IsARM]>, Sched<[WriteBrL]> {
2190 let Inst{23-0} = func;
2191 let DecoderMethod = "DecodeBranchImmInstruction";
2195 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2196 IIC_Br, "blx\t$func",
2197 [(ARMcall GPR:$func)]>,
2198 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2200 let Inst{31-4} = 0b1110000100101111111111110011;
2201 let Inst{3-0} = func;
2204 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2205 IIC_Br, "blx", "\t$func",
2206 [(ARMcall_pred GPR:$func)]>,
2207 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2209 let Inst{27-4} = 0b000100101111111111110011;
2210 let Inst{3-0} = func;
2214 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2215 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2216 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2217 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2220 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2221 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2222 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2224 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2225 // return stack predictor.
2226 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2227 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2228 Requires<[IsARM]>, Sched<[WriteBr]>;
2231 let isBranch = 1, isTerminator = 1 in {
2232 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2233 // a two-value operand where a dag node expects two operands. :(
2234 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2235 IIC_Br, "b", "\t$target",
2236 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2239 let Inst{23-0} = target;
2240 let DecoderMethod = "DecodeBranchImmInstruction";
2243 let isBarrier = 1 in {
2244 // B is "predicable" since it's just a Bcc with an 'always' condition.
2245 let isPredicable = 1 in
2246 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2247 // should be sufficient.
2248 // FIXME: Is B really a Barrier? That doesn't seem right.
2249 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2250 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2253 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in {
2254 def BR_JTr : ARMPseudoInst<(outs),
2255 (ins GPR:$target, i32imm:$jt),
2257 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2259 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2260 // into i12 and rs suffixed versions.
2261 def BR_JTm : ARMPseudoInst<(outs),
2262 (ins addrmode2:$target, i32imm:$jt),
2264 [(ARMbrjt (i32 (load addrmode2:$target)),
2265 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2266 def BR_JTadd : ARMPseudoInst<(outs),
2267 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2269 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2270 Sched<[WriteBrTbl]>;
2271 } // isNotDuplicable = 1, isIndirectBranch = 1
2277 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2278 "blx\t$target", []>,
2279 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2280 let Inst{31-25} = 0b1111101;
2282 let Inst{23-0} = target{24-1};
2283 let Inst{24} = target{0};
2287 // Branch and Exchange Jazelle
2288 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2289 [/* pattern left blank */]>, Sched<[WriteBr]> {
2291 let Inst{23-20} = 0b0010;
2292 let Inst{19-8} = 0xfff;
2293 let Inst{7-4} = 0b0010;
2294 let Inst{3-0} = func;
2300 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2301 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2304 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2307 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2309 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2310 Requires<[IsARM]>, Sched<[WriteBr]>;
2312 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2314 (BX GPR:$dst)>, Sched<[WriteBr]>,
2318 // Secure Monitor Call is a system instruction.
2319 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2320 []>, Requires<[IsARM, HasTrustZone]> {
2322 let Inst{23-4} = 0b01100000000000000111;
2323 let Inst{3-0} = opt;
2326 // Supervisor Call (Software Interrupt)
2327 let isCall = 1, Uses = [SP] in {
2328 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2331 let Inst{23-0} = svc;
2335 // Store Return State
2336 class SRSI<bit wb, string asm>
2337 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2338 NoItinerary, asm, "", []> {
2340 let Inst{31-28} = 0b1111;
2341 let Inst{27-25} = 0b100;
2345 let Inst{19-16} = 0b1101; // SP
2346 let Inst{15-5} = 0b00000101000;
2347 let Inst{4-0} = mode;
2350 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2351 let Inst{24-23} = 0;
2353 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2354 let Inst{24-23} = 0;
2356 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2357 let Inst{24-23} = 0b10;
2359 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2360 let Inst{24-23} = 0b10;
2362 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2363 let Inst{24-23} = 0b01;
2365 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2366 let Inst{24-23} = 0b01;
2368 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2369 let Inst{24-23} = 0b11;
2371 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2372 let Inst{24-23} = 0b11;
2375 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2376 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2378 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2379 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2381 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2382 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2384 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2385 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2387 // Return From Exception
2388 class RFEI<bit wb, string asm>
2389 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2390 NoItinerary, asm, "", []> {
2392 let Inst{31-28} = 0b1111;
2393 let Inst{27-25} = 0b100;
2397 let Inst{19-16} = Rn;
2398 let Inst{15-0} = 0xa00;
2401 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2402 let Inst{24-23} = 0;
2404 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2405 let Inst{24-23} = 0;
2407 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2408 let Inst{24-23} = 0b10;
2410 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2411 let Inst{24-23} = 0b10;
2413 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2414 let Inst{24-23} = 0b01;
2416 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2417 let Inst{24-23} = 0b01;
2419 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2420 let Inst{24-23} = 0b11;
2422 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2423 let Inst{24-23} = 0b11;
2426 // Hypervisor Call is a system instruction
2428 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2429 "hvc", "\t$imm", []>,
2430 Requires<[IsARM, HasVirtualization]> {
2433 // Even though HVC isn't predicable, it's encoding includes a condition field.
2434 // The instruction is undefined if the condition field is 0xf otherwise it is
2435 // unpredictable if it isn't condition AL (0xe).
2436 let Inst{31-28} = 0b1110;
2437 let Unpredictable{31-28} = 0b1111;
2438 let Inst{27-24} = 0b0001;
2439 let Inst{23-20} = 0b0100;
2440 let Inst{19-8} = imm{15-4};
2441 let Inst{7-4} = 0b0111;
2442 let Inst{3-0} = imm{3-0};
2446 // Return from exception in Hypervisor mode.
2447 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
2448 def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>,
2449 Requires<[IsARM, HasVirtualization]> {
2450 let Inst{23-0} = 0b011000000000000001101110;
2453 //===----------------------------------------------------------------------===//
2454 // Load / Store Instructions.
2460 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2461 UnOpFrag<(load node:$Src)>>;
2462 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2463 UnOpFrag<(zextloadi8 node:$Src)>>;
2464 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2465 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2466 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2467 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2469 // Special LDR for loads from non-pc-relative constpools.
2470 let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0,
2471 isReMaterializable = 1, isCodeGenOnly = 1 in
2472 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2473 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2477 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2478 let Inst{19-16} = 0b1111;
2479 let Inst{15-12} = Rt;
2480 let Inst{11-0} = addr{11-0}; // imm12
2483 // Loads with zero extension
2484 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2485 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2486 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2488 // Loads with sign extension
2489 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2490 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2491 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2493 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2494 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2495 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2497 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2499 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2500 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2501 Requires<[IsARM, HasV5TE]>;
2504 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2505 NoItinerary, "lda", "\t$Rt, $addr", []>;
2506 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2507 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2508 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2509 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2512 multiclass AI2_ldridx<bit isByte, string opc,
2513 InstrItinClass iii, InstrItinClass iir> {
2514 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2515 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2516 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2519 let Inst{23} = addr{12};
2520 let Inst{19-16} = addr{16-13};
2521 let Inst{11-0} = addr{11-0};
2522 let DecoderMethod = "DecodeLDRPreImm";
2525 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2526 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2527 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2530 let Inst{23} = addr{12};
2531 let Inst{19-16} = addr{16-13};
2532 let Inst{11-0} = addr{11-0};
2534 let DecoderMethod = "DecodeLDRPreReg";
2537 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2538 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2539 IndexModePost, LdFrm, iir,
2540 opc, "\t$Rt, $addr, $offset",
2541 "$addr.base = $Rn_wb", []> {
2547 let Inst{23} = offset{12};
2548 let Inst{19-16} = addr;
2549 let Inst{11-0} = offset{11-0};
2552 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2555 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2556 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2557 IndexModePost, LdFrm, iii,
2558 opc, "\t$Rt, $addr, $offset",
2559 "$addr.base = $Rn_wb", []> {
2565 let Inst{23} = offset{12};
2566 let Inst{19-16} = addr;
2567 let Inst{11-0} = offset{11-0};
2569 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2574 let mayLoad = 1, hasSideEffects = 0 in {
2575 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2576 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2577 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2578 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2581 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2582 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2583 (ins addrmode3_pre:$addr), IndexModePre,
2585 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2587 let Inst{23} = addr{8}; // U bit
2588 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2589 let Inst{19-16} = addr{12-9}; // Rn
2590 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2591 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2592 let DecoderMethod = "DecodeAddrMode3Instruction";
2594 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2595 (ins addr_offset_none:$addr, am3offset:$offset),
2596 IndexModePost, LdMiscFrm, itin,
2597 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2601 let Inst{23} = offset{8}; // U bit
2602 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2603 let Inst{19-16} = addr;
2604 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2605 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2606 let DecoderMethod = "DecodeAddrMode3Instruction";
2610 let mayLoad = 1, hasSideEffects = 0 in {
2611 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2612 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2613 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2614 let hasExtraDefRegAllocReq = 1 in {
2615 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2616 (ins addrmode3_pre:$addr), IndexModePre,
2617 LdMiscFrm, IIC_iLoad_d_ru,
2618 "ldrd", "\t$Rt, $Rt2, $addr!",
2619 "$addr.base = $Rn_wb", []> {
2621 let Inst{23} = addr{8}; // U bit
2622 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2623 let Inst{19-16} = addr{12-9}; // Rn
2624 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2625 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2626 let DecoderMethod = "DecodeAddrMode3Instruction";
2628 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2629 (ins addr_offset_none:$addr, am3offset:$offset),
2630 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2631 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2632 "$addr.base = $Rn_wb", []> {
2635 let Inst{23} = offset{8}; // U bit
2636 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2637 let Inst{19-16} = addr;
2638 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2639 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2640 let DecoderMethod = "DecodeAddrMode3Instruction";
2642 } // hasExtraDefRegAllocReq = 1
2643 } // mayLoad = 1, hasSideEffects = 0
2645 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2646 let mayLoad = 1, hasSideEffects = 0 in {
2647 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2648 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2649 IndexModePost, LdFrm, IIC_iLoad_ru,
2650 "ldrt", "\t$Rt, $addr, $offset",
2651 "$addr.base = $Rn_wb", []> {
2657 let Inst{23} = offset{12};
2658 let Inst{21} = 1; // overwrite
2659 let Inst{19-16} = addr;
2660 let Inst{11-5} = offset{11-5};
2662 let Inst{3-0} = offset{3-0};
2663 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2667 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2668 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2669 IndexModePost, LdFrm, IIC_iLoad_ru,
2670 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2676 let Inst{23} = offset{12};
2677 let Inst{21} = 1; // overwrite
2678 let Inst{19-16} = addr;
2679 let Inst{11-0} = offset{11-0};
2680 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2683 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2684 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2685 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2686 "ldrbt", "\t$Rt, $addr, $offset",
2687 "$addr.base = $Rn_wb", []> {
2693 let Inst{23} = offset{12};
2694 let Inst{21} = 1; // overwrite
2695 let Inst{19-16} = addr;
2696 let Inst{11-5} = offset{11-5};
2698 let Inst{3-0} = offset{3-0};
2699 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2703 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2704 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2705 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2706 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2712 let Inst{23} = offset{12};
2713 let Inst{21} = 1; // overwrite
2714 let Inst{19-16} = addr;
2715 let Inst{11-0} = offset{11-0};
2716 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2719 multiclass AI3ldrT<bits<4> op, string opc> {
2720 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2721 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2722 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2723 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2725 let Inst{23} = offset{8};
2727 let Inst{11-8} = offset{7-4};
2728 let Inst{3-0} = offset{3-0};
2730 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2731 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2732 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2733 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2735 let Inst{23} = Rm{4};
2738 let Unpredictable{11-8} = 0b1111;
2739 let Inst{3-0} = Rm{3-0};
2740 let DecoderMethod = "DecodeLDR";
2744 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2745 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2746 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2750 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2754 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
2759 // Stores with truncate
2760 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2761 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2762 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2765 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2766 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2767 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2768 Requires<[IsARM, HasV5TE]> {
2774 multiclass AI2_stridx<bit isByte, string opc,
2775 InstrItinClass iii, InstrItinClass iir> {
2776 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2777 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2779 opc, "\t$Rt, $addr!",
2780 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2783 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2784 let Inst{19-16} = addr{16-13}; // Rn
2785 let Inst{11-0} = addr{11-0}; // imm12
2786 let DecoderMethod = "DecodeSTRPreImm";
2789 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2790 (ins GPR:$Rt, ldst_so_reg:$addr),
2791 IndexModePre, StFrm, iir,
2792 opc, "\t$Rt, $addr!",
2793 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2796 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2797 let Inst{19-16} = addr{16-13}; // Rn
2798 let Inst{11-0} = addr{11-0};
2799 let Inst{4} = 0; // Inst{4} = 0
2800 let DecoderMethod = "DecodeSTRPreReg";
2802 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2803 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2804 IndexModePost, StFrm, iir,
2805 opc, "\t$Rt, $addr, $offset",
2806 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2812 let Inst{23} = offset{12};
2813 let Inst{19-16} = addr;
2814 let Inst{11-0} = offset{11-0};
2817 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2820 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2821 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2822 IndexModePost, StFrm, iii,
2823 opc, "\t$Rt, $addr, $offset",
2824 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2830 let Inst{23} = offset{12};
2831 let Inst{19-16} = addr;
2832 let Inst{11-0} = offset{11-0};
2834 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2838 let mayStore = 1, hasSideEffects = 0 in {
2839 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2840 // IIC_iStore_siu depending on whether it the offset register is shifted.
2841 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2842 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2845 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2846 am2offset_reg:$offset),
2847 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2848 am2offset_reg:$offset)>;
2849 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2850 am2offset_imm:$offset),
2851 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2852 am2offset_imm:$offset)>;
2853 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2854 am2offset_reg:$offset),
2855 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2856 am2offset_reg:$offset)>;
2857 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2858 am2offset_imm:$offset),
2859 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2860 am2offset_imm:$offset)>;
2862 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2863 // put the patterns on the instruction definitions directly as ISel wants
2864 // the address base and offset to be separate operands, not a single
2865 // complex operand like we represent the instructions themselves. The
2866 // pseudos map between the two.
2867 let usesCustomInserter = 1,
2868 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2869 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2870 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2873 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2874 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2875 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2878 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2879 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2880 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2883 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2884 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2885 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2888 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2889 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2890 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2893 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2898 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2899 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2900 StMiscFrm, IIC_iStore_bh_ru,
2901 "strh", "\t$Rt, $addr!",
2902 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
2904 let Inst{23} = addr{8}; // U bit
2905 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2906 let Inst{19-16} = addr{12-9}; // Rn
2907 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2908 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2909 let DecoderMethod = "DecodeAddrMode3Instruction";
2912 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2913 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2914 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2915 "strh", "\t$Rt, $addr, $offset",
2916 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb",
2917 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2918 addr_offset_none:$addr,
2919 am3offset:$offset))]> {
2922 let Inst{23} = offset{8}; // U bit
2923 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2924 let Inst{19-16} = addr;
2925 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2926 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2927 let DecoderMethod = "DecodeAddrMode3Instruction";
2930 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2931 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2932 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2933 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2934 "strd", "\t$Rt, $Rt2, $addr!",
2935 "$addr.base = $Rn_wb", []> {
2937 let Inst{23} = addr{8}; // U bit
2938 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2939 let Inst{19-16} = addr{12-9}; // Rn
2940 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2941 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2942 let DecoderMethod = "DecodeAddrMode3Instruction";
2945 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2946 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2948 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2949 "strd", "\t$Rt, $Rt2, $addr, $offset",
2950 "$addr.base = $Rn_wb", []> {
2953 let Inst{23} = offset{8}; // U bit
2954 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2955 let Inst{19-16} = addr;
2956 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2957 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2958 let DecoderMethod = "DecodeAddrMode3Instruction";
2960 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2962 // STRT, STRBT, and STRHT
2964 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2965 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2966 IndexModePost, StFrm, IIC_iStore_bh_ru,
2967 "strbt", "\t$Rt, $addr, $offset",
2968 "$addr.base = $Rn_wb", []> {
2974 let Inst{23} = offset{12};
2975 let Inst{21} = 1; // overwrite
2976 let Inst{19-16} = addr;
2977 let Inst{11-5} = offset{11-5};
2979 let Inst{3-0} = offset{3-0};
2980 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2984 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2985 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2986 IndexModePost, StFrm, IIC_iStore_bh_ru,
2987 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
2993 let Inst{23} = offset{12};
2994 let Inst{21} = 1; // overwrite
2995 let Inst{19-16} = addr;
2996 let Inst{11-0} = offset{11-0};
2997 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3001 : ARMAsmPseudo<"strbt${q} $Rt, $addr",
3002 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3004 let mayStore = 1, hasSideEffects = 0 in {
3005 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3006 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3007 IndexModePost, StFrm, IIC_iStore_ru,
3008 "strt", "\t$Rt, $addr, $offset",
3009 "$addr.base = $Rn_wb", []> {
3015 let Inst{23} = offset{12};
3016 let Inst{21} = 1; // overwrite
3017 let Inst{19-16} = addr;
3018 let Inst{11-5} = offset{11-5};
3020 let Inst{3-0} = offset{3-0};
3021 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3025 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3026 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3027 IndexModePost, StFrm, IIC_iStore_ru,
3028 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
3034 let Inst{23} = offset{12};
3035 let Inst{21} = 1; // overwrite
3036 let Inst{19-16} = addr;
3037 let Inst{11-0} = offset{11-0};
3038 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
3043 : ARMAsmPseudo<"strt${q} $Rt, $addr",
3044 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3046 multiclass AI3strT<bits<4> op, string opc> {
3047 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3048 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3049 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3050 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
3052 let Inst{23} = offset{8};
3054 let Inst{11-8} = offset{7-4};
3055 let Inst{3-0} = offset{3-0};
3057 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3058 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3059 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
3060 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3062 let Inst{23} = Rm{4};
3065 let Inst{3-0} = Rm{3-0};
3070 defm STRHT : AI3strT<0b1011, "strht">;
3072 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3073 NoItinerary, "stl", "\t$Rt, $addr", []>;
3074 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3075 NoItinerary, "stlb", "\t$Rt, $addr", []>;
3076 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3077 NoItinerary, "stlh", "\t$Rt, $addr", []>;
3079 //===----------------------------------------------------------------------===//
3080 // Load / store multiple Instructions.
3083 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
3084 InstrItinClass itin, InstrItinClass itin_upd> {
3085 // IA is the default, so no need for an explicit suffix on the
3086 // mnemonic here. Without it is the canonical spelling.
3088 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3089 IndexModeNone, f, itin,
3090 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3091 let Inst{24-23} = 0b01; // Increment After
3092 let Inst{22} = P_bit;
3093 let Inst{21} = 0; // No writeback
3094 let Inst{20} = L_bit;
3097 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3098 IndexModeUpd, f, itin_upd,
3099 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3100 let Inst{24-23} = 0b01; // Increment After
3101 let Inst{22} = P_bit;
3102 let Inst{21} = 1; // Writeback
3103 let Inst{20} = L_bit;
3105 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3108 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3109 IndexModeNone, f, itin,
3110 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3111 let Inst{24-23} = 0b00; // Decrement After
3112 let Inst{22} = P_bit;
3113 let Inst{21} = 0; // No writeback
3114 let Inst{20} = L_bit;
3117 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3118 IndexModeUpd, f, itin_upd,
3119 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3120 let Inst{24-23} = 0b00; // Decrement After
3121 let Inst{22} = P_bit;
3122 let Inst{21} = 1; // Writeback
3123 let Inst{20} = L_bit;
3125 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3128 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3129 IndexModeNone, f, itin,
3130 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3131 let Inst{24-23} = 0b10; // Decrement Before
3132 let Inst{22} = P_bit;
3133 let Inst{21} = 0; // No writeback
3134 let Inst{20} = L_bit;
3137 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3138 IndexModeUpd, f, itin_upd,
3139 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3140 let Inst{24-23} = 0b10; // Decrement Before
3141 let Inst{22} = P_bit;
3142 let Inst{21} = 1; // Writeback
3143 let Inst{20} = L_bit;
3145 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3148 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3149 IndexModeNone, f, itin,
3150 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3151 let Inst{24-23} = 0b11; // Increment Before
3152 let Inst{22} = P_bit;
3153 let Inst{21} = 0; // No writeback
3154 let Inst{20} = L_bit;
3157 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3158 IndexModeUpd, f, itin_upd,
3159 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3160 let Inst{24-23} = 0b11; // Increment Before
3161 let Inst{22} = P_bit;
3162 let Inst{21} = 1; // Writeback
3163 let Inst{20} = L_bit;
3165 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
3169 let hasSideEffects = 0 in {
3171 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3172 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
3173 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">;
3175 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3176 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
3178 ComplexDeprecationPredicate<"ARMStore">;
3182 // FIXME: remove when we have a way to marking a MI with these properties.
3183 // FIXME: Should pc be an implicit operand like PICADD, etc?
3184 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3185 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3186 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3187 reglist:$regs, variable_ops),
3188 4, IIC_iLoad_mBr, [],
3189 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3190 RegConstraint<"$Rn = $wb">;
3192 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3193 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
3196 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3197 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
3202 //===----------------------------------------------------------------------===//
3203 // Move Instructions.
3206 let hasSideEffects = 0 in
3207 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3208 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3212 let Inst{19-16} = 0b0000;
3213 let Inst{11-4} = 0b00000000;
3216 let Inst{15-12} = Rd;
3219 // A version for the smaller set of tail call registers.
3220 let hasSideEffects = 0 in
3221 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3222 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3226 let Inst{11-4} = 0b00000000;
3229 let Inst{15-12} = Rd;
3232 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3233 DPSoRegRegFrm, IIC_iMOVsr,
3234 "mov", "\t$Rd, $src",
3235 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3239 let Inst{15-12} = Rd;
3240 let Inst{19-16} = 0b0000;
3241 let Inst{11-8} = src{11-8};
3243 let Inst{6-5} = src{6-5};
3245 let Inst{3-0} = src{3-0};
3249 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3250 DPSoRegImmFrm, IIC_iMOVsr,
3251 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3252 UnaryDP, Sched<[WriteALU]> {
3255 let Inst{15-12} = Rd;
3256 let Inst{19-16} = 0b0000;
3257 let Inst{11-5} = src{11-5};
3259 let Inst{3-0} = src{3-0};
3263 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3264 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3265 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3270 let Inst{15-12} = Rd;
3271 let Inst{19-16} = 0b0000;
3272 let Inst{11-0} = imm;
3275 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3276 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3278 "movw", "\t$Rd, $imm",
3279 [(set GPR:$Rd, imm0_65535:$imm)]>,
3280 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3283 let Inst{15-12} = Rd;
3284 let Inst{11-0} = imm{11-0};
3285 let Inst{19-16} = imm{15-12};
3288 let DecoderMethod = "DecodeArmMOVTWInstruction";
3291 def : InstAlias<"mov${p} $Rd, $imm",
3292 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3295 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3296 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3299 let Constraints = "$src = $Rd" in {
3300 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3301 (ins GPR:$src, imm0_65535_expr:$imm),
3303 "movt", "\t$Rd, $imm",
3305 (or (and GPR:$src, 0xffff),
3306 lo16AllZero:$imm))]>, UnaryDP,
3307 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3310 let Inst{15-12} = Rd;
3311 let Inst{11-0} = imm{11-0};
3312 let Inst{19-16} = imm{15-12};
3315 let DecoderMethod = "DecodeArmMOVTWInstruction";
3318 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3319 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3324 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3325 Requires<[IsARM, HasV6T2]>;
3327 let Uses = [CPSR] in
3328 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3329 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3330 Requires<[IsARM]>, Sched<[WriteALU]>;
3332 // These aren't really mov instructions, but we have to define them this way
3333 // due to flag operands.
3335 let Defs = [CPSR] in {
3336 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3337 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3338 Sched<[WriteALU]>, Requires<[IsARM]>;
3339 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3340 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3341 Sched<[WriteALU]>, Requires<[IsARM]>;
3344 //===----------------------------------------------------------------------===//
3345 // Extend Instructions.
3350 def SXTB : AI_ext_rrot<0b01101010,
3351 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3352 def SXTH : AI_ext_rrot<0b01101011,
3353 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3355 def SXTAB : AI_exta_rrot<0b01101010,
3356 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3357 def SXTAH : AI_exta_rrot<0b01101011,
3358 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3360 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3362 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3366 let AddedComplexity = 16 in {
3367 def UXTB : AI_ext_rrot<0b01101110,
3368 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3369 def UXTH : AI_ext_rrot<0b01101111,
3370 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3371 def UXTB16 : AI_ext_rrot<0b01101100,
3372 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3374 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3375 // The transformation should probably be done as a combiner action
3376 // instead so we can include a check for masking back in the upper
3377 // eight bits of the source into the lower eight bits of the result.
3378 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3379 // (UXTB16r_rot GPR:$Src, 3)>;
3380 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3381 (UXTB16 GPR:$Src, 1)>;
3383 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3384 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3385 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3386 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3389 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3390 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3393 def SBFX : I<(outs GPRnopc:$Rd),
3394 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3395 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3396 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3397 Requires<[IsARM, HasV6T2]> {
3402 let Inst{27-21} = 0b0111101;
3403 let Inst{6-4} = 0b101;
3404 let Inst{20-16} = width;
3405 let Inst{15-12} = Rd;
3406 let Inst{11-7} = lsb;
3410 def UBFX : I<(outs GPRnopc:$Rd),
3411 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3412 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3413 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3414 Requires<[IsARM, HasV6T2]> {
3419 let Inst{27-21} = 0b0111111;
3420 let Inst{6-4} = 0b101;
3421 let Inst{20-16} = width;
3422 let Inst{15-12} = Rd;
3423 let Inst{11-7} = lsb;
3427 //===----------------------------------------------------------------------===//
3428 // Arithmetic Instructions.
3431 defm ADD : AsI1_bin_irs<0b0100, "add",
3432 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3433 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3434 defm SUB : AsI1_bin_irs<0b0010, "sub",
3435 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3436 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3438 // ADD and SUB with 's' bit set.
3440 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3441 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3442 // AdjustInstrPostInstrSelection where we determine whether or not to
3443 // set the "s" bit based on CPSR liveness.
3445 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3446 // support for an optional CPSR definition that corresponds to the DAG
3447 // node's second value. We can then eliminate the implicit def of CPSR.
3448 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3449 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3450 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3451 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3453 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3454 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3455 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3456 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3458 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3459 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3460 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3462 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3463 // CPSR and the implicit def of CPSR is not needed.
3464 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3465 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3467 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3468 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3470 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3471 // The assume-no-carry-in form uses the negation of the input since add/sub
3472 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3473 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3475 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3476 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3477 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3478 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3480 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3481 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3482 Requires<[IsARM, HasV6T2]>;
3483 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3484 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3485 Requires<[IsARM, HasV6T2]>;
3487 // The with-carry-in form matches bitwise not instead of the negation.
3488 // Effectively, the inverse interpretation of the carry flag already accounts
3489 // for part of the negation.
3490 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3491 (SBCri GPR:$src, mod_imm_not:$imm)>;
3492 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3493 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3494 Requires<[IsARM, HasV6T2]>;
3496 // Note: These are implemented in C++ code, because they have to generate
3497 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3499 // (mul X, 2^n+1) -> (add (X << n), X)
3500 // (mul X, 2^n-1) -> (rsb X, (X << n))
3502 // ARM Arithmetic Instruction
3503 // GPR:$dst = GPR:$a op GPR:$b
3504 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3505 list<dag> pattern = [],
3506 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3507 string asm = "\t$Rd, $Rn, $Rm">
3508 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3509 Sched<[WriteALU, ReadALU, ReadALU]> {
3513 let Inst{27-20} = op27_20;
3514 let Inst{11-4} = op11_4;
3515 let Inst{19-16} = Rn;
3516 let Inst{15-12} = Rd;
3519 let Unpredictable{11-8} = 0b1111;
3522 // Saturating add/subtract
3524 let DecoderMethod = "DecodeQADDInstruction" in
3525 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3526 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3527 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3529 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3530 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3531 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3532 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3533 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3535 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3536 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3539 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3540 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3541 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3542 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3543 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3544 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3545 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3546 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3547 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3548 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3549 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3550 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3552 // Signed/Unsigned add/subtract
3554 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3555 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3556 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3557 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3558 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3559 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3560 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3561 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3562 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3563 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3564 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3565 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3567 // Signed/Unsigned halving add/subtract
3569 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3570 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3571 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3572 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3573 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3574 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3575 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3576 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3577 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3578 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3579 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3580 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3582 // Unsigned Sum of Absolute Differences [and Accumulate].
3584 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3585 MulFrm /* for convenience */, NoItinerary, "usad8",
3586 "\t$Rd, $Rn, $Rm", []>,
3587 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3591 let Inst{27-20} = 0b01111000;
3592 let Inst{15-12} = 0b1111;
3593 let Inst{7-4} = 0b0001;
3594 let Inst{19-16} = Rd;
3595 let Inst{11-8} = Rm;
3598 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3599 MulFrm /* for convenience */, NoItinerary, "usada8",
3600 "\t$Rd, $Rn, $Rm, $Ra", []>,
3601 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3606 let Inst{27-20} = 0b01111000;
3607 let Inst{7-4} = 0b0001;
3608 let Inst{19-16} = Rd;
3609 let Inst{15-12} = Ra;
3610 let Inst{11-8} = Rm;
3614 // Signed/Unsigned saturate
3616 def SSAT : AI<(outs GPRnopc:$Rd),
3617 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3618 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3623 let Inst{27-21} = 0b0110101;
3624 let Inst{5-4} = 0b01;
3625 let Inst{20-16} = sat_imm;
3626 let Inst{15-12} = Rd;
3627 let Inst{11-7} = sh{4-0};
3628 let Inst{6} = sh{5};
3632 def SSAT16 : AI<(outs GPRnopc:$Rd),
3633 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3634 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3638 let Inst{27-20} = 0b01101010;
3639 let Inst{11-4} = 0b11110011;
3640 let Inst{15-12} = Rd;
3641 let Inst{19-16} = sat_imm;
3645 def USAT : AI<(outs GPRnopc:$Rd),
3646 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3647 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3652 let Inst{27-21} = 0b0110111;
3653 let Inst{5-4} = 0b01;
3654 let Inst{15-12} = Rd;
3655 let Inst{11-7} = sh{4-0};
3656 let Inst{6} = sh{5};
3657 let Inst{20-16} = sat_imm;
3661 def USAT16 : AI<(outs GPRnopc:$Rd),
3662 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3663 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3667 let Inst{27-20} = 0b01101110;
3668 let Inst{11-4} = 0b11110011;
3669 let Inst{15-12} = Rd;
3670 let Inst{19-16} = sat_imm;
3674 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3675 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3676 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3677 (USAT imm:$pos, GPRnopc:$a, 0)>;
3679 //===----------------------------------------------------------------------===//
3680 // Bitwise Instructions.
3683 defm AND : AsI1_bin_irs<0b0000, "and",
3684 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3685 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3686 defm ORR : AsI1_bin_irs<0b1100, "orr",
3687 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3688 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3689 defm EOR : AsI1_bin_irs<0b0001, "eor",
3690 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3691 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3692 defm BIC : AsI1_bin_irs<0b1110, "bic",
3693 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3694 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3696 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3697 // like in the actual instruction encoding. The complexity of mapping the mask
3698 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3699 // instruction description.
3700 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3701 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3702 "bfc", "\t$Rd, $imm", "$src = $Rd",
3703 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3704 Requires<[IsARM, HasV6T2]> {
3707 let Inst{27-21} = 0b0111110;
3708 let Inst{6-0} = 0b0011111;
3709 let Inst{15-12} = Rd;
3710 let Inst{11-7} = imm{4-0}; // lsb
3711 let Inst{20-16} = imm{9-5}; // msb
3714 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3715 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3716 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3717 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3718 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3719 bf_inv_mask_imm:$imm))]>,
3720 Requires<[IsARM, HasV6T2]> {
3724 let Inst{27-21} = 0b0111110;
3725 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3726 let Inst{15-12} = Rd;
3727 let Inst{11-7} = imm{4-0}; // lsb
3728 let Inst{20-16} = imm{9-5}; // width
3732 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3733 "mvn", "\t$Rd, $Rm",
3734 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3738 let Inst{19-16} = 0b0000;
3739 let Inst{11-4} = 0b00000000;
3740 let Inst{15-12} = Rd;
3743 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3744 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3745 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3750 let Inst{19-16} = 0b0000;
3751 let Inst{15-12} = Rd;
3752 let Inst{11-5} = shift{11-5};
3754 let Inst{3-0} = shift{3-0};
3756 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3757 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3758 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3763 let Inst{19-16} = 0b0000;
3764 let Inst{15-12} = Rd;
3765 let Inst{11-8} = shift{11-8};
3767 let Inst{6-5} = shift{6-5};
3769 let Inst{3-0} = shift{3-0};
3771 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3772 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3773 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3774 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3778 let Inst{19-16} = 0b0000;
3779 let Inst{15-12} = Rd;
3780 let Inst{11-0} = imm;
3783 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3784 (BICri GPR:$src, mod_imm_not:$imm)>;
3786 //===----------------------------------------------------------------------===//
3787 // Multiply Instructions.
3789 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3790 string opc, string asm, list<dag> pattern>
3791 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3795 let Inst{19-16} = Rd;
3796 let Inst{11-8} = Rm;
3799 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3800 string opc, string asm, list<dag> pattern>
3801 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3806 let Inst{19-16} = RdHi;
3807 let Inst{15-12} = RdLo;
3808 let Inst{11-8} = Rm;
3811 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3812 string opc, string asm, list<dag> pattern>
3813 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3818 let Inst{19-16} = RdHi;
3819 let Inst{15-12} = RdLo;
3820 let Inst{11-8} = Rm;
3824 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3825 // property. Remove them when it's possible to add those properties
3826 // on an individual MachineInstr, not just an instruction description.
3827 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3828 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3829 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3830 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3831 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3832 Requires<[IsARM, HasV6]> {
3833 let Inst{15-12} = 0b0000;
3834 let Unpredictable{15-12} = 0b1111;
3837 let Constraints = "@earlyclobber $Rd" in
3838 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3839 pred:$p, cc_out:$s),
3841 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3842 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3843 Requires<[IsARM, NoV6, UseMulOps]>;
3846 def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
3847 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
3848 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3849 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3850 Requires<[IsARM, HasV6, UseMulOps]> {
3852 let Inst{15-12} = Ra;
3855 let Constraints = "@earlyclobber $Rd" in
3856 def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
3857 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
3858 pred:$p, cc_out:$s), 4, IIC_iMAC32,
3859 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
3860 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3861 Requires<[IsARM, NoV6]>;
3863 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3864 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3865 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3866 Requires<[IsARM, HasV6T2, UseMulOps]> {
3871 let Inst{19-16} = Rd;
3872 let Inst{15-12} = Ra;
3873 let Inst{11-8} = Rm;
3877 // Extra precision multiplies with low / high results
3878 let hasSideEffects = 0 in {
3879 let isCommutable = 1 in {
3880 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3881 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3882 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3883 Requires<[IsARM, HasV6]>;
3885 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3886 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3887 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3888 Requires<[IsARM, HasV6]>;
3890 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3891 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3892 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3894 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3895 Requires<[IsARM, NoV6]>;
3897 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3898 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3900 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3901 Requires<[IsARM, NoV6]>;
3905 // Multiply + accumulate
3906 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3907 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3908 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3909 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3910 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3911 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3912 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3913 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3915 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3916 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3917 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3918 Requires<[IsARM, HasV6]> {
3923 let Inst{19-16} = RdHi;
3924 let Inst{15-12} = RdLo;
3925 let Inst{11-8} = Rm;
3930 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3931 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3932 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3934 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3935 pred:$p, cc_out:$s)>,
3936 Requires<[IsARM, NoV6]>;
3937 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3938 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3940 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3941 pred:$p, cc_out:$s)>,
3942 Requires<[IsARM, NoV6]>;
3947 // Most significant word multiply
3948 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3949 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3950 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3951 Requires<[IsARM, HasV6]> {
3952 let Inst{15-12} = 0b1111;
3955 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3956 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3957 Requires<[IsARM, HasV6]> {
3958 let Inst{15-12} = 0b1111;
3961 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3962 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3963 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3964 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3965 Requires<[IsARM, HasV6, UseMulOps]>;
3967 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3968 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3969 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3970 Requires<[IsARM, HasV6]>;
3972 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3973 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3974 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3975 Requires<[IsARM, HasV6, UseMulOps]>;
3977 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3978 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3979 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3980 Requires<[IsARM, HasV6]>;
3982 multiclass AI_smul<string opc, PatFrag opnode> {
3983 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3984 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3985 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3986 (sext_inreg GPR:$Rm, i16)))]>,
3987 Requires<[IsARM, HasV5TE]>;
3989 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3990 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3991 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3992 (sra GPR:$Rm, (i32 16))))]>,
3993 Requires<[IsARM, HasV5TE]>;
3995 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3996 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3997 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3998 (sext_inreg GPR:$Rm, i16)))]>,
3999 Requires<[IsARM, HasV5TE]>;
4001 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4002 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4003 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4004 (sra GPR:$Rm, (i32 16))))]>,
4005 Requires<[IsARM, HasV5TE]>;
4007 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4008 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4010 Requires<[IsARM, HasV5TE]>;
4012 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4013 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4015 Requires<[IsARM, HasV5TE]>;
4019 multiclass AI_smla<string opc, PatFrag opnode> {
4020 let DecoderMethod = "DecodeSMLAInstruction" in {
4021 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
4022 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4023 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4024 [(set GPRnopc:$Rd, (add GPR:$Ra,
4025 (opnode (sext_inreg GPRnopc:$Rn, i16),
4026 (sext_inreg GPRnopc:$Rm, i16))))]>,
4027 Requires<[IsARM, HasV5TE, UseMulOps]>;
4029 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
4030 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4031 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4033 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4034 (sra GPRnopc:$Rm, (i32 16)))))]>,
4035 Requires<[IsARM, HasV5TE, UseMulOps]>;
4037 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
4038 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4039 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4041 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4042 (sext_inreg GPRnopc:$Rm, i16))))]>,
4043 Requires<[IsARM, HasV5TE, UseMulOps]>;
4045 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
4046 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4047 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4049 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4050 (sra GPRnopc:$Rm, (i32 16)))))]>,
4051 Requires<[IsARM, HasV5TE, UseMulOps]>;
4053 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
4054 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4055 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4057 Requires<[IsARM, HasV5TE, UseMulOps]>;
4059 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
4060 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4061 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4063 Requires<[IsARM, HasV5TE, UseMulOps]>;
4067 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4068 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
4070 // Halfword multiply accumulate long: SMLAL<x><y>.
4071 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4072 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4073 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4074 Requires<[IsARM, HasV5TE]>;
4076 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4077 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4078 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4079 Requires<[IsARM, HasV5TE]>;
4081 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4082 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4083 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4084 Requires<[IsARM, HasV5TE]>;
4086 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4087 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4088 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4089 Requires<[IsARM, HasV5TE]>;
4091 // Helper class for AI_smld.
4092 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
4093 InstrItinClass itin, string opc, string asm>
4094 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
4097 let Inst{27-23} = 0b01110;
4098 let Inst{22} = long;
4099 let Inst{21-20} = 0b00;
4100 let Inst{11-8} = Rm;
4107 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
4108 InstrItinClass itin, string opc, string asm>
4109 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4111 let Inst{15-12} = 0b1111;
4112 let Inst{19-16} = Rd;
4114 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
4115 InstrItinClass itin, string opc, string asm>
4116 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4119 let Inst{19-16} = Rd;
4120 let Inst{15-12} = Ra;
4122 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
4123 InstrItinClass itin, string opc, string asm>
4124 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
4127 let Inst{19-16} = RdHi;
4128 let Inst{15-12} = RdLo;
4131 multiclass AI_smld<bit sub, string opc> {
4133 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
4134 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4135 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4137 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
4138 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4139 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4141 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4142 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4143 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4145 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4146 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4147 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
4151 defm SMLA : AI_smld<0, "smla">;
4152 defm SMLS : AI_smld<1, "smls">;
4154 multiclass AI_sdml<bit sub, string opc> {
4156 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4157 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
4158 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4159 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
4162 defm SMUA : AI_sdml<0, "smua">;
4163 defm SMUS : AI_sdml<1, "smus">;
4165 //===----------------------------------------------------------------------===//
4166 // Division Instructions (ARMv7-A with virtualization extension)
4168 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4169 "sdiv", "\t$Rd, $Rn, $Rm",
4170 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4171 Requires<[IsARM, HasDivideInARM]>;
4173 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4174 "udiv", "\t$Rd, $Rn, $Rm",
4175 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4176 Requires<[IsARM, HasDivideInARM]>;
4178 //===----------------------------------------------------------------------===//
4179 // Misc. Arithmetic Instructions.
4182 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4183 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4184 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4187 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4188 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4189 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
4190 Requires<[IsARM, HasV6T2]>,
4193 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4194 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4195 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4198 let AddedComplexity = 5 in
4199 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4200 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4201 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4202 Requires<[IsARM, HasV6]>,
4205 def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)),
4206 (REV16 (LDRH addrmode3:$addr))>;
4207 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4208 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4210 let AddedComplexity = 5 in
4211 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4212 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4213 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4214 Requires<[IsARM, HasV6]>,
4217 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4218 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4221 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4222 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4223 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4224 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4225 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4227 Requires<[IsARM, HasV6]>,
4228 Sched<[WriteALUsi, ReadALU]>;
4230 // Alternate cases for PKHBT where identities eliminate some nodes.
4231 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4232 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4233 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4234 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4236 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4237 // will match the pattern below.
4238 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4239 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4240 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4241 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4242 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4244 Requires<[IsARM, HasV6]>,
4245 Sched<[WriteALUsi, ReadALU]>;
4247 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4248 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4249 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4250 // pkhtb src1, src2, asr (17..31).
4251 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4252 (srl GPRnopc:$src2, imm16:$sh)),
4253 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4254 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4255 (sra GPRnopc:$src2, imm16_31:$sh)),
4256 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4257 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4258 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4259 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4261 //===----------------------------------------------------------------------===//
4265 // + CRC32{B,H,W} 0x04C11DB7
4266 // + CRC32C{B,H,W} 0x1EDC6F41
4269 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4270 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4271 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4272 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4273 Requires<[IsARM, HasV8, HasCRC]> {
4278 let Inst{31-28} = 0b1110;
4279 let Inst{27-23} = 0b00010;
4280 let Inst{22-21} = sz;
4282 let Inst{19-16} = Rn;
4283 let Inst{15-12} = Rd;
4284 let Inst{11-10} = 0b00;
4287 let Inst{7-4} = 0b0100;
4290 let Unpredictable{11-8} = 0b1101;
4293 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4294 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4295 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4296 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4297 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4298 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4300 //===----------------------------------------------------------------------===//
4301 // ARMv8.1a Privilege Access Never extension
4305 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan",
4306 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> {
4309 let Inst{31-28} = 0b1111;
4310 let Inst{27-20} = 0b00010001;
4311 let Inst{19-16} = 0b0000;
4312 let Inst{15-10} = 0b000000;
4315 let Inst{7-4} = 0b0000;
4316 let Inst{3-0} = 0b0000;
4318 let Unpredictable{19-16} = 0b1111;
4319 let Unpredictable{15-10} = 0b111111;
4320 let Unpredictable{8} = 0b1;
4321 let Unpredictable{3-0} = 0b1111;
4324 //===----------------------------------------------------------------------===//
4325 // Comparison Instructions...
4328 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4329 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4330 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4332 // ARMcmpZ can re-use the above instruction definitions.
4333 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4334 (CMPri GPR:$src, mod_imm:$imm)>;
4335 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4336 (CMPrr GPR:$src, GPR:$rhs)>;
4337 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4338 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4339 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4340 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4342 // CMN register-integer
4343 let isCompare = 1, Defs = [CPSR] in {
4344 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4345 "cmn", "\t$Rn, $imm",
4346 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4347 Sched<[WriteCMP, ReadALU]> {
4352 let Inst{19-16} = Rn;
4353 let Inst{15-12} = 0b0000;
4354 let Inst{11-0} = imm;
4356 let Unpredictable{15-12} = 0b1111;
4359 // CMN register-register/shift
4360 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4361 "cmn", "\t$Rn, $Rm",
4362 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4363 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4366 let isCommutable = 1;
4369 let Inst{19-16} = Rn;
4370 let Inst{15-12} = 0b0000;
4371 let Inst{11-4} = 0b00000000;
4374 let Unpredictable{15-12} = 0b1111;
4377 def CMNzrsi : AI1<0b1011, (outs),
4378 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4379 "cmn", "\t$Rn, $shift",
4380 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4381 GPR:$Rn, so_reg_imm:$shift)]>,
4382 Sched<[WriteCMPsi, ReadALU]> {
4387 let Inst{19-16} = Rn;
4388 let Inst{15-12} = 0b0000;
4389 let Inst{11-5} = shift{11-5};
4391 let Inst{3-0} = shift{3-0};
4393 let Unpredictable{15-12} = 0b1111;
4396 def CMNzrsr : AI1<0b1011, (outs),
4397 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4398 "cmn", "\t$Rn, $shift",
4399 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4400 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4401 Sched<[WriteCMPsr, ReadALU]> {
4406 let Inst{19-16} = Rn;
4407 let Inst{15-12} = 0b0000;
4408 let Inst{11-8} = shift{11-8};
4410 let Inst{6-5} = shift{6-5};
4412 let Inst{3-0} = shift{3-0};
4414 let Unpredictable{15-12} = 0b1111;
4419 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4420 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4422 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4423 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4425 // Note that TST/TEQ don't set all the same flags that CMP does!
4426 defm TST : AI1_cmp_irs<0b1000, "tst",
4427 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4428 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1,
4429 "DecodeTSTInstruction">;
4430 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4431 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4432 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4434 // Pseudo i64 compares for some floating point compares.
4435 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4437 def BCCi64 : PseudoInst<(outs),
4438 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4440 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4443 def BCCZi64 : PseudoInst<(outs),
4444 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4445 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4447 } // usesCustomInserter
4450 // Conditional moves
4451 let hasSideEffects = 0 in {
4453 let isCommutable = 1, isSelect = 1 in
4454 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4455 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4457 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4459 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4461 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4462 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4465 (ARMcmov GPR:$false, so_reg_imm:$shift,
4467 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4468 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4469 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4471 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4473 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4476 let isMoveImm = 1 in
4478 : ARMPseudoInst<(outs GPR:$Rd),
4479 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4481 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4483 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4486 let isMoveImm = 1 in
4487 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4488 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4490 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4492 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4494 // Two instruction predicate mov immediate.
4495 let isMoveImm = 1 in
4497 : ARMPseudoInst<(outs GPR:$Rd),
4498 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4500 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4502 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4504 let isMoveImm = 1 in
4505 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4506 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4508 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4510 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4515 //===----------------------------------------------------------------------===//
4516 // Atomic operations intrinsics
4519 def MemBarrierOptOperand : AsmOperandClass {
4520 let Name = "MemBarrierOpt";
4521 let ParserMethod = "parseMemBarrierOptOperand";
4523 def memb_opt : Operand<i32> {
4524 let PrintMethod = "printMemBOption";
4525 let ParserMatchClass = MemBarrierOptOperand;
4526 let DecoderMethod = "DecodeMemBarrierOption";
4529 def InstSyncBarrierOptOperand : AsmOperandClass {
4530 let Name = "InstSyncBarrierOpt";
4531 let ParserMethod = "parseInstSyncBarrierOptOperand";
4533 def instsyncb_opt : Operand<i32> {
4534 let PrintMethod = "printInstSyncBOption";
4535 let ParserMatchClass = InstSyncBarrierOptOperand;
4536 let DecoderMethod = "DecodeInstSyncBarrierOption";
4539 // Memory barriers protect the atomic sequences
4540 let hasSideEffects = 1 in {
4541 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4542 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4543 Requires<[IsARM, HasDB]> {
4545 let Inst{31-4} = 0xf57ff05;
4546 let Inst{3-0} = opt;
4549 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4550 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4551 Requires<[IsARM, HasDB]> {
4553 let Inst{31-4} = 0xf57ff04;
4554 let Inst{3-0} = opt;
4557 // ISB has only full system option
4558 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4559 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
4560 Requires<[IsARM, HasDB]> {
4562 let Inst{31-4} = 0xf57ff06;
4563 let Inst{3-0} = opt;
4567 let usesCustomInserter = 1, Defs = [CPSR] in {
4569 // Pseudo instruction that combines movs + predicated rsbmi
4570 // to implement integer ABS
4571 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4574 let usesCustomInserter = 1 in {
4575 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4576 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4578 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4581 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4582 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4585 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4586 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4589 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4590 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4593 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4594 (int_arm_strex node:$val, node:$ptr), [{
4595 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4598 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4599 (int_arm_strex node:$val, node:$ptr), [{
4600 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4603 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4604 (int_arm_strex node:$val, node:$ptr), [{
4605 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4608 def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4609 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4612 def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4613 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4616 def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{
4617 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4620 def stlex_1 : PatFrag<(ops node:$val, node:$ptr),
4621 (int_arm_stlex node:$val, node:$ptr), [{
4622 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4625 def stlex_2 : PatFrag<(ops node:$val, node:$ptr),
4626 (int_arm_stlex node:$val, node:$ptr), [{
4627 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4630 def stlex_4 : PatFrag<(ops node:$val, node:$ptr),
4631 (int_arm_stlex node:$val, node:$ptr), [{
4632 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4635 let mayLoad = 1 in {
4636 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4637 NoItinerary, "ldrexb", "\t$Rt, $addr",
4638 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4639 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4640 NoItinerary, "ldrexh", "\t$Rt, $addr",
4641 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4642 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4643 NoItinerary, "ldrex", "\t$Rt, $addr",
4644 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4645 let hasExtraDefRegAllocReq = 1 in
4646 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4647 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4648 let DecoderMethod = "DecodeDoubleRegLoad";
4651 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4652 NoItinerary, "ldaexb", "\t$Rt, $addr",
4653 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4654 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4655 NoItinerary, "ldaexh", "\t$Rt, $addr",
4656 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4657 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4658 NoItinerary, "ldaex", "\t$Rt, $addr",
4659 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4660 let hasExtraDefRegAllocReq = 1 in
4661 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4662 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4663 let DecoderMethod = "DecodeDoubleRegLoad";
4667 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4668 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4669 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4670 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4671 addr_offset_none:$addr))]>;
4672 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4673 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4674 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4675 addr_offset_none:$addr))]>;
4676 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4677 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4678 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4679 addr_offset_none:$addr))]>;
4680 let hasExtraSrcRegAllocReq = 1 in
4681 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4682 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4683 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4684 let DecoderMethod = "DecodeDoubleRegStore";
4686 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4687 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4689 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4690 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4691 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4693 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4694 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4695 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4697 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4698 let hasExtraSrcRegAllocReq = 1 in
4699 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4700 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4701 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4702 let DecoderMethod = "DecodeDoubleRegStore";
4706 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4708 Requires<[IsARM, HasV7]> {
4709 let Inst{31-0} = 0b11110101011111111111000000011111;
4712 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4713 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4714 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4715 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4717 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4718 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4719 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4720 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4722 class acquiring_load<PatFrag base>
4723 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4724 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4725 return isAtLeastAcquire(Ordering);
4728 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4729 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4730 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4732 class releasing_store<PatFrag base>
4733 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4734 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4735 return isAtLeastRelease(Ordering);
4738 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4739 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4740 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4742 let AddedComplexity = 8 in {
4743 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4744 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4745 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4746 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4747 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4748 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4751 // SWP/SWPB are deprecated in V6/V7.
4752 let mayLoad = 1, mayStore = 1 in {
4753 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4754 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4756 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4757 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4761 //===----------------------------------------------------------------------===//
4762 // Coprocessor Instructions.
4765 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4766 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4767 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4768 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4769 imm:$CRm, imm:$opc2)]>,
4778 let Inst{3-0} = CRm;
4780 let Inst{7-5} = opc2;
4781 let Inst{11-8} = cop;
4782 let Inst{15-12} = CRd;
4783 let Inst{19-16} = CRn;
4784 let Inst{23-20} = opc1;
4787 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4788 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4789 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4790 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4791 imm:$CRm, imm:$opc2)]>,
4793 let Inst{31-28} = 0b1111;
4801 let Inst{3-0} = CRm;
4803 let Inst{7-5} = opc2;
4804 let Inst{11-8} = cop;
4805 let Inst{15-12} = CRd;
4806 let Inst{19-16} = CRn;
4807 let Inst{23-20} = opc1;
4810 class ACI<dag oops, dag iops, string opc, string asm,
4811 IndexMode im = IndexModeNone>
4812 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4814 let Inst{27-25} = 0b110;
4816 class ACInoP<dag oops, dag iops, string opc, string asm,
4817 IndexMode im = IndexModeNone>
4818 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4820 let Inst{31-28} = 0b1111;
4821 let Inst{27-25} = 0b110;
4823 multiclass LdStCop<bit load, bit Dbit, string asm> {
4824 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4825 asm, "\t$cop, $CRd, $addr"> {
4829 let Inst{24} = 1; // P = 1
4830 let Inst{23} = addr{8};
4831 let Inst{22} = Dbit;
4832 let Inst{21} = 0; // W = 0
4833 let Inst{20} = load;
4834 let Inst{19-16} = addr{12-9};
4835 let Inst{15-12} = CRd;
4836 let Inst{11-8} = cop;
4837 let Inst{7-0} = addr{7-0};
4838 let DecoderMethod = "DecodeCopMemInstruction";
4840 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4841 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4845 let Inst{24} = 1; // P = 1
4846 let Inst{23} = addr{8};
4847 let Inst{22} = Dbit;
4848 let Inst{21} = 1; // W = 1
4849 let Inst{20} = load;
4850 let Inst{19-16} = addr{12-9};
4851 let Inst{15-12} = CRd;
4852 let Inst{11-8} = cop;
4853 let Inst{7-0} = addr{7-0};
4854 let DecoderMethod = "DecodeCopMemInstruction";
4856 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4857 postidx_imm8s4:$offset),
4858 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4863 let Inst{24} = 0; // P = 0
4864 let Inst{23} = offset{8};
4865 let Inst{22} = Dbit;
4866 let Inst{21} = 1; // W = 1
4867 let Inst{20} = load;
4868 let Inst{19-16} = addr;
4869 let Inst{15-12} = CRd;
4870 let Inst{11-8} = cop;
4871 let Inst{7-0} = offset{7-0};
4872 let DecoderMethod = "DecodeCopMemInstruction";
4874 def _OPTION : ACI<(outs),
4875 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4876 coproc_option_imm:$option),
4877 asm, "\t$cop, $CRd, $addr, $option"> {
4882 let Inst{24} = 0; // P = 0
4883 let Inst{23} = 1; // U = 1
4884 let Inst{22} = Dbit;
4885 let Inst{21} = 0; // W = 0
4886 let Inst{20} = load;
4887 let Inst{19-16} = addr;
4888 let Inst{15-12} = CRd;
4889 let Inst{11-8} = cop;
4890 let Inst{7-0} = option;
4891 let DecoderMethod = "DecodeCopMemInstruction";
4894 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4895 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4896 asm, "\t$cop, $CRd, $addr"> {
4900 let Inst{24} = 1; // P = 1
4901 let Inst{23} = addr{8};
4902 let Inst{22} = Dbit;
4903 let Inst{21} = 0; // W = 0
4904 let Inst{20} = load;
4905 let Inst{19-16} = addr{12-9};
4906 let Inst{15-12} = CRd;
4907 let Inst{11-8} = cop;
4908 let Inst{7-0} = addr{7-0};
4909 let DecoderMethod = "DecodeCopMemInstruction";
4911 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4912 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4916 let Inst{24} = 1; // P = 1
4917 let Inst{23} = addr{8};
4918 let Inst{22} = Dbit;
4919 let Inst{21} = 1; // W = 1
4920 let Inst{20} = load;
4921 let Inst{19-16} = addr{12-9};
4922 let Inst{15-12} = CRd;
4923 let Inst{11-8} = cop;
4924 let Inst{7-0} = addr{7-0};
4925 let DecoderMethod = "DecodeCopMemInstruction";
4927 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4928 postidx_imm8s4:$offset),
4929 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4934 let Inst{24} = 0; // P = 0
4935 let Inst{23} = offset{8};
4936 let Inst{22} = Dbit;
4937 let Inst{21} = 1; // W = 1
4938 let Inst{20} = load;
4939 let Inst{19-16} = addr;
4940 let Inst{15-12} = CRd;
4941 let Inst{11-8} = cop;
4942 let Inst{7-0} = offset{7-0};
4943 let DecoderMethod = "DecodeCopMemInstruction";
4945 def _OPTION : ACInoP<(outs),
4946 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4947 coproc_option_imm:$option),
4948 asm, "\t$cop, $CRd, $addr, $option"> {
4953 let Inst{24} = 0; // P = 0
4954 let Inst{23} = 1; // U = 1
4955 let Inst{22} = Dbit;
4956 let Inst{21} = 0; // W = 0
4957 let Inst{20} = load;
4958 let Inst{19-16} = addr;
4959 let Inst{15-12} = CRd;
4960 let Inst{11-8} = cop;
4961 let Inst{7-0} = option;
4962 let DecoderMethod = "DecodeCopMemInstruction";
4966 defm LDC : LdStCop <1, 0, "ldc">;
4967 defm LDCL : LdStCop <1, 1, "ldcl">;
4968 defm STC : LdStCop <0, 0, "stc">;
4969 defm STCL : LdStCop <0, 1, "stcl">;
4970 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4971 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4972 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4973 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
4975 //===----------------------------------------------------------------------===//
4976 // Move between coprocessor and ARM core register.
4979 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4981 : ABI<0b1110, oops, iops, NoItinerary, opc,
4982 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4983 let Inst{20} = direction;
4993 let Inst{15-12} = Rt;
4994 let Inst{11-8} = cop;
4995 let Inst{23-21} = opc1;
4996 let Inst{7-5} = opc2;
4997 let Inst{3-0} = CRm;
4998 let Inst{19-16} = CRn;
5001 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5003 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5004 c_imm:$CRm, imm0_7:$opc2),
5005 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5006 imm:$CRm, imm:$opc2)]>,
5007 ComplexDeprecationPredicate<"MCR">;
5008 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
5009 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5010 c_imm:$CRm, 0, pred:$p)>;
5011 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
5012 (outs GPRwithAPSR:$Rt),
5013 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5015 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
5016 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5017 c_imm:$CRm, 0, pred:$p)>;
5019 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
5020 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5022 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
5024 : ABXI<0b1110, oops, iops, NoItinerary,
5025 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
5026 let Inst{31-24} = 0b11111110;
5027 let Inst{20} = direction;
5037 let Inst{15-12} = Rt;
5038 let Inst{11-8} = cop;
5039 let Inst{23-21} = opc1;
5040 let Inst{7-5} = opc2;
5041 let Inst{3-0} = CRm;
5042 let Inst{19-16} = CRn;
5045 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
5047 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5048 c_imm:$CRm, imm0_7:$opc2),
5049 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5050 imm:$CRm, imm:$opc2)]>,
5052 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
5053 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5055 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5056 (outs GPRwithAPSR:$Rt),
5057 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
5060 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
5061 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
5064 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
5065 imm:$CRm, imm:$opc2),
5066 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
5068 class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag>
5070 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
5073 let Inst{23-21} = 0b010;
5074 let Inst{20} = direction;
5082 let Inst{15-12} = Rt;
5083 let Inst{19-16} = Rt2;
5084 let Inst{11-8} = cop;
5085 let Inst{7-4} = opc1;
5086 let Inst{3-0} = CRm;
5089 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
5090 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
5091 GPRnopc:$Rt2, c_imm:$CRm),
5092 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
5093 GPRnopc:$Rt2, imm:$CRm)]>;
5094 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
5095 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5096 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
5098 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
5099 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5100 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5101 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5103 let Inst{31-28} = 0b1111;
5104 let Inst{23-21} = 0b010;
5105 let Inst{20} = direction;
5113 let Inst{15-12} = Rt;
5114 let Inst{19-16} = Rt2;
5115 let Inst{11-8} = cop;
5116 let Inst{7-4} = opc1;
5117 let Inst{3-0} = CRm;
5119 let DecoderMethod = "DecodeMRRC2";
5122 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5123 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5124 GPRnopc:$Rt2, imm:$CRm)]>;
5125 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5127 //===----------------------------------------------------------------------===//
5128 // Move between special register and ARM core register
5131 // Move to ARM core register from Special Register
5132 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5133 "mrs", "\t$Rd, apsr", []> {
5135 let Inst{23-16} = 0b00001111;
5136 let Unpredictable{19-17} = 0b111;
5138 let Inst{15-12} = Rd;
5140 let Inst{11-0} = 0b000000000000;
5141 let Unpredictable{11-0} = 0b110100001111;
5144 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5147 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5148 // section B9.3.9, with the R bit set to 1.
5149 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5150 "mrs", "\t$Rd, spsr", []> {
5152 let Inst{23-16} = 0b01001111;
5153 let Unpredictable{19-16} = 0b1111;
5155 let Inst{15-12} = Rd;
5157 let Inst{11-0} = 0b000000000000;
5158 let Unpredictable{11-0} = 0b110100001111;
5161 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
5162 // separate encoding (distinguished by bit 5.
5163 def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
5164 NoItinerary, "mrs", "\t$Rd, $banked", []>,
5165 Requires<[IsARM, HasVirtualization]> {
5170 let Inst{22} = banked{5}; // R bit
5171 let Inst{21-20} = 0b00;
5172 let Inst{19-16} = banked{3-0};
5173 let Inst{15-12} = Rd;
5174 let Inst{11-9} = 0b001;
5175 let Inst{8} = banked{4};
5176 let Inst{7-0} = 0b00000000;
5179 // Move from ARM core register to Special Register
5181 // No need to have both system and application versions of MSR (immediate) or
5182 // MSR (register), the encodings are the same and the assembly parser has no way
5183 // to distinguish between them. The mask operand contains the special register
5184 // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be
5185 // accessed in the special register.
5186 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5187 "msr", "\t$mask, $Rn", []> {
5192 let Inst{22} = mask{4}; // R bit
5193 let Inst{21-20} = 0b10;
5194 let Inst{19-16} = mask{3-0};
5195 let Inst{15-12} = 0b1111;
5196 let Inst{11-4} = 0b00000000;
5200 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5201 "msr", "\t$mask, $imm", []> {
5206 let Inst{22} = mask{4}; // R bit
5207 let Inst{21-20} = 0b10;
5208 let Inst{19-16} = mask{3-0};
5209 let Inst{15-12} = 0b1111;
5210 let Inst{11-0} = imm;
5213 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
5214 // separate encoding (distinguished by bit 5.
5215 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5216 NoItinerary, "msr", "\t$banked, $Rn", []>,
5217 Requires<[IsARM, HasVirtualization]> {
5222 let Inst{22} = banked{5}; // R bit
5223 let Inst{21-20} = 0b10;
5224 let Inst{19-16} = banked{3-0};
5225 let Inst{15-12} = 0b1111;
5226 let Inst{11-9} = 0b001;
5227 let Inst{8} = banked{4};
5228 let Inst{7-4} = 0b0000;
5232 // Dynamic stack allocation yields a _chkstk for Windows targets. These calls
5233 // are needed to probe the stack when allocating more than
5234 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
5235 // ensure that the guard pages used by the OS virtual memory manager are
5236 // allocated in correct sequence.
5237 // The main point of having separate instruction are extra unmodelled effects
5238 // (compared to ordinary calls) like stack pointer change.
5240 def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone,
5241 [SDNPHasChain, SDNPSideEffect]>;
5242 let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
5243 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>;
5245 //===----------------------------------------------------------------------===//
5249 // __aeabi_read_tp preserves the registers r1-r3.
5250 // This is a pseudo inst so that we can get the encoding right,
5251 // complete with fixup for the aeabi_read_tp function.
5252 // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
5253 // is defined in "ARMInstrThumb.td".
5255 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5256 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
5257 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5260 //===----------------------------------------------------------------------===//
5261 // SJLJ Exception handling intrinsics
5262 // eh_sjlj_setjmp() is an instruction sequence to store the return
5263 // address and save #0 in R0 for the non-longjmp case.
5264 // Since by its nature we may be coming from some other function to get
5265 // here, and we're using the stack frame for the containing function to
5266 // save/restore registers, we can't keep anything live in regs across
5267 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5268 // when we get here from a longjmp(). We force everything out of registers
5269 // except for our own input by listing the relevant registers in Defs. By
5270 // doing so, we also cause the prologue/epilogue code to actively preserve
5271 // all of the callee-saved resgisters, which is exactly what we want.
5272 // A constant value is passed in $val, and we use the location as a scratch.
5274 // These are pseudo-instructions and are lowered to individual MC-insts, so
5275 // no encoding information is necessary.
5277 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5278 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5279 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5280 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5282 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5283 Requires<[IsARM, HasVFP2]>;
5287 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5288 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5289 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5291 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5292 Requires<[IsARM, NoVFP]>;
5295 // FIXME: Non-IOS version(s)
5296 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5297 Defs = [ R7, LR, SP ] in {
5298 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5300 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5304 // eh.sjlj.dispatchsetup pseudo-instruction.
5305 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5306 // the pseudo is expanded (which happens before any passes that need the
5307 // instruction size).
5308 let isBarrier = 1 in
5309 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5312 //===----------------------------------------------------------------------===//
5313 // Non-Instruction Patterns
5316 // ARMv4 indirect branch using (MOVr PC, dst)
5317 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5318 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5319 4, IIC_Br, [(brind GPR:$dst)],
5320 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5321 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5323 // Large immediate handling.
5325 // 32-bit immediate using two piece mod_imms or movw + movt.
5326 // This is a single pseudo instruction, the benefit is that it can be remat'd
5327 // as a single unit instead of having to handle reg inputs.
5328 // FIXME: Remove this when we can do generalized remat.
5329 let isReMaterializable = 1, isMoveImm = 1 in
5330 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5331 [(set GPR:$dst, (arm_i32imm:$src))]>,
5334 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5335 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5336 Requires<[IsARM, DontUseMovt]>;
5338 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5339 // It also makes it possible to rematerialize the instructions.
5340 // FIXME: Remove this when we can do generalized remat and when machine licm
5341 // can properly the instructions.
5342 let isReMaterializable = 1 in {
5343 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5345 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5346 Requires<[IsARM, UseMovt]>;
5348 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5351 (ARMWrapperPIC tglobaladdr:$addr))]>,
5352 Requires<[IsARM, DontUseMovt]>;
5354 let AddedComplexity = 10 in
5355 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5358 (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5359 Requires<[IsARM, DontUseMovt]>;
5361 let AddedComplexity = 10 in
5362 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5364 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5365 Requires<[IsARM, UseMovt]>;
5366 } // isReMaterializable
5368 // ConstantPool, GlobalAddress, and JumpTable
5369 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5370 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5371 Requires<[IsARM, UseMovt]>;
5372 def : ARMPat<(ARMWrapperJT tjumptable:$dst),
5373 (LEApcrelJT tjumptable:$dst)>;
5375 // TODO: add,sub,and, 3-instr forms?
5377 // Tail calls. These patterns also apply to Thumb mode.
5378 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5379 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5380 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5383 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5384 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5385 (BMOVPCB_CALL texternalsym:$func)>;
5387 // zextload i1 -> zextload i8
5388 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5389 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5391 // extload -> zextload
5392 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5393 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5394 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5395 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5397 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5399 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5400 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5403 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5404 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5405 (SMULBB GPR:$a, GPR:$b)>;
5406 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5407 (SMULBB GPR:$a, GPR:$b)>;
5408 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5409 (sra GPR:$b, (i32 16))),
5410 (SMULBT GPR:$a, GPR:$b)>;
5411 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5412 (SMULBT GPR:$a, GPR:$b)>;
5413 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5414 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5415 (SMULTB GPR:$a, GPR:$b)>;
5416 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5417 (SMULTB GPR:$a, GPR:$b)>;
5419 def : ARMV5MOPat<(add GPR:$acc,
5420 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5421 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5422 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5423 def : ARMV5MOPat<(add GPR:$acc,
5424 (mul sext_16_node:$a, sext_16_node:$b)),
5425 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5426 def : ARMV5MOPat<(add GPR:$acc,
5427 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5428 (sra GPR:$b, (i32 16)))),
5429 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5430 def : ARMV5MOPat<(add GPR:$acc,
5431 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5432 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5433 def : ARMV5MOPat<(add GPR:$acc,
5434 (mul (sra GPR:$a, (i32 16)),
5435 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5436 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5437 def : ARMV5MOPat<(add GPR:$acc,
5438 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5439 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5442 // Pre-v7 uses MCR for synchronization barriers.
5443 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5444 Requires<[IsARM, HasV6]>;
5446 // SXT/UXT with no rotate
5447 let AddedComplexity = 16 in {
5448 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5449 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5450 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5451 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5452 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5453 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5454 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5457 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5458 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5460 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5461 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5462 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5463 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5465 // Atomic load/store patterns
5466 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5467 (LDRBrs ldst_so_reg:$src)>;
5468 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5469 (LDRBi12 addrmode_imm12:$src)>;
5470 def : ARMPat<(atomic_load_16 addrmode3:$src),
5471 (LDRH addrmode3:$src)>;
5472 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5473 (LDRrs ldst_so_reg:$src)>;
5474 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5475 (LDRi12 addrmode_imm12:$src)>;
5476 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5477 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5478 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5479 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5480 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5481 (STRH GPR:$val, addrmode3:$ptr)>;
5482 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5483 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5484 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5485 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5488 //===----------------------------------------------------------------------===//
5492 include "ARMInstrThumb.td"
5494 //===----------------------------------------------------------------------===//
5498 include "ARMInstrThumb2.td"
5500 //===----------------------------------------------------------------------===//
5501 // Floating Point Support
5504 include "ARMInstrVFP.td"
5506 //===----------------------------------------------------------------------===//
5507 // Advanced SIMD (NEON) Support
5510 include "ARMInstrNEON.td"
5512 //===----------------------------------------------------------------------===//
5513 // Assembler aliases
5517 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5518 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5519 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5521 // System instructions
5522 def : MnemonicAlias<"swi", "svc">;
5524 // Load / Store Multiple
5525 def : MnemonicAlias<"ldmfd", "ldm">;
5526 def : MnemonicAlias<"ldmia", "ldm">;
5527 def : MnemonicAlias<"ldmea", "ldmdb">;
5528 def : MnemonicAlias<"stmfd", "stmdb">;
5529 def : MnemonicAlias<"stmia", "stm">;
5530 def : MnemonicAlias<"stmea", "stm">;
5532 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5533 // shift amount is zero (i.e., unspecified).
5534 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5535 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5536 Requires<[IsARM, HasV6]>;
5537 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5538 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5539 Requires<[IsARM, HasV6]>;
5541 // PUSH/POP aliases for STM/LDM
5542 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5543 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5545 // SSAT/USAT optional shift operand.
5546 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5547 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5548 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5549 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5552 // Extend instruction optional rotate operand.
5553 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5554 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5555 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5556 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5557 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5558 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5559 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5560 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5561 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5562 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5563 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5564 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5566 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5567 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5568 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5569 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5570 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5571 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5572 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5573 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5574 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5575 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5576 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5577 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5581 def : MnemonicAlias<"rfefa", "rfeda">;
5582 def : MnemonicAlias<"rfeea", "rfedb">;
5583 def : MnemonicAlias<"rfefd", "rfeia">;
5584 def : MnemonicAlias<"rfeed", "rfeib">;
5585 def : MnemonicAlias<"rfe", "rfeia">;
5588 def : MnemonicAlias<"srsfa", "srsib">;
5589 def : MnemonicAlias<"srsea", "srsia">;
5590 def : MnemonicAlias<"srsfd", "srsdb">;
5591 def : MnemonicAlias<"srsed", "srsda">;
5592 def : MnemonicAlias<"srs", "srsia">;
5595 def : MnemonicAlias<"qsubaddx", "qsax">;
5597 def : MnemonicAlias<"saddsubx", "sasx">;
5598 // SHASX == SHADDSUBX
5599 def : MnemonicAlias<"shaddsubx", "shasx">;
5600 // SHSAX == SHSUBADDX
5601 def : MnemonicAlias<"shsubaddx", "shsax">;
5603 def : MnemonicAlias<"ssubaddx", "ssax">;
5605 def : MnemonicAlias<"uaddsubx", "uasx">;
5606 // UHASX == UHADDSUBX
5607 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5608 // UHSAX == UHSUBADDX
5609 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5610 // UQASX == UQADDSUBX
5611 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5612 // UQSAX == UQSUBADDX
5613 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5615 def : MnemonicAlias<"usubaddx", "usax">;
5617 // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like
5619 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5620 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5621 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5622 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
5623 // Same for AND <--> BIC
5624 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5625 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5626 pred:$p, cc_out:$s)>;
5627 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5628 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5629 pred:$p, cc_out:$s)>;
5630 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5631 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
5632 pred:$p, cc_out:$s)>;
5633 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5634 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
5635 pred:$p, cc_out:$s)>;
5637 // Likewise, "add Rd, mod_imm_neg" -> sub
5638 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5639 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5640 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5641 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5642 // Same for CMP <--> CMN via mod_imm_neg
5643 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5644 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5645 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5646 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
5648 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5649 // LSR, ROR, and RRX instructions.
5650 // FIXME: We need C++ parser hooks to map the alias to the MOV
5651 // encoding. It seems we should be able to do that sort of thing
5652 // in tblgen, but it could get ugly.
5653 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5654 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5655 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5657 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5658 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5660 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5661 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5663 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5664 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5667 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5668 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5669 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5670 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5671 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5673 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5674 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5676 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5677 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5679 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5680 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5684 // "neg" is and alias for "rsb rd, rn, #0"
5685 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5686 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5688 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5689 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5690 Requires<[IsARM, NoV6]>;
5692 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5693 // the instruction definitions need difference constraints pre-v6.
5694 // Use these aliases for the assembly parsing on pre-v6.
5695 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
5696 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
5697 Requires<[IsARM, NoV6]>;
5698 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
5699 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
5700 pred:$p, cc_out:$s)>,
5701 Requires<[IsARM, NoV6]>;
5702 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5703 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5704 Requires<[IsARM, NoV6]>;
5705 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5706 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5707 Requires<[IsARM, NoV6]>;
5708 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5709 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5710 Requires<[IsARM, NoV6]>;
5711 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5712 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5713 Requires<[IsARM, NoV6]>;
5715 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5717 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5718 ComplexDeprecationPredicate<"IT">;
5720 let mayLoad = 1, mayStore =1, hasSideEffects = 1 in
5721 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5723 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;